1 //============================================================
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4 // This file is for 8192E TXBF mechanism
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6 //============================================================
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7 #include "mp_precomp.h"
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8 #include "../phydm_precomp.h"
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10 #if (BEAMFORMING_SUPPORT == 1)
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11 #if (RTL8192E_SUPPORT == 1)
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14 HalTxbf8192E_setNDPArate(
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20 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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22 ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8192E, (Rate << 2 | BW));
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27 halTxbf8192E_RfMode(
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29 IN PRT_BEAMFORMING_INFO pBeamInfo
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32 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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33 BOOLEAN bSelfBeamformer = FALSE;
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34 BOOLEAN bSelfBeamformee = FALSE;
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35 BEAMFORMING_CAP BeamformCap = BEAMFORMING_CAP_NONE;
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37 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
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39 if (pDM_Odm->RFType == ODM_1T1R)
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42 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); /*RF Mode table write enable*/
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43 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, 0x80000, 0x1); /*RF Mode table write enable*/
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45 if (pBeamInfo->beamformee_su_cnt > 0) {
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47 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0xfffff, 0x18000); /*Select RX mode 0x30=0x18000*/
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48 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x0000f); /*Set Table data*/
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49 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0x77fc2); /*Enable TXIQGEN in RX mode*/
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51 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0xfffff, 0x18000); /*Select RX mode*/
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52 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x0000f); /*Set Table data*/
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53 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0x77fc2); /*Enable TXIQGEN in RX mode*/
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56 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0xfffff, 0x18000); /*Select RX mode*/
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57 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x0000f); /*Set Table data*/
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58 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0x77f82); /*Disable TXIQGEN in RX mode*/
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60 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0xfffff, 0x18000); /*Select RX mode*/
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61 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x0000f); /*Set Table data*/
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62 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0x77f82); /*Disable TXIQGEN in RX mode*/
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65 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); /*RF Mode table write disable*/
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66 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, 0x80000, 0x0); /*RF Mode table write disable*/
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68 if (pBeamInfo->beamformee_su_cnt > 0) {
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69 ODM_SetBBReg(pDM_Odm, rFPGA1_TxInfo, bMaskDWord, 0x83321333);
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70 ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, bMaskByte3, 0xc1);
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72 ODM_SetBBReg(pDM_Odm, rFPGA1_TxInfo, bMaskDWord, 0x81121313);
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78 halTxbf8192E_FwTxBFCmd(
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82 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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83 u1Byte Idx, Period0 = 0, Period1 = 0;
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84 u1Byte PageNum0 = 0xFF, PageNum1 = 0xFF;
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85 u1Byte u1TxBFParm[3] = {0};
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86 PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;
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88 for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) {
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89 if (pBeamInfo->BeamformeeEntry[Idx].BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
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91 if (pBeamInfo->BeamformeeEntry[Idx].bSound)
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94 PageNum0 = 0xFF; //stop sounding
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95 Period0 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod);
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96 } else if (Idx == 1) {
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97 if (pBeamInfo->BeamformeeEntry[Idx].bSound)
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100 PageNum1 = 0xFF; //stop sounding
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101 Period1 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod);
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106 u1TxBFParm[0] = PageNum0;
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107 u1TxBFParm[1] = PageNum1;
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108 u1TxBFParm[2] = (Period1 << 4) | Period0;
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109 ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_TXBF, 3, u1TxBFParm);
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111 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD,
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112 ("[%s] PageNum0 = %d Period0 = %d, PageNum1 = %d Period1 %d\n", __func__, PageNum0, Period0, PageNum1, Period1));
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117 halTxbf8192E_DownloadNDPA(
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122 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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123 u1Byte u1bTmp = 0, tmpReg422 = 0, Head_Page;
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124 u1Byte BcnValidReg = 0, count = 0, DLBcnCount = 0;
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125 BOOLEAN bSendBeacon = FALSE;
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126 PADAPTER Adapter = pDM_Odm->Adapter;
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127 u1Byte TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812;
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128 /*default reseved 1 page for the IC type which is undefined.*/
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129 PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;
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130 PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx;
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132 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
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133 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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134 *pDM_Odm->pbFwDwRsvdPageInProgress = TRUE;
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141 Adapter->HalFunc.GetHalDefVarHandler(Adapter, HAL_DEF_TX_PAGE_BOUNDARY, (pu1Byte)&TxPageBndy);
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143 /*Set REG_CR bit 8. DMA beacon by SW.*/
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144 u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8192E+1);
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145 ODM_Write1Byte(pDM_Odm, REG_CR_8192E+1, (u1bTmp | BIT0));
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147 /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
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148 tmpReg422 = ODM_Read1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8192E+2);
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149 ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8192E+2, tmpReg422 & (~BIT6));
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151 if (tmpReg422 & BIT6) {
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152 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_WARNING, ("%s There is an Adapter is sending beacon.\n", __func__));
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153 bSendBeacon = TRUE;
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156 /*TDECTRL[15:8] 0x209[7:0] = 0xFE/0xFD NDPA Head for TXDMA*/
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157 ODM_Write1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+1, Head_Page);
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160 /*Clear beacon valid check bit.*/
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161 BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2);
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162 ODM_Write1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2, (BcnValidReg | BIT0));
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164 // download NDPA rsvd page.
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165 Beamforming_SendHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->SoundBW, BEACON_QUEUE);
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167 #if(DEV_BUS_TYPE == RT_PCI_INTERFACE)
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168 u1bTmp = ODM_Read1Byte(pDM_Odm, REG_MGQ_TXBD_NUM_8192E+3);
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170 while ((count < 20) && (u1bTmp & BIT4)) {
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173 u1bTmp = ODM_Read1Byte(pDM_Odm, REG_MGQ_TXBD_NUM_8192E+3);
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175 ODM_Write1Byte(pDM_Odm, REG_MGQ_TXBD_NUM_8192E+3, u1bTmp | BIT4);
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178 /*check rsvd page download OK.*/
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179 BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2);
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181 while (!(BcnValidReg & BIT0) && count < 20) {
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184 BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2);
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187 } while (!(BcnValidReg & BIT0) && DLBcnCount < 5);
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189 if (!(BcnValidReg & BIT0))
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190 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_WARNING, ("%s Download RSVD page failed!\n", __func__));
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192 /*TDECTRL[15:8] 0x209[7:0] = 0xF9 Beacon Head for TXDMA*/
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193 ODM_Write1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+1, TxPageBndy);
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195 /*To make sure that if there exists an adapter which would like to send beacon.*/
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196 /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
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197 /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/
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198 /*the beacon cannot be sent by HW.*/
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199 /*2010.06.23. Added by tynli.*/
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201 ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8192E+2, tmpReg422);
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203 /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
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204 /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
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205 u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8192E+1);
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206 ODM_Write1Byte(pDM_Odm, REG_CR_8192E+1, (u1bTmp & (~BIT0)));
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208 pBeamEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED;
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209 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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210 *pDM_Odm->pbFwDwRsvdPageInProgress = FALSE;
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216 HalTxbf8192E_Enter(
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218 IN u1Byte BFerBFeeIdx
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221 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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223 u1Byte BFerIdx = (BFerBFeeIdx & 0xF0) >> 4;
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224 u1Byte BFeeIdx = (BFerBFeeIdx & 0xF);
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226 PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo;
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227 RT_BEAMFORMEE_ENTRY BeamformeeEntry;
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228 RT_BEAMFORMER_ENTRY BeamformerEntry;
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231 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
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233 halTxbf8192E_RfMode(pDM_Odm, pBeamformingInfo);
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235 if (pDM_Odm->RFType == ODM_2T2R)
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236 ODM_Write4Byte(pDM_Odm, 0xd80, 0x00000000); /*Nc =2*/
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238 if ((pBeamformingInfo->beamformer_su_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) {
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239 BeamformerEntry = pBeamformingInfo->BeamformerEntry[BFerIdx];
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241 /*Sounding protocol control*/
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242 ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8192E, 0xCB);
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244 /*MAC address/Partial AID of Beamformer*/
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245 if (BFerIdx == 0) {
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246 for (i = 0; i < 6 ; i++)
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247 ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8192E+i), BeamformerEntry.MacAddr[i]);
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249 for (i = 0; i < 6 ; i++)
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250 ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER1_INFO_8192E+i), BeamformerEntry.MacAddr[i]);
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253 /*CSI report parameters of Beamformer Default use Nc = 2*/
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254 CSI_Param = 0x03090309;
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256 ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8192E, CSI_Param);
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257 ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8192E, CSI_Param);
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258 ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8192E, CSI_Param);
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260 /*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us, MP chip)*/
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261 ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8192E+3, 0x50);
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265 if ((pBeamformingInfo->beamformee_su_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) {
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266 BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[BFeeIdx];
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268 if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS))
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269 STAid = BeamformeeEntry.MacId;
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271 STAid = BeamformeeEntry.P_AID;
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273 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s], STAid=0x%X\n", __func__, STAid));
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275 /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
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276 if (BFeeIdx == 0) {
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277 ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E, STAid);
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278 ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8192E+3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8192E+3) | BIT4 | BIT6 | BIT7);
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280 ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E+2, STAid | BIT12 | BIT14 | BIT15);
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282 /*CSI report parameters of Beamformee*/
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283 if (BFeeIdx == 0) {
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284 /*Get BIT24 & BIT25*/
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285 u1Byte tmp = ODM_Read1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+3) & 0x3;
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287 ODM_Write1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+3, tmp | 0x60);
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288 ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E, STAid | BIT9);
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291 ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, STAid | 0xE200);
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293 phydm_Beamforming_Notify(pDM_Odm);
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300 HalTxbf8192E_Leave(
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305 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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306 PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;
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308 halTxbf8192E_RfMode(pDM_Odm, pBeamInfo);
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310 /* Clear P_AID of Beamformee
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311 * Clear MAC addresss of Beamformer
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312 * Clear Associated Bfmee Sel
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314 if (pBeamInfo->BeamformCap == BEAMFORMING_CAP_NONE)
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315 ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8192E, 0xC8);
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318 ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E, 0);
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319 ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8192E, 0);
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320 ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8192E+4, 0);
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321 ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E, 0);
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323 ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E+2, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8192E+2) & 0xF000);
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324 ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8192E, 0);
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325 ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8192E+4, 0);
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326 ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, ODM_Read2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2) & 0x60);
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329 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Idx %d\n", __func__, Idx));
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334 HalTxbf8192E_Status(
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339 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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340 u2Byte BeamCtrlVal;
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341 u4Byte BeamCtrlReg;
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342 PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;
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343 RT_BEAMFORMEE_ENTRY BeamformEntry = pBeamInfo->BeamformeeEntry[Idx];
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345 if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS))
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346 BeamCtrlVal = BeamformEntry.MacId;
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348 BeamCtrlVal = BeamformEntry.P_AID;
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351 BeamCtrlReg = REG_TXBF_CTRL_8192E;
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353 BeamCtrlReg = REG_TXBF_CTRL_8192E+2;
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354 BeamCtrlVal |= BIT12 | BIT14 | BIT15;
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357 if ((BeamformEntry.BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (pBeamInfo->applyVmatrix == TRUE)) {
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358 if (BeamformEntry.SoundBW == CHANNEL_WIDTH_20)
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359 BeamCtrlVal |= BIT9;
\r
360 else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_40)
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361 BeamCtrlVal |= BIT10;
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363 BeamCtrlVal &= ~(BIT9 | BIT10 | BIT11);
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365 ODM_Write2Byte(pDM_Odm, BeamCtrlReg, BeamCtrlVal);
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367 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Idx %d BeamCtrlReg %x BeamCtrlVal %x\n", __func__, Idx, BeamCtrlReg, BeamCtrlVal));
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372 HalTxbf8192E_FwTxBF(
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377 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
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378 PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo;
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379 PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx;
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381 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
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383 if (pBeamEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING)
\r
384 halTxbf8192E_DownloadNDPA(pDM_Odm, Idx);
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386 halTxbf8192E_FwTxBFCmd(pDM_Odm);
\r
389 #endif /* #if (RTL8192E_SUPPORT == 1)*/
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