drivers/net/wireless/rockchip_wlan/rtl8822be/hal/phydm/rtl8822b/phydm_hal_api8822b.c

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *                                        \r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *\r
  19  ******************************************************************************/\r
  20 \r
  21 #include "mp_precomp.h"\r
  22 #include "../phydm_precomp.h"\r
  23 \r
  24 #if (RTL8822B_SUPPORT == 1)  \r
  25 \r
  26 /* ======================================================================== */\r
  27 /* These following functions can be used for PHY DM only*/\r
  28 \r
  29 u4Byte  reg82c_8822b;\r
  30 u4Byte  reg838_8822b;\r
  31 u4Byte  reg830_8822b;\r
  32 u4Byte  reg83c_8822b;\r
  33 u4Byte  rega20_8822b;\r
  34 u4Byte  rega24_8822b;\r
  35 u4Byte  rega28_8822b;\r
  36 ODM_BW_E        bw_8822b;\r
  37 u1Byte  central_ch_8822b;\r
  38 \r
  39 u4Byte  cca_ifem_ccut[12][4] = {\r
  40         /*20M*/\r
  41         {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/\r
  42         {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/\r
  43         {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg838*/\r
  44         {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/\r
  45         /*40M*/                                 \r
  46         {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/\r
  47         {0x00000000, 0x79a0ea28, 0x00000000, 0x79a0ea28}, /*Reg830*/\r
  48         {0x87765541, 0x87766341, 0x87765541, 0x87766341}, /*Reg838*/\r
  49         {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/\r
  50         /*80M*/\r
  51         {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/\r
  52         {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/\r
  53         {0x00000000, 0x87746641, 0x00000000, 0x87746641}, /*Reg838*/\r
  54         {0x00000000, 0x00000000, 0x00000000, 0x00000000}}; /*Reg83C*/\r
  55 u4Byte  cca_efem_ccut[12][4] = {\r
  56         /*20M*/\r
  57         {0x75A76010, 0x75A76010, 0x75A76010, 0x75A75010}, /*Reg82C*/\r
  58         {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/\r
  59         {0x87766651, 0x87766431, 0x87766451, 0x87766431}, /*Reg838*/\r
  60         {0x9194b2b9, 0x9194b2b9, 0x9194b2b9, 0x9194b2b9}, /*Reg83C*/\r
  61         /*40M*/\r
  62         {0x75A85010, 0x75A75010, 0x75A85010, 0x75A75010}, /*Reg82C*/\r
  63         {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/\r
  64         {0x87766431, 0x87766431, 0x87766431, 0x87766431}, /*Reg838*/\r
  65         {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/\r
  66         /*80M*/\r
  67         {0x76BA7010, 0x75BA7010, 0x76BA7010, 0x75BA7010}, /*Reg82C*/\r
  68         {0x79a0ea28, 0x00000000, 0x79a0ea28, 0x00000000}, /*Reg830*/\r
  69         {0x76666641, 0x76666641, 0x76666641, 0x76666641}, /*Reg838*/\r
  70         {0x00000000, 0x00000000, 0x00000000, 0x00000000}}; /*Reg83C*/\r
  71 u4Byte  cca_ifem_ccut_RFTType5[12][4] = {\r
  72         /*20M*/\r
  73         {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/\r
  74         {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/\r
  75         {0x00000000, 0x00000000, 0x87766461, 0x87766461}, /*Reg838*/\r
  76         {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/\r
  77         /*40M*/                                 \r
  78         {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/\r
  79         {0x00000000, 0x79a0ea28, 0x00000000, 0x79a0ea28}, /*Reg830*/\r
  80         {0x87765541, 0x87766341, 0x87765541, 0x87766341}, /*Reg838*/\r
  81         {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/\r
  82         /*80M*/\r
  83         {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/\r
  84         {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/\r
  85         {0x00000000, 0x76666641, 0x00000000, 0x76666641}, /*Reg838*/\r
  86         {0x00000000, 0x00000000, 0x00000000, 0x00000000}}; /*Reg83C*/\r
  87 u4Byte  cca_ifem_ccut_RFTType3[12][4] = {\r
  88         /*20M*/\r
  89         {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/\r
  90         {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/\r
  91         {0x00000000, 0x00000000, 0x87766461, 0x87766461}, /*Reg838*/\r
  92         {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/\r
  93         /*40M*/                                 \r
  94         {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/\r
  95         {0x00000000, 0x79a0ea28, 0x00000000, 0x79a0ea28}, /*Reg830*/\r
  96         {0x87765541, 0x87766341, 0x87765541, 0x87766341}, /*Reg838*/\r
  97         {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/\r
  98         /*80M*/\r
  99         {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/\r
 100         {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/\r
 101         {0x00000000, 0x76666641, 0x00000000, 0x76666641}, /*Reg838*/\r
 102         {0x00000000, 0x00000000, 0x00000000, 0x00000000}}; /*Reg83C*/\r
 103 \r
 104 BOOLEAN\r
 105 phydm_rfe_8822b(\r
 106         IN      PDM_ODM_T                               pDM_Odm,\r
 107         IN      u1Byte                                  channel\r
 108         )\r
 109 {\r
 110         if (pDM_Odm->RFEType == 4) {\r
 111 \r
 112                 /*TRSW  = trsw_forced_BT ? 0x804[0] : (0xCB8[2] ? 0xCB8[0] : trsw_lut); trsw_lut = TXON*/\r
 113                 /*TRSWB = trsw_forced_BT ? (~0x804[0]) : (0xCB8[2] ? 0xCB8[1] : trswb_lut);     trswb_lut = TXON*/\r
 114                 /*trsw_forced_BT = 0x804[1] ? 0 : (~GNT_WL); */\r
 115                 /*ODM_SetBBReg(pDM_Odm, 0x804, (BIT1|BIT0), 0x0);*/\r
 116                 /* Default setting is in PHY parameters */\r
 117         \r
 118                 if (channel <= 14) {\r
 119                         /* signal source */\r
 120                         ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x745774);\r
 121                         ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x745774);\r
 122                         ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x57);\r
 123                         ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x57);\r
 124 \r
 125                         /* inverse or not */\r
 126                         ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x8);\r
 127                         ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT11|BIT10), 0x2);\r
 128                         ODM_SetBBReg(pDM_Odm, 0xebc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x8);\r
 129                         ODM_SetBBReg(pDM_Odm, 0xebc, (BIT11|BIT10), 0x2);\r
 130 \r
 131                         /* antenna switch table */\r
 132                         if ((pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) || (pDM_Odm->TXAntStatus == (ODM_RF_A|ODM_RF_B))) {\r
 133                                 /* 2TX or 2RX */\r
 134                                 ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xf050);\r
 135                                 ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xf050);\r
 136                         } else if (pDM_Odm->RXAntStatus == pDM_Odm->TXAntStatus) {\r
 137                                 /* TXA+RXA or TXB+RXB */\r
 138                                 ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xf055);\r
 139                                 ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xf055);\r
 140                         } else {\r
 141                                 /* TXB+RXA or TXA+RXB */\r
 142                                 ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xf550);\r
 143                                 ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xf550);\r
 144                         }\r
 145                                 \r
 146                 } else if (channel > 35) {\r
 147                         /* signal source */\r
 148                         ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x477547);\r
 149                         ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x477547);\r
 150                         ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x75);\r
 151                         ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x75);\r
 152 \r
 153                         /* inverse or not */\r
 154                         ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0);\r
 155                         ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT11|BIT10), 0x0);\r
 156                         ODM_SetBBReg(pDM_Odm, 0xebc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0);\r
 157                         ODM_SetBBReg(pDM_Odm, 0xebc, (BIT11|BIT10), 0x0);\r
 158 \r
 159                         /* antenna switch table */\r
 160                         if ((pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) || (pDM_Odm->TXAntStatus == (ODM_RF_A|ODM_RF_B))) {\r
 161                                 /* 2TX or 2RX */\r
 162                                 ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa501);\r
 163                                 ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa501);\r
 164                         } else if (pDM_Odm->RXAntStatus == pDM_Odm->TXAntStatus) {\r
 165                                 /* TXA+RXA or TXB+RXB */\r
 166                                 ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa500);\r
 167                                 ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa500);\r
 168                         } else {\r
 169                                 /* TXB+RXA or TXA+RXB */\r
 170                                 ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa005);\r
 171                                 ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa005);\r
 172                         }\r
 173                 } else\r
 174                         return FALSE;\r
 175 \r
 176                 \r
 177         } else {\r
 178                 if (((pDM_Odm->CutVersion == ODM_CUT_A) || (pDM_Odm->CutVersion == ODM_CUT_B)) && (pDM_Odm->RFEType < 2)) {\r
 179                         if (channel <= 14) {\r
 180                                 /* signal source */\r
 181                                 ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x704570);\r
 182                                 ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x704570);\r
 183                                 ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x45);\r
 184                                 ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x45);\r
 185                         } else if (channel > 35) {\r
 186                                 ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x174517);\r
 187                                 ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x174517);\r
 188                                 ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x45);\r
 189                                 ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x45);\r
 190                         } else\r
 191                                 return FALSE;\r
 192 \r
 193                         /* delay 400ns for PAPE */\r
 194                         ODM_SetBBReg(pDM_Odm, 0x810, bMaskByte3|BIT20|BIT21|BIT22|BIT23, 0x211);\r
 195 \r
 196                         /* antenna switch table */\r
 197                         ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa555);\r
 198                         ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa555);\r
 199 \r
 200                         /* inverse or not */\r
 201                         ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0);\r
 202                         ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT11|BIT10), 0x0);\r
 203                         ODM_SetBBReg(pDM_Odm, 0xebc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0);\r
 204                         ODM_SetBBReg(pDM_Odm, 0xebc, (BIT11|BIT10), 0x0);\r
 205 \r
 206                         ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Using old RFE control pin setting for A-cut and B-cut\n", __func__));\r
 207                 } else {\r
 208                         if (channel <= 14) {\r
 209                                 /* signal source */\r
 210                                 ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x745774);\r
 211                                 ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x745774);\r
 212                                 ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x57);\r
 213                                 ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x57);\r
 214                         } else if (channel > 35) {\r
 215                                 /* signal source */\r
 216                                 ODM_SetBBReg(pDM_Odm, 0xcb0, (bMaskByte2|bMaskLWord), 0x477547);\r
 217                                 ODM_SetBBReg(pDM_Odm, 0xeb0, (bMaskByte2|bMaskLWord), 0x477547);\r
 218                                 ODM_SetBBReg(pDM_Odm, 0xcb4, bMaskByte1, 0x75);\r
 219                                 ODM_SetBBReg(pDM_Odm, 0xeb4, bMaskByte1, 0x75);\r
 220                         } else\r
 221                                 return FALSE;\r
 222 \r
 223                         /* inverse or not */\r
 224                         ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0);\r
 225                         ODM_SetBBReg(pDM_Odm, 0xcbc, (BIT11|BIT10), 0x0);\r
 226                         ODM_SetBBReg(pDM_Odm, 0xebc, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x0);\r
 227                         ODM_SetBBReg(pDM_Odm, 0xebc, (BIT11|BIT10), 0x0);\r
 228 \r
 229                         /* delay 400ns for PAPE */\r
 230                         /* ODM_SetBBReg(pDM_Odm, 0x810, bMaskByte3|BIT20|BIT21|BIT22|BIT23, 0x211); */\r
 231 \r
 232                         /* antenna switch table */\r
 233                         if ((pDM_Odm->RXAntStatus == (ODM_RF_A|ODM_RF_B)) || (pDM_Odm->TXAntStatus == (ODM_RF_A|ODM_RF_B))) {\r
 234                                 /* 2TX or 2RX */\r
 235                                 ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa501);\r
 236                                 ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa501);\r
 237                         } else if (pDM_Odm->RXAntStatus == pDM_Odm->TXAntStatus) {\r
 238                                 /* TXA+RXA or TXB+RXB */\r
 239                                 ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa500);\r
 240                                 ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa500);\r
 241                         } else {\r
 242                                 /* TXB+RXA or TXA+RXB */\r
 243                                 ODM_SetBBReg(pDM_Odm, 0xca0, bMaskLWord, 0xa005);\r
 244                                 ODM_SetBBReg(pDM_Odm, 0xea0, bMaskLWord, 0xa005);\r
 245                         }\r
 246                 }\r
 247         }\r
 248         \r
 249         /* chip top mux */\r
 250         ODM_SetBBReg(pDM_Odm, 0x64, BIT29|BIT28, 0x3);\r
 251         ODM_SetBBReg(pDM_Odm, 0x4c, BIT26|BIT25, 0x0);\r
 252         ODM_SetBBReg(pDM_Odm, 0x40, BIT2, 0x1);\r
 253 \r
 254         /* from s0 or s1 */\r
 255         ODM_SetBBReg(pDM_Odm, 0x1990, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x30);\r
 256         ODM_SetBBReg(pDM_Odm, 0x1990, (BIT11|BIT10), 0x3);\r
 257 \r
 258         /* input or output */\r
 259         ODM_SetBBReg(pDM_Odm, 0x974, (BIT5|BIT4|BIT3|BIT2|BIT1|BIT0), 0x3f);\r
 260         ODM_SetBBReg(pDM_Odm, 0x974, (BIT11|BIT10), 0x3);\r
 261 \r
 262         ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Update RFE control pin setting (ch%d, TxPath 0x%x, RxPath 0x%x)\n", __func__, channel, pDM_Odm->TXAntStatus, pDM_Odm->RXAntStatus));\r
 263 \r
 264         return TRUE;\r
 265 }\r
 266 \r
 267 VOID\r
 268 phydm_ccapar_by_rfe_8822b(\r
 269         IN      PDM_ODM_T                               pDM_Odm\r
 270         )\r
 271 {\r
 272 #if !(DM_ODM_SUPPORT_TYPE == ODM_CE)\r
 273         u4Byte  cca_ifem_bcut[12][4] = {\r
 274                 /*20M*/\r
 275                 {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/\r
 276                 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/\r
 277                 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg838*/\r
 278                 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/\r
 279                 /*40M*/                                 \r
 280                 {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/\r
 281                 {0x00000000, 0x79a0ea28, 0x00000000, 0x79a0ea28}, /*Reg830*/\r
 282                 {0x87765541, 0x87766341, 0x87765541, 0x87766341}, /*Reg838*/\r
 283                 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/\r
 284                 /*80M*/\r
 285                 {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/\r
 286                 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/\r
 287                 {0x00000000, 0x87746641, 0x00000000, 0x87746641}, /*Reg838*/\r
 288                 {0x00000000, 0x00000000, 0x00000000, 0x00000000} }; /*Reg83C*/\r
 289         u4Byte  cca_efem_bcut[12][4] = {\r
 290                 /*20M*/\r
 291                 {0x75A76010, 0x75A76010, 0x75A76010, 0x75A75010}, /*Reg82C*/\r
 292                 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/\r
 293                 {0x87766651, 0x87766431, 0x87766451, 0x87766431}, /*Reg838*/\r
 294                 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/\r
 295                 /*40M*/\r
 296                 {0x75A75010, 0x75A75010, 0x75A75010, 0x75A75010}, /*Reg82C*/\r
 297                 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/\r
 298                 {0x87766431, 0x87766431, 0x87766431, 0x87766431}, /*Reg838*/\r
 299                 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/\r
 300                 /*80M*/\r
 301                 {0x75BA7010, 0x75BA7010, 0x75BA7010, 0x75BA7010}, /*Reg82C*/\r
 302                 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/\r
 303                 {0x87766431, 0x87766431, 0x87766431, 0x87766431}, /*Reg838*/\r
 304                 {0x00000000, 0x00000000, 0x00000000, 0x00000000}}; /*Reg83C*/\r
 305 #endif\r
 306 \r
 307         u4Byte  cca_ifem[12][4], cca_efem[12][4];\r
 308         u1Byte  row, col;\r
 309         u4Byte  reg82c, reg830, reg838, reg83c;\r
 310 \r
 311         if (pDM_Odm->CutVersion == ODM_CUT_A)\r
 312                 return;\r
 313 #if !(DM_ODM_SUPPORT_TYPE == ODM_CE)\r
 314         if (pDM_Odm->CutVersion == ODM_CUT_B) {\r
 315                 ODM_MoveMemory(pDM_Odm, cca_efem, cca_efem_bcut, 48*4);\r
 316                 ODM_MoveMemory(pDM_Odm, cca_ifem, cca_ifem_bcut, 48*4);\r
 317                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Update CCA parameters for Bcut\n", __func__));\r
 318         } else\r
 319 #endif\r
 320         {\r
 321                 ODM_MoveMemory(pDM_Odm, cca_efem, cca_efem_ccut, 48*4);\r
 322                 if (pDM_Odm->RFEType == 5) {\r
 323                         ODM_MoveMemory(pDM_Odm, cca_ifem, cca_ifem_ccut_RFTType5, 48*4);\r
 324                 } else if (pDM_Odm->RFEType == 3) {\r
 325                         ODM_MoveMemory(pDM_Odm, cca_ifem, cca_ifem_ccut_RFTType3, 48*4);\r
 326                 } else {\r
 327                 ODM_MoveMemory(pDM_Odm, cca_ifem, cca_ifem_ccut, 48*4);\r
 328                 } ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: Update CCA parameters for Ccut\n", __func__));\r
 329         }       \r
 330 \r
 331         if (bw_8822b == ODM_BW20M)\r
 332                 row = 0;\r
 333         else if (bw_8822b == ODM_BW40M)\r
 334                 row = 4;\r
 335         else\r
 336                 row = 8;\r
 337 \r
 338         if (central_ch_8822b <= 14) {\r
 339                 if ((pDM_Odm->RXAntStatus == ODM_RF_A) || (pDM_Odm->RXAntStatus == ODM_RF_B))\r
 340                         col = 0;\r
 341                 else\r
 342                         col = 1;\r
 343         } else {\r
 344                 if ((pDM_Odm->RXAntStatus == ODM_RF_A) || (pDM_Odm->RXAntStatus == ODM_RF_B))\r
 345                         col = 2;\r
 346                 else\r
 347                         col = 3;\r
 348         }\r
 349 \r
 350         if ((pDM_Odm->RFEType == 1) || (pDM_Odm->RFEType == 4) || (pDM_Odm->RFEType == 6) || (pDM_Odm->RFEType == 7)) {\r
 351                 /*eFEM => RFE type 1 & RFE type 4 & RFE type 6 & RFE type 7*/\r
 352                 reg82c = (cca_efem[row][col] != 0)?cca_efem[row][col]:reg82c_8822b;\r
 353                 reg830 = (cca_efem[row + 1][col] != 0)?cca_efem[row + 1][col]:reg830_8822b;\r
 354                 reg838 = (cca_efem[row + 2][col] != 0)?cca_efem[row + 2][col]:reg838_8822b;\r
 355                 reg83c = (cca_efem[row + 3][col] != 0)?cca_efem[row + 3][col]:reg83c_8822b;\r
 356         } else if ((pDM_Odm->RFEType == 2)||(pDM_Odm->RFEType == 9)) {\r
 357                 /*5G eFEM, 2G iFEM => RFE type 2, 5G eFEM => RFE type 9 */\r
 358                 if (central_ch_8822b <= 14) {\r
 359                         reg82c = (cca_ifem[row][col] != 0)?cca_ifem[row][col]:reg82c_8822b;\r
 360                         reg830 = (cca_ifem[row + 1][col] != 0)?cca_ifem[row + 1][col]:reg830_8822b;\r
 361                         reg838 = (cca_ifem[row + 2][col] != 0)?cca_ifem[row + 2][col]:reg838_8822b;\r
 362                         reg83c = (cca_ifem[row + 3][col] != 0)?cca_ifem[row + 3][col]:reg83c_8822b;\r
 363                 } else {\r
 364                         reg82c = (cca_efem[row][col] != 0)?cca_efem[row][col]:reg82c_8822b;\r
 365                         reg830 = (cca_efem[row + 1][col] != 0)?cca_efem[row + 1][col]:reg830_8822b;\r
 366                         reg838 = (cca_efem[row + 2][col] != 0)?cca_efem[row + 2][col]:reg838_8822b;\r
 367                         reg83c = (cca_efem[row + 3][col] != 0)?cca_efem[row + 3][col]:reg83c_8822b;\r
 368                 }\r
 369         } else {\r
 370                 /*iFEM =>RFE type 0 & RFE type 8*/\r
 371                 reg82c = (cca_ifem[row][col] != 0)?cca_ifem[row][col]:reg82c_8822b;\r
 372                 reg830 = (cca_ifem[row + 1][col] != 0)?cca_ifem[row + 1][col]:reg830_8822b;\r
 373                 reg838 = (cca_ifem[row + 2][col] != 0)?cca_ifem[row + 2][col]:reg838_8822b;\r
 374                 reg83c = (cca_ifem[row + 3][col] != 0)?cca_ifem[row + 3][col]:reg83c_8822b;\r
 375         }\r
 376         \r
 377         ODM_SetBBReg(pDM_Odm, 0x82c, bMaskDWord, reg82c);\r
 378         ODM_SetBBReg(pDM_Odm, 0x830, bMaskDWord, reg830);\r
 379         ODM_SetBBReg(pDM_Odm, 0x838, bMaskDWord, reg838);\r
 380         ODM_SetBBReg(pDM_Odm, 0x83c, bMaskDWord, reg83c);\r
 381         ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: (Pkt%d, Intf%d, RFE%d), row = %d, col = %d\n", \r
 382                 __func__, pDM_Odm->PackageType, pDM_Odm->SupportInterface, pDM_Odm->RFEType, row, col));\r
 383 }\r
 384 \r
 385 VOID\r
 386 phydm_ccapar_by_bw_8822b(\r
 387         IN      PDM_ODM_T                               pDM_Odm,\r
 388         IN      ODM_BW_E                                bandwidth\r
 389         )\r
 390 {\r
 391         u4Byte          reg82c;\r
 392 \r
 393 \r
 394         if (pDM_Odm->CutVersion != ODM_CUT_A)\r
 395                 return;\r
 396 \r
 397         /* A-cut */\r
 398         reg82c = ODM_GetBBReg(pDM_Odm, 0x82c, bMaskDWord);\r
 399 \r
 400         if (bandwidth == ODM_BW20M) {\r
 401                 /* 82c[15:12] = 4 */\r
 402                 /* 82c[27:24] = 6 */\r
 403                 \r
 404                 reg82c &= (~(0x0f00f000));\r
 405                 reg82c |= ((0x4) << 12);\r
 406                 reg82c |= ((0x6) << 24);\r
 407         } else if (bandwidth == ODM_BW40M) {\r
 408                 /* 82c[19:16] = 9 */\r
 409                 /* 82c[27:24] = 6 */\r
 410         \r
 411                 reg82c &= (~(0x0f0f0000));\r
 412                 reg82c |= ((0x9) << 16);\r
 413                 reg82c |= ((0x6) << 24);\r
 414         } else if (bandwidth == ODM_BW80M) {\r
 415                 /* 82c[15:12] 7 */\r
 416                 /* 82c[19:16] b */\r
 417                 /* 82c[23:20] d */\r
 418                 /* 82c[27:24] 3 */\r
 419         \r
 420                 reg82c &= (~(0x0ffff000));\r
 421                 reg82c |= ((0xdb7) << 12);\r
 422                 reg82c |= ((0x3) << 24);\r
 423         }\r
 424 \r
 425         ODM_SetBBReg(pDM_Odm, 0x82c, bMaskDWord, reg82c);\r
 426         ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_CcaParByBw_8822b(): Update CCA parameters for Acut\n"));\r
 427         \r
 428 }\r
 429 \r
 430 VOID\r
 431 phydm_ccapar_by_rxpath_8822b(\r
 432         IN      PDM_ODM_T                               pDM_Odm\r
 433         )\r
 434 {\r
 435 \r
 436         if (pDM_Odm->CutVersion != ODM_CUT_A)\r
 437                 return;\r
 438 \r
 439         if ((pDM_Odm->RXAntStatus == ODM_RF_A) || (pDM_Odm->RXAntStatus == ODM_RF_B)) {\r
 440                 /* 838[7:4] = 8 */\r
 441                 /* 838[11:8] = 7 */\r
 442                 /* 838[15:12] = 6 */\r
 443                 /* 838[19:16] = 7 */\r
 444                 /* 838[23:20] = 7 */\r
 445                 /* 838[27:24] = 7 */\r
 446                 ODM_SetBBReg(pDM_Odm, 0x838, 0x0ffffff0, 0x777678);\r
 447         } else {\r
 448                 /* 838[7:4] = 3 */\r
 449                 /* 838[11:8] = 3 */\r
 450                 /* 838[15:12] = 6 */\r
 451                 /* 838[19:16] = 6 */\r
 452                 /* 838[23:20] = 7 */\r
 453                 /* 838[27:24] = 7 */\r
 454                 ODM_SetBBReg(pDM_Odm, 0x838, 0x0ffffff0, 0x776633);\r
 455         }\r
 456         ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_CcaParByRxPath_8822b(): Update CCA parameters for Acut\n"));\r
 457 \r
 458 }\r
 459 \r
 460 VOID\r
 461 phydm_rxdfirpar_by_bw_8822b(\r
 462         IN      PDM_ODM_T                               pDM_Odm,\r
 463         IN      ODM_BW_E                                bandwidth\r
 464         )\r
 465 {\r
 466         if (bandwidth == ODM_BW40M) {\r
 467                 /* RX DFIR for BW40 */\r
 468                 ODM_SetBBReg(pDM_Odm, 0x948, BIT29|BIT28, 0x1);\r
 469                 ODM_SetBBReg(pDM_Odm, 0x94c, BIT29|BIT28, 0x0);\r
 470                 ODM_SetBBReg(pDM_Odm, 0xc20, BIT31, 0x0);\r
 471                 ODM_SetBBReg(pDM_Odm, 0xe20, BIT31, 0x0);\r
 472         } else if (bandwidth == ODM_BW80M) {\r
 473                 /* RX DFIR for BW80 */\r
 474                 ODM_SetBBReg(pDM_Odm, 0x948, BIT29|BIT28, 0x2);\r
 475                 ODM_SetBBReg(pDM_Odm, 0x94c, BIT29|BIT28, 0x1);\r
 476                 ODM_SetBBReg(pDM_Odm, 0xc20, BIT31, 0x0);\r
 477                 ODM_SetBBReg(pDM_Odm, 0xe20, BIT31, 0x0);\r
 478         } else {\r
 479                 /* RX DFIR for BW20, BW10 and BW5*/\r
 480                 ODM_SetBBReg(pDM_Odm, 0x948, BIT29|BIT28, 0x2);\r
 481                 ODM_SetBBReg(pDM_Odm, 0x94c, BIT29|BIT28, 0x2);\r
 482                 ODM_SetBBReg(pDM_Odm, 0xc20, BIT31, 0x1);\r
 483                 ODM_SetBBReg(pDM_Odm, 0xe20, BIT31, 0x1);\r
 484         }\r
 485 }\r
 486 \r
 487 BOOLEAN\r
 488 phydm_write_txagc_1byte_8822b(\r
 489         IN      PDM_ODM_T                               pDM_Odm,\r
 490         IN      u4Byte                                  PowerIndex,\r
 491         IN      ODM_RF_RADIO_PATH_E             Path,   \r
 492         IN      u1Byte                                  HwRate\r
 493         )\r
 494 {\r
 495         u4Byte  offset_txagc[2] = {0x1d00, 0x1d80};\r
 496         u1Byte  rate_idx = (HwRate & 0xfc), i;\r
 497         u1Byte  rate_offset = (HwRate & 0x3);\r
 498         u4Byte  txagc_content = 0x0;\r
 499 \r
 500         /* For debug command only!!!! */\r
 501 \r
 502         /* Error handling  */\r
 503         if ((Path > ODM_RF_PATH_B) || (HwRate > 0x53)) {\r
 504                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_write_txagc_1byte_8822b(): unsupported path (%d)\n", Path));\r
 505                 return FALSE;\r
 506         }\r
 507 \r
 508         /* For HW limitation, We can't write TXAGC once a byte. */\r
 509         for (i = 0; i < 4; i++) {\r
 510                 if (i != rate_offset)\r
 511                         txagc_content = txagc_content|(config_phydm_read_txagc_8822b(pDM_Odm, Path, rate_idx + i) << (i << 3));\r
 512                 else\r
 513                         txagc_content = txagc_content|((PowerIndex & 0x3f) << (i << 3));\r
 514         }\r
 515         ODM_SetBBReg(pDM_Odm, (offset_txagc[Path] + rate_idx), bMaskDWord, txagc_content);\r
 516 \r
 517         ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_write_txagc_1byte_8822b(): Path-%d Rate index 0x%x (0x%x) = 0x%x\n", \r
 518                 Path, HwRate, (offset_txagc[Path] + HwRate), PowerIndex));\r
 519         return TRUE;\r
 520 }\r
 521 \r
 522 VOID\r
 523 phydm_init_hw_info_by_rfe_type_8822b(\r
 524         IN      PDM_ODM_T                               pDM_Odm\r
 525 )\r
 526 {\r
 527         u2Byte  mask_path_a = 0x0303;\r
 528         u2Byte  mask_path_b = 0x0c0c;\r
 529         /*u2Byte        mask_path_c = 0x3030;*/\r
 530         /*u2Byte        mask_path_d = 0xc0c0;*/\r
 531 \r
 532         pDM_Odm->bInitHwInfoByRfe = FALSE;\r
 533 \r
 534         if ((pDM_Odm->RFEType == 1) || (pDM_Odm->RFEType == 6) || (pDM_Odm->RFEType == 7)) {\r
 535                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA|ODM_BOARD_EXT_LNA_5G|ODM_BOARD_EXT_PA|ODM_BOARD_EXT_PA_5G));\r
 536 \r
 537                 if (pDM_Odm->RFEType == 6) {\r
 538                         ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, (TYPE_GPA1 & (mask_path_a|mask_path_b)));\r
 539                         ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA1 & (mask_path_a|mask_path_b)));\r
 540                         ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, (TYPE_GLNA1 & (mask_path_a|mask_path_b)));\r
 541                         ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA1 & (mask_path_a|mask_path_b)));\r
 542                 } else if (pDM_Odm->RFEType == 7) {\r
 543                         ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, (TYPE_GPA2 & (mask_path_a|mask_path_b)));\r
 544                         ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA2 & (mask_path_a|mask_path_b)));\r
 545                         ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, (TYPE_GLNA2 & (mask_path_a|mask_path_b)));\r
 546                         ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA2 & (mask_path_a|mask_path_b)));\r
 547                 } else {\r
 548                         ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, (TYPE_GPA0 & (mask_path_a|mask_path_b)));\r
 549                         ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA0 & (mask_path_a|mask_path_b)));\r
 550                         ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, (TYPE_GLNA0 & (mask_path_a|mask_path_b)));\r
 551                         ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a|mask_path_b)));\r
 552                 }\r
 553 \r
 554                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 1);\r
 555                 \r
 556                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, TRUE);\r
 557                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, TRUE);\r
 558                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, TRUE);\r
 559                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, TRUE);\r
 560         } else if (pDM_Odm->RFEType == 2) {\r
 561                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA_5G|ODM_BOARD_EXT_PA_5G));\r
 562                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA0 & (mask_path_a|mask_path_b)));     \r
 563                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a|mask_path_b)));   \r
 564                 \r
 565                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 2);\r
 566                 \r
 567                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE);\r
 568                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, TRUE);\r
 569                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE);\r
 570                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, TRUE);\r
 571         } else if (pDM_Odm->RFEType == 9) {\r
 572                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA_5G));\r
 573                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a|mask_path_b)));   \r
 574                 \r
 575                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 1);\r
 576                 \r
 577                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE);\r
 578                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, TRUE);\r
 579                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE);\r
 580                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, FALSE);\r
 581         } else if ((pDM_Odm->RFEType == 3) || (pDM_Odm->RFEType == 5)) {\r
 582                 /* RFE type 3: 8822BS\8822BU TFBGA iFEM */\r
 583                 /* RFE type 5: 8822BE TFBGA iFEM */\r
 584                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, 0);\r
 585                 \r
 586                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 2);\r
 587                 \r
 588                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE);\r
 589                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, FALSE);\r
 590                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE);\r
 591                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, FALSE);\r
 592         } else if (pDM_Odm->RFEType == 4) {\r
 593                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, (ODM_BOARD_EXT_LNA|ODM_BOARD_EXT_LNA_5G|ODM_BOARD_EXT_PA|ODM_BOARD_EXT_PA_5G));\r
 594                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, (TYPE_GPA0 & (mask_path_a|mask_path_b)));\r
 595                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, (TYPE_APA0 & (mask_path_a|mask_path_b)));\r
 596                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, (TYPE_GLNA0 & (mask_path_a|mask_path_b)));\r
 597                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, (TYPE_ALNA0 & (mask_path_a|mask_path_b)));   \r
 598 \r
 599                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 2);\r
 600                 \r
 601                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, TRUE);\r
 602                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, TRUE);\r
 603                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, TRUE);\r
 604                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, TRUE);\r
 605         } else if (pDM_Odm->RFEType == 8) {\r
 606                 /* RFE Type 8: TFBGA iFEM AP */\r
 607                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, 0);\r
 608                 \r
 609                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 2);\r
 610                 \r
 611                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE);\r
 612                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, FALSE);\r
 613                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE);\r
 614                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, FALSE);\r
 615         } else {\r
 616                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, 0);\r
 617                 \r
 618                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, 1);\r
 619                 \r
 620                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, FALSE);\r
 621                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, FALSE);\r
 622                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, FALSE);\r
 623                 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, FALSE);\r
 624         }\r
 625 \r
 626         pDM_Odm->bInitHwInfoByRfe = TRUE;\r
 627 \r
 628         ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_init_hw_info_by_rfe_type_8822b(): RFE type (%d), Board type (0x%x), Package type (%d)\n", pDM_Odm->RFEType, pDM_Odm->BoardType, pDM_Odm->PackageType));\r
 629         ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_init_hw_info_by_rfe_type_8822b(): 5G ePA (%d), 5G eLNA (%d), 2G ePA (%d), 2G eLNA (%d)\n", pDM_Odm->ExtPA5G, pDM_Odm->ExtLNA5G, pDM_Odm->ExtPA, pDM_Odm->ExtLNA));\r
 630         ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("phydm_init_hw_info_by_rfe_type_8822b(): 5G PA type (%d), 5G LNA type (%d), 2G PA type (%d), 2G LNA type (%d)\n", pDM_Odm->TypeAPA, pDM_Odm->TypeALNA, pDM_Odm->TypeGPA, pDM_Odm->TypeGLNA));\r
 631 }\r
 632 \r
 633 s4Byte\r
 634 phydm_get_condition_number_8822B(\r
 635         IN      PDM_ODM_T                               pDM_Odm\r
 636 )\r
 637 {\r
 638         s4Byte  ret_val;\r
 639 \r
 640         ODM_SetBBReg( pDM_Odm, 0x1988, BIT22, 0x1);\r
 641         ret_val = (s4Byte)ODM_GetBBReg(pDM_Odm, 0xf84, (BIT17|BIT16|bMaskLWord));\r
 642 \r
 643         if (bw_8822b == 0) {\r
 644                 ret_val = ret_val << (8 - 4);\r
 645                 ret_val = ret_val / 234;\r
 646         } else if (bw_8822b == 1) {\r
 647                 ret_val = ret_val << (7 - 4);\r
 648                 ret_val = ret_val / 108;\r
 649         } else if (bw_8822b == 2) {\r
 650                 ret_val = ret_val << (6 - 4);\r
 651                 ret_val = ret_val / 52;\r
 652         }\r
 653         \r
 654         return ret_val;\r
 655 }\r
 656 \r
 657 \r
 658 /* ======================================================================== */\r
 659 \r
 660 /* ======================================================================== */\r
 661 /* These following functions can be used by driver*/\r
 662 \r
 663 u4Byte\r
 664 config_phydm_read_rf_reg_8822b(\r
 665         IN      PDM_ODM_T                               pDM_Odm,\r
 666         IN      ODM_RF_RADIO_PATH_E             RFPath,\r
 667         IN      u4Byte                                  RegAddr,\r
 668         IN      u4Byte                                  BitMask\r
 669         )\r
 670 {\r
 671         u4Byte  Readback_Value, Direct_Addr;\r
 672         u4Byte  offset_readRF[2] = {0x2800, 0x2c00};\r
 673         u4Byte  power_RF[2] = {0x1c, 0xec};\r
 674 \r
 675         /* Error handling.*/\r
 676         if (RFPath > ODM_RF_PATH_B) {\r
 677                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_rf_reg_8822b(): unsupported path (%d)\n", RFPath));\r
 678                 return INVALID_RF_DATA;\r
 679         }\r
 680 \r
 681         /*  Error handling. Check if RF power is enable or not */\r
 682         /*  0xffffffff means RF power is disable */\r
 683         if (ODM_GetMACReg(pDM_Odm, power_RF[RFPath], bMaskByte3) != 0x7) {\r
 684                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_rf_reg_8822b(): Read fail, RF is disabled\n"));\r
 685                 return INVALID_RF_DATA;\r
 686         }\r
 687 \r
 688         /* Calculate offset */\r
 689         RegAddr &= 0xff;\r
 690         Direct_Addr = offset_readRF[RFPath] + (RegAddr << 2);\r
 691 \r
 692         /* RF register only has 20bits */\r
 693         BitMask &= bRFRegOffsetMask;\r
 694 \r
 695         /* Read RF register directly */\r
 696         Readback_Value = ODM_GetBBReg(pDM_Odm, Direct_Addr, BitMask);\r
 697         ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_rf_reg_8822b(): RF-%d 0x%x = 0x%x, bit mask = 0x%x\n", \r
 698                 RFPath, RegAddr, Readback_Value, BitMask));\r
 699         return Readback_Value;\r
 700 }\r
 701 \r
 702 BOOLEAN\r
 703 config_phydm_write_rf_reg_8822b(\r
 704         IN      PDM_ODM_T                               pDM_Odm,\r
 705         IN      ODM_RF_RADIO_PATH_E             RFPath,\r
 706         IN      u4Byte                                  RegAddr,\r
 707         IN      u4Byte                                  BitMask,\r
 708         IN      u4Byte                                  Data\r
 709         )\r
 710 {\r
 711         u4Byte  DataAndAddr = 0, Data_original = 0;\r
 712         u4Byte  offset_writeRF[2] = {0xc90, 0xe90};\r
 713         u4Byte  power_RF[2] = {0x1c, 0xec};\r
 714         u1Byte  BitShift;\r
 715 \r
 716         /* Error handling.*/\r
 717         if (RFPath > ODM_RF_PATH_B) {\r
 718                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8822b(): unsupported path (%d)\n", RFPath));\r
 719                 return FALSE;\r
 720         }\r
 721 \r
 722         /* Read RF register content first */\r
 723         RegAddr &= 0xff;\r
 724         BitMask = BitMask & bRFRegOffsetMask;\r
 725 \r
 726         if (BitMask != bRFRegOffsetMask) {\r
 727                 Data_original = config_phydm_read_rf_reg_8822b(pDM_Odm, RFPath, RegAddr, bRFRegOffsetMask);\r
 728 \r
 729                 /* Error handling. RF is disabled */\r
 730                 if (config_phydm_read_rf_check_8822b(Data_original) == FALSE) {\r
 731                         ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8822b(): Write fail, RF is disable\n"));\r
 732                         return FALSE;\r
 733                 }\r
 734 \r
 735                 /* check bit mask */\r
 736                 if (BitMask != 0xfffff) {\r
 737                         for (BitShift = 0; BitShift <= 19; BitShift++) {\r
 738                                 if (((BitMask >> BitShift) & 0x1) == 1)\r
 739                                         break;\r
 740                         }\r
 741                         Data = ((Data_original) & (~BitMask)) | (Data << BitShift);\r
 742                 }\r
 743         } else if (ODM_GetMACReg(pDM_Odm, power_RF[RFPath], bMaskByte3) != 0x7) {\r
 744                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8822b(): Write fail, RF is disabled\n"));\r
 745                 return FALSE;\r
 746         }\r
 747 \r
 748         /* Put write addr in [27:20]  and write data in [19:00] */\r
 749         DataAndAddr = ((RegAddr<<20) | (Data&0x000fffff)) & 0x0fffffff; \r
 750 \r
 751         /* Write Operation */\r
 752         ODM_SetBBReg(pDM_Odm, offset_writeRF[RFPath], bMaskDWord, DataAndAddr);\r
 753         ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_rf_reg_8822b(): RF-%d 0x%x = 0x%x (original: 0x%x), bit mask = 0x%x\n", \r
 754                 RFPath, RegAddr, Data, Data_original, BitMask));\r
 755         return TRUE;\r
 756 }\r
 757 \r
 758 BOOLEAN\r
 759 config_phydm_write_txagc_8822b(\r
 760         IN      PDM_ODM_T                               pDM_Odm,\r
 761         IN      u4Byte                                  PowerIndex,\r
 762         IN      ODM_RF_RADIO_PATH_E             Path,   \r
 763         IN      u1Byte                                  HwRate\r
 764         )\r
 765 {\r
 766         u4Byte  offset_txagc[2] = {0x1d00, 0x1d80};\r
 767         u1Byte  rate_idx = (HwRate & 0xfc);\r
 768 \r
 769         /* Input need to be HW rate index, not driver rate index!!!! */\r
 770 \r
 771         if (pDM_Odm->bDisablePhyApi) {\r
 772                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_txagc_8822b(): disable PHY API for debug!!\n"));\r
 773                 return TRUE;\r
 774         }\r
 775 \r
 776         /* Error handling  */\r
 777         if ((Path > ODM_RF_PATH_B) || (HwRate > 0x53)) {\r
 778                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_txagc_8822b(): unsupported path (%d)\n", Path));\r
 779                 return FALSE;\r
 780         }\r
 781 \r
 782         /* driver need to construct a 4-byte power index */\r
 783         ODM_SetBBReg(pDM_Odm, (offset_txagc[Path] + rate_idx), bMaskDWord, PowerIndex);\r
 784 \r
 785         ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_write_txagc_8822b(): Path-%d Rate index 0x%x (0x%x) = 0x%x\n", \r
 786                 Path, HwRate, (offset_txagc[Path] + HwRate), PowerIndex));\r
 787         return TRUE;\r
 788 }\r
 789 \r
 790 u1Byte\r
 791 config_phydm_read_txagc_8822b(\r
 792         IN      PDM_ODM_T                               pDM_Odm,\r
 793         IN      ODM_RF_RADIO_PATH_E             Path,\r
 794         IN      u1Byte                                  HwRate\r
 795         )\r
 796 {\r
 797         u1Byte  readBack_data;\r
 798 \r
 799         /* Input need to be HW rate index, not driver rate index!!!! */\r
 800 \r
 801         /* Error handling  */\r
 802         if ((Path > ODM_RF_PATH_B) || (HwRate > 0x53)) {\r
 803                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_txagc_8822b(): unsupported path (%d)\n", Path));\r
 804                 return INVALID_TXAGC_DATA;\r
 805         }\r
 806 \r
 807         /* Disable TX AGC report */\r
 808         ODM_SetBBReg(pDM_Odm, 0x1998, BIT16, 0x0);                                                      /* need to check */\r
 809 \r
 810         /* Set data rate index (bit0~6) and path index (bit7) */\r
 811         ODM_SetBBReg(pDM_Odm, 0x1998, bMaskByte0, (HwRate|(Path << 7)));\r
 812 \r
 813         /* Enable TXAGC report */\r
 814         ODM_SetBBReg(pDM_Odm, 0x1998, BIT16, 0x1);\r
 815 \r
 816         /* Read TX AGC report */\r
 817         readBack_data = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xd30, 0x7f0000);\r
 818 \r
 819         /* Driver have to disable TXAGC report after reading TXAGC (ref. user guide v11) */\r
 820         ODM_SetBBReg(pDM_Odm, 0x1998, BIT16, 0x0);      \r
 821         \r
 822         ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_read_txagc_8822b(): Path-%d rate index 0x%x = 0x%x\n", Path, HwRate, readBack_data));\r
 823         return readBack_data;\r
 824 }\r
 825 \r
 826 BOOLEAN\r
 827 config_phydm_switch_band_8822b( \r
 828         IN      PDM_ODM_T                               pDM_Odm,\r
 829         IN      u1Byte                                  central_ch\r
 830         )\r
 831 {\r
 832         u4Byte          rf_reg18;\r
 833         BOOLEAN         rf_reg_status = TRUE;\r
 834 \r
 835         ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b()======================>\n"));    \r
 836 \r
 837         if (pDM_Odm->bDisablePhyApi) {\r
 838                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b(): disable PHY API for debug!!\n"));\r
 839                 return TRUE;\r
 840         }\r
 841 \r
 842         rf_reg18 = config_phydm_read_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask);\r
 843         rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18);\r
 844 \r
 845         if (central_ch <= 14) {\r
 846                 /* 2.4G */\r
 847 \r
 848                 /* Enable CCK block */\r
 849                 ODM_SetBBReg(pDM_Odm, 0x808, BIT28, 0x1);\r
 850 \r
 851                 /* Disable MAC CCK check */\r
 852                 ODM_SetBBReg(pDM_Odm, 0x454, BIT7, 0x0);\r
 853 \r
 854                 /* Disable BB CCK check */\r
 855                 ODM_SetBBReg(pDM_Odm, 0xa80, BIT18, 0x0);\r
 856 \r
 857                 /*CCA Mask*/\r
 858                 ODM_SetBBReg(pDM_Odm, 0x814, 0x0000FC00, 15); /*default value*/\r
 859 \r
 860                 /* RF band */\r
 861                 rf_reg18 = (rf_reg18 & (~(BIT16|BIT9|BIT8)));\r
 862         } else if (central_ch > 35) {\r
 863                 /* 5G */\r
 864 \r
 865                 /* Enable BB CCK check */\r
 866                 ODM_SetBBReg(pDM_Odm, 0xa80, BIT18, 0x1);\r
 867                 \r
 868                 /* Enable CCK check */\r
 869                 ODM_SetBBReg(pDM_Odm, 0x454, BIT7, 0x1);\r
 870 \r
 871                 /* Disable CCK block */\r
 872                 ODM_SetBBReg(pDM_Odm, 0x808, BIT28, 0x0);\r
 873 \r
 874                 /*CCA Mask*/\r
 875                 ODM_SetBBReg(pDM_Odm, 0x814, 0x0000FC00, 15); /*default value*/\r
 876                 //ODM_SetBBReg(pDM_Odm, 0x814, 0x0000FC00, 34); /*CCA mask = 13.6us*/\r
 877 \r
 878                 /* RF band */\r
 879                 rf_reg18 = (rf_reg18 & (~(BIT16|BIT9|BIT8)));\r
 880                 rf_reg18 = (rf_reg18|BIT8|BIT16);\r
 881         } else {\r
 882                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b(): Fail to switch band (ch: %d)\n", central_ch));\r
 883                 return FALSE;\r
 884         }\r
 885 \r
 886         rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask, rf_reg18);\r
 887 \r
 888         if (pDM_Odm->RFType > ODM_1T1R)\r
 889                 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_B, 0x18, bRFRegOffsetMask, rf_reg18);\r
 890 \r
 891         if (phydm_rfe_8822b(pDM_Odm, central_ch) == FALSE)\r
 892                 return FALSE;\r
 893 \r
 894         if (rf_reg_status == FALSE) {\r
 895                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b(): Fail to switch band (ch: %d), because writing RF register is fail\n", central_ch));    \r
 896                 return FALSE;\r
 897         }\r
 898 \r
 899         ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_band_8822b(): Success to switch band (ch: %d)\n", central_ch));      \r
 900         return TRUE;\r
 901 }\r
 902 \r
 903 BOOLEAN\r
 904 config_phydm_switch_channel_8822b(      \r
 905         IN      PDM_ODM_T                               pDM_Odm,\r
 906         IN      u1Byte                                  central_ch\r
 907         )\r
 908 {\r
 909         pDIG_T          pDM_DigTable = &pDM_Odm->DM_DigTable;\r
 910         u4Byte          rf_reg18 = 0, rf_regB8 = 0, rf_regBE = 0xff;\r
 911         BOOLEAN         rf_reg_status = TRUE;\r
 912         u1Byte          low_band[15] = {0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7, 0xff, 0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6};\r
 913         u1Byte          middle_band[23] = {0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6, 0xff, 0x0, 0x0, 0x7, 0x6, 0x6, 0x5, 0x0, 0xff, 0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7};\r
 914         u1Byte          high_band[15] = {0x5, 0x5, 0x0, 0x7, 0x7, 0x6, 0x5, 0xff, 0x0, 0x7, 0x7, 0x6, 0x5, 0x5, 0x0};\r
 915 \r
 916         ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b()====================>\n"));\r
 917 \r
 918         if (pDM_Odm->bDisablePhyApi) {\r
 919                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): disable PHY API for debug!!\n"));\r
 920                 return TRUE;\r
 921         }\r
 922 \r
 923         central_ch_8822b = central_ch;\r
 924         rf_reg18 = config_phydm_read_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask);\r
 925         rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18);\r
 926         rf_reg18 = (rf_reg18 & (~(BIT18|BIT17|bMaskByte0)));\r
 927 \r
 928         if (pDM_Odm->CutVersion == ODM_CUT_A) {\r
 929                 rf_regB8 = config_phydm_read_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xb8, bRFRegOffsetMask);\r
 930                 rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8822b(rf_regB8);\r
 931         }\r
 932 \r
 933         /* Switch band and channel */\r
 934         if (central_ch <= 14) {\r
 935                 /* 2.4G */\r
 936 \r
 937                 /* 1. RF band and channel*/\r
 938                 rf_reg18 = (rf_reg18|central_ch);\r
 939 \r
 940                 /* 2. AGC table selection */\r
 941                 ODM_SetBBReg(pDM_Odm, 0x958, 0x1f, 0x0);\r
 942                 pDM_DigTable->agcTableIdx = 0x0;\r
 943 \r
 944                 /* 3. Set central frequency for clock offset tracking */\r
 945                 ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x96a);\r
 946 \r
 947                 /* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */\r
 948                 if (pDM_Odm->CutVersion == ODM_CUT_A)\r
 949                         rf_regB8 = rf_regB8 | BIT19;\r
 950 \r
 951                 /* CCK TX filter parameters */\r
 952                 if (central_ch == 14) {\r
 953                         ODM_SetBBReg(pDM_Odm, 0xa20, bMaskHWord, 0x8488);\r
 954                         ODM_SetBBReg(pDM_Odm, 0xa24, bMaskDWord, 0x00006577);\r
 955                         ODM_SetBBReg(pDM_Odm, 0xa28, bMaskLWord, 0x0000);\r
 956                 } else {\r
 957                         ODM_SetBBReg(pDM_Odm, 0xa20, bMaskHWord, (rega20_8822b>>16));\r
 958                         ODM_SetBBReg(pDM_Odm, 0xa24, bMaskDWord, rega24_8822b);\r
 959                         ODM_SetBBReg(pDM_Odm, 0xa28, bMaskLWord, (rega28_8822b & bMaskLWord));\r
 960                 }\r
 961 \r
 962         } else if (central_ch > 35) {\r
 963                 /* 5G */\r
 964 \r
 965                 /* 1. RF band and channel*/\r
 966                 rf_reg18 = (rf_reg18 | central_ch);\r
 967 \r
 968                 /* 2. AGC table selection */\r
 969                 if ((central_ch >= 36) && (central_ch <= 64)) {\r
 970                         ODM_SetBBReg(pDM_Odm, 0x958, 0x1f, 0x1);\r
 971                         pDM_DigTable->agcTableIdx = 0x1;\r
 972                 } else if ((central_ch >= 100) && (central_ch <= 144)) {\r
 973                         ODM_SetBBReg(pDM_Odm, 0x958, 0x1f, 0x2);\r
 974                         pDM_DigTable->agcTableIdx = 0x2;\r
 975                 } else if (central_ch >= 149) {\r
 976                         ODM_SetBBReg(pDM_Odm, 0x958, 0x1f, 0x3);\r
 977                         pDM_DigTable->agcTableIdx = 0x3;\r
 978                 } else {\r
 979                         ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (AGC) (ch: %d)\n", central_ch));\r
 980                         return FALSE;\r
 981                 }\r
 982 \r
 983                 /* 3. Set central frequency for clock offset tracking */\r
 984                 if ((central_ch >= 36) && (central_ch <= 48))\r
 985                         ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x494);\r
 986                 else if ((central_ch >= 52) && (central_ch <= 64))\r
 987                         ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x453);\r
 988                 else if ((central_ch >= 100) && (central_ch <= 116))\r
 989                         ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x452);\r
 990                 else if ((central_ch >= 118) && (central_ch <= 177))\r
 991                         ODM_SetBBReg(pDM_Odm, 0x860, 0x1ffe0000, 0x412);\r
 992                 else {\r
 993                         ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (fc_area) (ch: %d)\n", central_ch));\r
 994                         return FALSE;\r
 995                 }\r
 996 \r
 997                 /* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */\r
 998                 if (pDM_Odm->CutVersion == ODM_CUT_A) {\r
 999                         if ((central_ch >= 57) && (central_ch <= 75))\r
1000                                 rf_regB8 = rf_regB8 & (~BIT19);\r
1001                         else\r
1002                                 rf_regB8 = rf_regB8 | BIT19;\r
1003                 }\r
1004         } else {\r
1005                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (ch: %d)\n", central_ch));\r
1006                 return FALSE;\r
1007         }\r
1008 \r
1009         /* Modify IGI for MP driver to aviod PCIE interference */\r
1010         if ((pDM_Odm->mp_mode == TRUE) && ((pDM_Odm->RFEType == 3) || (pDM_Odm->RFEType == 5))) {\r
1011                 if (central_ch == 14)\r
1012                         ODM_Write_DIG(pDM_Odm, 0x26);\r
1013                 else\r
1014                         ODM_Write_DIG(pDM_Odm, 0x20);\r
1015         }\r
1016 \r
1017         /* Modify the setting of register 0xBE to reduce phase noise */\r
1018         if (central_ch <= 14)\r
1019                 rf_regBE = 0x0;\r
1020         else if ((central_ch >= 36) && (central_ch <= 64))\r
1021                 rf_regBE = low_band[(central_ch - 36)>>1];\r
1022         else if ((central_ch >= 100) && (central_ch <= 144))\r
1023                 rf_regBE = middle_band[(central_ch - 100)>>1];\r
1024         else if ((central_ch >= 149) && (central_ch <= 177))\r
1025                 rf_regBE = high_band[(central_ch - 149)>>1];\r
1026         else\r
1027                 rf_regBE = 0xff;\r
1028 \r
1029         if (rf_regBE != 0xff)\r
1030                 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xbe, (BIT17|BIT16|BIT15), rf_regBE);\r
1031         else {\r
1032                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (ch: %d, Phase noise)\n", central_ch));\r
1033                 return FALSE;\r
1034         }\r
1035 \r
1036         /* Fix channel 144 issue, ask by RFSI Alvin*/\r
1037         /* 00 when freq < 5400;  01 when 5400<=freq<=5720; 10 when freq > 5720; 2G don't care*/\r
1038         /* need to set 0xdf[18]=1 before writing RF18 when channel 144 */\r
1039         if (central_ch == 144) {\r
1040                 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xdf, BIT18, 0x1);\r
1041                 rf_reg18 = (rf_reg18 | BIT17);\r
1042         } else {\r
1043                 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xdf, BIT18, 0x0);\r
1044 \r
1045                 if (central_ch > 144)\r
1046                         rf_reg18 = (rf_reg18 | BIT18);\r
1047                 else if (central_ch >= 80)\r
1048                         rf_reg18 = (rf_reg18 | BIT17);\r
1049         }\r
1050 \r
1051         rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask, rf_reg18);\r
1052 \r
1053         if (pDM_Odm->CutVersion == ODM_CUT_A)\r
1054                 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xb8, bRFRegOffsetMask, rf_regB8);\r
1055 \r
1056         if (pDM_Odm->RFType > ODM_1T1R) {\r
1057                 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_B, 0x18, bRFRegOffsetMask, rf_reg18);\r
1058 \r
1059                 if (pDM_Odm->CutVersion == ODM_CUT_A)\r
1060                         rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_B, 0xb8, bRFRegOffsetMask, rf_regB8);\r
1061         }\r
1062 \r
1063         if (rf_reg_status == FALSE) {\r
1064                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Fail to switch channel (ch: %d), because writing RF register is fail\n", central_ch));\r
1065                 return FALSE;\r
1066         }\r
1067 \r
1068         phydm_ccapar_by_rfe_8822b(pDM_Odm);\r
1069         ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_channel_8822b(): Success to switch channel (ch: %d)\n", central_ch));\r
1070         return TRUE;\r
1071 }\r
1072 \r
1073 BOOLEAN\r
1074 config_phydm_switch_bandwidth_8822b(    \r
1075         IN      PDM_ODM_T                               pDM_Odm,\r
1076         IN      u1Byte                                  primary_ch_idx,\r
1077         IN      ODM_BW_E                                bandwidth\r
1078         )\r
1079 {\r
1080         u4Byte          rf_reg18;\r
1081         u1Byte          IGI;\r
1082         BOOLEAN         rf_reg_status = TRUE;\r
1083 \r
1084         ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b()===================>\n"));\r
1085 \r
1086         if (pDM_Odm->bDisablePhyApi) {\r
1087                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): disable PHY API for debug!!\n"));\r
1088                 return TRUE;\r
1089         }\r
1090 \r
1091         /* Error handling  */\r
1092         if ((bandwidth >= ODM_BW_MAX) || ((bandwidth == ODM_BW40M) && (primary_ch_idx > 2)) || ((bandwidth == ODM_BW80M) && (primary_ch_idx > 4))) {\r
1093                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): Fail to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx));\r
1094                 return FALSE;\r
1095         }\r
1096 \r
1097         bw_8822b = bandwidth;\r
1098         rf_reg18 = config_phydm_read_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask);\r
1099         rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18);\r
1100 \r
1101         /* Switch bandwidth */\r
1102         switch (bandwidth) {\r
1103         case ODM_BW20M:\r
1104         {\r
1105                 /* Small BW([7:6]) = 0, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */\r
1106                 ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, ODM_BW20M);\r
1107 \r
1108                 /* ADC clock = 160M clock for BW20 */\r
1109                 ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT9|BIT8), 0x0);\r
1110                 ODM_SetBBReg(pDM_Odm, 0x8ac, BIT16, 0x1);\r
1111 \r
1112                 /* DAC clock = 160M clock for BW20 */\r
1113                 ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT21|BIT20), 0x0);\r
1114                 ODM_SetBBReg(pDM_Odm, 0x8ac, BIT28, 0x1);\r
1115 \r
1116                 /* ADC buffer clock */\r
1117                 ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x1);\r
1118 \r
1119                 /* RF bandwidth */\r
1120                 rf_reg18 = (rf_reg18 | BIT11 | BIT10);\r
1121 \r
1122                 break;\r
1123         }\r
1124         case ODM_BW40M:\r
1125         {\r
1126                 /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel, rf mode([1:0]) = 40M */\r
1127                 ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, (((primary_ch_idx & 0xf) << 2)|ODM_BW40M));\r
1128 \r
1129                 /* CCK primary channel */\r
1130                 if (primary_ch_idx == 1)\r
1131                         ODM_SetBBReg(pDM_Odm, 0xa00, BIT4, primary_ch_idx);\r
1132                 else\r
1133                         ODM_SetBBReg(pDM_Odm, 0xa00, BIT4, 0);\r
1134 \r
1135                 /* ADC clock = 160M clock for BW40 */\r
1136                 ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT11|BIT10), 0x0);\r
1137                 ODM_SetBBReg(pDM_Odm, 0x8ac, BIT17, 0x1);\r
1138 \r
1139                 /* DAC clock = 160M clock for BW20 */\r
1140                 ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT23|BIT22), 0x0);\r
1141                 ODM_SetBBReg(pDM_Odm, 0x8ac, BIT29, 0x1);\r
1142 \r
1143                 /* ADC buffer clock */\r
1144                 ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x1);\r
1145 \r
1146                 /* RF bandwidth */\r
1147                 rf_reg18 = (rf_reg18 & (~(BIT11|BIT10)));\r
1148                 rf_reg18 = (rf_reg18|BIT11);            \r
1149 \r
1150                 break;\r
1151         }\r
1152         case ODM_BW80M:\r
1153         {\r
1154                 /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel, rf mode([1:0]) = 80M */\r
1155                 ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, (((primary_ch_idx & 0xf) << 2)|ODM_BW80M));\r
1156 \r
1157                 /* ADC clock = 160M clock for BW80 */\r
1158                 ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT13|BIT12), 0x0);\r
1159                 ODM_SetBBReg(pDM_Odm, 0x8ac, BIT18, 0x1);\r
1160 \r
1161                 /* DAC clock = 160M clock for BW20 */\r
1162                 ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT25|BIT24), 0x0);\r
1163                 ODM_SetBBReg(pDM_Odm, 0x8ac, BIT30, 0x1);\r
1164 \r
1165                 /* ADC buffer clock */\r
1166                 ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x1);\r
1167 \r
1168                 /* RF bandwidth */\r
1169                 rf_reg18 = (rf_reg18 & (~(BIT11|BIT10)));\r
1170                 rf_reg18 = (rf_reg18|BIT10);\r
1171 \r
1172                 break;\r
1173         }\r
1174         case ODM_BW5M:\r
1175         {\r
1176                 /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */\r
1177                 ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, (BIT6|ODM_BW20M));\r
1178 \r
1179                 /* ADC clock = 40M clock */\r
1180                 ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT9|BIT8), 0x2);\r
1181                 ODM_SetBBReg(pDM_Odm, 0x8ac, BIT16, 0x0);\r
1182 \r
1183                 /* DAC clock = 160M clock for BW20 */\r
1184                 ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT21|BIT20), 0x2);\r
1185                 ODM_SetBBReg(pDM_Odm, 0x8ac, BIT28, 0x0);\r
1186 \r
1187                 /* ADC buffer clock */\r
1188                 ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x0);\r
1189                 ODM_SetBBReg(pDM_Odm, 0x8c8, BIT31, 0x1);\r
1190 \r
1191                 /* RF bandwidth */\r
1192                 rf_reg18 = (rf_reg18|BIT11|BIT10);\r
1193 \r
1194                 break;\r
1195         }\r
1196         case ODM_BW10M:\r
1197         {\r
1198                 /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */\r
1199                 ODM_SetBBReg(pDM_Odm, 0x8ac, bMaskByte0, (BIT7|ODM_BW20M));\r
1200 \r
1201                 /* ADC clock = 80M clock */\r
1202                 ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT9|BIT8), 0x3);\r
1203                 ODM_SetBBReg(pDM_Odm, 0x8ac, BIT16, 0x0);\r
1204 \r
1205                 /* DAC clock = 160M clock for BW20 */\r
1206                 ODM_SetBBReg(pDM_Odm, 0x8ac, (BIT21|BIT20), 0x3);\r
1207                 ODM_SetBBReg(pDM_Odm, 0x8ac, BIT28, 0x0);\r
1208 \r
1209                 /* ADC buffer clock */\r
1210                 ODM_SetBBReg(pDM_Odm, 0x8c4, BIT30, 0x0);\r
1211                 ODM_SetBBReg(pDM_Odm, 0x8c8, BIT31, 0x1);\r
1212 \r
1213                 /* RF bandwidth */\r
1214                 rf_reg18 = (rf_reg18|BIT11|BIT10);\r
1215 \r
1216                 break;\r
1217         }\r
1218         default:\r
1219                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): Fail to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx));\r
1220         }\r
1221 \r
1222         /* Write RF register */\r
1223         rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask, rf_reg18);\r
1224 \r
1225         if (pDM_Odm->RFType > ODM_1T1R)\r
1226                 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_B, 0x18, bRFRegOffsetMask, rf_reg18);\r
1227 \r
1228         if (rf_reg_status == FALSE) {\r
1229                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): Fail to switch bandwidth (bw: %d, primary ch: %d), because writing RF register is fail\n", bandwidth, primary_ch_idx));\r
1230                 return FALSE;\r
1231         }\r
1232 \r
1233         /* Modify RX DFIR parameters */\r
1234         phydm_rxdfirpar_by_bw_8822b(pDM_Odm, bandwidth);\r
1235 \r
1236         /* Modify CCA parameters */\r
1237         phydm_ccapar_by_bw_8822b(pDM_Odm, bandwidth);\r
1238         phydm_ccapar_by_rfe_8822b(pDM_Odm);\r
1239 \r
1240         /* Toggle RX path to avoid RX dead zone issue */\r
1241         ODM_SetBBReg(pDM_Odm, 0x808, bMaskByte0, 0x0);\r
1242         ODM_SetBBReg(pDM_Odm, 0x808, bMaskByte0, (pDM_Odm->RXAntStatus|(pDM_Odm->RXAntStatus<<4)));\r
1243 \r
1244         /* Toggle IGI to let RF enter RX mode, because BB doesn't send 3-wire command when RX path is enable */\r
1245         IGI = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm));\r
1246         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), IGI - 2);\r
1247         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), IGI - 2);\r
1248         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), IGI);\r
1249         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), IGI);\r
1250 \r
1251         ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_switch_bandwidth_8822b(): Success to switch bandwidth (bw: %d, primary ch: %d)\n", bandwidth, primary_ch_idx));\r
1252         return TRUE;\r
1253 }\r
1254 \r
1255 BOOLEAN\r
1256 config_phydm_switch_channel_bw_8822b(   \r
1257         IN      PDM_ODM_T                               pDM_Odm,\r
1258         IN      u1Byte                                  central_ch,\r
1259         IN      u1Byte                                  primary_ch_idx,\r
1260         IN      ODM_BW_E                                bandwidth\r
1261         )\r
1262 {\r
1263 \r
1264         /* Switch band */\r
1265         if (config_phydm_switch_band_8822b(pDM_Odm, central_ch) == FALSE)\r
1266                 return FALSE;\r
1267 \r
1268         /* Switch channel */\r
1269         if (config_phydm_switch_channel_8822b(pDM_Odm, central_ch) == FALSE)\r
1270                 return FALSE;\r
1271 \r
1272         /* Switch bandwidth */\r
1273         if (config_phydm_switch_bandwidth_8822b(pDM_Odm, primary_ch_idx, bandwidth) == FALSE)\r
1274                 return FALSE;\r
1275 \r
1276         return TRUE;\r
1277 }\r
1278 \r
1279 BOOLEAN\r
1280 config_phydm_trx_mode_8822b(\r
1281         IN      PDM_ODM_T                               pDM_Odm,\r
1282         IN      ODM_RF_PATH_E                   TxPath,\r
1283         IN      ODM_RF_PATH_E                   RxPath,\r
1284         IN      BOOLEAN                                 bTx2Path\r
1285         )\r
1286 {\r
1287         BOOLEAN         rf_reg_status = TRUE;\r
1288         u1Byte          IGI;\r
1289         u4Byte          rf_reg33 = 0;\r
1290         u2Byte          counter = 0;\r
1291         //PDM_ODM_T             pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
1292         //PADAPTER              pAdapter        = pDM_Odm->Adapter;\r
1293         //PMGNT_INFO            pMgntInfo = &(pAdapter->MgntInfo);\r
1294 \r
1295         ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b()=====================>\n"));        \r
1296 \r
1297         if (pDM_Odm->bDisablePhyApi) {\r
1298                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): disable PHY API for debug!!\n"));\r
1299                 return TRUE;\r
1300         }\r
1301 \r
1302         if ((TxPath & (~(ODM_RF_A|ODM_RF_B))) != 0) {\r
1303                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Wrong TX setting (TX: 0x%x)\n", TxPath));\r
1304                 return FALSE;\r
1305         }\r
1306 \r
1307         if ((RxPath & (~(ODM_RF_A|ODM_RF_B))) != 0) {\r
1308                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Wrong RX setting (RX: 0x%x)\n", RxPath));\r
1309                 return FALSE;\r
1310         }\r
1311 \r
1312         /* RF mode of path-A and path-B */\r
1313         /* Cannot shut down path-A, beacause synthesizer will be shut down when path-A is in shut down mode */\r
1314         if ((TxPath|RxPath) & ODM_RF_A)\r
1315                 ODM_SetBBReg(pDM_Odm, 0xc08, bMaskLWord, 0x3231);\r
1316         else\r
1317                 ODM_SetBBReg(pDM_Odm, 0xc08, bMaskLWord, 0x1111);\r
1318 \r
1319         if ((TxPath|RxPath) & ODM_RF_B)\r
1320                 ODM_SetBBReg(pDM_Odm, 0xe08, bMaskLWord, 0x3231);\r
1321         else\r
1322                 ODM_SetBBReg(pDM_Odm, 0xe08, bMaskLWord, 0x1111);\r
1323 \r
1324         /* Set TX antenna by Nsts */\r
1325         ODM_SetBBReg(pDM_Odm, 0x93c, (BIT19|BIT18), 0x3);\r
1326         ODM_SetBBReg(pDM_Odm, 0x80c, (BIT29|BIT28), 0x1);\r
1327 \r
1328         /* Control CCK TX path by 0xa07[7] */\r
1329         ODM_SetBBReg(pDM_Odm, 0x80c, BIT30, 0x1);\r
1330 \r
1331         /* TX logic map and TX path en for Nsts = 1, and CCK TX path*/  \r
1332         if (TxPath & ODM_RF_A) {\r
1333                 ODM_SetBBReg(pDM_Odm, 0x93c, 0xfff00000, 0x001);\r
1334                 ODM_SetBBReg(pDM_Odm, 0xa04, 0xf0000000, 0x8);\r
1335         } else if (TxPath & ODM_RF_B) {\r
1336                 ODM_SetBBReg(pDM_Odm, 0x93c, 0xfff00000, 0x002);\r
1337                 ODM_SetBBReg(pDM_Odm, 0xa04, 0xf0000000, 0x4);\r
1338         }\r
1339                 \r
1340         /* TX logic map and TX path en for Nsts = 2*/\r
1341         if ((TxPath == ODM_RF_A) || (TxPath == ODM_RF_B))\r
1342                 ODM_SetBBReg(pDM_Odm, 0x940, 0xfff0, 0x01);\r
1343         else\r
1344                 ODM_SetBBReg(pDM_Odm, 0x940, 0xfff0, 0x43);\r
1345 \r
1346         /* TX path enable */\r
1347         ODM_SetBBReg(pDM_Odm, 0x80c, bMaskByte0, ((TxPath << 4)|TxPath));\r
1348 \r
1349         /* Tx2path for 1ss */\r
1350         if (!((TxPath == ODM_RF_A) || (TxPath == ODM_RF_B))) {\r
1351                 if (bTx2Path || pDM_Odm->mp_mode) {\r
1352                         /* 2Tx for OFDM */\r
1353                         ODM_SetBBReg(pDM_Odm, 0x93c, 0xfff00000, 0x043);\r
1354 \r
1355                         /* 2Tx for CCK */\r
1356                         ODM_SetBBReg(pDM_Odm, 0xa04, 0xf0000000, 0xc);\r
1357                 }\r
1358         }\r
1359 \r
1360         /* Always disable MRC for CCK CCA */\r
1361         ODM_SetBBReg(pDM_Odm, 0xa2c, BIT22, 0x0);\r
1362 \r
1363         /* Always disable MRC for CCK barker */\r
1364         ODM_SetBBReg(pDM_Odm, 0xa2c, BIT18, 0x0);\r
1365 \r
1366         /* CCK RX 1st and 2nd path setting*/    \r
1367         if (RxPath & ODM_RF_A)\r
1368                 ODM_SetBBReg(pDM_Odm, 0xa04, 0x0f000000, 0x0);\r
1369         else if (RxPath & ODM_RF_B)\r
1370                 ODM_SetBBReg(pDM_Odm, 0xa04, 0x0f000000, 0x5);\r
1371 \r
1372         /* RX path enable */\r
1373         ODM_SetBBReg(pDM_Odm, 0x808, bMaskByte0, ((RxPath << 4)|RxPath));\r
1374 \r
1375         if ((RxPath == ODM_RF_A) || (RxPath == ODM_RF_B)) {\r
1376                 /* 1R */\r
1377 \r
1378                 /* Disable MRC for CCA */\r
1379                 /* ODM_SetBBReg(pDM_Odm, 0xa2c, BIT22, 0x0); */\r
1380 \r
1381                 /* Disable MRC for barker */\r
1382                 /* ODM_SetBBReg(pDM_Odm, 0xa2c, BIT18, 0x0); */\r
1383                 \r
1384                 /* Disable CCK antenna diversity */\r
1385                 /* ODM_SetBBReg(pDM_Odm, 0xa00, BIT15, 0x0); */\r
1386 \r
1387                 /* Disable Antenna weighting */\r
1388                 ODM_SetBBReg(pDM_Odm, 0x1904, BIT16, 0x0);\r
1389                 ODM_SetBBReg(pDM_Odm, 0x800, BIT28, 0x0);\r
1390                 ODM_SetBBReg(pDM_Odm, 0x850, BIT23, 0x0);\r
1391         } else {\r
1392                 /* 2R */\r
1393 \r
1394                 /* Enable MRC for CCA */\r
1395                 /* ODM_SetBBReg(pDM_Odm, 0xa2c, BIT22, 0x1); */\r
1396 \r
1397                 /* Enable MRC for barker */\r
1398                 /* ODM_SetBBReg(pDM_Odm, 0xa2c, BIT18, 0x1); */\r
1399 \r
1400                 /* Disable CCK antenna diversity */\r
1401                 /* ODM_SetBBReg(pDM_Odm, 0xa00, BIT15, 0x0); */\r
1402 \r
1403                 /* Enable Antenna weighting */\r
1404                 ODM_SetBBReg(pDM_Odm, 0x1904, BIT16, 0x1);\r
1405                 ODM_SetBBReg(pDM_Odm, 0x800, BIT28, 0x1);\r
1406                 ODM_SetBBReg(pDM_Odm, 0x850, BIT23, 0x1);\r
1407         }\r
1408 \r
1409         /* Update TXRX antenna status for PHYDM */\r
1410         pDM_Odm->TXAntStatus =  (TxPath & 0x3);\r
1411         pDM_Odm->RXAntStatus =  (RxPath & 0x3);\r
1412 \r
1413         /* MP driver need to support path-B TX\RX */\r
1414 \r
1415         while(1){\r
1416                 counter++;\r
1417                 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x80000);\r
1418                 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask, 0x00001);\r
1419 \r
1420                 ODM_delay_us(2);\r
1421                 rf_reg33 = config_phydm_read_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask);\r
1422                 \r
1423                 if ((rf_reg33 == 0x00001) && (config_phydm_read_rf_check_8822b(rf_reg33)))\r
1424                         break;\r
1425                 else if (counter == 100) {\r
1426                         ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Fail to set TRx mode setting, because writing RF mode table is fail\n"));\r
1427                         return FALSE;\r
1428                 }\r
1429         }\r
1430 \r
1431         if ((pDM_Odm->mp_mode) || (*pDM_Odm->pAntennaTest) || (pDM_Odm->Normalrxpath)) {\r
1432                 /*      0xef 0x80000  0x33 0x00001  0x3e 0x00034  0x3f 0x4080e  0xef 0x00000    suggested by Lucas*/\r
1433                 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x80000);\r
1434                 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask, 0x00001);\r
1435                 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x3e, bRFRegOffsetMask, 0x00034);\r
1436                 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x3f, bRFRegOffsetMask, 0x4080e);\r
1437                 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x00000);\r
1438                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): MP mode or Antenna test mode!! support path-B TX and RX\n"));\r
1439         } else {\r
1440                 /*      0xef 0x80000  0x33 0x00001  0x3e 0x00034  0x3f 0x4080c  0xef 0x00000 */\r
1441                 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x80000);\r
1442                 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x33, bRFRegOffsetMask, 0x00001);\r
1443                 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x3e, bRFRegOffsetMask, 0x00034);\r
1444                 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0x3f, bRFRegOffsetMask, 0x4080c);\r
1445                 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x00000);\r
1446                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Normal mode!! Do not support path-B TX and RX\n"));\r
1447         }\r
1448 \r
1449         rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(pDM_Odm, ODM_RF_PATH_A, 0xef, bRFRegOffsetMask, 0x00000);\r
1450 \r
1451         if (rf_reg_status == FALSE) {\r
1452                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Fail to set TRx mode setting (TX: 0x%x, RX: 0x%x), because writing RF register is fail\n", TxPath, RxPath));\r
1453                 return FALSE;\r
1454         }\r
1455 \r
1456         /* Toggle IGI to let RF enter RX mode, because BB doesn't send 3-wire command when RX path is enable */\r
1457         IGI = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm));\r
1458         ODM_Write_DIG(pDM_Odm, IGI - 2);\r
1459         ODM_Write_DIG(pDM_Odm, IGI);\r
1460 \r
1461         /* Modify CCA parameters */\r
1462         phydm_ccapar_by_rxpath_8822b(pDM_Odm);\r
1463         phydm_ccapar_by_rfe_8822b(pDM_Odm);\r
1464         phydm_rfe_8822b(pDM_Odm, central_ch_8822b);\r
1465 \r
1466         ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_trx_mode_8822b(): Success to set TRx mode setting (TX: 0x%x, RX: 0x%x)\n", TxPath, RxPath));\r
1467         return TRUE;\r
1468 }\r
1469 \r
1470 BOOLEAN\r
1471 config_phydm_parameter_init(\r
1472         IN      PDM_ODM_T                               pDM_Odm,\r
1473         IN      ODM_PARAMETER_INIT_E    type\r
1474         )\r
1475 {\r
1476         if (type == ODM_PRE_SETTING) {\r
1477                 ODM_SetBBReg(pDM_Odm, 0x808, (BIT28|BIT29), 0x0);\r
1478                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_parameter_init(): Pre setting: disable OFDM and CCK block\n"));\r
1479         } else if (type == ODM_POST_SETTING) {\r
1480                 ODM_SetBBReg(pDM_Odm, 0x808, (BIT28|BIT29), 0x3);\r
1481                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_parameter_init(): Post setting: enable OFDM and CCK block\n"));\r
1482                 reg82c_8822b = ODM_GetBBReg(pDM_Odm, 0x82c, bMaskDWord);\r
1483                 reg838_8822b = ODM_GetBBReg(pDM_Odm, 0x838, bMaskDWord);\r
1484                 reg830_8822b = ODM_GetBBReg(pDM_Odm, 0x830, bMaskDWord);\r
1485                 reg83c_8822b = ODM_GetBBReg(pDM_Odm, 0x83c, bMaskDWord);\r
1486                 rega20_8822b = ODM_GetBBReg(pDM_Odm, 0xa20, bMaskDWord);\r
1487                 rega24_8822b = ODM_GetBBReg(pDM_Odm, 0xa24, bMaskDWord);\r
1488                 rega28_8822b = ODM_GetBBReg(pDM_Odm, 0xa28, bMaskDWord);\r
1489         } else {\r
1490                 ODM_RT_TRACE(pDM_Odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("config_phydm_parameter_init(): Wrong type!!\n"));\r
1491                 return FALSE;\r
1492         }\r
1493 \r
1494         return TRUE;\r
1495 }\r
1496 \r
1497 /* ======================================================================== */\r
1498 #endif  /* RTL8822B_SUPPORT == 1 */\r
1499 \r