1 /******************************************************************************
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3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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5 * This program is free software; you can redistribute it and/or modify it
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6 * under the terms of version 2 of the GNU General Public License as
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7 * published by the Free Software Foundation.
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9 * This program is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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14 * You should have received a copy of the GNU General Public License along with
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15 * this program; if not, write to the Free Software Foundation, Inc.,
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16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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19 ******************************************************************************/
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21 #ifndef __PHYDMRAINFO_H__
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22 #define __PHYDMRAINFO_H__
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24 /*#define RAINFO_VERSION "2.0" //2014.11.04*/
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25 /*#define RAINFO_VERSION "3.0" //2015.01.13 Dino*/
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26 /*#define RAINFO_VERSION "3.1" //2015.01.14 Dino*/
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27 /*#define RAINFO_VERSION "3.3" 2015.07.29 YuChen*/
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28 /*#define RAINFO_VERSION "3.4"*/ /*2015.12.15 Stanley*/
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29 /*#define RAINFO_VERSION "4.0"*/ /*2016.03.24 Dino, Add more RA mask state and Phydm-lize partial ra mask function */
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30 #define RAINFO_VERSION "4.1" /*2016.04.20 Dino, Add new function to adjust PCR RA threshold */
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32 #define H2C_0X42_LENGTH 5
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34 #define RA_FLOOR_UP_GAP 3
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35 #define RA_FLOOR_TABLE_SIZE 7
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37 #define ACTIVE_TP_THRESHOLD 150
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38 #define RA_RETRY_DESCEND_NUM 2
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39 #define RA_RETRY_LIMIT_LOW 4
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40 #define RA_RETRY_LIMIT_HIGH 32
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42 #define RAINFO_BE_RX_STATE BIT0 // 1:RX //ULDL
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43 #define RAINFO_STBC_STATE BIT1
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44 //#define RAINFO_LDPC_STATE BIT2
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45 #define RAINFO_NOISY_STATE BIT2 // set by Noisy_Detection
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46 #define RAINFO_SHURTCUT_STATE BIT3
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47 #define RAINFO_SHURTCUT_FLAG BIT4
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48 #define RAINFO_INIT_RSSI_RATE_STATE BIT5
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49 #define RAINFO_BF_STATE BIT6
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50 #define RAINFO_BE_TX_STATE BIT7 // 1:TX
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52 #define RA_MASK_CCK 0xf
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53 #define RA_MASK_OFDM 0xff0
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54 #define RA_MASK_HT1SS 0xff000
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55 #define RA_MASK_HT2SS 0xff00000
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56 /*#define RA_MASK_MCS3SS */
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57 #define RA_MASK_HT4SS 0xff0
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58 #define RA_MASK_VHT1SS 0x3ff000
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59 #define RA_MASK_VHT2SS 0xffc00000
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61 #if(DM_ODM_SUPPORT_TYPE == ODM_AP)
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62 #define RA_FIRST_MACID 1
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63 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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64 #define RA_FIRST_MACID 0
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65 #define WIN_DEFAULT_PORT_MACID 0
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66 #define WIN_BT_PORT_MACID 2
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67 #else /*if (DM_ODM_SUPPORT_TYPE == ODM_CE)*/
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68 #define RA_FIRST_MACID 0
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71 #define AP_InitRateAdaptiveState ODM_RateAdaptiveStateApInit
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73 #if (RA_MASK_PHYDMLIZE_CE || RA_MASK_PHYDMLIZE_AP || RA_MASK_PHYDMLIZE_WIN)
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74 #define DM_RATR_STA_INIT 0
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75 #define DM_RATR_STA_HIGH 1
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76 #define DM_RATR_STA_MIDDLE 2
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77 #define DM_RATR_STA_LOW 3
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78 #define DM_RATR_STA_ULTRA_LOW 4
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81 typedef enum _phydm_arfr_num {
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82 ARFR_0_RATE_ID = 0x9,
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83 ARFR_1_RATE_ID = 0xa,
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84 ARFR_2_RATE_ID = 0xb,
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85 ARFR_3_RATE_ID = 0xc,
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86 ARFR_4_RATE_ID = 0xd,
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87 ARFR_5_RATE_ID = 0xe
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88 } PHYDM_RA_ARFR_NUM_E;
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90 typedef enum _Phydm_ra_dbg_para {
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91 RADBG_PCR_TH_OFFSET = 0,
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92 RADBG_RTY_PENALTY = 1,
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95 RADBG_TRATE_UP_TABLE = 4,
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96 RADBG_TRATE_DOWN_TABLE = 5,
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97 RADBG_TRYING_NECESSARY = 6,
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98 RADBG_TDROPING_NECESSARY = 7,
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99 RADBG_RATE_UP_RTY_RATIO = 8,
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100 RADBG_RATE_DOWN_RTY_RATIO = 9, //u8
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102 RADBG_DEBUG_MONITOR1 = 0xc,
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103 RADBG_DEBUG_MONITOR2 = 0xd,
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104 RADBG_DEBUG_MONITOR3 = 0xe,
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105 RADBG_DEBUG_MONITOR4 = 0xf,
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106 RADBG_DEBUG_MONITOR5 = 0x10,
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108 } PHYDM_RA_DBG_PARA_E;
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110 typedef enum PHYDM_WIRELESS_MODE {
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112 PHYDM_WIRELESS_MODE_UNKNOWN = 0x00,
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113 PHYDM_WIRELESS_MODE_A = 0x01,
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114 PHYDM_WIRELESS_MODE_B = 0x02,
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115 PHYDM_WIRELESS_MODE_G = 0x04,
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116 PHYDM_WIRELESS_MODE_AUTO = 0x08,
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117 PHYDM_WIRELESS_MODE_N_24G = 0x10,
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118 PHYDM_WIRELESS_MODE_N_5G = 0x20,
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119 PHYDM_WIRELESS_MODE_AC_5G = 0x40,
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120 PHYDM_WIRELESS_MODE_AC_24G = 0x80,
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121 PHYDM_WIRELESS_MODE_AC_ONLY = 0x100,
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122 PHYDM_WIRELESS_MODE_MAX = 0x800,
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123 PHYDM_WIRELESS_MODE_ALL = 0xFFFF
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124 } PHYDM_WIRELESS_MODE_E;
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126 typedef enum PHYDM_RATEID_IDX_ {
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128 PHYDM_BGN_40M_2SS = 0,
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129 PHYDM_BGN_40M_1SS = 1,
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130 PHYDM_BGN_20M_2SS = 2,
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131 PHYDM_BGN_20M_1SS = 3,
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137 PHYDM_ARFR0_AC_2SS = 9,
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138 PHYDM_ARFR1_AC_1SS = 10,
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139 PHYDM_ARFR2_AC_2G_1SS = 11,
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140 PHYDM_ARFR3_AC_2G_2SS = 12,
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141 PHYDM_ARFR4_AC_3SS = 13,
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142 PHYDM_ARFR5_N_3SS = 14
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143 } PHYDM_RATEID_IDX_E;
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145 typedef enum _PHYDM_RF_TYPE_DEFINITION {
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149 PHYDM_RF_2T2R_GREEN,
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156 } PHYDM_RF_TYPE_DEF_E;
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158 typedef enum _PHYDM_BW {
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169 #if (RATE_ADAPTIVE_SUPPORT == 1)//88E RA
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170 typedef struct _ODM_RA_Info_ {
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176 u1Byte PreRssiStaRA;
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178 u1Byte DecisionRate;
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180 u1Byte HighestRate;
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189 u1Byte RAWaitingCounter;
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190 u1Byte RAPendingCounter;
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191 u1Byte RADropAfterDown;
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192 #if 1 //POWER_TRAINING_ACTIVE == 1 // For compile pass only~!
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193 u1Byte PTActive; // on or off
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194 u1Byte PTTryState; // 0 trying state, 1 for decision state
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195 u1Byte PTStage; // 0~6
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196 u1Byte PTStopCount; //Stop PT counter
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197 u1Byte PTPreRate; // if rate change do PT
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198 u1Byte PTPreRssi; // if RSSI change 5% do PT
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199 u1Byte PTModeSS; // decide whitch rate should do PT
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200 u1Byte RAstage; // StageRA, decide how many times RA will be done between PT
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201 u1Byte PTSmoothFactor;
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203 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
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204 u1Byte RateDownCounter;
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205 u1Byte RateUpCounter;
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206 u1Byte RateDirection;
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207 u1Byte BoundingType;
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208 u1Byte BoundingCounter;
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209 u1Byte BoundingLearningTime;
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210 u1Byte RateDownStartTime;
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212 } ODM_RA_INFO_T, *PODM_RA_INFO_T;
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216 typedef struct _Rate_Adaptive_Table_ {
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217 u1Byte firstconnect;
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218 #if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
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219 BOOLEAN PT_collision_pre;
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222 #if (defined(CONFIG_RA_DBG_CMD))
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223 BOOLEAN is_ra_dbg_init;
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225 u1Byte RTY_P[ODM_NUM_RATE_IDX];
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226 u1Byte RTY_P_default[ODM_NUM_RATE_IDX];
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227 BOOLEAN RTY_P_modify_note[ODM_NUM_RATE_IDX];
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229 u1Byte RATE_UP_RTY_RATIO[ODM_NUM_RATE_IDX];
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230 u1Byte RATE_UP_RTY_RATIO_default[ODM_NUM_RATE_IDX];
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231 BOOLEAN RATE_UP_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX];
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233 u1Byte RATE_DOWN_RTY_RATIO[ODM_NUM_RATE_IDX];
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234 u1Byte RATE_DOWN_RTY_RATIO_default[ODM_NUM_RATE_IDX];
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235 BOOLEAN RATE_DOWN_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX];
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237 BOOLEAN RA_Para_feedback_req;
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243 u1Byte rate_length;
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245 u1Byte link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM];
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246 u1Byte highest_client_tx_order;
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247 u2Byte highest_client_tx_rate_order;
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248 u1Byte power_tracking_flag;
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249 u1Byte RA_threshold_offset;
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250 u1Byte RA_offset_direction;
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252 #if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT))
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253 u1Byte per_rate_retrylimit_20M[ODM_NUM_RATE_IDX];
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254 u1Byte per_rate_retrylimit_40M[ODM_NUM_RATE_IDX];
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255 u1Byte retry_descend_num;
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256 u1Byte retrylimit_low;
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257 u1Byte retrylimit_high;
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263 typedef struct _ODM_RATE_ADAPTIVE {
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264 u1Byte Type; // DM_Type_ByFW/DM_Type_ByDriver
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265 u1Byte HighRSSIThresh; // if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH
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266 u1Byte LowRSSIThresh; // if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW
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267 u1Byte RATRState; // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW
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269 #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
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270 u1Byte LdpcThres; // if RSSI > LdpcThres => switch from LPDC to BCC
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271 BOOLEAN bLowerRtsRate;
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274 #if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
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276 #elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
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279 u1Byte UltraLowRSSIThresh;
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280 u4Byte LastRATR; // RATR Register Content
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283 } ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE;
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285 #if (defined(CONFIG_RA_DBG_CMD))
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290 IN u4Byte *const dm_value
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294 odm_RA_ParaAdjust_init(
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301 phydm_RA_debug_PCR(
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303 IN u4Byte *const dm_value,
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306 IN u4Byte *_out_len
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312 ODM_C2HRaParaReportHandler(
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324 phydm_ra_dynamic_retry_count(
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329 phydm_ra_dynamic_retry_limit(
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334 phydm_ra_dynamic_rate_id_on_assoc(
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336 IN u1Byte wireless_mode,
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337 IN u1Byte init_rate_id
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344 IN u4Byte dbg_component
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348 phydm_c2h_ra_report_handler(
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355 phydm_rate_order_compute(
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361 phydm_ra_info_watchdog(
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366 phydm_ra_info_init(
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371 odm_RSSIMonitorInit(
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376 odm_RSSIMonitorCheck(
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386 phydm_vht_en_mapping(
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388 IN u4Byte WirelessMode
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392 phydm_rate_id_mapping(
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394 IN u4Byte WirelessMode,
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400 phydm_UpdateHalRAMask(
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402 IN u4Byte wirelessMode,
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405 IN u1Byte MimoPs_enable,
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406 IN u1Byte disable_cck_rate,
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407 IN u4Byte *ratr_bitmap_msb_in,
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408 IN u4Byte *ratr_bitmap_in,
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409 IN u1Byte tx_rate_level
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413 odm_RateAdaptiveMaskInit(
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418 odm_RefreshRateAdaptiveMask(
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423 odm_RefreshRateAdaptiveMaskMP(
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428 odm_RefreshRateAdaptiveMaskCE(
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433 odm_RefreshRateAdaptiveMaskAPADSL(
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438 phydm_RA_level_decision(
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441 IN u1Byte Ratr_State
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448 IN BOOLEAN bForceUpdate,
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449 OUT pu1Byte pRATRState
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453 odm_RefreshBasicRateMask(
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457 ODM_RAPostActionOnAssoc(
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461 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
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467 IN BOOLEAN bErpProtect
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471 ODM_UpdateNoisyState(
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473 IN BOOLEAN bNoisyStateFromC2H
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477 phydm_update_pwr_track(
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482 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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485 phydm_FindMinimumRSSI(
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486 IN PDM_ODM_T pDM_Odm,
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487 IN PADAPTER pAdapter,
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488 IN OUT BOOLEAN *pbLink_temp
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492 ODM_UpdateInitRateWorkItemCallback(
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497 odm_RSSIDumpToRegister(
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502 odm_RefreshLdpcRtsMP(
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503 IN PADAPTER pAdapter,
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504 IN PDM_ODM_T pDM_Odm,
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507 IN s4Byte UndecoratedSmoothedPWDB
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512 ODM_DynamicARFBSelect(
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515 IN BOOLEAN Collision_State
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520 ODM_RateAdaptiveStateApInit(
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521 IN PVOID PADAPTER_VOID,
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522 IN PRT_WLAN_STA pEntry
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524 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
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528 IN PADAPTER pAdapter
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532 PhyDM_Get_Rate_Bitmap_Ex(
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536 IN u1Byte rssi_level,
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537 OUT u8Byte *dm_RA_Mask,
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538 OUT u1Byte *dm_RteID
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541 ODM_Get_Rate_Bitmap(
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545 IN u1Byte rssi_level
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548 void phydm_ra_rssi_rpt_wk(PVOID pContext);
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549 #endif/*#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)*/
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551 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
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554 phydm_gen_ramask_h2c_AP(
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556 IN struct rtl8192cd_priv *priv,
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557 IN PSTA_INFO_T *pEntry,
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558 IN u1Byte rssi_level
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561 #endif/*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))*/
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563 #endif /*#ifndef __ODMRAINFO_H__*/
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