drivers/net/wireless/rockchip_wlan/rtl8822be/hal/halmac/halmac_type.h

   1 #ifndef _HALMAC_TYPE_H_
   2 #define _HALMAC_TYPE_H_
   3
   4 #include "halmac_2_platform.h"
   5 #include "halmac_hw_cfg.h"
   6 #include "halmac_fw_info.h"
   7
   8
   9 #define IN
  10 #define OUT
  11 #define INOUT
  12 #define VOID void
  13
  14 #define HALMAC_SCAN_CH_NUM_MAX                  28
  15 #define HALMAC_BCN_IE_BMP_SIZE                  24 /* ID0~ID191, 192/8=24 */
  16 #define HALMAC_PHY_PARAMETER_SIZE               12
  17 #define HALMAC_PHY_PARAMETER_MAX_NUM            128
  18 #define HALMAC_MAX_SSID_LEN                     32
  19 #define HALMAC_SUPPORT_NLO_NUM                  16
  20 #define HALMAC_SUPPORT_PROBE_REQ_NUM                    8
  21 #define HALMC_DDMA_POLLING_COUNT                1000
  22 #define API_ARRAY_SIZE                                                  32
  23
  24 /* platform api */
  25 #define PLATFORM_SDIO_CMD52_READ                                pHalmac_adapter->pHalmac_platform_api->SDIO_CMD52_READ
  26 #define PLATFORM_SDIO_CMD53_READ_8              pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_READ_8
  27 #define PLATFORM_SDIO_CMD53_READ_16             pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_READ_16
  28 #define PLATFORM_SDIO_CMD53_READ_32             pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_READ_32
  29 #define PLATFORM_SDIO_CMD52_WRITE               pHalmac_adapter->pHalmac_platform_api->SDIO_CMD52_WRITE
  30 #define PLATFORM_SDIO_CMD53_WRITE_8             pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_WRITE_8
  31 #define PLATFORM_SDIO_CMD53_WRITE_16                    pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_WRITE_16
  32 #define PLATFORM_SDIO_CMD53_WRITE_32                    pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_WRITE_32
  33
  34 #define PLATFORM_REG_READ_8                     pHalmac_adapter->pHalmac_platform_api->REG_READ_8
  35 #define PLATFORM_REG_READ_16                    pHalmac_adapter->pHalmac_platform_api->REG_READ_16
  36 #define PLATFORM_REG_READ_32                    pHalmac_adapter->pHalmac_platform_api->REG_READ_32
  37 #define PLATFORM_REG_WRITE_8                    pHalmac_adapter->pHalmac_platform_api->REG_WRITE_8
  38 #define PLATFORM_REG_WRITE_16                   pHalmac_adapter->pHalmac_platform_api->REG_WRITE_16
  39 #define PLATFORM_REG_WRITE_32                   pHalmac_adapter->pHalmac_platform_api->REG_WRITE_32
  40
  41 #define PLATFORM_SEND_RSVD_PAGE                 pHalmac_adapter->pHalmac_platform_api->SEND_RSVD_PAGE
  42 #define PLATFORM_SEND_H2C_PKT                   pHalmac_adapter->pHalmac_platform_api->SEND_H2C_PKT
  43
  44 #define PLATFORM_RTL_FREE                       pHalmac_adapter->pHalmac_platform_api->RTL_FREE
  45 #define PLATFORM_RTL_MALLOC                     pHalmac_adapter->pHalmac_platform_api->RTL_MALLOC
  46 #define PLATFORM_RTL_MEMCPY                     pHalmac_adapter->pHalmac_platform_api->RTL_MEMCPY
  47 #define PLATFORM_RTL_MEMSET                     pHalmac_adapter->pHalmac_platform_api->RTL_MEMSET
  48 #define PLATFORM_RTL_DELAY_US                   pHalmac_adapter->pHalmac_platform_api->RTL_DELAY_US
  49
  50 #define PLATFORM_MUTEX_INIT                     pHalmac_adapter->pHalmac_platform_api->MUTEX_INIT
  51 #define PLATFORM_MUTEX_DEINIT                   pHalmac_adapter->pHalmac_platform_api->MUTEX_DEINIT
  52 #define PLATFORM_MUTEX_LOCK                     pHalmac_adapter->pHalmac_platform_api->MUTEX_LOCK
  53 #define PLATFORM_MUTEX_UNLOCK                   pHalmac_adapter->pHalmac_platform_api->MUTEX_UNLOCK
  54
  55 #define PLATFORM_EVENT_INDICATION               pHalmac_adapter->pHalmac_platform_api->EVENT_INDICATION
  56
  57
  58 #if HALMAC_DBG_MSG_ENABLE
  59 #define PLATFORM_MSG_PRINT                      pHalmac_adapter->pHalmac_platform_api->MSG_PRINT
  60 #else
  61 #define PLATFORM_MSG_PRINT(pDriver_adapter, msg_type, msg_level, fmt, ...)
  62 #endif
  63
  64 #if HALMAC_PLATFORM_TESTPROGRAM
  65 #define PLATFORM_WRITE_DATA_SDIO_ADDR            pHalmac_adapter->pHalmac_platform_api->WRITE_DATA_SDIO_ADDR
  66 #define PLATFORM_WRITE_DATA_USB_BULKOUT_ID       pHalmac_adapter->pHalmac_platform_api->WRITE_DATA_USB_BULKOUT_ID
  67 #define PLATFORM_WRITE_DATA_PCIE_QUEUE           pHalmac_adapter->pHalmac_platform_api->WRITE_DATA_PCIE_QUEUE
  68 #define PLATFORM_READ_DATA                       pHalmac_adapter->pHalmac_platform_api->READ_DATA
  69 #endif
  70
  71 #define HALMAC_REG_READ_8                        pHalmac_api->halmac_reg_read_8
  72 #define HALMAC_REG_READ_16                       pHalmac_api->halmac_reg_read_16
  73 #define HALMAC_REG_READ_32                       pHalmac_api->halmac_reg_read_32
  74 #define HALMAC_REG_WRITE_8                       pHalmac_api->halmac_reg_write_8
  75 #define HALMAC_REG_WRITE_16                      pHalmac_api->halmac_reg_write_16
  76 #define HALMAC_REG_WRITE_32                      pHalmac_api->halmac_reg_write_32
  77
  78 /* Swap Little-endian <-> Big-endia*/
  79 #define SWAP32(x) ((u32)( \
  80                            (((u32)(x) & (u32)0x000000ff) << 24) | \
  81                            (((u32)(x) & (u32)0x0000ff00) << 8) | \
  82                            (((u32)(x) & (u32)0x00ff0000) >> 8) | \
  83                            (((u32)(x) & (u32)0xff000000) >> 24)))
  84
  85 #define SWAP16(x) ((u16)( \
  86                            (((u16)(x) & (u16)0x00ff) << 8) | \
  87                            (((u16)(x) & (u16)0xff00) >> 8)))
  88
  89 /*1->Little endian 0->Big endian*/
  90 #if HALMAC_SYSTEM_ENDIAN
  91 #ifndef rtk_le16_to_cpu
  92 #define rtk_cpu_to_le32(x)              ((u32)(x))
  93 #define rtk_le32_to_cpu(x)              ((u32)(x))
  94 #define rtk_cpu_to_le16(x)              ((u16)(x))
  95 #define rtk_le16_to_cpu(x)              ((u16)(x))
  96 #define rtk_cpu_to_be32(x)              SWAP32((x))
  97 #define rtk_be32_to_cpu(x)              SWAP32((x))
  98 #define rtk_cpu_to_be16(x)              SWAP16((x))
  99 #define rtk_be16_to_cpu(x)              SWAP16((x))
 100 #endif
 101 #else
 102 #ifndef rtk_le16_to_cpu
 103 #define rtk_cpu_to_le32(x)              SWAP32((x))
 104 #define rtk_le32_to_cpu(x)              SWAP32((x))
 105 #define rtk_cpu_to_le16(x)              SWAP16((x))
 106 #define rtk_le16_to_cpu(x)              SWAP16((x))
 107 #define rtk_cpu_to_be32(x)              ((u32)(x))
 108 #define rtk_be32_to_cpu(x)              ((u32)(x))
 109 #define rtk_cpu_to_be16(x)              ((u16)(x))
 110 #define rtk_be16_to_cpu(x)              ((u16)(x))
 111 #endif
 112 #endif
 113
 114 #define HALMAC_ALIGN(x, a)               HALMAC_ALIGN_MASK(x, (a) - 1)
 115 #define HALMAC_ALIGN_MASK(x, mask)       (((x) + (mask)) & ~(mask))
 116
 117 /* #if !HALMAC_PLATFORM_WINDOWS */
 118 #if !((HALMAC_PLATFORM_WINDOWS == 1) && (HALMAC_PLATFORM_TESTPROGRAM == 0))
 119
 120 /* Byte Swapping routine */
 121 #ifndef EF1Byte
 122 #define EF1Byte (u8)
 123 #endif
 124
 125 #ifndef EF2Byte
 126 #define EF2Byte rtk_le16_to_cpu
 127 #endif
 128
 129 #ifndef EF4Byte
 130 #define EF4Byte rtk_le32_to_cpu
 131 #endif
 132
 133 /* Example:
 134  * BIT_LEN_MASK_32(0) => 0x00000000
 135  * BIT_LEN_MASK_32(1) => 0x00000001
 136  * BIT_LEN_MASK_32(2) => 0x00000003
 137  * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
 138  */
 139 #ifndef BIT_LEN_MASK_32
 140 #define BIT_LEN_MASK_32(__BitLen) \
 141         (0xFFFFFFFF >> (32 - (__BitLen)))
 142 #endif
 143
 144 /* Example:
 145  * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
 146  * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
 147  */
 148 #ifndef BIT_OFFSET_LEN_MASK_32
 149 #define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) \
 150         (BIT_LEN_MASK_32(__BitLen) << (__BitOffset))
 151 #endif
 152
 153 /* Return 4-byte value in host byte ordering from
 154  * 4-byte pointer in litten-endian system
 155  */
 156 #ifndef LE_P4BYTE_TO_HOST_4BYTE
 157 #define LE_P4BYTE_TO_HOST_4BYTE(__pStart) \
 158         (EF4Byte(*((u32 *)(__pStart))))
 159 #endif
 160
 161
 162 /* Translate subfield (continuous bits in little-endian) of
 163  * 4-byte value in litten byte to 4-byte value in host byte ordering
 164  */
 165 #ifndef LE_BITS_TO_4BYTE
 166 #define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
 167         ( \
 168                 (LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset)) \
 169                 & \
 170                 BIT_LEN_MASK_32(__BitLen) \
 171         )
 172 #endif
 173
 174 /* Mask subfield (continuous bits in little-endian) of 4-byte
 175  * value in litten byte oredering and return the result in 4-byte
 176  * value in host byte ordering
 177  */
 178 #ifndef LE_BITS_CLEARED_TO_4BYTE
 179 #define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
 180         ( \
 181                 LE_P4BYTE_TO_HOST_4BYTE(__pStart) \
 182                 & \
 183                 (~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen)) \
 184         )
 185 #endif
 186
 187 /* Set subfield of little-endian 4-byte value to specified value */
 188 #ifndef SET_BITS_TO_LE_4BYTE
 189 #define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \
 190         do { \
 191                 *((u32 *)(__pStart)) = \
 192                         EF4Byte( \
 193                                 LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
 194                                 | \
 195                                 ((((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset)) \
 196                         ); \
 197         } while (0)
 198 #endif
 199
 200 #ifndef HALMAC_BIT_OFFSET_VAL_MASK_32
 201 #define HALMAC_BIT_OFFSET_VAL_MASK_32(__BitVal, __BitOffset) \
 202         (__BitVal << (__BitOffset))
 203 #endif
 204
 205 #ifndef SET_MEM_OP
 206 #define SET_MEM_OP(Dw, Value32, Mask, Shift) \
 207         (((Dw) & ~((Mask) << (Shift))) | (((Value32) & (Mask)) << (Shift)))
 208 #endif
 209
 210 #ifndef HALMAC_SET_DESC_FIELD_CLR
 211 #define HALMAC_SET_DESC_FIELD_CLR(Dw, Value32, Mask, Shift) \
 212         (Dw = (rtk_cpu_to_le32(SET_MEM_OP(rtk_cpu_to_le32(Dw), Value32, Mask, Shift))))
 213 #endif
 214
 215 #ifndef HALMAC_SET_DESC_FIELD_NO_CLR
 216 #define HALMAC_SET_DESC_FIELD_NO_CLR(Dw, Value32, Mask, Shift) \
 217         (Dw |= (rtk_cpu_to_le32(((Value32) & (Mask)) << (Shift))))
 218 #endif
 219
 220 #ifndef HALMAC_GET_DESC_FIELD
 221 #define HALMAC_GET_DESC_FIELD(Dw, Mask, Shift) \
 222         ((rtk_le32_to_cpu(Dw) >> (Shift)) & (Mask))
 223 #endif
 224
 225 #define HALMAC_SET_BD_FIELD_CLR HALMAC_SET_DESC_FIELD_CLR
 226 #define HALMAC_SET_BD_FIELD_NO_CLR HALMAC_SET_DESC_FIELD_NO_CLR
 227 #define HALMAC_GET_BD_FIELD HALMAC_GET_DESC_FIELD
 228
 229 #ifndef GET_H2C_FIELD
 230 #define GET_H2C_FIELD   LE_BITS_TO_4BYTE
 231 #endif
 232
 233 #ifndef SET_H2C_FIELD_CLR
 234 #define SET_H2C_FIELD_CLR       SET_BITS_TO_LE_4BYTE
 235 #endif
 236
 237 #ifndef SET_H2C_FIELD_NO_CLR
 238 #define SET_H2C_FIELD_NO_CLR    SET_BITS_TO_LE_4BYTE
 239 #endif
 240
 241 #ifndef GET_C2H_FIELD
 242 #define GET_C2H_FIELD   LE_BITS_TO_4BYTE
 243 #endif
 244
 245 #ifndef SET_C2H_FIELD_CLR
 246 #define SET_C2H_FIELD_CLR       SET_BITS_TO_LE_4BYTE
 247 #endif
 248
 249 #ifndef SET_C2H_FIELD_NO_CLR
 250 #define SET_C2H_FIELD_NO_CLR    SET_BITS_TO_LE_4BYTE
 251 #endif
 252
 253 #endif /* #if !HALMAC_PLATFORM_WINDOWS */
 254
 255 #ifndef BIT
 256 #define BIT(x)              (1 << (x))
 257 #endif
 258
 259 /* HALMAC API return status*/
 260 typedef enum _HALMAC_RET_STATUS {
 261         HALMAC_RET_SUCCESS = 0x00,
 262         HALMAC_RET_SUCCESS_ENQUEUE = 0x01,
 263         HALMAC_RET_PLATFORM_API_NULL = 0x02,
 264         HALMAC_RET_EFUSE_SIZE_INCORRECT = 0x03,
 265         HALMAC_RET_MALLOC_FAIL = 0x04,
 266         HALMAC_RET_ADAPTER_INVALID = 0x05,
 267         HALMAC_RET_ITF_INCORRECT = 0x06,
 268         HALMAC_RET_DLFW_FAIL = 0x07,
 269         HALMAC_RET_PORT_NOT_SUPPORT = 0x08,
 270         HALMAC_RET_TRXMODE_NOT_SUPPORT = 0x09,
 271         HALMAC_RET_INIT_LLT_FAIL = 0x0A,
 272         HALMAC_RET_POWER_STATE_INVALID = 0x0B,
 273         HALMAC_RET_H2C_ACK_NOT_RECEIVED = 0x0C,
 274         HALMAC_RET_DL_RSVD_PAGE_FAIL = 0x0D,
 275         HALMAC_RET_EFUSE_R_FAIL = 0x0E,
 276         HALMAC_RET_EFUSE_W_FAIL = 0x0F,
 277         HALMAC_RET_H2C_SW_RES_FAIL = 0x10,
 278         HALMAC_RET_SEND_H2C_FAIL = 0x11,
 279         HALMAC_RET_PARA_NOT_SUPPORT = 0x12,
 280         HALMAC_RET_PLATFORM_API_INCORRECT = 0x13,
 281         HALMAC_RET_ENDIAN_ERR = 0x14,
 282         HALMAC_RET_FW_SIZE_ERR = 0x15,
 283         HALMAC_RET_TRX_MODE_NOT_SUPPORT = 0x16,
 284         HALMAC_RET_FAIL = 0x17,
 285         HALMAC_RET_CHANGE_PS_FAIL = 0x18,
 286         HALMAC_RET_CFG_PARA_FAIL = 0x19,
 287         HALMAC_RET_UPDATE_PROBE_FAIL = 0x1A,
 288         HALMAC_RET_SCAN_FAIL = 0x1B,
 289         HALMAC_RET_STOP_SCAN_FAIL = 0x1C,
 290         HALMAC_RET_BCN_PARSER_CMD_FAIL = 0x1D,
 291         HALMAC_RET_POWER_ON_FAIL = 0x1E,
 292         HALMAC_RET_POWER_OFF_FAIL = 0x1F,
 293         HALMAC_RET_RX_AGG_MODE_FAIL = 0x20,
 294         HALMAC_RET_DATA_BUF_NULL = 0x21,
 295         HALMAC_RET_DATA_SIZE_INCORRECT = 0x22,
 296         HALMAC_RET_QSEL_INCORRECT = 0x23,
 297         HALMAC_RET_DMA_MAP_INCORRECT = 0x24,
 298         HALMAC_RET_SEND_ORIGINAL_H2C_FAIL = 0x25,
 299         HALMAC_RET_DDMA_FAIL = 0x26,
 300         HALMAC_RET_FW_CHECKSUM_FAIL = 0x27,
 301         HALMAC_RET_PWRSEQ_POLLING_FAIL = 0x28,
 302         HALMAC_RET_PWRSEQ_CMD_INCORRECT = 0x29,
 303         HALMAC_RET_WRITE_DATA_FAIL = 0x2A,
 304         HALMAC_RET_DUMP_FIFOSIZE_INCORRECT = 0x2B,
 305         HALMAC_RET_NULL_POINTER = 0x2C,
 306         HALMAC_RET_PROBE_NOT_FOUND = 0x2D,
 307         HALMAC_RET_FW_NO_MEMORY = 0x2E,
 308         HALMAC_RET_H2C_STATUS_ERR = 0x2F,
 309         HALMAC_RET_GET_H2C_SPACE_ERR = 0x30,
 310         HALMAC_RET_H2C_SPACE_FULL = 0x31,
 311         HALMAC_RET_DATAPACK_NO_FOUND = 0x32,
 312         HALMAC_RET_CANNOT_FIND_H2C_RESOURCE = 0x33,
 313         HALMAC_RET_TX_DMA_ERR = 0x34,
 314         HALMAC_RET_RX_DMA_ERR = 0x35,
 315         HALMAC_RET_CHIP_NOT_SUPPORT = 0x36,
 316         HALMAC_RET_FREE_SPACE_NOT_ENOUGH = 0x37,
 317         HALMAC_RET_CH_SW_SEQ_WRONG = 0x38,
 318         HALMAC_RET_CH_SW_NO_BUF = 0x39,
 319         HALMAC_RET_SW_CASE_NOT_SUPPORT = 0x3A,
 320         HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL = 0x3B,
 321         HALMAC_RET_INVALID_SOUNDING_SETTING = 0x3C,
 322         HALMAC_RET_GEN_INFO_NOT_SENT = 0x3D,
 323         HALMAC_RET_STATE_INCORRECT = 0x3E,
 324         HALMAC_RET_H2C_BUSY = 0x3F,
 325         HALMAC_RET_INVALID_FEATURE_ID = 0x40,
 326         HALMAC_RET_BUFFER_TOO_SMALL = 0x41,
 327         HALMAC_RET_ZERO_LEN_RSVD_PACKET = 0x42,
 328         HALMAC_RET_BUSY_STATE = 0x43,
 329         HALMAC_RET_ERROR_STATE = 0x44,
 330         HALMAC_RET_API_INVALID = 0x45,
 331         HALMAC_RET_POLLING_BCN_VALID_FAIL = 0x46,
 332         HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL = 0x47,
 333         HALMAC_RET_EEPROM_PARSING_FAIL = 0x48,
 334         HALMAC_RET_EFUSE_NOT_ENOUGH = 0x49,
 335         HALMAC_RET_WRONG_ARGUMENT = 0x4A,
 336         HALMAC_RET_NOT_SUPPORT = 0x4B,
 337         HALMAC_RET_C2H_NOT_HANDLED = 0x4C,
 338         HALMAC_RET_PARA_SENDING = 0x4D,
 339         HALMAC_RET_CFG_DLFW_SIZE_FAIL = 0x4E,
 340         HALMAC_RET_CFG_TXFIFO_PAGE_FAIL = 0x4F,
 341         HALMAC_RET_SWITCH_CASE_ERROR = 0x50,
 342         HALMAC_RET_EFUSE_BANK_INCORRECT = 0x51,
 343         HALMAC_RET_SWITCH_EFUSE_BANK_FAIL = 0x52,
 344         HALMAC_RET_USB_MODE_UNCHANGE = 0x53,
 345         HALMAC_RET_NO_DLFW = 0x54,
 346         HALMAC_RET_USB2_3_SWITCH_UNSUPPORT = 0x55,
 347 } HALMAC_RET_STATUS;
 348
 349 typedef enum _HALMAC_MAC_CLOCK_HW_DEF {
 350         HALMAC_MAC_CLOCK_HW_DEF_80M = 0,
 351         HALMAC_MAC_CLOCK_HW_DEF_40M = 1,
 352         HALMAC_MAC_CLOCK_HW_DEF_20M = 2,
 353 } HALMAC_MAC_CLOCK_HW_DEF;
 354
 355 /* Rx aggregation parameters */
 356 typedef enum _HALMAC_NORMAL_RXAGG_TH_TO {
 357         HALMAC_NORMAL_RXAGG_THRESHOLD = 0xFF,
 358         HALMAC_NORMAL_RXAGG_TIMEOUT = 0x01,
 359 } HALMAC_NORMAL_RXAGG_TH_TO;
 360
 361 typedef enum _HALMAC_LOOPBACK_RXAGG_TH_TO {
 362         HALMAC_LOOPBACK_RXAGG_THRESHOLD = 0xFF,
 363         HALMAC_LOOPBACK_RXAGG_TIMEOUT = 0x01,
 364 } HALMAC_LOOPBACK_RXAGG_TH_TO;
 365
 366 /* Chip ID*/
 367 typedef enum _HALMAC_CHIP_ID {
 368         HALMAC_CHIP_ID_8822B = 0,
 369         HALMAC_CHIP_ID_8821C = 1,
 370         HALMAC_CHIP_ID_8824B = 2,
 371         HALMAC_CHIP_ID_8197F = 3,
 372         HALMAC_CHIP_ID_UNDEFINE = 0x7F,
 373 } HALMAC_CHIP_ID;
 374
 375 typedef enum _HALMAC_CHIP_ID_HW_DEF {
 376         HALMAC_CHIP_ID_HW_DEF_8723A = 0x01,
 377         HALMAC_CHIP_ID_HW_DEF_8188E = 0x02,
 378         HALMAC_CHIP_ID_HW_DEF_8881A = 0x03,
 379         HALMAC_CHIP_ID_HW_DEF_8812A = 0x04,
 380         HALMAC_CHIP_ID_HW_DEF_8821A = 0x05,
 381         HALMAC_CHIP_ID_HW_DEF_8723B = 0x06,
 382         HALMAC_CHIP_ID_HW_DEF_8192E = 0x07,
 383         HALMAC_CHIP_ID_HW_DEF_8814A = 0x08,
 384         HALMAC_CHIP_ID_HW_DEF_8821C = 0x09,
 385         HALMAC_CHIP_ID_HW_DEF_8822B = 0x0A,
 386         HALMAC_CHIP_ID_HW_DEF_8703B = 0x0B,
 387         HALMAC_CHIP_ID_HW_DEF_8188F = 0x0C,
 388         HALMAC_CHIP_ID_HW_DEF_8192F = 0x0D,
 389         HALMAC_CHIP_ID_HW_DEF_8197F = 0x0E,
 390         HALMAC_CHIP_ID_HW_DEF_8723D = 0x0F,
 391         HALMAC_CHIP_ID_HW_DEF_UNDEFINE = 0x7F,
 392         HALMAC_CHIP_ID_HW_DEF_PS = 0xEA,
 393 } HALMAC_CHIP_ID_HW_DEF;
 394
 395 /* Chip Version*/
 396 typedef enum _HALMAC_CHIP_VER {
 397         HALMAC_CHIP_VER_A_CUT = 0x00,
 398         HALMAC_CHIP_VER_B_CUT = 0x01,
 399         HALMAC_CHIP_VER_C_CUT = 0x02,
 400         HALMAC_CHIP_VER_D_CUT = 0x03,
 401         HALMAC_CHIP_VER_E_CUT = 0x04,
 402         HALMAC_CHIP_VER_F_CUT = 0x05,
 403         HALMAC_CHIP_VER_TEST = 0xFF,
 404         HALMAC_CHIP_VER_UNDEFINE = 0x7FFF,
 405 } HALMAC_CHIP_VER;
 406
 407 /* Network type select */
 408 typedef enum _HALMAC_NETWORK_TYPE_SELECT {
 409         HALMAC_NETWORK_NO_LINK = 0,
 410         HALMAC_NETWORK_ADHOC = 1,
 411         HALMAC_NETWORK_INFRASTRUCTURE = 2,
 412         HALMAC_NETWORK_AP = 3,
 413         HALMAC_NETWORK_UNDEFINE = 0x7F,
 414 } HALMAC_NETWORK_TYPE_SELECT;
 415
 416 /* Transfer mode select */
 417 typedef enum _HALMAC_TRNSFER_MODE_SELECT {
 418         HALMAC_TRNSFER_NORMAL = 0x0,
 419         HALMAC_TRNSFER_LOOPBACK_DIRECT = 0xB,
 420         HALMAC_TRNSFER_LOOPBACK_DELAY = 0x3,
 421         HALMAC_TRNSFER_UNDEFINE = 0x7F,
 422 } HALMAC_TRNSFER_MODE_SELECT;
 423
 424 /* Queue select */
 425 typedef enum _HALMAC_DMA_MAPPING {
 426         HALMAC_DMA_MAPPING_EXTRA = 0,
 427         HALMAC_DMA_MAPPING_LOW = 1,
 428         HALMAC_DMA_MAPPING_NORMAL = 2,
 429         HALMAC_DMA_MAPPING_HIGH = 3,
 430         HALMAC_DMA_MAPPING_UNDEFINE = 0x7F,
 431 } HALMAC_DMA_MAPPING;
 432
 433 /* TXDESC queue select TID */
 434 typedef enum _HALMAC_TXDESC_QUEUE_TID {
 435         HALMAC_TXDESC_QSEL_TID0 = 0,
 436         HALMAC_TXDESC_QSEL_TID1 = 1,
 437         HALMAC_TXDESC_QSEL_TID2 = 2,
 438         HALMAC_TXDESC_QSEL_TID3 = 3,
 439         HALMAC_TXDESC_QSEL_TID4 = 4,
 440         HALMAC_TXDESC_QSEL_TID5 = 5,
 441         HALMAC_TXDESC_QSEL_TID6 = 6,
 442         HALMAC_TXDESC_QSEL_TID7 = 7,
 443         HALMAC_TXDESC_QSEL_TID8 = 8,
 444         HALMAC_TXDESC_QSEL_TID9 = 9,
 445         HALMAC_TXDESC_QSEL_TIDA = 10,
 446         HALMAC_TXDESC_QSEL_TIDB = 11,
 447         HALMAC_TXDESC_QSEL_TIDC = 12,
 448         HALMAC_TXDESC_QSEL_TIDD = 13,
 449         HALMAC_TXDESC_QSEL_TIDE = 14,
 450         HALMAC_TXDESC_QSEL_TIDF = 15,
 451
 452         HALMAC_TXDESC_QSEL_BEACON = 0x10,
 453         HALMAC_TXDESC_QSEL_HIGH = 0x11,
 454         HALMAC_TXDESC_QSEL_MGT = 0x12,
 455         HALMAC_TXDESC_QSEL_H2C_CMD = 0x13,
 456
 457         HALMAC_TXDESC_QSEL_UNDEFINE = 0x7F,
 458 } HALMAC_TXDESC_QUEUE_TID;
 459
 460 typedef enum _HALMAC_PTCL_QUEUE {
 461         HALMAC_PTCL_QUEUE_VO = 0x0,
 462         HALMAC_PTCL_QUEUE_VI = 0x1,
 463         HALMAC_PTCL_QUEUE_BE = 0x2,
 464         HALMAC_PTCL_QUEUE_BK = 0x3,
 465         HALMAC_PTCL_QUEUE_MG = 0x4,
 466         HALMAC_PTCL_QUEUE_HI = 0x5,
 467         HALMAC_PTCL_QUEUE_NUM = 0x6,
 468         HALMAC_PTCL_QUEUE_UNDEFINE = 0x7F,
 469 } HALMAC_PTCL_QUEUE;
 470
 471 typedef enum {
 472         HALMAC_QUEUE_SELECT_VO = HALMAC_TXDESC_QSEL_TID6,
 473         HALMAC_QUEUE_SELECT_VI = HALMAC_TXDESC_QSEL_TID4,
 474         HALMAC_QUEUE_SELECT_BE = HALMAC_TXDESC_QSEL_TID0,
 475         HALMAC_QUEUE_SELECT_BK = HALMAC_TXDESC_QSEL_TID1,
 476         HALMAC_QUEUE_SELECT_VO_V2 = HALMAC_TXDESC_QSEL_TID7,
 477         HALMAC_QUEUE_SELECT_VI_V2 = HALMAC_TXDESC_QSEL_TID5,
 478         HALMAC_QUEUE_SELECT_BE_V2 = HALMAC_TXDESC_QSEL_TID3,
 479         HALMAC_QUEUE_SELECT_BK_V2 = HALMAC_TXDESC_QSEL_TID2,
 480         HALMAC_QUEUE_SELECT_BCN = HALMAC_TXDESC_QSEL_BEACON,
 481         HALMAC_QUEUE_SELECT_HIGH = HALMAC_TXDESC_QSEL_HIGH,
 482         HALMAC_QUEUE_SELECT_MGNT = HALMAC_TXDESC_QSEL_MGT,
 483         HALMAC_QUEUE_SELECT_CMD = HALMAC_TXDESC_QSEL_H2C_CMD,
 484         HALMAC_QUEUE_SELECT_UNDEFINE = 0x7F,
 485 } HALMAC_QUEUE_SELECT;
 486
 487
 488 /* USB burst size */
 489 typedef enum _HALMAC_USB_BURST_SIZE {
 490         HALMAC_USB_BURST_SIZE_3_0 = 0x0,
 491         HALMAC_USB_BURST_SIZE_2_0_HSPEED = 0x1,
 492         HALMAC_USB_BURST_SIZE_2_0_FSPEED = 0x2,
 493         HALMAC_USB_BURST_SIZE_2_0_OTHERS = 0x3,
 494         HALMAC_USB_BURST_SIZE_UNDEFINE = 0x7F,
 495 } HALMAC_USB_BURST_SIZE;
 496
 497 /* HAL API  function parameters*/
 498 typedef enum _HALMAC_INTERFACE {
 499         HALMAC_INTERFACE_PCIE = 0x0,
 500         HALMAC_INTERFACE_USB = 0x1,
 501         HALMAC_INTERFACE_SDIO = 0x2,
 502         HALMAC_INTERFACE_UNDEFINE = 0x7F,
 503 } HALMAC_INTERFACE;
 504
 505 typedef enum _HALMAC_RX_AGG_MODE {
 506         HALMAC_RX_AGG_MODE_NONE = 0x0,
 507         HALMAC_RX_AGG_MODE_DMA = 0x1,
 508         HALMAC_RX_AGG_MODE_USB = 0x2,
 509         HALMAC_RX_AGG_MODE_UNDEFINE = 0x7F,
 510 } HALMAC_RX_AGG_MODE;
 511 typedef struct _HALMAC_RXAGG_TH {
 512         u8 drv_define;
 513         u8 timeout;
 514         u8 size;
 515 } HALMAC_RXAGG_TH, *PHALMAC_RXAGG_TH;
 516
 517 typedef struct _HALMAC_RXAGG_CFG {
 518         HALMAC_RX_AGG_MODE mode;
 519         HALMAC_RXAGG_TH threshold;
 520 } HALMAC_RXAGG_CFG, *PHALMAC_RXAGG_CFG;
 521
 522
 523 typedef enum _HALMAC_MAC_POWER {
 524         HALMAC_MAC_POWER_OFF = 0x0,
 525         HALMAC_MAC_POWER_ON = 0x1,
 526         HALMAC_MAC_POWER_UNDEFINE = 0x7F,
 527 } HALMAC_MAC_POWER;
 528
 529 typedef enum _HALMAC_PS_STATE {
 530         HALMAC_PS_STATE_ACT = 0x0,
 531         HALMAC_PS_STATE_LPS = 0x1,
 532         HALMAC_PS_STATE_IPS = 0x2,
 533         HALMAC_PS_STATE_UNDEFINE = 0x7F,
 534 } HALMAC_PS_STATE;
 535
 536 typedef enum _HALMAC_TRX_MODE {
 537         HALMAC_TRX_MODE_NORMAL = 0x0,
 538         HALMAC_TRX_MODE_TRXSHARE = 0x1,
 539         HALMAC_TRX_MODE_WMM = 0x2,
 540         HALMAC_TRX_MODE_P2P = 0x3,
 541         HALMAC_TRX_MODE_LOOPBACK = 0x4,
 542         HALMAC_TRX_MODE_DELAY_LOOPBACK = 0x5,
 543         HALMAC_TRX_MODE_UNDEFINE = 0x7F,
 544 } HALMAC_TRX_MODE;
 545
 546 typedef enum _HALMAC_WIRELESS_MODE {
 547         HALMAC_WIRELESS_MODE_B = 0x0,
 548         HALMAC_WIRELESS_MODE_G = 0x1,
 549         HALMAC_WIRELESS_MODE_N = 0x2,
 550         HALMAC_WIRELESS_MODE_AC = 0x3,
 551         HALMAC_WIRELESS_MODE_UNDEFINE = 0x7F,
 552 } HALMAC_WIRELESS_MODE;
 553
 554 typedef enum _HALMAC_BW {
 555         HALMAC_BW_20 = 0x00,
 556         HALMAC_BW_40 = 0x01,
 557         HALMAC_BW_80 = 0x02,
 558         HALMAC_BW_160 = 0x03,
 559         HALMAC_BW_5 = 0x04,
 560         HALMAC_BW_10 = 0x05,
 561         HALMAC_BW_MAX = 0x06,
 562         HALMAC_BW_UNDEFINE = 0x7F,
 563 } HALMAC_BW;
 564
 565
 566 typedef enum _HALMAC_EFUSE_READ_CFG {
 567         HALMAC_EFUSE_R_AUTO = 0x00,
 568         HALMAC_EFUSE_R_DRV = 0x01,
 569         HALMAC_EFUSE_R_FW = 0x02,
 570         HALMAC_EFUSE_R_UNDEFINE = 0x7F,
 571 } HALMAC_EFUSE_READ_CFG;
 572
 573
 574 typedef struct _HALMAC_TX_DESC {
 575         u32     Dword0;
 576         u32     Dword1;
 577         u32     Dword2;
 578         u32     Dword3;
 579         u32     Dword4;
 580         u32     Dword5;
 581         u32     Dword6;
 582         u32     Dword7;
 583         u32     Dword8;
 584         u32     Dword9;
 585         u32     Dword10;
 586         u32     Dword11;
 587 } HALMAC_TX_DESC, *PHALMAC_TX_DESC;
 588
 589 typedef struct _HALMAC_RX_DESC {
 590         u32     Dword0;
 591         u32     Dword1;
 592         u32     Dword2;
 593         u32     Dword3;
 594         u32     Dword4;
 595         u32     Dword5;
 596 } HALMAC_RX_DESC, *PHALMAC_RX_DESC;
 597
 598 typedef struct _HALMAC_FWLPS_OPTION {
 599         u8      mode;
 600         u8      clk_request;
 601         u8      rlbm;
 602         u8      smart_ps;
 603         u8      awake_interval;
 604         u8      all_queue_uapsd;
 605         u8      pwr_state;
 606         u8      low_pwr_rx_beacon;
 607         u8      ant_auto_switch;
 608         u8      ps_allow_bt_high_Priority;
 609         u8      protect_bcn;
 610         u8      silence_period;
 611         u8      fast_bt_connect;
 612         u8      two_antenna_en;
 613         u8      adopt_user_Setting;
 614         u8      drv_bcn_early_shift;
 615         u8      enter_32K;
 616 } HALMAC_FWLPS_OPTION, *PHALMAC_FWLPS_OPTION;
 617
 618 typedef struct _HALMAC_FWIPS_OPTION {
 619         u8 adopt_user_Setting;
 620 } HALMAC_FWIPS_OPTION, *PHALMAC_FWIPS_OPTION;
 621
 622 typedef struct _HALMAC_WOWLAN_OPTION {
 623         u8 adopt_user_Setting;
 624 } HALMAC_WOWLAN_OPTION, *PHALMAC_WOWLAN_OPTION;
 625
 626 typedef struct _HALMAC_BCN_IE_INFO {
 627         u8      func_en;
 628         u8      size_th;
 629         u8      timeout;
 630         u8      ie_bmp[HALMAC_BCN_IE_BMP_SIZE];
 631 } HALMAC_BCN_IE_INFO, *PHALMAC_BCN_IE_INFO;
 632
 633 typedef enum _HALMAC_REG_TYPE {
 634         HALMAC_REG_TYPE_MAC = 0x0,
 635         HALMAC_REG_TYPE_BB = 0x1,
 636         HALMAC_REG_TYPE_RF = 0x2,
 637         HALMAC_REG_TYPE_UNDEFINE = 0x7F,
 638 } HALMAC_REG_TYPE;
 639
 640 typedef enum _HALMAC_PARAMETER_CMD {
 641         /* HALMAC_PARAMETER_CMD_LLT                             = 0x1, */
 642         /* HALMAC_PARAMETER_CMD_R_EFUSE                 = 0x2, */
 643         /* HALMAC_PARAMETER_CMD_EFUSE_PATCH     = 0x3, */
 644         HALMAC_PARAMETER_CMD_MAC_W8 = 0x4,
 645         HALMAC_PARAMETER_CMD_MAC_W16 = 0x5,
 646         HALMAC_PARAMETER_CMD_MAC_W32 = 0x6,
 647         HALMAC_PARAMETER_CMD_RF_W = 0x7,
 648         HALMAC_PARAMETER_CMD_BB_W8 = 0x8,
 649         HALMAC_PARAMETER_CMD_BB_W16 = 0x9,
 650         HALMAC_PARAMETER_CMD_BB_W32 = 0XA,
 651         HALMAC_PARAMETER_CMD_DELAY_US = 0X10,
 652         HALMAC_PARAMETER_CMD_DELAY_MS = 0X11,
 653         HALMAC_PARAMETER_CMD_END = 0XFF,
 654 } HALMAC_PARAMETER_CMD;
 655
 656 typedef union _HALMAC_PARAMETER_CONTENT {
 657         struct _MAC_REG_W {
 658                 u32     value;
 659                 u32     msk;
 660                 u16     offset;
 661                 u8      msk_en;
 662         } MAC_REG_W;
 663         struct _BB_REG_W {
 664                 u32     value;
 665                 u32     msk;
 666                 u16     offset;
 667                 u8      msk_en;
 668         } BB_REG_W;
 669         struct _RF_REG_W {
 670                 u32     value;
 671                 u32     msk;
 672                 u8      offset;
 673                 u8      msk_en;
 674                 u8      rf_path;
 675         } RF_REG_W;
 676         struct _DELAY_TIME {
 677                 u32     rsvd1;
 678                 u32     rsvd2;
 679                 u16     delay_time;
 680                 u8      rsvd3;
 681         } DELAY_TIME;
 682 } HALMAC_PARAMETER_CONTENT, *PHALMAC_PARAMETER_CONTENT;
 683
 684 typedef struct _HALMAC_PHY_PARAMETER_INFO {
 685         HALMAC_PARAMETER_CMD cmd_id;
 686         HALMAC_PARAMETER_CONTENT content;
 687 } HALMAC_PHY_PARAMETER_INFO, *PHALMAC_PHY_PARAMETER_INFO;
 688
 689 typedef struct _HALMAC_H2C_INFO {
 690         u16 h2c_seq_num; /* H2C sequence number */
 691         u8 in_use; /* 0 : empty 1 : used */
 692         HALMAC_H2C_RETURN_CODE  status;
 693 } HALMAC_H2C_INFO, *PHALMAC_H2C_INFO;
 694
 695 typedef struct _HALMAC_PG_EFUSE_INFO {
 696         u8 *pEfuse_map;
 697         u32     efuse_map_size;
 698         u8 *pEfuse_mask;
 699         u32 efuse_mask_size;
 700 } HALMAC_PG_EFUSE_INFO, *PHALMAC_PG_EFUSE_INFO;
 701
 702 typedef struct _HALMAC_TXAGG_BUFF_INFO {
 703         u8 *pTx_agg_buf;
 704         u8 *pCurr_pkt_buf;
 705         u32     avai_buf_size;
 706         u32     total_pkt_size;
 707         u8 agg_num;
 708 } HALMAC_TXAGG_BUFF_INFO, *PHALMAC_TXAGG_BUFF_INFO;
 709
 710 typedef struct _HALMAC_CONFIG_PARA_INFO {
 711         u32 para_buf_size; /* Parameter buffer size */
 712         u8 *pCfg_para_buf; /* Buffer for config parameter */
 713         u8 *pPara_buf_w; /* Write pointer of the parameter buffer */
 714         u32 para_num; /* Parameter numbers in parameter buffer */
 715         u32 avai_para_buf_size; /* Free size of parameter buffer */
 716         u32 offset_accumulation;
 717         u32 value_accumulation;
 718         HALMAC_DATA_TYPE data_type; /*DataType which is passed to FW*/
 719         u8 datapack_segment; /*DataPack Segment, from segment0...*/
 720         u8 full_fifo_mode; /* Used full tx fifo to save cfg parameter */
 721 } HALMAC_CONFIG_PARA_INFO, *PHALMAC_CONFIG_PARA_INFO;
 722
 723 typedef struct _HALMAC_HW_CONFIG_INFO {
 724         u32     efuse_size; /* Record efuse size */
 725         u32     eeprom_size; /* Record eeprom size */
 726         u32 bt_efuse_size; /* Record BT efuse size */
 727         u32     tx_fifo_size; /* Record tx fifo size */
 728         u32 rx_fifo_size; /* Record rx fifo size */
 729         u8 txdesc_size; /* Record tx desc size */
 730         u8 rxdesc_size; /* Record rx desc size */
 731         u8 cam_entry_num; /* Record CAM entry number */
 732 } HALMAC_HW_CONFIG_INFO, *PHALMAC_HW_CONFIG_INFO;
 733
 734 typedef struct _HALMAC_SDIO_FREE_SPACE {
 735         u16     high_queue_number; /* Free space of HIQ */
 736         u16     normal_queue_number; /* Free space of MIDQ */
 737         u16     low_queue_number; /* Free space of LOWQ */
 738         u16     public_queue_number; /* Free space of PUBQ */
 739         u16     extra_queue_number; /* Free space of EXBQ */
 740         u8 ac_oqt_number;
 741         u8 non_ac_oqt_number;
 742 } HALMAC_SDIO_FREE_SPACE, *PHALMAC_SDIO_FREE_SPACE;
 743
 744 typedef enum _HAL_FIFO_SEL {
 745         HAL_FIFO_SEL_TX,
 746         HAL_FIFO_SEL_RX,
 747         HAL_FIFO_SEL_RSVD_PAGE,
 748         HAL_FIFO_SEL_REPORT,
 749         HAL_FIFO_SEL_LLT,
 750 } HAL_FIFO_SEL;
 751
 752 typedef enum _HALMAC_DRV_INFO {
 753         HALMAC_DRV_INFO_NONE, /* No information is appended in rx_pkt */
 754         HALMAC_DRV_INFO_PHY_STATUS, /* PHY status is appended after rx_desc */
 755         HALMAC_DRV_INFO_PHY_SNIFFER, /* PHY status and sniffer info are appended after rx_desc */
 756         HALMAC_DRV_INFO_PHY_PLCP, /* PHY status and plcp header are appended after rx_desc */
 757         HALMAC_DRV_INFO_UNDEFINE,
 758 } HALMAC_DRV_INFO;
 759
 760 typedef struct _HALMAC_BT_COEX_CMD {
 761         u8 element_id;
 762         u8 op_code;
 763         u8 op_code_ver;
 764         u8 req_num;
 765         u8 data0;
 766         u8 data1;
 767         u8 data2;
 768         u8 data3;
 769         u8 data4;
 770 } HALMAC_BT_COEX_CMD, *PHALMAC_BT_COEX_CMD;
 771
 772 typedef enum _HALMAC_PRI_CH_IDX {
 773         HALMAC_CH_IDX_UNDEFINE = 0,
 774         HALMAC_CH_IDX_1 = 1,
 775         HALMAC_CH_IDX_2 = 2,
 776         HALMAC_CH_IDX_3 = 3,
 777         HALMAC_CH_IDX_4 = 4,
 778         HALMAC_CH_IDX_MAX = 5,
 779 } HALMAC_PRI_CH_IDX;
 780
 781 typedef struct _HALMAC_CH_INFO {
 782         HALMAC_CS_ACTION_ID     action_id;
 783         HALMAC_BW bw;
 784         HALMAC_PRI_CH_IDX pri_ch_idx;
 785         u8 channel;
 786         u8 timeout;
 787         u8 extra_info;
 788 } HALMAC_CH_INFO, *PHALMAC_CH_INFO;
 789
 790 typedef struct _HALMAC_CH_EXTRA_INFO {
 791         u8 extra_info;
 792         HALMAC_CS_EXTRA_ACTION_ID extra_action_id;
 793         u8 extra_info_size;
 794         u8 *extra_info_data;
 795 } HALMAC_CH_EXTRA_INFO, *PHALMAC_CH_EXTRA_INFO;
 796
 797 typedef enum _HALMAC_CS_PERIODIC_OPTION {
 798         HALMAC_CS_PERIODIC_NONE,
 799         HALMAC_CS_PERIODIC_NORMAL,
 800         HALMAC_CS_PERIODIC_2_PHASE,
 801         HALMAC_CS_PERIODIC_SEAMLESS,
 802 } HALMAC_CS_PERIODIC_OPTION;
 803
 804 typedef struct _HALMAC_CH_SWITCH_OPTION {
 805         HALMAC_BW dest_bw;
 806         HALMAC_CS_PERIODIC_OPTION periodic_option;
 807         HALMAC_PRI_CH_IDX dest_pri_ch_idx;
 808         /* u32 tsf_high; */
 809         u32 tsf_low;
 810         u8 switch_en;
 811         u8 dest_ch_en;
 812         u8 absolute_time_en;
 813         u8 dest_ch;
 814         u8 normal_period;
 815         u8 normal_cycle;
 816         u8 phase_2_period;
 817 } HALMAC_CH_SWITCH_OPTION, *PHALMAC_CH_SWITCH_OPTION;
 818
 819 typedef struct _HALMAC_FW_VERSION {
 820         u16 version;
 821         u8 sub_version;
 822         u8 sub_index;
 823 } HALMAC_FW_VERSION, *PHALMAC_FW_VERSION;
 824
 825 typedef enum _HALMAC_RF_TYPE {
 826         HALMAC_RF_1T2R = 0,
 827         HALMAC_RF_2T4R = 1,
 828         HALMAC_RF_2T2R = 2,
 829         HALMAC_RF_2T3R = 3,
 830         HALMAC_RF_1T1R = 4,
 831         HALMAC_RF_2T2R_GREEN = 5,
 832         HALMAC_RF_3T3R = 6,
 833         HALMAC_RF_3T4R = 7,
 834         HALMAC_RF_4T4R = 8,
 835         HALMAC_RF_MAX_TYPE = 0xF,
 836 } HALMAC_RF_TYPE;
 837
 838 typedef struct _HALMAC_GENERAL_INFO {
 839         u8 rfe_type;
 840         HALMAC_RF_TYPE rf_type;
 841 } HALMAC_GENERAL_INFO, *PHALMAC_GENERAL_INFO;
 842
 843 typedef struct _HALMAC_PWR_TRACKING_PARA {
 844         u8 enable;
 845         u8 tx_pwr_index;
 846         u8 pwr_tracking_offset_value;
 847         u8 tssi_value;
 848 } HALMAC_PWR_TRACKING_PARA, *PHALMAC_PWR_TRACKING_PARA;
 849
 850 typedef struct _HALMAC_PWR_TRACKING_OPTION {
 851         u8 type;
 852         u8 bbswing_index;
 853         HALMAC_PWR_TRACKING_PARA pwr_tracking_para[4]; /* pathA, pathB, pathC, pathD */
 854 } HALMAC_PWR_TRACKING_OPTION, *PHALMAC_PWR_TRACKING_OPTION;
 855
 856 typedef struct _HALMAC_NLO_CFG {
 857         u8 num_of_ssid;
 858         u8 num_of_hidden_ap;
 859         u8 rsvd[2];
 860         u32     pattern_check;
 861         u32     rsvd1;
 862         u32     rsvd2;
 863         u8 ssid_len[HALMAC_SUPPORT_NLO_NUM];
 864         u8 ChiperType[HALMAC_SUPPORT_NLO_NUM];
 865         u8 rsvd3[HALMAC_SUPPORT_NLO_NUM];
 866         u8 loc_probeReq[HALMAC_SUPPORT_PROBE_REQ_NUM];
 867         u8 rsvd4[56];
 868         u8 ssid[HALMAC_SUPPORT_NLO_NUM][HALMAC_MAX_SSID_LEN];
 869 } HALMAC_NLO_CFG, *PHALMAC_NLO_CFG;
 870
 871
 872 typedef enum _HALMAC_DATA_RATE {
 873         HALMAC_CCK1,
 874         HALMAC_CCK2,
 875         HALMAC_CCK5_5,
 876         HALMAC_CCK11,
 877         HALMAC_OFDM6,
 878         HALMAC_OFDM9,
 879         HALMAC_OFDM12,
 880         HALMAC_OFDM18,
 881         HALMAC_OFDM24,
 882         HALMAC_OFDM36,
 883         HALMAC_OFDM48,
 884         HALMAC_OFDM54,
 885         HALMAC_MCS0,
 886         HALMAC_MCS1,
 887         HALMAC_MCS2,
 888         HALMAC_MCS3,
 889         HALMAC_MCS4,
 890         HALMAC_MCS5,
 891         HALMAC_MCS6,
 892         HALMAC_MCS7,
 893         HALMAC_MCS8,
 894         HALMAC_MCS9,
 895         HALMAC_MCS10,
 896         HALMAC_MCS11,
 897         HALMAC_MCS12,
 898         HALMAC_MCS13,
 899         HALMAC_MCS14,
 900         HALMAC_MCS15,
 901         HALMAC_MCS16,
 902         HALMAC_MCS17,
 903         HALMAC_MCS18,
 904         HALMAC_MCS19,
 905         HALMAC_MCS20,
 906         HALMAC_MCS21,
 907         HALMAC_MCS22,
 908         HALMAC_MCS23,
 909         HALMAC_MCS24,
 910         HALMAC_MCS25,
 911         HALMAC_MCS26,
 912         HALMAC_MCS27,
 913         HALMAC_MCS28,
 914         HALMAC_MCS29,
 915         HALMAC_MCS30,
 916         HALMAC_MCS31,
 917         HALMAC_VHT_NSS1_MCS0,
 918         HALMAC_VHT_NSS1_MCS1,
 919         HALMAC_VHT_NSS1_MCS2,
 920         HALMAC_VHT_NSS1_MCS3,
 921         HALMAC_VHT_NSS1_MCS4,
 922         HALMAC_VHT_NSS1_MCS5,
 923         HALMAC_VHT_NSS1_MCS6,
 924         HALMAC_VHT_NSS1_MCS7,
 925         HALMAC_VHT_NSS1_MCS8,
 926         HALMAC_VHT_NSS1_MCS9,
 927         HALMAC_VHT_NSS2_MCS0,
 928         HALMAC_VHT_NSS2_MCS1,
 929         HALMAC_VHT_NSS2_MCS2,
 930         HALMAC_VHT_NSS2_MCS3,
 931         HALMAC_VHT_NSS2_MCS4,
 932         HALMAC_VHT_NSS2_MCS5,
 933         HALMAC_VHT_NSS2_MCS6,
 934         HALMAC_VHT_NSS2_MCS7,
 935         HALMAC_VHT_NSS2_MCS8,
 936         HALMAC_VHT_NSS2_MCS9,
 937         HALMAC_VHT_NSS3_MCS0,
 938         HALMAC_VHT_NSS3_MCS1,
 939         HALMAC_VHT_NSS3_MCS2,
 940         HALMAC_VHT_NSS3_MCS3,
 941         HALMAC_VHT_NSS3_MCS4,
 942         HALMAC_VHT_NSS3_MCS5,
 943         HALMAC_VHT_NSS3_MCS6,
 944         HALMAC_VHT_NSS3_MCS7,
 945         HALMAC_VHT_NSS3_MCS8,
 946         HALMAC_VHT_NSS3_MCS9,
 947         HALMAC_VHT_NSS4_MCS0,
 948         HALMAC_VHT_NSS4_MCS1,
 949         HALMAC_VHT_NSS4_MCS2,
 950         HALMAC_VHT_NSS4_MCS3,
 951         HALMAC_VHT_NSS4_MCS4,
 952         HALMAC_VHT_NSS4_MCS5,
 953         HALMAC_VHT_NSS4_MCS6,
 954         HALMAC_VHT_NSS4_MCS7,
 955         HALMAC_VHT_NSS4_MCS8,
 956         HALMAC_VHT_NSS4_MCS9
 957 } HALMAC_DATA_RATE;
 958
 959 typedef enum _HALMAC_RF_PATH {
 960         HALMAC_RF_PATH_A,
 961         HALMAC_RF_PATH_B,
 962         HALMAC_RF_PATH_C,
 963         HALMAC_RF_PATH_D
 964 } HALMAC_RF_PATH;
 965
 966 typedef enum _HALMAC_SND_PKT_SEL {
 967         HALMAC_UNI_NDPA,
 968         HALMAC_BMC_NDPA,
 969         HALMAC_NON_FINAL_BFRPRPOLL,
 970         HALMAC_FINAL_BFRPTPOLL,
 971 } HALMAC_SND_PKT_SEL;
 972
 973 #if HALMAC_PLATFORM_TESTPROGRAM
 974
 975 typedef enum _HALMAC_PWR_SEQ_ID {
 976         HALMAC_PWR_SEQ_ENABLE,
 977         HALMAC_PWR_SEQ_DISABLE,
 978         HALMAC_PWR_SEQ_ENTER_LPS,
 979         HALMAC_PWR_SEQ_ENTER_DEEP_LPS,
 980         HALMAC_PWR_SEQ_LEAVE_LPS,
 981         HALMAC_PWR_SEQ_MAX
 982 } HALMAC_PWR_SEQ_ID;
 983
 984 typedef enum _HAL_TX_ID {
 985         HAL_TX_ID_VO,
 986         HAL_TX_ID_VI,
 987         HAL_TX_ID_BE,
 988         HAL_TX_ID_BK,
 989         HAL_TX_ID_BCN,
 990         HAL_TX_ID_H2C,
 991         HAL_TX_ID_MAX
 992 } HAL_TX_ID;
 993
 994 typedef enum _HAL_QSEL {
 995         HAL_QSEL_TID0,
 996         HAL_QSEL_TID1,
 997         HAL_QSEL_TID2,
 998         HAL_QSEL_TID3,
 999         HAL_QSEL_TID4,
1000         HAL_QSEL_TID5,
1001         HAL_QSEL_TID6,
1002         HAL_QSEL_TID7,
1003
1004         HAL_QSEL_BEACON = 0x10,
1005         HAL_QSEL_HIGH = 0x11,
1006         HAL_QSEL_MGT = 0x12,
1007         HAL_QSEL_CMD = 0x13
1008 } HAL_QSEL;
1009
1010 typedef enum _HAL_RTS_MODE {
1011         HAL_RTS_MODE_NONE,
1012         HAL_RTS_MODE_CTS2SELF,
1013         HAL_RTS_MODE_RTS,
1014 } HAL_RTS_MODE;
1015
1016 typedef enum _HAL_DATA_BW {
1017         HAL_DATA_BW_20M,
1018         HAL_DATA_BW_40M,
1019         HAL_DATA_BW_80M,
1020         HAL_DATA_BW_160M,
1021 } HAL_DATA_BW;
1022
1023 typedef enum _HAL_RTS_SHORT {
1024         HAL_RTS_SHORT_SHORT,
1025         HAL_RTS_SHORT_LONG,
1026 } HAL_RTS_SHORT;
1027
1028 typedef enum _HAL_SECURITY_TYPE {
1029         HAL_SECURITY_TYPE_NONE = 0,
1030         HAL_SECURITY_TYPE_WEP40 = 1,
1031         HAL_SECURITY_TYPE_WEP104 = 2,
1032         HAL_SECURITY_TYPE_TKIP = 3,
1033         HAL_SECURITY_TYPE_AES128 = 4,
1034         HAL_SECURITY_TYPE_WAPI = 5,
1035         HAL_SECURITY_TYPE_AES256 = 6,
1036         HAL_SECURITY_TYPE_GCMP128 = 7,
1037         HAL_SECURITY_TYPE_GCMP256 = 8,
1038         HAL_SECURITY_TYPE_GCMSMS4 = 9,
1039         HAL_SECURITY_TYPE_BIP = 10,
1040         HAL_SECURITY_TYPE_UNDEFINE = 0x7F,
1041 } HAL_SECURITY_TYPE;
1042
1043 typedef enum _HAL_SECURITY_METHOD {
1044         HAL_SECURITY_METHOD_HW = 0,
1045         HAL_SECURITY_METHOD_SW = 1,
1046         HAL_SECURITY_METHOD_UNDEFINE = 0x7F,
1047 } HAL_SECURITY_METHOD;
1048
1049 typedef struct _HAL_SECURITY_INFO {
1050         HAL_SECURITY_TYPE type;
1051         HAL_SECURITY_METHOD tx_method;
1052         HAL_SECURITY_METHOD     rx_method;
1053 } HAL_SECURITY_INFO, *PHAL_SECURITY_INFO;
1054
1055 typedef struct _HAL_TXDESC_INFO {
1056         u32 txdesc_length;
1057         u32 packet_size; /* payload + wlheader */
1058         HAL_TX_ID tx_id;
1059         HALMAC_DATA_RATE data_rate;
1060         HAL_RTS_MODE rts_mode;
1061         HAL_DATA_BW data_bw;
1062         HAL_RTS_SHORT rts_short;
1063         HAL_SECURITY_TYPE security_type;
1064         HAL_SECURITY_METHOD encryption_method;
1065         u16 seq_num;
1066         u8 retry_limit_en;
1067         u8 retry_limit_number;
1068         u8 rts_threshold;
1069         u8 qos;
1070         u8 ht;
1071         u8 ampdu;
1072         u8 early_mode;
1073         u8 bm_cast;
1074         u8 data_short;
1075         u8 mac_id;
1076 } HAL_TXDESC_INFO, *PHAL_TXDESC_INFO;
1077
1078 typedef struct _HAL_RXDESC_INFO {
1079         u8 c2h;
1080         u8 *pWifi_pkt;
1081         u32     packet_size;
1082         u8 crc_err;
1083         u8 icv_err;
1084 } HAL_RXDESC_INFO, *PHAL_RXDESC_INFO;
1085
1086 typedef struct _HAL_TXDESC_PARSER {
1087         u8 txdesc_len;
1088         u16     txpkt_size;
1089 } HAL_TXDESC_PARSER, *PHAL_TXDESC_PARSER;
1090
1091 typedef struct _HAL_RXDESC_PARSER {
1092         u32 driver_info_size;
1093         u16     rxpkt_size;
1094         u8 rxdesc_len;
1095         u8 c2h;
1096         u8 crc_err;
1097         u8 icv_err;
1098 } HAL_RXDESC_PARSER, *PHAL_RXDESC_PARSER;
1099
1100 typedef struct _HAL_RF_REG_INFO {
1101         HALMAC_RF_PATH rf_path;
1102         u32 offset;
1103         u32 bit_mask;
1104         u32 data;
1105 } HAL_RF_REG_INFO, *PHAL_RF_REG_INFO;
1106
1107 typedef struct _HALMAC_SDIO_HIMR_INFO {
1108         u8 rx_request;
1109         u8 aval_msk;
1110 } HALMAC_SDIO_HIMR_INFO, *PHALMAC_SDIO_HIMR_INFO;
1111
1112 typedef struct _HALMAC_BEACON_INFO {
1113 } HALMAC_BEACON_INFO, *PHALMAC_BEACON_INFO;
1114
1115 typedef struct _HALMAC_MGNT_INFO {
1116         u8 mu_enable;
1117         u8 bip;
1118         u8 unicast;
1119         u32     packet_size;
1120 } HALMAC_MGNT_INFO, *PHALMAC_MGNT_INFO;
1121
1122 typedef struct _HALMAC_CTRL_INFO {
1123         u8 snd_enable;
1124         HALMAC_SND_PKT_SEL snd_pkt_sel; /* 0:unicast ndpa 1:broadcast ndpa 3:non-final BF Rpt Poll 4:final BF Rpt Poll */
1125         u8 *pPacket_desc;
1126         u32 desc_size;
1127         u16 seq_num;
1128         u8 bw;
1129         u16 paid;
1130 } HALMAC_CTRL_INFO, *PHALMAC_CTRL_INFO;
1131
1132 typedef struct _HALMAC_HIGH_QUEUE_INFO {
1133         u8 *pPacket_desc;
1134         u32     desc_size;
1135 } HALMAC_HIGH_QUEUE_INFO, *PHALMAC_HIGH_QUEUE_INFO;
1136
1137 typedef struct _HALMAC_CHIP_TYPE {
1138         HALMAC_CHIP_ID chip_id;
1139         HALMAC_CHIP_VER chip_version;
1140 } HALMAC_CHIP_TYPE, *PHALMAC_CHIP_TYPE;
1141
1142 typedef struct _HALMAC_CAM_ENTRY_FORMAT {
1143         u16     key_id : 2;
1144         u16     type : 3;
1145         u16     mic : 1;
1146         u16     grp : 1;
1147         u16     spp_mode : 1;
1148         u16     rpt_md : 1;
1149         u16     ext_sectype : 1;
1150         u16 mgnt : 1;
1151         u16     rsvd1 : 4;
1152         u16 valid : 1;
1153         u8 mac_address[6];
1154         u32     key[4];
1155         u32     rsvd[2];
1156 } HALMAC_CAM_ENTRY_FORMAT, *PHALMAC_CAM_ENTRY_FORMAT;
1157
1158 typedef struct _HALMAC_CAM_ENTRY_INFO {
1159         HAL_SECURITY_TYPE security_type;
1160         u32 key[4];
1161         u32 key_ext[4];
1162         u8 mac_address[6];
1163         u8 unicast;
1164         u8 key_id;
1165         u8 valid;
1166 } HALMAC_CAM_ENTRY_INFO, *PHALMAC_CAM_ENTRY_INFO;
1167
1168 #endif /* End of test program */
1169
1170 typedef enum _HALMAC_DBG_MSG_INFO {
1171         HALMAC_DBG_ERR,
1172         HALMAC_DBG_WARN,
1173         HALMAC_DBG_TRACE,
1174 } HALMAC_DBG_MSG_INFO;
1175
1176 typedef enum _HALMAC_DBG_MSG_TYPE {
1177         HALMAC_MSG_INIT,
1178         HALMAC_MSG_EFUSE,
1179         HALMAC_MSG_FW,
1180         HALMAC_MSG_H2C,
1181         HALMAC_MSG_PWR,
1182         HALMAC_MSG_SND,
1183         HALMAC_MSG_COMMON,
1184 } HALMAC_DBG_MSG_TYPE;
1185
1186 typedef enum _HALMAC_CMD_PROCESS_STATUS {
1187         HALMAC_CMD_PROCESS_IDLE = 0x01,                 /* Init status */
1188         HALMAC_CMD_PROCESS_SENDING = 0x02,              /* Wait ack */
1189         HALMAC_CMD_PROCESS_RCVD = 0x03,                 /* Rcvd ack */
1190         HALMAC_CMD_PROCESS_DONE = 0x04,                 /* Event done */
1191         HALMAC_CMD_PROCESS_ERROR = 0x05,                /* Return code error */
1192         HALMAC_CMD_PROCESS_UNDEFINE = 0x7F,
1193 } HALMAC_CMD_PROCESS_STATUS;
1194
1195 typedef enum _HALMAC_FEATURE_ID {
1196         HALMAC_FEATURE_CFG_PARA,                /* Support */
1197         HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE,     /* Support */
1198         HALMAC_FEATURE_DUMP_LOGICAL_EFUSE,      /* Support */
1199         HALMAC_FEATURE_UPDATE_PACKET,           /* Support */
1200         HALMAC_FEATURE_UPDATE_DATAPACK,
1201         HALMAC_FEATURE_RUN_DATAPACK,
1202         HALMAC_FEATURE_CHANNEL_SWITCH,  /* Support */
1203         HALMAC_FEATURE_IQK,             /* Support */
1204         HALMAC_FEATURE_POWER_TRACKING,  /* Support */
1205         HALMAC_FEATURE_PSD,             /* Support */
1206         HALMAC_FEATURE_ALL,             /* Support, only for reset */
1207 } HALMAC_FEATURE_ID;
1208
1209 typedef enum _HALMAC_DRV_RSVD_PG_NUM {
1210         HALMAC_RSVD_PG_NUM16,   /* 2K */
1211         HALMAC_RSVD_PG_NUM24,   /* 3K */
1212         HALMAC_RSVD_PG_NUM32,   /* 4K */
1213 } HALMAC_DRV_RSVD_PG_NUM;
1214
1215
1216 /* Platform API setting */
1217 typedef struct _HALMAC_PLATFORM_API {
1218         /* R/W register */
1219         u8 (*SDIO_CMD52_READ)(VOID *pDriver_adapter, u32 offset);
1220         u8 (*SDIO_CMD53_READ_8)(VOID *pDriver_adapter, u32 offset);
1221         u16 (*SDIO_CMD53_READ_16)(VOID *pDriver_adapter, u32 offset);
1222         u32 (*SDIO_CMD53_READ_32)(VOID *pDriver_adapter, u32 offset);
1223         VOID (*SDIO_CMD52_WRITE)(VOID *pDriver_adapter, u32 offset, u8 value);
1224         VOID (*SDIO_CMD53_WRITE_8)(VOID *pDriver_adapter, u32 offset, u8 value);
1225         VOID (*SDIO_CMD53_WRITE_16)(VOID *pDriver_adapter, u32 offset, u16 value);
1226         VOID (*SDIO_CMD53_WRITE_32)(VOID *pDriver_adapter, u32 offset, u32 value);
1227         u8 (*REG_READ_8)(VOID *pDriver_adapter, u32 offset);
1228         u16 (*REG_READ_16)(VOID *pDriver_adapter, u32 offset);
1229         u32 (*REG_READ_32)(VOID *pDriver_adapter, u32 offset);
1230         VOID (*REG_WRITE_8)(VOID *pDriver_adapter, u32 offset, u8 value);
1231         VOID (*REG_WRITE_16)(VOID *pDriver_adapter, u32 offset, u16 value);
1232         VOID (*REG_WRITE_32)(VOID *pDriver_adapter, u32 offset, u32 value);
1233
1234         /* send pBuf to reserved page, the tx_desc is not included in pBuf, driver need to fill tx_desc with qsel = bcn */
1235         u8 (*SEND_RSVD_PAGE)(VOID *pDriver_adapter, u8 *pBuf, u32 size);
1236         /* send pBuf to h2c queue, the tx_desc is not included in pBuf, driver need to fill tx_desc with qsel = h2c */
1237         u8 (*SEND_H2C_PKT)(VOID *pDriver_adapter, u8 *pBuf, u32 size);
1238
1239         u8 (*RTL_FREE)(VOID *pDriver_adapter, VOID *pBuf, u32 size);
1240         VOID* (*RTL_MALLOC)(VOID *pDriver_adapter, u32 size);
1241         u8 (*RTL_MEMCPY)(VOID *pDriver_adapter, VOID *dest, VOID *src, u32 size);
1242         u8 (*RTL_MEMSET)(VOID *pDriver_adapter, VOID *pAddress, u8 value, u32 size);
1243         VOID (*RTL_DELAY_US)(VOID *pDriver_adapter, u32 us);
1244
1245         u8 (*MUTEX_INIT)(VOID *pDriver_adapter, HALMAC_MUTEX *pMutex);
1246         u8 (*MUTEX_DEINIT)(VOID *pDriver_adapter, HALMAC_MUTEX *pMutex);
1247         u8 (*MUTEX_LOCK)(VOID *pDriver_adapter, HALMAC_MUTEX *pMutex);
1248         u8 (*MUTEX_UNLOCK)(VOID *pDriver_adapter, HALMAC_MUTEX *pMutex);
1249
1250         u8 (*MSG_PRINT)(VOID *pDriver_adapter, u32 msg_type, u8 msg_level, s8 *fmt, ...);
1251
1252         u8 (*EVENT_INDICATION)(VOID *pDriver_adapter, HALMAC_FEATURE_ID feature_id, HALMAC_CMD_PROCESS_STATUS process_status, u8 *buf, u32 size);
1253
1254 #if HALMAC_PLATFORM_TESTPROGRAM
1255         VOID* (*PCI_ALLOC_COMM_BUFF)(VOID *pDriver_adapter, u32 size, u32 *physical_addr, u8 cache_en);
1256         VOID (*PCI_FREE_COMM_BUFF)(VOID *pDriver_adapter, u32 size, u32 physical_addr, VOID *virtual_addr, u8 cache_en);
1257         u8 (*WRITE_DATA_SDIO_ADDR)(VOID *pDriver_adapter, u8 *pBuf, u32 size, u32 addr);
1258         u8 (*WRITE_DATA_USB_BULKOUT_ID)(VOID *pDriver_adapter, u8 *pBuf, u32 size, u8 bulkout_id);
1259         u8 (*WRITE_DATA_PCIE_QUEUE)(VOID *pDriver_adapter, u8 *pBuf, u32 size, u8 queue);
1260         u8 (*READ_DATA)(VOID *pDriver_adapter, u8 *pBuf, u32 *read_length);
1261 #endif
1262 } HALMAC_PLATFORM_API, *PHALMAC_PLATFORM_API;
1263
1264 /*1->Little endian 0->Big endian*/
1265 #if HALMAC_SYSTEM_ENDIAN
1266
1267 /* User can not use members in Address_L_H, use Address[6] is mandatory */
1268 typedef union _HALMAC_WLAN_ADDR {
1269         u8 Address[6]; /* WLAN address (MACID, BSSID, Brodcast ID). Address[0] is lowest, Address[5] is highest*/
1270         struct {
1271                 union {
1272                         u32     Address_Low;
1273                         u8 Address_Low_B[4];
1274                 };
1275                 union {
1276                         u16     Address_High;
1277                         u8 Address_High_B[2];
1278                 };
1279         } Address_L_H;
1280 } HALMAC_WLAN_ADDR, *PHALMAC_WLAN_ADDR;
1281
1282 #else
1283
1284 /* User can not use members in Address_L_H, use Address[6] is mandatory */
1285 typedef union _HALMAC_WLAN_ADDR {
1286         u8 Address[6]; /* WLAN address (MACID, BSSID, Brodcast ID). Address[0] is lowest, Address[5] is highest*/
1287         struct {
1288                 union {
1289                         u32     Address_Low;
1290                         u8 Address_Low_B[4];
1291                 };
1292                 union {
1293                         u16     Address_High;
1294                         u8 Address_High_B[2];
1295                 };
1296         } Address_L_H;
1297 } HALMAC_WLAN_ADDR, *PHALMAC_WLAN_ADDR;
1298
1299 #endif
1300
1301 typedef enum _HALMAC_SND_ROLE {
1302         HAL_BFER = 0,
1303         HAL_BFEE = 1,
1304 } HALMAC_SND_ROLE;
1305
1306 typedef enum _HALMAC_CSI_SEG_LEN {
1307         HAL_CSI_SEG_4K = 0,
1308         HAL_CSI_SEG_8K = 1,
1309         HAL_CSI_SEG_11K = 2,
1310 } HALMAC_CSI_SEG_LEN;
1311
1312
1313 typedef struct _HALMAC_CFG_MUMIMO_PARA {
1314         HALMAC_SND_ROLE role;
1315         u8 sounding_sts[6];
1316         u16 grouping_bitmap;
1317         u8 mu_tx_en;
1318         u32 given_gid_tab[2];
1319         u32 given_user_pos[4];
1320 } HALMAC_CFG_MUMIMO_PARA, *PHALMAC_CFG_MUMIMO_PARA;
1321
1322 typedef struct _HALMAC_SU_BFER_INIT_PARA {
1323         u8 userid;
1324         u16 paid;
1325         u16 csi_para;
1326         PHALMAC_WLAN_ADDR pbfer_address;
1327 } HALMAC_SU_BFER_INIT_PARA, *PHALMAC_SU_BFER_INIT_PARA;
1328
1329 typedef struct _HALMAC_MU_BFEE_INIT_PARA {
1330         u8 userid;
1331         u16 paid;
1332         u32 user_position_l;
1333         u32 user_position_h;
1334 } HALMAC_MU_BFEE_INIT_PARA, *PHALMAC_MU_BFEE_INIT_PARA;
1335
1336 typedef struct _HALMAC_MU_BFER_INIT_PARA {
1337         u16 paid;
1338         u16 csi_para;
1339         u16 my_aid;
1340         HALMAC_CSI_SEG_LEN csi_length_sel;
1341         PHALMAC_WLAN_ADDR pbfer_address;
1342 } HALMAC_MU_BFER_INIT_PARA, *PHALMAC_MU_BFER_INIT_PARA;
1343
1344 typedef struct _HALMAC_SND_INFO {
1345         u16 paid;
1346         u8 userid;
1347         HALMAC_DATA_RATE ndpa_rate;
1348         u16 csi_para;
1349         u16 my_aid;
1350         HALMAC_DATA_RATE csi_rate;
1351         HALMAC_CSI_SEG_LEN csi_length_sel;
1352         HALMAC_SND_ROLE role;
1353         HALMAC_WLAN_ADDR bfer_address;
1354         HALMAC_BW bw;
1355         u8 txbf_en;
1356         PHALMAC_SU_BFER_INIT_PARA pSu_bfer_init;
1357         PHALMAC_MU_BFER_INIT_PARA pMu_bfer_init;
1358         PHALMAC_MU_BFEE_INIT_PARA pMu_bfee_init;
1359 } HALMAC_SND_INFO, *PHALMAC_SND_INFO;
1360
1361 typedef struct _HALMAC_CS_INFO {
1362         u8 *ch_info_buf;
1363         u8 *ch_info_buf_w;
1364         u8 extra_info_en;
1365         u32     buf_size;       /* buffer size */
1366         u32     avai_buf_size;  /* buffer size */
1367         u32     total_size;
1368         u32     accu_timeout;
1369         u32     ch_num;
1370 } HALMAC_CS_INFO, *PHALMAC_CS_INFO;
1371
1372 typedef struct _HALMAC_RESTORE_INFO {
1373         u32     mac_register;
1374         u32     value;
1375         u8 length;
1376 } HALMAC_RESTORE_INFO, *PHALMAC_RESTORE_INFO;
1377
1378 typedef struct _HALMAC_EVENT_TRIGGER {
1379         u32     physical_efuse_map : 1;
1380         u32     logical_efuse_map : 1;
1381         u32     rsvd1 : 28;
1382 } HALMAC_EVENT_TRIGGER, *PHALMAC_EVENT_TRIGGER;
1383
1384 typedef struct _HALMAC_H2C_HEADER_INFO {
1385         u16     sub_cmd_id;
1386         u16     content_size;
1387         u8 ack;
1388 } HALMAC_H2C_HEADER_INFO, *PHALMAC_H2C_HEADER_INFO;
1389
1390 typedef enum _HALMAC_DLFW_STATE {
1391         HALMAC_DLFW_NONE = 0,
1392         HALMAC_DLFW_DONE = 1,
1393         HALMAC_GEN_INFO_SENT = 2,
1394         HALMAC_DLFW_UNDEFINED = 0x7F,
1395 } HALMAC_DLFW_STATE;
1396
1397 typedef enum _HALMAC_EFUSE_CMD_CONSTRUCT_STATE {
1398         HALMAC_EFUSE_CMD_CONSTRUCT_IDLE = 0,
1399         HALMAC_EFUSE_CMD_CONSTRUCT_BUSY = 1,
1400         HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT = 2,
1401         HALMAC_EFUSE_CMD_CONSTRUCT_STATE_NUM = 3,
1402         HALMAC_EFUSE_CMD_CONSTRUCT_UNDEFINED = 0x7F,
1403 } HALMAC_EFUSE_CMD_CONSTRUCT_STATE;
1404
1405 typedef enum _HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE {
1406         HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE = 0,
1407         HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING = 1,
1408         HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT = 2,
1409         HALMAC_CFG_PARA_CMD_CONSTRUCT_NUM = 3,
1410         HALMAC_CFG_PARA_CMD_CONSTRUCT_UNDEFINED = 0x7F,
1411 } HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE;
1412
1413 typedef enum _HALMAC_SCAN_CMD_CONSTRUCT_STATE {
1414         HALMAC_SCAN_CMD_CONSTRUCT_IDLE = 0,
1415         HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED = 1,
1416         HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING = 2,
1417         HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT = 3,
1418         HALMAC_SCAN_CMD_CONSTRUCT_STATE_NUM = 4,
1419         HALMAC_SCAN_CMD_CONSTRUCT_UNDEFINED = 0x7F,
1420 } HALMAC_SCAN_CMD_CONSTRUCT_STATE;
1421
1422 typedef enum _HALMAC_API_STATE {
1423         HALMAC_API_STATE_INIT = 0,
1424         HALMAC_API_STATE_HALT = 1,
1425         HALMAC_API_STATE_UNDEFINED = 0x7F,
1426 } HALMAC_API_STATE;
1427
1428 typedef struct _HALMAC_EFUSE_STATE_SET {
1429         HALMAC_EFUSE_CMD_CONSTRUCT_STATE efuse_cmd_construct_state;
1430         HALMAC_CMD_PROCESS_STATUS process_status;
1431         u8 fw_return_code;
1432         u16 seq_num;
1433 } HALMAC_EFUSE_STATE_SET, *PHALMAC_EFUSE_STATE_SET;
1434
1435 typedef struct _HALMAC_CFG_PARA_STATE_SET {
1436         HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE cfg_para_cmd_construct_state;
1437         HALMAC_CMD_PROCESS_STATUS process_status;
1438         u8 fw_return_code;
1439         u16 seq_num;
1440 } HALMAC_CFG_PARA_STATE_SET, *PHALMAC_CFG_PARA_STATE_SET;
1441
1442 typedef struct _HALMAC_SCAN_STATE_SET {
1443         HALMAC_SCAN_CMD_CONSTRUCT_STATE scan_cmd_construct_state;
1444         HALMAC_CMD_PROCESS_STATUS process_status;
1445         u8 fw_return_code;
1446         u16 seq_num;
1447 } HALMAC_SCAN_STATE_SET, *PHALMAC_SCAN_STATE_SET;
1448
1449 typedef struct _HALMAC_UPDATE_PACKET_STATE_SET {
1450         HALMAC_CMD_PROCESS_STATUS process_status;
1451         u8 fw_return_code;
1452         u16 seq_num;
1453 } HALMAC_UPDATE_PACKET_STATE_SET, *PHALMAC_UPDATE_PACKET_STATE_SET;
1454
1455 typedef struct _HALMAC_IQK_STATE_SET {
1456         HALMAC_CMD_PROCESS_STATUS process_status;
1457         u8 fw_return_code;
1458         u16 seq_num;
1459 } HALMAC_IQK_STATE_SET, *PHALMAC_IQK_STATE_SET;
1460
1461 typedef struct _HALMAC_POWER_TRACKING_STATE_SET {
1462         HALMAC_CMD_PROCESS_STATUS       process_status;
1463         u8 fw_return_code;
1464         u16 seq_num;
1465 } HALMAC_POWER_TRACKING_STATE_SET, *PHALMAC_POWER_TRACKING_STATE_SET;
1466
1467 typedef struct _HALMAC_PSD_STATE_SET {
1468         HALMAC_CMD_PROCESS_STATUS process_status;
1469         u16 data_size;
1470         u16 segment_size;
1471         u8 *pData;
1472         u8 fw_return_code;
1473         u16 seq_num;
1474 } HALMAC_PSD_STATE_SET, *PHALMAC_PSD_STATE_SET;
1475
1476 typedef struct _HALMAC_STATE {
1477         HALMAC_EFUSE_STATE_SET efuse_state_set; /* State machine + cmd process status */
1478         HALMAC_CFG_PARA_STATE_SET cfg_para_state_set; /* State machine + cmd process status */
1479         HALMAC_SCAN_STATE_SET scan_state_set; /* State machine + cmd process status */
1480         HALMAC_UPDATE_PACKET_STATE_SET update_packet_set; /* cmd process status */
1481         HALMAC_IQK_STATE_SET iqk_set; /* cmd process status */
1482         HALMAC_POWER_TRACKING_STATE_SET power_tracking_set; /* cmd process status */
1483         HALMAC_PSD_STATE_SET psd_set; /* cmd process status */
1484         HALMAC_API_STATE api_state; /* Halmac api state */
1485         HALMAC_MAC_POWER mac_power; /* 0 : power off, 1 : power on*/
1486         HALMAC_PS_STATE ps_state; /* power saving state */
1487         HALMAC_DLFW_STATE dlfw_state; /* download FW state */
1488 } HALMAC_STATE, *PHALMAC_STATE;
1489
1490 typedef struct _HALMAC_VER {
1491         u8 major_ver;
1492         u8 prototype_ver;
1493         u8 minor_ver;
1494 } HALMAC_VER, *PHALMAC_VER;
1495
1496
1497 typedef enum _HALMAC_API_ID {
1498         /*stuff, need to be the 1st*/
1499         HALMAC_API_STUFF = 0x0,
1500         /*stuff, need to be the 1st*/
1501         HALMAC_API_MAC_POWER_SWITCH = 0x1,
1502         HALMAC_API_DOWNLOAD_FIRMWARE = 0x2,
1503         HALMAC_API_CFG_MAC_ADDR = 0x3,
1504         HALMAC_API_CFG_BSSID = 0x4,
1505         HALMAC_API_CFG_MULTICAST_ADDR = 0x5,
1506         HALMAC_API_PRE_INIT_SYSTEM_CFG = 0x6,
1507         HALMAC_API_INIT_SYSTEM_CFG = 0x7,
1508         HALMAC_API_INIT_TRX_CFG = 0x8,
1509         HALMAC_API_CFG_RX_AGGREGATION = 0x9,
1510         HALMAC_API_INIT_PROTOCOL_CFG = 0xA,
1511         HALMAC_API_INIT_EDCA_CFG = 0xB,
1512         HALMAC_API_CFG_OPERATION_MODE = 0xC,
1513         HALMAC_API_CFG_CH_BW = 0xD,
1514         HALMAC_API_CFG_BW = 0xE,
1515         HALMAC_API_INIT_WMAC_CFG = 0xF,
1516         HALMAC_API_INIT_MAC_CFG = 0x10,
1517         HALMAC_API_INIT_SDIO_CFG = 0x11,
1518         HALMAC_API_INIT_USB_CFG = 0x12,
1519         HALMAC_API_INIT_PCIE_CFG = 0x13,
1520         HALMAC_API_INIT_INTERFACE_CFG = 0x14,
1521         HALMAC_API_DEINIT_SDIO_CFG = 0x15,
1522         HALMAC_API_DEINIT_USB_CFG = 0x16,
1523         HALMAC_API_DEINIT_PCIE_CFG = 0x17,
1524         HALMAC_API_DEINIT_INTERFACE_CFG = 0x18,
1525         HALMAC_API_GET_EFUSE_SIZE = 0x19,
1526         HALMAC_API_DUMP_EFUSE_MAP = 0x1A,
1527         HALMAC_API_WRITE_EFUSE = 0x1B,
1528         HALMAC_API_READ_EFUSE = 0x1C,
1529         HALMAC_API_GET_LOGICAL_EFUSE_SIZE = 0x1D,
1530         HALMAC_API_DUMP_LOGICAL_EFUSE_MAP = 0x1E,
1531         HALMAC_API_WRITE_LOGICAL_EFUSE = 0x1F,
1532         HALMAC_API_READ_LOGICAL_EFUSE = 0x20,
1533         HALMAC_API_PG_EFUSE_BY_MAP = 0x21,
1534         HALMAC_API_GET_C2H_INFO = 0x22,
1535         HALMAC_API_CFG_FWLPS_OPTION = 0x23,
1536         HALMAC_API_CFG_FWIPS_OPTION = 0x24,
1537         HALMAC_API_ENTER_WOWLAN = 0x25,
1538         HALMAC_API_LEAVE_WOWLAN = 0x26,
1539         HALMAC_API_ENTER_PS = 0x27,
1540         HALMAC_API_LEAVE_PS = 0x28,
1541         HALMAC_API_H2C_LB = 0x29,
1542         HALMAC_API_DEBUG = 0x2A,
1543         HALMAC_API_CFG_PARAMETER = 0x2B,
1544         HALMAC_API_UPDATE_PACKET = 0x2C,
1545         HALMAC_API_BCN_IE_FILTER = 0x2D,
1546         HALMAC_API_REG_READ_8 = 0x2E,
1547         HALMAC_API_REG_WRITE_8 = 0x2F,
1548         HALMAC_API_REG_READ_16 = 0x30,
1549         HALMAC_API_REG_WRITE_16 = 0x31,
1550         HALMAC_API_REG_READ_32 = 0x32,
1551         HALMAC_API_REG_WRITE_32 = 0x33,
1552         HALMAC_API_TX_ALLOWED_SDIO = 0x34,
1553         HALMAC_API_SET_BULKOUT_NUM = 0x35,
1554         HALMAC_API_GET_SDIO_TX_ADDR = 0x36,
1555         HALMAC_API_GET_USB_BULKOUT_ID = 0x37,
1556         HALMAC_API_TIMER_2S = 0x38,
1557         HALMAC_API_FILL_TXDESC_CHECKSUM = 0x39,
1558         HALMAC_API_SEND_ORIGINAL_H2C = 0x3A,
1559         HALMAC_API_UPDATE_DATAPACK = 0x3B,
1560         HALMAC_API_RUN_DATAPACK = 0x3C,
1561         HALMAC_API_CFG_DRV_INFO = 0x3D,
1562         HALMAC_API_SEND_BT_COEX = 0x3E,
1563         HALMAC_API_VERIFY_PLATFORM_API = 0x3F,
1564         HALMAC_API_GET_FIFO_SIZE = 0x40,
1565         HALMAC_API_DUMP_FIFO = 0x41,
1566         HALMAC_API_CFG_TXBF = 0x42,
1567         HALMAC_API_CFG_MUMIMO = 0x43,
1568         HALMAC_API_CFG_SOUNDING = 0x44,
1569         HALMAC_API_DEL_SOUNDING = 0x45,
1570         HALMAC_API_SU_BFER_ENTRY_INIT = 0x46,
1571         HALMAC_API_SU_BFEE_ENTRY_INIT = 0x47,
1572         HALMAC_API_MU_BFER_ENTRY_INIT = 0x48,
1573         HALMAC_API_MU_BFEE_ENTRY_INIT = 0x49,
1574         HALMAC_API_SU_BFER_ENTRY_DEL = 0x4A,
1575         HALMAC_API_SU_BFEE_ENTRY_DEL = 0x4B,
1576         HALMAC_API_MU_BFER_ENTRY_DEL = 0x4C,
1577         HALMAC_API_MU_BFEE_ENTRY_DEL = 0x4D,
1578
1579         HALMAC_API_ADD_CH_INFO = 0x4E,
1580         HALMAC_API_ADD_EXTRA_CH_INFO = 0x4F,
1581         HALMAC_API_CTRL_CH_SWITCH = 0x50,
1582         HALMAC_API_CLEAR_CH_INFO = 0x51,
1583
1584         HALMAC_API_SEND_GENERAL_INFO = 0x52,
1585         HALMAC_API_START_IQK = 0x53,
1586         HALMAC_API_CTRL_PWR_TRACKING = 0x54,
1587         HALMAC_API_PSD = 0x55,
1588         HALMAC_API_CFG_TX_AGG_ALIGN = 0x56,
1589
1590         HALMAC_API_QUERY_STATE = 0x57,
1591         HALMAC_API_RESET_FEATURE = 0x58,
1592         HALMAC_API_CHECK_FW_STATUS = 0x59,
1593         HALMAC_API_DUMP_FW_DMEM = 0x5A,
1594         HALMAC_API_CFG_MAX_DL_SIZE = 0x5B,
1595
1596         HALMAC_API_INIT_OBJ = 0x5C,
1597         HALMAC_API_DEINIT_OBJ = 0x5D,
1598         HALMAC_API_CFG_LA_MODE = 0x5E,
1599         HALMAC_API_GET_HW_VALUE = 0x5F,
1600         HALMAC_API_SET_HW_VALUE = 0x60,
1601         HALMAC_API_CFG_DRV_RSVD_PG_NUM = 0x61,
1602         HALMAC_API_SWITCH_EFUSE_BANK = 0x62,
1603         HALMAC_API_WRITE_EFUSE_BT = 0x63,
1604         HALMAC_API_DUMP_EFUSE_MAP_BT = 0x64,
1605         HALMAC_API_MAX
1606 } HALMAC_API_ID;
1607
1608
1609 typedef struct _HALMAC_API_RECORD {
1610         HALMAC_API_ID api_array[API_ARRAY_SIZE];
1611         u8 array_wptr;
1612 } HALMAC_API_RECORD, *PHALMAC_API_RECORD;
1613
1614 typedef enum _HALMAC_LA_MODE {
1615         HALMAC_LA_MODE_DISABLE = 0,
1616         HALMAC_LA_MODE_PARTIAL = 1,
1617         HALMAC_LA_MODE_FULL = 2,
1618         HALMAC_LA_MODE_UNDEFINE = 0x7F,
1619 } HALMAC_LA_MODE;
1620
1621 typedef enum _HALMAC_USB_MODE {
1622         HALMAC_USB_MODE_U2 = 1,
1623         HALMAC_USB_MODE_U3 = 2,
1624 } HALMAC_USB_MODE;
1625
1626 typedef enum _HALMAC_HW_ID {
1627         HALMAC_HW_RQPN_MAPPING = 0,
1628         HALMAC_HW_EFUSE_SIZE = 1,
1629         HALMAC_HW_EEPROM_SIZE = 2,
1630         HALMAC_HW_TXFIFO_SIZE = 3,
1631         HALMAC_HW_RSVD_PG_BNDY = 4,
1632         HALMAC_HW_CAM_ENTRY_NUM = 5,
1633         HALMAC_HW_HRPWM = 6,
1634         HALMAC_HW_HCPWM = 7,
1635         HALMAC_HW_HRPWM2 = 8,
1636         HALMAC_HW_HCPWM2 = 9,
1637         HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE = 10,
1638         HALMAC_HW_TXFF_ALLOCATION = 11,
1639         HALMAC_HW_USB_MODE = 12,
1640         HALMAC_HW_SEQ_EN = 13,
1641         HALMAC_HW_BANDWIDTH = 14,
1642         HALMAC_HW_CHANNEL = 15,
1643         HALMAC_HW_PRI_CHANNEL_IDX = 16,
1644         HALMAC_HW_EN_BB_RF = 17,
1645         HALMAC_HW_BT_BANK_EFUSE_SIZE = 18,
1646         HALMAC_HW_BT_BANK1_EFUSE_SIZE = 19,
1647         HALMAC_HW_BT_BANK2_EFUSE_SIZE = 20,
1648         HALMAC_HW_ID_UNDEFINE = 0x7F,
1649 } HALMAC_HW_ID;
1650 typedef enum _HALMAC_EFUSE_BANK {
1651         HALMAC_EFUSE_BANK_WIFI = 0,
1652         HALMAC_EFUSE_BANK_BT = 1,
1653         HALMAC_EFUSE_BANK_BT_1 = 2,
1654         HALMAC_EFUSE_BANK_BT_2 = 3,
1655         HALMAC_EFUSE_BANK_MAX,
1656         HALMAC_EFUSE_BANK_UNDEFINE = 0X7F,
1657 } HALMAC_EFUSE_BANK;
1658
1659 typedef struct _HALMAC_TXFF_ALLOCATION {
1660         u16 tx_fifo_pg_num;
1661         u16 rsvd_pg_num;
1662         u16 rsvd_drv_pg_num;
1663         u16 ac_q_pg_num;
1664         u16 high_queue_pg_num;
1665         u16 low_queue_pg_num;
1666         u16 normal_queue_pg_num;
1667         u16 extra_queue_pg_num;
1668         u16 pub_queue_pg_num;
1669         u16 rsvd_pg_bndy;
1670         u16     rsvd_drv_pg_bndy;
1671         u16     rsvd_h2c_extra_info_pg_bndy;
1672         u16     rsvd_h2c_queue_pg_bndy;
1673         u16     rsvd_cpu_instr_pg_bndy;
1674         u16     rsvd_fw_txbuff_pg_bndy;
1675         HALMAC_LA_MODE la_mode;
1676 } HALMAC_TXFF_ALLOCATION, *PHALMAC_TXFF_ALLOCATION;
1677
1678 typedef struct _HALMAC_RQPN_MAP {
1679         HALMAC_DMA_MAPPING dma_map_vo;
1680         HALMAC_DMA_MAPPING dma_map_vi;
1681         HALMAC_DMA_MAPPING dma_map_be;
1682         HALMAC_DMA_MAPPING dma_map_bk;
1683         HALMAC_DMA_MAPPING dma_map_mg;
1684         HALMAC_DMA_MAPPING dma_map_hi;
1685 } HALMAC_RQPN_MAP, *PHALMAC_RQPN_MAP;
1686
1687 /* Hal mac adapter */
1688 typedef struct _HALMAC_ADAPTER {
1689         HALMAC_DMA_MAPPING halmac_ptcl_queue[HALMAC_PTCL_QUEUE_NUM]; /* Dma mapping of protocol queues */
1690         HALMAC_FWLPS_OPTION     fwlps_option; /* low power state option */
1691         HALMAC_WLAN_ADDR pHal_mac_addr[2]; /* mac address information, suppot 2 ports */
1692         HALMAC_WLAN_ADDR pHal_bss_addr[2]; /* bss address information, suppot 2 ports */
1693         HALMAC_MUTEX h2c_seq_mutex; /* Protect h2c_packet_seq packet*/
1694         HALMAC_MUTEX EfuseMutex; /* Protect Efuse map memory of halmac_adapter */
1695         HALMAC_CONFIG_PARA_INFO config_para_info;
1696         HALMAC_CS_INFO ch_sw_info;
1697         HALMAC_EVENT_TRIGGER event_trigger;
1698         HALMAC_HW_CONFIG_INFO hw_config_info; /* HW related information */
1699         HALMAC_SDIO_FREE_SPACE sdio_free_space;
1700         HALMAC_SND_INFO snd_info;
1701         VOID *pHalAdapter_backup; /* Backup HalAdapter address */
1702         VOID *pDriver_adapter; /* Driver or FW adapter address. Do not write this memory*/
1703         u8 *pHalEfuse_map;
1704         VOID *pHalmac_api; /* Record function pointer of halmac api */
1705         PHALMAC_PLATFORM_API pHalmac_platform_api; /* Record function pointer of platform api */
1706         u32 efuse_end; /* Record efuse used memory */
1707         u32 h2c_buf_free_space;
1708         u32     h2c_buff_size;
1709         u32     max_download_size;
1710         HALMAC_CHIP_ID chip_id; /* Chip ID, 8822B, 8821C... */
1711         HALMAC_CHIP_VER chip_version; /* A cut, B cut... */
1712         HALMAC_FW_VERSION fw_version;
1713         HALMAC_STATE halmac_state;
1714         HALMAC_INTERFACE halmac_interface; /* Interface information, get from driver */
1715         HALMAC_TRX_MODE trx_mode; /* Noraml, WMM, P2P, LoopBack... */
1716         HALMAC_TXFF_ALLOCATION txff_allocation;
1717         u8 h2c_packet_seq; /* current h2c packet sequence number */
1718         u16 ack_h2c_packet_seq; /*the acked h2c packet sequence number */
1719         u8 hal_efuse_map_valid;
1720         u8 efuse_segment_size;
1721         u8 rpwm_record; /* record rpwm value */
1722         u8 low_clk; /*LPS 32K or IPS 32K*/
1723         u8 halmac_bulkout_num; /* USB bulkout num */
1724         HALMAC_API_RECORD api_record; /* API record */
1725         u8 gen_info_valid;
1726         HALMAC_GENERAL_INFO general_info;
1727 #if HALMAC_PLATFORM_TESTPROGRAM
1728         HALMAC_TXAGG_BUFF_INFO halmac_tx_buf_info[4];
1729         HALMAC_MUTEX agg_buff_mutex; /*used for tx_agg_buffer */
1730         u8 max_agg_num;
1731         u8 send_bcn_reg_cr_backup;
1732 #endif
1733 } HALMAC_ADAPTER, *PHALMAC_ADAPTER;
1734
1735
1736 /* Fuction pointer of  Hal mac API */
1737 typedef struct _HALMAC_API {
1738         HALMAC_RET_STATUS (*halmac_mac_power_switch)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_MAC_POWER halmac_power);
1739         HALMAC_RET_STATUS (*halmac_download_firmware)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size);
1740         HALMAC_RET_STATUS (*halmac_get_fw_version)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_FW_VERSION pFw_version);
1741         HALMAC_RET_STATUS (*halmac_cfg_mac_addr)(PHALMAC_ADAPTER pHalmac_adapter, u8 halmac_port, PHALMAC_WLAN_ADDR pHal_address);
1742         HALMAC_RET_STATUS (*halmac_cfg_bssid)(PHALMAC_ADAPTER pHalmac_adapter, u8 halmac_port, PHALMAC_WLAN_ADDR pHal_address);
1743         HALMAC_RET_STATUS (*halmac_cfg_multicast_addr)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_WLAN_ADDR pHal_address);
1744         HALMAC_RET_STATUS (*halmac_pre_init_system_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
1745         HALMAC_RET_STATUS (*halmac_init_system_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
1746         HALMAC_RET_STATUS (*halmac_init_trx_cfg)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_TRX_MODE Mode);
1747         HALMAC_RET_STATUS (*halmac_init_h2c)(PHALMAC_ADAPTER pHalmac_adapter);
1748         HALMAC_RET_STATUS (*halmac_cfg_rx_aggregation)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_RXAGG_CFG phalmac_rxagg_cfg);
1749         HALMAC_RET_STATUS (*halmac_init_protocol_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
1750         HALMAC_RET_STATUS (*halmac_init_edca_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
1751         HALMAC_RET_STATUS (*halmac_cfg_operation_mode)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_WIRELESS_MODE wireless_mode);
1752         HALMAC_RET_STATUS (*halmac_cfg_ch_bw)(PHALMAC_ADAPTER pHalmac_adapter, u8 channel, HALMAC_PRI_CH_IDX pri_ch_idx, HALMAC_BW bw);
1753         HALMAC_RET_STATUS (*halmac_cfg_bw)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_BW bw);
1754         HALMAC_RET_STATUS (*halmac_init_wmac_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
1755         HALMAC_RET_STATUS (*halmac_init_mac_cfg)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_TRX_MODE Mode);
1756         HALMAC_RET_STATUS (*halmac_init_sdio_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
1757         HALMAC_RET_STATUS (*halmac_init_usb_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
1758         HALMAC_RET_STATUS (*halmac_init_pcie_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
1759         HALMAC_RET_STATUS (*halmac_init_interface_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
1760         HALMAC_RET_STATUS (*halmac_deinit_sdio_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
1761         HALMAC_RET_STATUS (*halmac_deinit_usb_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
1762         HALMAC_RET_STATUS (*halmac_deinit_pcie_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
1763         HALMAC_RET_STATUS (*halmac_deinit_interface_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
1764         HALMAC_RET_STATUS (*halmac_get_efuse_size)(PHALMAC_ADAPTER pHalmac_adapter, u32 *halmac_size);
1765         HALMAC_RET_STATUS (*halmac_get_efuse_available_size)(PHALMAC_ADAPTER pHalmac_adapter, u32 *halmac_size);
1766         HALMAC_RET_STATUS (*halmac_dump_efuse_map)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_EFUSE_READ_CFG cfg);
1767         HALMAC_RET_STATUS (*halmac_dump_efuse_map_bt)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_EFUSE_BANK halmac_efues_bank, u32 bt_efuse_map_size, u8 *pBT_efuse_map);
1768         HALMAC_RET_STATUS (*halmac_write_efuse)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 halmac_value);
1769         HALMAC_RET_STATUS (*halmac_read_efuse)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 *pValue);
1770         HALMAC_RET_STATUS (*halmac_switch_efuse_bank)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_EFUSE_BANK halmac_efues_bank);
1771         HALMAC_RET_STATUS (*halmac_write_efuse_bt)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 halmac_value, HALMAC_EFUSE_BANK halmac_efues_bank);
1772         HALMAC_RET_STATUS (*halmac_get_logical_efuse_size)(PHALMAC_ADAPTER pHalmac_adapter, u32 *halmac_size);
1773         HALMAC_RET_STATUS (*halmac_dump_logical_efuse_map)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_EFUSE_READ_CFG cfg);
1774         HALMAC_RET_STATUS (*halmac_write_logical_efuse)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 halmac_value);
1775         HALMAC_RET_STATUS (*halmac_read_logical_efuse)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 *pValue);
1776         HALMAC_RET_STATUS (*halmac_pg_efuse_by_map)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_PG_EFUSE_INFO pPg_efuse_info, HALMAC_EFUSE_READ_CFG cfg);
1777         HALMAC_RET_STATUS (*halmac_get_c2h_info)(PHALMAC_ADAPTER pHalmac_adapter, u8 *halmac_buf, u32 halmac_size);
1778         HALMAC_RET_STATUS (*halmac_cfg_fwlps_option)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_FWLPS_OPTION pLps_option);
1779         HALMAC_RET_STATUS (*halmac_cfg_fwips_option)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_FWIPS_OPTION pIps_option);
1780         HALMAC_RET_STATUS (*halmac_enter_wowlan)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_WOWLAN_OPTION pWowlan_option);
1781         HALMAC_RET_STATUS (*halmac_leave_wowlan)(PHALMAC_ADAPTER pHalmac_adapter);
1782         HALMAC_RET_STATUS (*halmac_enter_ps)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_PS_STATE ps_state);
1783         HALMAC_RET_STATUS (*halmac_leave_ps)(PHALMAC_ADAPTER pHalmac_adapter);
1784         HALMAC_RET_STATUS (*halmac_h2c_lb)(PHALMAC_ADAPTER pHalmac_adapter);
1785         HALMAC_RET_STATUS (*halmac_debug)(PHALMAC_ADAPTER pHalmac_adapter);
1786         HALMAC_RET_STATUS (*halmac_cfg_parameter)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_PHY_PARAMETER_INFO para_info, u8 full_fifo);
1787         HALMAC_RET_STATUS (*halmac_update_packet)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_PACKET_ID pkt_id, u8 *pkt, u32 pkt_size);
1788         HALMAC_RET_STATUS (*halmac_bcn_ie_filter)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_BCN_IE_INFO pBcn_ie_info);
1789         u8 (*halmac_reg_read_8)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset);
1790         HALMAC_RET_STATUS (*halmac_reg_write_8)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 halmac_data);
1791         u16 (*halmac_reg_read_16)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset);
1792         HALMAC_RET_STATUS (*halmac_reg_write_16)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u16 halmac_data);
1793         u32 (*halmac_reg_read_32)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset);
1794         HALMAC_RET_STATUS (*halmac_reg_write_32)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u32 halmac_data);
1795         HALMAC_RET_STATUS (*halmac_tx_allowed_sdio)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHalmac_buf, u32 halmac_size);
1796         HALMAC_RET_STATUS (*halmac_set_bulkout_num)(PHALMAC_ADAPTER pHalmac_adapter, u8 bulkout_num);
1797         HALMAC_RET_STATUS (*halmac_get_sdio_tx_addr)(PHALMAC_ADAPTER pHalmac_adapter, u8 *halmac_buf, u32 halmac_size, u32 *pcmd53_addr);
1798         HALMAC_RET_STATUS (*halmac_get_usb_bulkout_id)(PHALMAC_ADAPTER pHalmac_adapter, u8 *halmac_buf, u32 halmac_size, u8 *bulkout_id);
1799         HALMAC_RET_STATUS (*halmac_timer_2s)(PHALMAC_ADAPTER pHalmac_adapter);
1800         HALMAC_RET_STATUS (*halmac_fill_txdesc_checksum)(PHALMAC_ADAPTER pHalmac_adapter, u8 *cur_desc);
1801         HALMAC_RET_STATUS (*halmac_update_datapack)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DATA_TYPE halmac_data_type, PHALMAC_PHY_PARAMETER_INFO para_info);
1802         HALMAC_RET_STATUS (*halmac_run_datapack)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DATA_TYPE halmac_data_type);
1803         HALMAC_RET_STATUS (*halmac_cfg_drv_info)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DRV_INFO halmac_drv_info);
1804         HALMAC_RET_STATUS (*halmac_send_bt_coex)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBt_buf, u32 bt_size, u8 ack);
1805         HALMAC_RET_STATUS (*halmac_verify_platform_api)(PHALMAC_ADAPTER pHalmac_adapte);
1806         u32 (*halmac_get_fifo_size)(PHALMAC_ADAPTER pHalmac_adapter, HAL_FIFO_SEL halmac_fifo_sel);
1807         HALMAC_RET_STATUS (*halmac_dump_fifo)(PHALMAC_ADAPTER pHalmac_adapter, HAL_FIFO_SEL halmac_fifo_sel, u8 *pFifo_map, u32 halmac_fifo_dump_size);
1808         HALMAC_RET_STATUS (*halmac_cfg_txbf)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid, HALMAC_BW bw, u8 txbf_en);
1809         HALMAC_RET_STATUS (*halmac_cfg_mumimo)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CFG_MUMIMO_PARA pCfgmu);
1810         HALMAC_RET_STATUS (*halmac_cfg_sounding)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_SND_ROLE role, HALMAC_DATA_RATE datarate);
1811         HALMAC_RET_STATUS (*halmac_del_sounding)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_SND_ROLE role);
1812         HALMAC_RET_STATUS (*halmac_su_bfer_entry_init)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_SU_BFER_INIT_PARA pSu_bfer_init);
1813         HALMAC_RET_STATUS (*halmac_su_bfee_entry_init)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid, u16 paid);
1814         HALMAC_RET_STATUS (*halmac_mu_bfer_entry_init)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_MU_BFER_INIT_PARA pMu_bfer_init);
1815         HALMAC_RET_STATUS (*halmac_mu_bfee_entry_init)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_MU_BFEE_INIT_PARA pMu_bfee_init);
1816         HALMAC_RET_STATUS (*halmac_su_bfer_entry_del)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid);
1817         HALMAC_RET_STATUS (*halmac_su_bfee_entry_del)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid);
1818         HALMAC_RET_STATUS (*halmac_mu_bfer_entry_del)(PHALMAC_ADAPTER pHalmac_adapter);
1819         HALMAC_RET_STATUS (*halmac_mu_bfee_entry_del)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid);
1820         HALMAC_RET_STATUS (*halmac_add_ch_info)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CH_INFO pCh_info);
1821         HALMAC_RET_STATUS (*halmac_add_extra_ch_info)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CH_EXTRA_INFO pCh_extra_info);
1822         HALMAC_RET_STATUS (*halmac_ctrl_ch_switch)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CH_SWITCH_OPTION pCs_option);
1823         HALMAC_RET_STATUS (*halmac_clear_ch_info)(PHALMAC_ADAPTER pHalmac_adapter);
1824         HALMAC_RET_STATUS (*halmac_send_general_info)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_GENERAL_INFO pgGeneral_info);
1825         HALMAC_RET_STATUS (*halmac_start_iqk)(PHALMAC_ADAPTER pHalmac_adapter, u8 clear);
1826         HALMAC_RET_STATUS (*halmac_ctrl_pwr_tracking)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_PWR_TRACKING_OPTION pPwr_tracking_opt);
1827         HALMAC_RET_STATUS (*halmac_psd)(PHALMAC_ADAPTER pHalmac_adapter, u16 start_psd, u16 end_psd);
1828         HALMAC_RET_STATUS (*halmac_cfg_tx_agg_align)(PHALMAC_ADAPTER pHalmac_adapter, u8 enable, u16 align_size);
1829         HALMAC_RET_STATUS (*halmac_query_status)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_FEATURE_ID feature_id, HALMAC_CMD_PROCESS_STATUS *pProcess_status, u8 *data, u32 *size);
1830         HALMAC_RET_STATUS (*halmac_reset_feature)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_FEATURE_ID feature_id);
1831         HALMAC_RET_STATUS (*halmac_check_fw_status)(PHALMAC_ADAPTER pHalmac_adapter, u8 *fw_status);
1832         HALMAC_RET_STATUS (*halmac_dump_fw_dmem)(PHALMAC_ADAPTER pHalmac_adapter, u8 *dmem, u32 *size);
1833         HALMAC_RET_STATUS (*halmac_cfg_max_dl_size)(PHALMAC_ADAPTER pHalmac_adapter, u32 size);
1834         HALMAC_RET_STATUS (*halmac_cfg_la_mode)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_LA_MODE la_mode);
1835         HALMAC_RET_STATUS (*halmac_get_hw_value)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_HW_ID hw_id, VOID *pvalue);
1836         HALMAC_RET_STATUS (*halmac_set_hw_value)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_HW_ID hw_id, VOID *pvalue);
1837         HALMAC_RET_STATUS (*halmac_cfg_drv_rsvd_pg_num)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DRV_RSVD_PG_NUM pg_num);
1838         HALMAC_RET_STATUS (*halmac_get_chip_version)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_VER *version);
1839         HALMAC_RET_STATUS (*halmac_chk_txdesc)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHalmac_buf, u32 halmac_size);
1840 #if HALMAC_PLATFORM_TESTPROGRAM
1841         HALMAC_RET_STATUS (*halmac_gen_txdesc)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pPcket_buffer, PHAL_TXDESC_INFO pTxdesc_info);
1842         HALMAC_RET_STATUS (*halmac_txdesc_parser)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pTxdesc, PHAL_TXDESC_PARSER pTxdesc_parser);
1843         HALMAC_RET_STATUS (*halmac_rxdesc_parser)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pRxdesc, PHAL_RXDESC_PARSER pRxdesc_parser);
1844         HALMAC_RET_STATUS (*halmac_get_txdesc_size)(PHALMAC_ADAPTER pHalmac_adapter, PHAL_TXDESC_INFO pTxdesc_info, u32 *size);
1845         HALMAC_RET_STATUS (*halmac_send_packet)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 size, PHAL_TXDESC_INFO pTxdesc_Info);
1846         HALMAC_RET_STATUS (*halmac_get_pcie_packet)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 *size);
1847         HALMAC_RET_STATUS (*halmac_gen_txagg_desc)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pPcket_buffer, u32 agg_num);
1848         HALMAC_RET_STATUS (*halmac_parse_packet)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, PHAL_RXDESC_INFO pRxdesc_info, u8 **next_pkt);
1849         u32 (*halmac_bb_reg_read)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 len);
1850         HALMAC_RET_STATUS (*halmac_bb_reg_write)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u32 halmac_data, u8 len);
1851         u32 (*halmac_rf_reg_read)(PHALMAC_ADAPTER pHalmac_adapter, PHAL_RF_REG_INFO pRf_reg_info);
1852         HALMAC_RET_STATUS (*halmac_rf_reg_write)(PHALMAC_ADAPTER pHalmac_adapter, PHAL_RF_REG_INFO pRf_reg_info);
1853         HALMAC_RET_STATUS (*halmac_init_antenna_selection)(PHALMAC_ADAPTER pHalmac_adapter);
1854         HALMAC_RET_STATUS (*halmac_bb_preconfig)(PHALMAC_ADAPTER pHalmac_adapter);
1855         HALMAC_RET_STATUS (*halmac_init_crystal_capacity)(PHALMAC_ADAPTER pHalmac_adapter);
1856         HALMAC_RET_STATUS (*halmac_trx_antenna_setting)(PHALMAC_ADAPTER pHalmac_adapter);
1857         HALMAC_RET_STATUS (*halmac_himr_setting_sdio)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_SDIO_HIMR_INFO sdio_himr_sdio);
1858         HALMAC_RET_STATUS (*halmac_config_security)(PHALMAC_ADAPTER pHalmac_adapter, PHAL_SECURITY_INFO pSecurity_info);
1859         HALMAC_RET_STATUS (*halmac_write_cam)(PHALMAC_ADAPTER pHalmac_adapter, u32 entry_index, PHALMAC_CAM_ENTRY_INFO pCam_entry_info);
1860         HALMAC_RET_STATUS (*halmac_read_cam)(PHALMAC_ADAPTER pHalmac_adapter, u32 entry_index, PHALMAC_CAM_ENTRY_FORMAT pContent);
1861         HALMAC_RET_STATUS (*halmac_dump_cam_table)(PHALMAC_ADAPTER pHalmac_adapter, u32 entry_num, PHALMAC_CAM_ENTRY_FORMAT pCam_table);
1862         HALMAC_RET_STATUS (*halmac_load_cam_table)(PHALMAC_ADAPTER pHalmac_adapter, u8 entry_num, PHALMAC_CAM_ENTRY_FORMAT pCam_table);
1863         HALMAC_RET_STATUS (*halmac_send_beacon)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 size, PHALMAC_BEACON_INFO pbeacon_info);
1864         HALMAC_RET_STATUS (*halmac_get_management_txdesc)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 *pSize, PHALMAC_MGNT_INFO pmgnt_info);
1865         HALMAC_RET_STATUS (*halmac_send_control)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 size, PHALMAC_CTRL_INFO pctrl_info);
1866         HALMAC_RET_STATUS (*halmac_send_hiqueue)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 size, PHALMAC_HIGH_QUEUE_INFO pHigh_info);
1867         HALMAC_RET_STATUS (*halmac_run_pwrseq)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_PWR_SEQ_ID seq);
1868         HALMAC_RET_STATUS (*halmac_media_status_rpt)(PHALMAC_ADAPTER pHalmac_adapter, u8 op_mode, u8 mac_id_ind, u8 mac_id, u8 mac_id_end);
1869         HALMAC_RET_STATUS (*halmac_stop_beacon)(PHALMAC_ADAPTER pHalmac_adapter);
1870         HALMAC_RET_STATUS (*halmac_check_trx_status)(PHALMAC_ADAPTER pHalmac_adapter);
1871         HALMAC_RET_STATUS (*halmac_set_agg_num)(PHALMAC_ADAPTER pHalmac_adapter, u8 agg_num);
1872         HALMAC_RET_STATUS (*halmac_timer_10ms)(PHALMAC_ADAPTER pHalmac_adapter);
1873         HALMAC_RET_STATUS (*halmac_download_firmware_fpag)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size, u32 iram_address);
1874         HALMAC_RET_STATUS (*halmac_download_rom_fpga)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size, u32 rom_address);
1875         HALMAC_RET_STATUS (*halmac_download_flash)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size, u32 rom_address);
1876         HALMAC_RET_STATUS (*halmac_erase_flash)(PHALMAC_ADAPTER pHalmac_adapter);
1877         HALMAC_RET_STATUS (*halmac_check_flash)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size);
1878         HALMAC_RET_STATUS (*halmac_send_nlo)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_NLO_CFG pNlo_cfg);
1879         HALMAC_RET_STATUS (*halmac_get_chip_type)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CHIP_TYPE pChip_type);
1880         u32 (*halmac_get_rx_agg_num)(PHALMAC_ADAPTER pHalmac_adapter, u32 pkt_size, u8 *pPkt_buff);
1881 #endif
1882 } HALMAC_API, *PHALMAC_API;
1883
1884 #define HALMAC_GET_API(phalmac_adapter) ((PHALMAC_API)phalmac_adapter->pHalmac_api)
1885
1886 static HALMAC_INLINE HALMAC_RET_STATUS
1887 halmac_adapter_validate(
1888         PHALMAC_ADAPTER pHalmac_adapter
1889 )
1890 {
1891         if ((NULL == pHalmac_adapter) || (pHalmac_adapter->pHalAdapter_backup != pHalmac_adapter))
1892                 return HALMAC_RET_ADAPTER_INVALID;
1893
1894         return HALMAC_RET_SUCCESS;
1895 }
1896
1897 static HALMAC_INLINE HALMAC_RET_STATUS
1898 halmac_api_validate(
1899         PHALMAC_ADAPTER pHalmac_adapter
1900 )
1901 {
1902         if (HALMAC_API_STATE_INIT != pHalmac_adapter->halmac_state.api_state)
1903                 return HALMAC_RET_API_INVALID;
1904
1905         return HALMAC_RET_SUCCESS;
1906 }
1907
1908 static HALMAC_INLINE HALMAC_RET_STATUS
1909 halmac_fw_validate(
1910         PHALMAC_ADAPTER pHalmac_adapter
1911 )
1912 {
1913         if (HALMAC_DLFW_DONE != pHalmac_adapter->halmac_state.dlfw_state && HALMAC_GEN_INFO_SENT != pHalmac_adapter->halmac_state.dlfw_state)
1914                 return HALMAC_RET_NO_DLFW;
1915
1916         return HALMAC_RET_SUCCESS;
1917 }
1918
1919 #endif