1 /******************************************************************************
3 * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
20 #ifndef _RTL8822B_HAL_H_
21 #define _RTL8822B_HAL_H_
23 #include <osdep_service.h> /* BIT(x) */
24 #include <drv_types.h> /* PADAPTER */
25 #include "../hal/halmac/halmac_api.h" /* MAC REG definition */
28 #define MAX_RECVBUF_SZ HALMAC_RX_FIFO_SIZE_8822B
31 * MAC Register definition
33 #define REG_AFE_XTAL_CTRL REG_AFE_CTRL1_8822B /* hal_com.c & phydm */
34 #define REG_AFE_PLL_CTRL REG_AFE_CTRL2_8822B /* hal_com.c & phydm */
35 #define REG_MAC_PHY_CTRL REG_AFE_CTRL3_8822B /* phydm only */
36 #define REG_LEDCFG0 REG_LED_CFG_8822B /* rtw_mp.c */
37 #define MSR (REG_CR_8822B + 2) /* rtw_mp.c & hal_com.c */
38 #define MSR1 REG_CR_EXT_8822B /* rtw_mp.c & hal_com.c */
39 #define REG_C2HEVT_MSG_NORMAL 0x1A0 /* hal_com.c */
40 #define REG_C2HEVT_CLEAR 0x1AF /* hal_com.c */
41 #define REG_BCN_CTRL_1 REG_BCN_CTRL_CLINT0_8822B /* hal_com.c */
42 #define REG_TSFTR1 REG_FREERUN_CNT_8822B /* hal_com.c */
43 #define REG_RXFLTMAP2 REG_RXFLTMAP_8822B /* rtw_mp.c */
44 #define REG_WOWLAN_WAKE_REASON 0x01C7 /* hal_com.c */
45 #define REG_GPIO_PIN_CTRL_2 REG_GPIO_EXT_CTRL_8822B /* hal_com.c */
47 /* RXERR_RPT, for rtw_mp.c */
48 #define RXERR_TYPE_OFDM_PPDU 0
49 #define RXERR_TYPE_OFDM_FALSE_ALARM 2
50 #define RXERR_TYPE_OFDM_MPDU_OK 0
51 #define RXERR_TYPE_OFDM_MPDU_FAIL 1
52 #define RXERR_TYPE_CCK_PPDU 3
53 #define RXERR_TYPE_CCK_FALSE_ALARM 5
54 #define RXERR_TYPE_CCK_MPDU_OK 3
55 #define RXERR_TYPE_CCK_MPDU_FAIL 4
56 #define RXERR_TYPE_HT_PPDU 8
57 #define RXERR_TYPE_HT_FALSE_ALARM 9
58 #define RXERR_TYPE_HT_MPDU_TOTAL 6
59 #define RXERR_TYPE_HT_MPDU_OK 6
60 #define RXERR_TYPE_HT_MPDU_FAIL 7
61 #define RXERR_TYPE_RX_FULL_DROP 10
63 #define RXERR_COUNTER_MASK BIT_MASK_RPT_COUNTER_8822B
64 #define RXERR_RPT_RST BIT_RXERR_RPT_RST_8822B
65 #define _RXERR_RPT_SEL(type) (BIT_RXERR_RPT_SEL_V1_3_0_8822B(type) \
66 | ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8822B : 0))
69 * BB Register definition
71 #define rPMAC_Reset 0x100 /* hal_mp.c */
73 #define rFPGA0_RFMOD 0x800
74 #define rFPGA0_TxInfo 0x804
75 #define rOFDMCCKEN_Jaguar 0x808 /* hal_mp.c */
76 #define rFPGA0_TxGainStage 0x80C /* phydm only */
77 #define rFPGA0_XA_HSSIParameter1 0x820 /* hal_mp.c */
78 #define rFPGA0_XA_HSSIParameter2 0x824 /* hal_mp.c */
79 #define rFPGA0_XB_HSSIParameter1 0x828 /* hal_mp.c */
80 #define rFPGA0_XB_HSSIParameter2 0x82C /* hal_mp.c */
81 #define rTxAGC_B_Rate18_06 0x830
82 #define rTxAGC_B_Rate54_24 0x834
83 #define rTxAGC_B_CCK1_55_Mcs32 0x838
84 #define rCCAonSec_Jaguar 0x838 /* hal_mp.c */
85 #define rTxAGC_B_Mcs03_Mcs00 0x83C
86 #define rTxAGC_B_Mcs07_Mcs04 0x848
87 #define rTxAGC_B_Mcs11_Mcs08 0x84C
88 #define rFPGA0_XA_RFInterfaceOE 0x860
89 #define rFPGA0_XB_RFInterfaceOE 0x864
90 #define rTxAGC_B_Mcs15_Mcs12 0x868
91 #define rTxAGC_B_CCK11_A_CCK2_11 0x86C
92 #define rFPGA0_XAB_RFInterfaceSW 0x870
93 #define rFPGA0_XAB_RFParameter 0x878
94 #define rFPGA0_AnalogParameter4 0x88C /* hal_mp.c & phydm */
95 #define rFPGA0_XB_LSSIReadBack 0x8A4 /* phydm */
96 #define rHSSIRead_Jaguar 0x8B0 /* RF read addr (rtl8822b_phy.c) */
98 #define rC_TxScale_Jaguar2 0x181C /* Pah_C TX scaling factor (hal_mp.c) */
99 #define rC_IGI_Jaguar2 0x1850 /* Initial Gain for path-C (hal_mp.c) */
101 #define rFPGA1_TxInfo 0x90C /* hal_mp.c */
102 #define rSingleTone_ContTx_Jaguar 0x914 /* hal_mp.c */
104 #define REG_BB_TX_PATH_SEL_1_8822B 0x93C /* rtl8822b_phy.c */
105 #define REG_BB_TX_PATH_SEL_2_8822B 0x940 /* rtl8822b_phy.c */
108 #define REG_BB_TXBF_ANT_SET_BF1_8822B 0x19AC /* rtl8822b_phy.c */
109 #define REG_BB_TXBF_ANT_SET_BF0_8822B 0x19B4 /* rtl8822b_phy.c */
111 #define rCCK0_System 0xA00
112 #define rCCK0_AFESetting 0xA04
114 #define rCCK0_DSPParameter2 0xA1C
115 #define rCCK0_TxFilter1 0xA20
116 #define rCCK0_TxFilter2 0xA24
117 #define rCCK0_DebugPort 0xA28
118 #define rCCK0_FalseAlarmReport 0xA2C
120 #define rD_TxScale_Jaguar2 0x1A1C /* Path_D TX scaling factor (hal_mp.c) */
121 #define rD_IGI_Jaguar2 0x1A50 /* Initial Gain for path-D (hal_mp.c) */
123 #define rOFDM0_TRxPathEnable 0xC04
124 #define rOFDM0_TRMuxPar 0xC08
125 #define rA_TxScale_Jaguar 0xC1C /* Pah_A TX scaling factor (hal_mp.c) */
126 #define rOFDM0_RxDetector1 0xC30 /* rtw_mp.c */
127 #define rOFDM0_ECCAThreshold 0xC4C /* phydm only */
128 #define rOFDM0_XAAGCCore1 0xC50 /* phydm only */
129 #define rA_IGI_Jaguar 0xC50 /* Initial Gain for path-A (hal_mp.c) */
130 #define rOFDM0_XBAGCCore1 0xC58 /* phydm only */
131 #define rOFDM0_XATxIQImbalance 0xC80 /* phydm only */
132 #define rA_LSSIWrite_Jaguar 0xC90 /* RF write addr, LSSI Parameter (rtl8822b_phy.c) */
133 #define rA_RFE_Pinmux_Jaguar 0xCB0 /* hal_mp.c */
135 #define rOFDM1_LSTF 0xD00
136 #define rOFDM1_TRxPathEnable 0xD04 /* hal_mp.c */
137 #define rA_PIRead_Jaguar 0xD04 /* RF readback with PI (rtl8822b_phy.c) */
138 #define rA_SIRead_Jaguar 0xD08 /* RF readback with SI (rtl8822b_phy.c) */
139 #define rB_PIRead_Jaguar 0xD44 /* RF readback with PI (rtl8822b_phy.c) */
140 #define rB_SIRead_Jaguar 0xD48 /* RF readback with SI (rtl8822b_phy.c) */
142 #define rTxAGC_A_Rate18_06 0xE00
143 #define rTxAGC_A_Rate54_24 0xE04
144 #define rTxAGC_A_CCK1_Mcs32 0xE08
145 #define rTxAGC_A_Mcs03_Mcs00 0xE10
146 #define rTxAGC_A_Mcs07_Mcs04 0xE14
147 #define rTxAGC_A_Mcs11_Mcs08 0xE18
148 #define rTxAGC_A_Mcs15_Mcs12 0xE1C
149 #define rB_TxScale_Jaguar 0xE1C /* Path_B TX scaling factor (hal_mp.c) */
150 #define rB_IGI_Jaguar 0xE50 /* Initial Gain for path-B (hal_mp.c) */
151 #define rB_LSSIWrite_Jaguar 0xE90 /* RF write addr, LSSI Parameter (rtl8822b_phy.c) */
152 #define rB_RFE_Pinmux_Jaguar 0xEB0 /* hal_mp.c */
155 #define bBBResetB 0x100
158 #define bCCKEn 0x1000000
159 #define bOFDMEn 0x2000000
160 /* Reg 0x80C rFPGA0_TxGainStage */
161 #define bXBTxAGC 0xF00
162 #define bXCTxAGC 0xF000
163 #define bXDTxAGC 0xF0000
166 #define bCCKBBMode 0x3
168 #define bCCKScramble 0x8
169 #define bCCKTxRate 0x3000
172 #define bMaskByte0 0xFF /* mp, rtw_odm.c & phydm */
173 #define bMaskByte1 0xFF00 /* hal_mp.c & phydm */
174 #define bMaskByte2 0xFF0000 /* hal_mp.c & phydm */
175 #define bMaskByte3 0xFF000000 /* hal_mp.c & phydm */
176 #define bMaskHWord 0xFFFF0000 /* hal_com.c, rtw_mp.c */
177 #define bMaskLWord 0x0000FFFF /* mp, hal_com.c & phydm */
178 #define bMaskDWord 0xFFFFFFFF /* mp, hal, rtw_odm.c & phydm */
180 #define bEnable 0x1 /* hal_mp.c, rtw_mp.c */
181 #define bDisable 0x0 /* rtw_mp.c */
183 #define MAX_STALL_TIME 50 /* unit: us, hal_com_phycfg.c */
185 #define Rx_Smooth_Factor 20 /* phydm only */
188 * RF Register definition
191 #define RF_AC_Jaguar 0x00 /* hal_mp.c */
192 #define RF_CHNLBW 0x18 /* rtl8822b_phy.c */
193 #define RF_ModeTableAddr 0x30 /* rtl8822b_phy.c */
194 #define RF_ModeTableData0 0x31 /* rtl8822b_phy.c */
195 #define RF_ModeTableData1 0x32 /* rtl8822b_phy.c */
197 #define RF_WeLut_Jaguar 0xEF /* rtl8822b_phy.c */
199 /* General Functions */
200 void rtl8822b_init_hal_spec(PADAPTER); /* hal/hal_com.c */
202 #ifdef CONFIG_MP_INCLUDED
204 #include <rtw_mp.h> /* struct mp_priv */
205 void rtl8822b_phy_init_haldm(PADAPTER); /* rtw_mp.c */
206 void rtl8822b_prepare_mp_txdesc(PADAPTER, struct mp_priv *); /* rtw_mp.c */
207 void rtl8822b_mp_config_rfpath(PADAPTER); /* hal_mp.c */
210 #ifdef CONFIG_USB_HCI
211 #include <rtl8822bu_hal.h>
212 #elif defined(CONFIG_SDIO_HCI)
213 #include <rtl8822bs_hal.h>
214 #elif defined(CONFIG_PCI_HCI)
215 #include <rtl8822be_hal.h>
218 #endif /* _RTL8822B_HAL_H_ */