1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 *******************************************************************************/
19 #ifndef __RTL8723B_SPEC_H__
20 #define __RTL8723B_SPEC_H__
25 #define HAL_NAV_UPPER_UNIT_8723B 128 /* micro-second */
27 /* -----------------------------------------------------
29 * 0x0000h ~ 0x00FFh System Configuration
31 * ----------------------------------------------------- */
32 #define REG_RSV_CTRL_8723B 0x001C /* 3 Byte */
33 #define REG_BT_WIFI_ANTENNA_SWITCH_8723B 0x0038
34 #define REG_HSISR_8723B 0x005c
35 #define REG_PAD_CTRL1_8723B 0x0064
36 #define REG_AFE_CTRL_4_8723B 0x0078
37 #define REG_HMEBOX_DBG_0_8723B 0x0088
38 #define REG_HMEBOX_DBG_1_8723B 0x008A
39 #define REG_HMEBOX_DBG_2_8723B 0x008C
40 #define REG_HMEBOX_DBG_3_8723B 0x008E
41 #define REG_HIMR0_8723B 0x00B0
42 #define REG_HISR0_8723B 0x00B4
43 #define REG_HIMR1_8723B 0x00B8
44 #define REG_HISR1_8723B 0x00BC
45 #define REG_PMC_DBG_CTRL2_8723B 0x00CC
47 /* -----------------------------------------------------
49 * 0x0100h ~ 0x01FFh MACTOP General Configuration
51 * ----------------------------------------------------- */
52 #define REG_C2HEVT_CMD_ID_8723B 0x01A0
53 #define REG_C2HEVT_CMD_LEN_8723B 0x01AE
54 #define REG_WOWLAN_WAKE_REASON 0x01C7
55 #define REG_WOWLAN_GTK_DBG1 0x630
56 #define REG_WOWLAN_GTK_DBG2 0x634
58 #define REG_HMEBOX_EXT0_8723B 0x01F0
59 #define REG_HMEBOX_EXT1_8723B 0x01F4
60 #define REG_HMEBOX_EXT2_8723B 0x01F8
61 #define REG_HMEBOX_EXT3_8723B 0x01FC
63 /* -----------------------------------------------------
65 * 0x0200h ~ 0x027Fh TXDMA Configuration
67 * ----------------------------------------------------- */
69 /* -----------------------------------------------------
71 * 0x0280h ~ 0x02FFh RXDMA Configuration
73 * ----------------------------------------------------- */
74 #define REG_RXDMA_CONTROL_8723B 0x0286 /* Control the RX DMA. */
75 #define REG_RXDMA_MODE_CTRL_8723B 0x0290
77 /* -----------------------------------------------------
79 * 0x0300h ~ 0x03FFh PCIe
81 * ----------------------------------------------------- */
82 #define REG_PCIE_CTRL_REG_8723B 0x0300
83 #define REG_INT_MIG_8723B 0x0304 /* Interrupt Migration */
84 #define REG_BCNQ_DESA_8723B 0x0308 /* TX Beacon Descriptor Address */
85 #define REG_HQ_DESA_8723B 0x0310 /* TX High Queue Descriptor Address */
86 #define REG_MGQ_DESA_8723B 0x0318 /* TX Manage Queue Descriptor Address */
87 #define REG_VOQ_DESA_8723B 0x0320 /* TX VO Queue Descriptor Address */
88 #define REG_VIQ_DESA_8723B 0x0328 /* TX VI Queue Descriptor Address */
89 #define REG_BEQ_DESA_8723B 0x0330 /* TX BE Queue Descriptor Address */
90 #define REG_BKQ_DESA_8723B 0x0338 /* TX BK Queue Descriptor Address */
91 #define REG_RX_DESA_8723B 0x0340 /* RX Queue Descriptor Address */
92 #define REG_DBI_WDATA_8723B 0x0348 /* DBI Write Data */
93 #define REG_DBI_RDATA_8723B 0x034C /* DBI Read Data */
94 #define REG_DBI_ADDR_8723B 0x0350 /* DBI Address */
95 #define REG_DBI_FLAG_8723B 0x0352 /* DBI Read/Write Flag */
96 #define REG_MDIO_WDATA_8723B 0x0354 /* MDIO for Write PCIE PHY */
97 #define REG_MDIO_RDATA_8723B 0x0356 /* MDIO for Reads PCIE PHY */
98 #define REG_MDIO_CTL_8723B 0x0358 /* MDIO for Control */
99 #define REG_DBG_SEL_8723B 0x0360 /* Debug Selection Register */
100 #define REG_PCIE_HRPWM_8723B 0x0361 /* PCIe RPWM */
101 #define REG_PCIE_HCPWM_8723B 0x0363 /* PCIe CPWM */
102 #define REG_PCIE_MULTIFET_CTRL_8723B 0x036A /* PCIE Multi-Fethc Control */
104 /* -----------------------------------------------------
106 * 0x0400h ~ 0x047Fh Protocol Configuration
108 * ----------------------------------------------------- */
109 #define REG_TXPKTBUF_BCNQ_BDNY_8723B 0x0424
110 #define REG_TXPKTBUF_MGQ_BDNY_8723B 0x0425
111 #define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B 0x045D
113 #define REG_TXPKTBUF_IV_LOW 0x0484
114 #define REG_TXPKTBUF_IV_HIGH 0x0488
116 #define REG_AMPDU_BURST_MODE_8723B 0x04BC
118 /* -----------------------------------------------------
120 * 0x0500h ~ 0x05FFh EDCA Configuration
122 * ----------------------------------------------------- */
123 #define REG_SECONDARY_CCA_CTRL_8723B 0x0577
125 /* -----------------------------------------------------
127 * 0x0600h ~ 0x07FFh WMAC Configuration
129 * ----------------------------------------------------- */
132 /* ************************************************************
133 * SDIO Bus Specification
134 * ************************************************************ */
136 /* -----------------------------------------------------
137 * SDIO CMD Address Mapping
138 * ----------------------------------------------------- */
140 /* -----------------------------------------------------
141 * I/O bus domain (Host)
142 * ----------------------------------------------------- */
144 /* -----------------------------------------------------
146 * ----------------------------------------------------- */
147 #define SDIO_REG_HCPWM1_8723B 0x025 /* HCI Current Power Mode 1 */
150 /* ****************************************************************************
151 * 8723 Regsiter Bit and Content definition
152 * **************************************************************************** */
155 * interrupt mask which needs to clear */
156 #define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\
162 /* -----------------------------------------------------
164 * 0x0100h ~ 0x01FFh MACTOP General Configuration
166 * ----------------------------------------------------- */
168 #define IS_E_CUT(version) FALSE
170 #define IS_F_CUT(version) ((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? TRUE : FALSE)
172 /* -----------------------------------------------------
174 * 0x0200h ~ 0x027Fh TXDMA Configuration
176 * ----------------------------------------------------- */
178 /* -----------------------------------------------------
180 * 0x0280h ~ 0x02FFh RXDMA Configuration
182 * ----------------------------------------------------- */
183 #define BIT_USB_RXDMA_AGG_EN BIT(31)
184 #define RXDMA_AGG_MODE_EN BIT(1)
187 #define RXPKT_RELEASE_POLL BIT(16)
188 #define RXDMA_IDLE BIT(17)
189 #define RW_RELEASE_EN BIT(18)
192 /* -----------------------------------------------------
194 * 0x0400h ~ 0x047Fh Protocol Configuration
196 * ----------------------------------------------------- */
198 /* ----------------------------------------------------------------------------
199 * 8723B REG_CCK_CHECK (offset 0x454)
200 * ---------------------------------------------------------------------------- */
201 #define BIT_BCN_PORT_SEL BIT(5)
203 /* -----------------------------------------------------
205 * 0x0500h ~ 0x05FFh EDCA Configuration
207 * ----------------------------------------------------- */
209 /* -----------------------------------------------------
211 * 0x0600h ~ 0x07FFh WMAC Configuration
213 * ----------------------------------------------------- */
214 #ifdef CONFIG_RF_POWER_TRIM
216 #ifdef CONFIG_RTL8723B
217 #define EEPROM_RF_GAIN_OFFSET 0xC1
220 #define EEPROM_RF_GAIN_VAL 0x1F6
221 #endif /*CONFIG_RF_POWER_TRIM*/
224 /* ----------------------------------------------------------------------------
225 * 8195 IMR/ISR bits (offset 0xB0, 8bits)
226 * ---------------------------------------------------------------------------- */
227 #define IMR_DISABLED_8723B 0
228 /* IMR DW0(0x00B0-00B3) Bit 0-31 */
229 #define IMR_TIMER2_8723B BIT(31) /* Timeout interrupt 2 */
230 #define IMR_TIMER1_8723B BIT(30) /* Timeout interrupt 1 */
231 #define IMR_PSTIMEOUT_8723B BIT(29) /* Power Save Time Out Interrupt */
232 #define IMR_GTINT4_8723B BIT(28) /* When GTIMER4 expires, this bit is set to 1 */
233 #define IMR_GTINT3_8723B BIT(27) /* When GTIMER3 expires, this bit is set to 1 */
234 #define IMR_TXBCN0ERR_8723B BIT(26) /* Transmit Beacon0 Error */
235 #define IMR_TXBCN0OK_8723B BIT(25) /* Transmit Beacon0 OK */
236 #define IMR_TSF_BIT32_TOGGLE_8723B BIT(24) /* TSF Timer BIT(32) toggle indication interrupt */
237 #define IMR_BCNDMAINT0_8723B BIT(20) /* Beacon DMA Interrupt 0 */
238 #define IMR_BCNDERR0_8723B BIT(16) /* Beacon Queue DMA OK0 */
239 #define IMR_HSISR_IND_ON_INT_8723B BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
240 #define IMR_BCNDMAINT_E_8723B BIT(14) /* Beacon DMA Interrupt Extension for Win7 */
241 #define IMR_ATIMEND_8723B BIT(12) /* CTWidnow End or ATIM Window End */
242 #define IMR_C2HCMD_8723B BIT(10) /* CPU to Host Command INT Status, Write 1 clear */
243 #define IMR_CPWM2_8723B BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */
244 #define IMR_CPWM_8723B BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */
245 #define IMR_HIGHDOK_8723B BIT(7) /* High Queue DMA OK */
246 #define IMR_MGNTDOK_8723B BIT(6) /* Management Queue DMA OK */
247 #define IMR_BKDOK_8723B BIT(5) /* AC_BK DMA OK */
248 #define IMR_BEDOK_8723B BIT(4) /* AC_BE DMA OK */
249 #define IMR_VIDOK_8723B BIT(3) /* AC_VI DMA OK */
250 #define IMR_VODOK_8723B BIT(2) /* AC_VO DMA OK */
251 #define IMR_RDU_8723B BIT(1) /* Rx Descriptor Unavailable */
252 #define IMR_ROK_8723B BIT(0) /* Receive DMA OK */
254 /* IMR DW1(0x00B4-00B7) Bit 0-31 */
255 #define IMR_BCNDMAINT7_8723B BIT(27) /* Beacon DMA Interrupt 7 */
256 #define IMR_BCNDMAINT6_8723B BIT(26) /* Beacon DMA Interrupt 6 */
257 #define IMR_BCNDMAINT5_8723B BIT(25) /* Beacon DMA Interrupt 5 */
258 #define IMR_BCNDMAINT4_8723B BIT(24) /* Beacon DMA Interrupt 4 */
259 #define IMR_BCNDMAINT3_8723B BIT(23) /* Beacon DMA Interrupt 3 */
260 #define IMR_BCNDMAINT2_8723B BIT(22) /* Beacon DMA Interrupt 2 */
261 #define IMR_BCNDMAINT1_8723B BIT(21) /* Beacon DMA Interrupt 1 */
262 #define IMR_BCNDOK7_8723B BIT(20) /* Beacon Queue DMA OK Interrupt 7 */
263 #define IMR_BCNDOK6_8723B BIT(19) /* Beacon Queue DMA OK Interrupt 6 */
264 #define IMR_BCNDOK5_8723B BIT(18) /* Beacon Queue DMA OK Interrupt 5 */
265 #define IMR_BCNDOK4_8723B BIT(17) /* Beacon Queue DMA OK Interrupt 4 */
266 #define IMR_BCNDOK3_8723B BIT(16) /* Beacon Queue DMA OK Interrupt 3 */
267 #define IMR_BCNDOK2_8723B BIT(15) /* Beacon Queue DMA OK Interrupt 2 */
268 #define IMR_BCNDOK1_8723B BIT(14) /* Beacon Queue DMA OK Interrupt 1 */
269 #define IMR_ATIMEND_E_8723B BIT(13) /* ATIM Window End Extension for Win7 */
270 #define IMR_TXERR_8723B BIT(11) /* Tx Error Flag Interrupt Status, write 1 clear. */
271 #define IMR_RXERR_8723B BIT(10) /* Rx Error Flag INT Status, Write 1 clear */
272 #define IMR_TXFOVW_8723B BIT(9) /* Transmit FIFO Overflow */
273 #define IMR_RXFOVW_8723B BIT(8) /* Receive FIFO Overflow */
275 #ifdef CONFIG_PCI_HCI
276 /* #define IMR_RX_MASK (IMR_ROK_8723B|IMR_RDU_8723B|IMR_RXFOVW_8723B) */
277 #define IMR_TX_MASK (IMR_VODOK_8723B | IMR_VIDOK_8723B | IMR_BEDOK_8723B | IMR_BKDOK_8723B | IMR_MGNTDOK_8723B | IMR_HIGHDOK_8723B)
279 #define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8723B | IMR_TXBCN0OK_8723B | IMR_TXBCN0ERR_8723B | IMR_BCNDERR0_8723B)
281 #define RT_AC_INT_MASKS (IMR_VIDOK_8723B | IMR_VODOK_8723B | IMR_BEDOK_8723B | IMR_BKDOK_8723B)
284 #endif /* __RTL8723B_SPEC_H__ */