1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
20 #ifndef __INC_HAL8723DPHYREG_H__
21 #define __INC_HAL8723DPHYREG_H__
23 #define rSYM_WLBT_PAPE_SEL 0x64
25 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
26 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
27 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
28 * 3. RF register 0x00-2E
29 * 4. Bit Mask for BB/RF register
30 * 5. Other definition for BB/RF R/W
35 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
38 #define rPMAC_Reset 0x100
39 #define rPMAC_TxStart 0x104
40 #define rPMAC_TxLegacySIG 0x108
41 #define rPMAC_TxHTSIG1 0x10c
42 #define rPMAC_TxHTSIG2 0x110
43 #define rPMAC_PHYDebug 0x114
44 #define rPMAC_TxPacketNum 0x118
45 #define rPMAC_TxIdle 0x11c
46 #define rPMAC_TxMACHeader0 0x120
47 #define rPMAC_TxMACHeader1 0x124
48 #define rPMAC_TxMACHeader2 0x128
49 #define rPMAC_TxMACHeader3 0x12c
50 #define rPMAC_TxMACHeader4 0x130
51 #define rPMAC_TxMACHeader5 0x134
52 #define rPMAC_TxDataType 0x138
53 #define rPMAC_TxRandomSeed 0x13c
54 #define rPMAC_CCKPLCPPreamble 0x140
55 #define rPMAC_CCKPLCPHeader 0x144
56 #define rPMAC_CCKCRC16 0x148
57 #define rPMAC_OFDMRxCRC32OK 0x170
58 #define rPMAC_OFDMRxCRC32Er 0x174
59 #define rPMAC_OFDMRxParityEr 0x178
60 #define rPMAC_OFDMRxCRC8Er 0x17c
61 #define rPMAC_CCKCRxRC16Er 0x180
62 #define rPMAC_CCKCRxRC32Er 0x184
63 #define rPMAC_CCKCRxRC32OK 0x188
64 #define rPMAC_TxStatus 0x18c
69 * The following two definition are only used for USB interface. */
70 #define RF_BB_CMD_ADDR 0x02c0 /* RF/BB read/write command address. */
71 #define RF_BB_CMD_DATA 0x02c4 /* RF/BB read/write command data. */
76 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC // RF BW Setting?? */
78 #define rFPGA0_TxInfo 0x804 /* Status report?? */
79 #define rFPGA0_PSDFunction 0x808
81 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */
83 #define rFPGA0_RFTiming1 0x810 /* Useless now */
84 #define rFPGA0_RFTiming2 0x814
86 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
87 #define rFPGA0_XA_HSSIParameter2 0x824
88 #define rFPGA0_XB_HSSIParameter1 0x828
89 #define rFPGA0_XB_HSSIParameter2 0x82c
90 #define rTxAGC_B_Rate18_06 0x830
91 #define rTxAGC_B_Rate54_24 0x834
92 #define rTxAGC_B_CCK1_55_Mcs32 0x838
93 #define rTxAGC_B_Mcs03_Mcs00 0x83c
95 #define rTxAGC_B_Mcs07_Mcs04 0x848
96 #define rTxAGC_B_Mcs11_Mcs08 0x84c
98 #define rFPGA0_XA_LSSIParameter 0x840
99 #define rFPGA0_XB_LSSIParameter 0x844
101 #define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */
102 #define rFPGA0_RFSleepUpParameter 0x854
104 #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */
105 #define rFPGA0_XCD_SwitchControl 0x85c
107 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */
108 #define rFPGA0_XB_RFInterfaceOE 0x864
110 #define rTxAGC_B_Mcs15_Mcs12 0x868
111 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c
113 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */
114 #define rFPGA0_XCD_RFInterfaceSW 0x874
116 #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */
117 #define rFPGA0_XCD_RFParameter 0x87c
119 #define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */
120 #define rFPGA0_AnalogParameter2 0x884
121 #define rFPGA0_AnalogParameter3 0x888 /* Useless now */
122 #define rFPGA0_AnalogParameter4 0x88c
124 #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */
125 #define rFPGA0_XB_LSSIReadBack 0x8a4
126 #define rFPGA0_XC_LSSIReadBack 0x8a8
127 #define rFPGA0_XD_LSSIReadBack 0x8ac
129 #define rFPGA0_PSDReport 0x8b4 /* Useless now */
130 #define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */
131 #define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */
132 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now // RF Interface Readback Value */
133 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */
138 #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC // RF BW Setting?? */
139 #define rFPGA1_TxBlock 0x904 /* Useless now */
140 #define rFPGA1_DebugSelect 0x908 /* Useless now */
141 #define rFPGA1_TxInfo 0x90c /* Useless now // Status report?? */
142 #define rDPDT_control 0x92c
143 #define rfe_ctrl_anta_src 0x930
144 #define rS0S1_PathSwitch 0x948
145 #define rBBrx_DFIR 0x954
150 * Set Control channel to upper or lower. These settings are required only for 40MHz */
151 #define rCCK0_System 0xa00
153 #define rCCK0_AFESetting 0xa04 /* Disable init gain now // Select RX path by RSSI */
154 #define rCCK0_CCA 0xa08 /* Disable init gain now // Init gain */
156 #define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */
157 #define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */
159 #define rCCK0_RxHP 0xa14
161 #define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */
162 #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */
164 #define rCCK0_TxFilter1 0xa20
165 #define rCCK0_TxFilter2 0xa24
166 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */
167 #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */
168 #define rCCK0_TRSSIReport 0xa50
169 #define rCCK0_RxReport 0xa54 /* 0xa57 */
170 #define rCCK0_FACounterLower 0xa5c /* 0xa5b */
171 #define rCCK0_FACounterUpper 0xa58 /* 0xa5c */
176 #define rPdp_AntA 0xb00
177 #define rPdp_AntA_4 0xb04
178 #define rPdp_AntA_8 0xb08
179 #define rPdp_AntA_C 0xb0c
180 #define rPdp_AntA_10 0xb10
181 #define rPdp_AntA_14 0xb14
182 #define rPdp_AntA_18 0xb18
183 #define rPdp_AntA_1C 0xb1c
184 #define rPdp_AntA_20 0xb20
185 #define rPdp_AntA_24 0xb24
187 #define rConfig_Pmpd_AntA 0xb28
188 #define rConfig_ram64x16 0xb2c
191 #define rHssiPar 0xb34
193 #define rConfig_AntA 0xb68
194 #define rConfig_AntB 0xb6c
196 #define rPdp_AntB 0xb70
197 #define rPdp_AntB_4 0xb74
198 #define rPdp_AntB_8 0xb78
199 #define rPdp_AntB_C 0xb7c
200 #define rPdp_AntB_10 0xb80
201 #define rPdp_AntB_14 0xb84
202 #define rPdp_AntB_18 0xb88
203 #define rPdp_AntB_1C 0xb8c
204 #define rPdp_AntB_20 0xb90
205 #define rPdp_AntB_24 0xb94
207 #define rConfig_Pmpd_AntB 0xb98
212 #define rPm_Rx0_AntA 0xbdc
213 #define rPm_Rx1_AntA 0xbe0
214 #define rPm_Rx2_AntA 0xbe4
215 #define rPm_Rx3_AntA 0xbe8
216 #define rPm_Rx0_AntB 0xbec
217 #define rPm_Rx1_AntB 0xbf0
218 #define rPm_Rx2_AntB 0xbf4
219 #define rPm_Rx3_AntB 0xbf8
223 #define rOFDM0_LSTF 0xc00
225 #define rOFDM0_TRxPathEnable 0xc04
226 #define rOFDM0_TRMuxPar 0xc08
227 #define rOFDM0_TRSWIsolation 0xc0c
229 #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */
230 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imbalance matrix */
231 #define rOFDM0_XBRxAFE 0xc18
232 #define rOFDM0_XBRxIQImbalance 0xc1c
233 #define rOFDM0_XCRxAFE 0xc20
234 #define rOFDM0_XCRxIQImbalance 0xc24
235 #define rOFDM0_XDRxAFE 0xc28
236 #define rOFDM0_XDRxIQImbalance 0xc2c
238 #define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD // DM tune init gain */
239 #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */
240 #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */
241 #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */
243 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */
244 #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */
245 #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */
246 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */
248 #define rOFDM0_XAAGCCore1 0xc50 /* DIG */
249 #define rOFDM0_XAAGCCore2 0xc54
250 #define rOFDM0_XBAGCCore1 0xc58
251 #define rOFDM0_XBAGCCore2 0xc5c
252 #define rOFDM0_XCAGCCore1 0xc60
253 #define rOFDM0_XCAGCCore2 0xc64
254 #define rOFDM0_XDAGCCore1 0xc68
255 #define rOFDM0_XDAGCCore2 0xc6c
257 #define rOFDM0_AGCParameter1 0xc70
258 #define rOFDM0_AGCParameter2 0xc74
259 #define rOFDM0_AGCRSSITable 0xc78
260 #define rOFDM0_HTSTFAGC 0xc7c
262 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */
263 #define rOFDM0_XATxAFE 0xc84
264 #define rOFDM0_XBTxIQImbalance 0xc88
265 #define rOFDM0_XBTxAFE 0xc8c
266 #define rOFDM0_XCTxIQImbalance 0xc90
267 #define rOFDM0_XCTxAFE 0xc94
268 #define rOFDM0_XDTxIQImbalance 0xc98
269 #define rOFDM0_XDTxAFE 0xc9c
271 #define rOFDM0_RxIQExtAnta 0xca0
272 #define rOFDM0_TxCoeff1 0xca4
273 #define rOFDM0_TxCoeff2 0xca8
274 #define rOFDM0_TxCoeff3 0xcac
275 #define rOFDM0_TxCoeff4 0xcb0
276 #define rOFDM0_TxCoeff5 0xcb4
277 #define rOFDM0_TxCoeff6 0xcb8
278 #define rOFDM0_RxHPParameter 0xce0
279 #define rOFDM0_TxPseudoNoiseWgt 0xce4
280 #define rOFDM0_FrameSync 0xcf0
281 #define rOFDM0_DFSReport 0xcf4
286 #define rOFDM1_LSTF 0xd00
287 #define rOFDM1_TRxPathEnable 0xd04
289 #define rOFDM1_CFO 0xd08 /* No setting now */
290 #define rOFDM1_CSI1 0xd10
291 #define rOFDM1_SBD 0xd14
292 #define rOFDM1_CSI2 0xd18
293 #define rOFDM1_CFOTracking 0xd2c
294 #define rOFDM1_TRxMesaure1 0xd34
295 #define rOFDM1_IntfDet 0xd3c
296 #define rOFDM1_PseudoNoiseStateAB 0xd50
297 #define rOFDM1_PseudoNoiseStateCD 0xd54
298 #define rOFDM1_RxPseudoNoiseWgt 0xd58
300 #define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */
301 #define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */
302 #define rOFDM_PHYCounter3 0xda8 /* MCS not support */
304 #define rOFDM_ShortCFOAB 0xdac /* No setting now */
305 #define rOFDM_ShortCFOCD 0xdb0
306 #define rOFDM_LongCFOAB 0xdb4
307 #define rOFDM_LongCFOCD 0xdb8
308 #define rOFDM_TailCFOAB 0xdbc
309 #define rOFDM_TailCFOCD 0xdc0
310 #define rOFDM_PWMeasure1 0xdc4
311 #define rOFDM_PWMeasure2 0xdc8
312 #define rOFDM_BWReport 0xdcc
313 #define rOFDM_AGCReport 0xdd0
314 #define rOFDM_RxSNR 0xdd4
315 #define rOFDM_RxEVMCSI 0xdd8
316 #define rOFDM_SIGReport 0xddc
322 #define rTxAGC_A_Rate18_06 0xe00
323 #define rTxAGC_A_Rate54_24 0xe04
324 #define rTxAGC_A_CCK1_Mcs32 0xe08
325 #define rTxAGC_A_Mcs03_Mcs00 0xe10
326 #define rTxAGC_A_Mcs07_Mcs04 0xe14
327 #define rTxAGC_A_Mcs11_Mcs08 0xe18
328 #define rTxAGC_A_Mcs15_Mcs12 0xe1c
330 #define rFPGA0_IQK 0xe28
331 #define rTx_IQK_Tone_A 0xe30
332 #define rRx_IQK_Tone_A 0xe34
333 #define rTx_IQK_PI_A 0xe38
334 #define rRx_IQK_PI_A 0xe3c
336 #define rTx_IQK 0xe40
337 #define rRx_IQK 0xe44
338 #define rIQK_AGC_Pts 0xe48
339 #define rIQK_AGC_Rsp 0xe4c
340 #define rTx_IQK_Tone_B 0xe50
341 #define rRx_IQK_Tone_B 0xe54
342 #define rTx_IQK_PI_B 0xe58
343 #define rRx_IQK_PI_B 0xe5c
344 #define rIQK_AGC_Cont 0xe60
346 #define rBlue_Tooth 0xe6c
347 #define rRx_Wait_CCA 0xe70
348 #define rTx_CCK_RFON 0xe74
349 #define rTx_CCK_BBON 0xe78
350 #define rTx_OFDM_RFON 0xe7c
351 #define rTx_OFDM_BBON 0xe80
352 #define rTx_To_Rx 0xe84
353 #define rTx_To_Tx 0xe88
354 #define rRx_CCK 0xe8c
356 #define rTx_Power_Before_IQK_A 0xe94
357 #define rTx_Power_After_IQK_A 0xe9c
359 #define rRx_Power_Before_IQK_A 0xea0
360 #define rRx_Power_Before_IQK_A_2 0xea4
361 #define rRx_Power_After_IQK_A 0xea8
362 #define rRx_Power_After_IQK_A_2 0xeac
364 #define rTx_Power_Before_IQK_B 0xeb4
365 #define rTx_Power_After_IQK_B 0xebc
367 #define rRx_Power_Before_IQK_B 0xec0
368 #define rRx_Power_Before_IQK_B_2 0xec4
369 #define rRx_Power_After_IQK_B 0xec8
370 #define rRx_Power_After_IQK_B_2 0xecc
372 #define rRx_OFDM 0xed0
373 #define rRx_Wait_RIFS 0xed4
374 #define rRx_TO_Rx 0xed8
375 #define rStandby 0xedc
377 #define rPMPD_ANAEN 0xeec
380 * 7. RF Register 0x00-0x2E (RF 8256)
384 #define rZebra1_HSSIEnable 0x0 /* Useless now */
385 #define rZebra1_TRxEnable1 0x1
386 #define rZebra1_TRxEnable2 0x2
387 #define rZebra1_AGC 0x4
388 #define rZebra1_ChargePump 0x5
389 #define rZebra1_Channel 0x7 /* RF channel switch */
392 #define rZebra1_TxGain 0x8 /* Useless now */
393 #define rZebra1_TxLPF 0x9
394 #define rZebra1_RxLPF 0xb
395 #define rZebra1_RxHPFCorner 0xc
398 #define rGlobalCtrl 0 /* Useless now */
399 #define rRTL8256_TxLPF 19
400 #define rRTL8256_RxLPF 11
403 #define rRTL8258_TxLPF 0x11 /* Useless now */
404 #define rRTL8258_RxLPF 0x13
405 #define rRTL8258_RSSILPF 0xa
408 * RL6052 Register definition
410 #define RF_AC 0x00 /* */
412 #define RF_IQADJ_G1 0x01 /* */
413 #define RF_IQADJ_G2 0x02 /* */
414 #define RF_BS_PA_APSET_G1_G4 0x03
415 #define RF_BS_PA_APSET_G5_G8 0x04
416 #define RF_POW_TRSW 0x05 /* */
418 #define RF_GAIN_RX 0x06 /* */
419 #define RF_GAIN_TX 0x07 /* */
421 #define RF_TXM_IDAC 0x08 /* */
422 #define RF_IPA_G 0x09 /* */
423 #define RF_TXBIAS_G 0x0A
424 #define RF_TXPA_AG 0x0B
425 #define RF_IPA_A 0x0C /* */
426 #define RF_TXBIAS_A 0x0D
427 #define RF_BS_PA_APSET_G9_G11 0x0E
428 #define RF_BS_IQGEN 0x0F /* */
430 #define RF_MODE1 0x10 /* */
431 #define RF_MODE2 0x11 /* */
433 #define RF_RX_AGC_HP 0x12 /* */
434 #define RF_TX_AGC 0x13 /* */
435 #define RF_BIAS 0x14 /* */
436 #define RF_IPA 0x15 /* */
437 #define RF_TXBIAS 0x16
438 #define RF_POW_ABILITY 0x17 /* */
439 #define RF_MODE_AG 0x18 /* */
440 #define rRfChannel 0x18 /* RF channel and BW switch */
441 #define RF_CHNLBW 0x18 /* RF channel and BW switch */
442 #define RF_TOP 0x19 /* */
444 #define RF_RX_G1 0x1A /* */
445 #define RF_RX_G2 0x1B /* */
447 #define RF_RX_BB2 0x1C /* */
448 #define RF_RX_BB1 0x1D /* */
450 #define RF_RCK1 0x1E /* */
451 #define RF_RCK2 0x1F /* */
453 #define RF_TX_G1 0x20 /* */
454 #define RF_TX_G2 0x21 /* */
455 #define RF_TX_G3 0x22 /* */
457 #define RF_TX_BB1 0x23 /* */
459 #define RF_T_METER 0x24 /* */
461 #define RF_SYN_G1 0x25 /* RF TX Power control */
462 #define RF_SYN_G2 0x26 /* RF TX Power control */
463 #define RF_SYN_G3 0x27 /* RF TX Power control */
464 #define RF_SYN_G4 0x28 /* RF TX Power control */
465 #define RF_SYN_G5 0x29 /* RF TX Power control */
466 #define RF_SYN_G6 0x2A /* RF TX Power control */
467 #define RF_SYN_G7 0x2B /* RF TX Power control */
468 #define RF_SYN_G8 0x2C /* RF TX Power control */
470 #define RF_RCK_OS 0x30 /* RF TX PA control */
472 #define RF_TXPA_G1 0x31 /* RF TX PA control */
473 #define RF_TXPA_G2 0x32 /* RF TX PA control */
474 #define RF_TXPA_G3 0x33 /* RF TX PA control */
475 #define RF_TX_BIAS_A 0x35
476 #define RF_TX_BIAS_D 0x36
477 #define RF_LOBF_9 0x38
478 #define RF_RXRF_A3 0x3C /* */
481 #define RF_TXRF_A2 0x41
482 #define RF_T_METER_88E 0x42
483 #define RF_TXPA_G4 0x46
484 #define RF_TXPA_A4 0x4B
486 #define RF_WE_LUT 0xEF
493 #define bBBResetB 0x100 /* Useless now? */
494 #define bGlobalResetB 0x200
495 #define bOFDMTxStart 0x4
496 #define bCCKTxStart 0x8
497 #define bCRC32Debug 0x100
498 #define bPMACLoopback 0x10
499 #define bTxLSIG 0xffffff
500 #define bOFDMTxRate 0xf
501 #define bOFDMTxReserved 0x10
502 #define bOFDMTxLength 0x1ffe0
503 #define bOFDMTxParity 0x20000
504 #define bTxHTSIG1 0xffffff
505 #define bTxHTMCSRate 0x7f
507 #define bTxHTLength 0xffff00
508 #define bTxHTSIG2 0xffffff
509 #define bTxHTSmoothing 0x1
510 #define bTxHTSounding 0x2
511 #define bTxHTReserved 0x4
512 #define bTxHTAggreation 0x8
513 #define bTxHTSTBC 0x30
514 #define bTxHTAdvanceCoding 0x40
515 #define bTxHTShortGI 0x80
516 #define bTxHTNumberHT_LTF 0x300
517 #define bTxHTCRC8 0x3fc00
518 #define bCounterReset 0x10000
519 #define bNumOfOFDMTx 0xffff
520 #define bNumOfCCKTx 0xffff0000
521 #define bTxIdleInterval 0xffff
522 #define bOFDMService 0xffff0000
523 #define bTxMACHeader 0xffffffff
524 #define bTxDataInit 0xff
525 #define bTxHTMode 0x100
526 #define bTxDataType 0x30000
527 #define bTxRandomSeed 0xffffffff
528 #define bCCKTxPreamble 0x1
529 #define bCCKTxSFD 0xffff0000
530 #define bCCKTxSIG 0xff
531 #define bCCKTxService 0xff00
532 #define bCCKLengthExt 0x8000
533 #define bCCKTxLength 0xffff0000
534 #define bCCKTxCRC16 0xffff
535 #define bCCKTxStatus 0x1
536 #define bOFDMTxStatus 0x2
538 #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))
539 #define RF_TX_GAIN_OFFSET_8723D(_val) (abs((_val)) | (((_val) > 0) ? BIT(4) : 0))
541 /* 2. Page8(0x800) */
542 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */
543 #define bJapanMode 0x2
544 #define bCCKTxSC 0x30
545 #define bCCKEn 0x1000000
546 #define bOFDMEn 0x2000000
548 #define bOFDMRxADCPhase 0x10000 /* Useless now */
549 #define bOFDMTxDACPhase 0x40000
550 #define bXATxAGC 0x3f
552 #define bAntennaSelect 0x0300
554 #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */
555 #define bXCTxAGC 0xf000
556 #define bXDTxAGC 0xf0000
558 #define bPAStart 0xf0000000 /* Useless now */
559 #define bTRStart 0x00f00000
560 #define bRFStart 0x0000f000
561 #define bBBStart 0x000000f0
562 #define bBBCCKStart 0x0000000f
563 #define bPAEnd 0xf /* Reg0x814 */
564 #define bTREnd 0x0f000000
565 #define bRFEnd 0x000f0000
566 #define bCCAMask 0x000000f0 /* T2R */
567 #define bR2RCCAMask 0x00000f00
568 #define bHSSI_R2TDelay 0xf8000000
569 #define bHSSI_T2RDelay 0xf80000
570 #define bContTxHSSI 0x400 /* chane gain at continue Tx */
571 #define bIGFromCCK 0x200
572 #define bAGCAddress 0x3f
573 #define bRxHPTx 0x7000
574 #define bRxHPT2R 0x38000
575 #define bRxHPCCKIni 0xc0000
576 #define bAGCTxCode 0xc00000
577 #define bAGCRxCode 0x300000
579 #define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */
580 #define b3WireAddressLength 0x400
582 #define b3WireRFPowerDown 0x1 /* Useless now
583 * #define bHWSISelect 0x8 */
584 #define b5GPAPEPolarity 0x40000000
585 #define b2GPAPEPolarity 0x80000000
586 #define bRFSW_TxDefaultAnt 0x3
587 #define bRFSW_TxOptionAnt 0x30
588 #define bRFSW_RxDefaultAnt 0x300
589 #define bRFSW_RxOptionAnt 0x3000
590 #define bRFSI_3WireData 0x1
591 #define bRFSI_3WireClock 0x2
592 #define bRFSI_3WireLoad 0x4
593 #define bRFSI_3WireRW 0x8
594 #define bRFSI_3Wire 0xf
596 #define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */
598 #define bRFSI_TRSW 0x20 /* Useless now */
599 #define bRFSI_TRSWB 0x40
600 #define bRFSI_ANTSW 0x100
601 #define bRFSI_ANTSWB 0x200
602 #define bRFSI_PAPE 0x400
603 #define bRFSI_PAPE5G 0x800
604 #define bBandSelect 0x1
605 #define bHTSIG2_GI 0x80
606 #define bHTSIG2_Smoothing 0x01
607 #define bHTSIG2_Sounding 0x02
608 #define bHTSIG2_Aggreaton 0x08
609 #define bHTSIG2_STBC 0x30
610 #define bHTSIG2_AdvCoding 0x40
611 #define bHTSIG2_NumOfHTLTF 0x300
612 #define bHTSIG2_CRC8 0x3fc
613 #define bHTSIG1_MCS 0x7f
614 #define bHTSIG1_BandWidth 0x80
615 #define bHTSIG1_HTLength 0xffff
616 #define bLSIG_Rate 0xf
617 #define bLSIG_Reserved 0x10
618 #define bLSIG_Length 0x1fffe
619 #define bLSIG_Parity 0x20
620 #define bCCKRxPhase 0x4
622 #define bLSSIReadAddress 0x7f800000 /* T65 RF */
624 #define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */
626 #define bLSSIReadBackData 0xfffff /* T65 RF */
628 #define bLSSIReadOKFlag 0x1000 /* Useless now */
629 #define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */
630 #define bRegulator0Standby 0x1
631 #define bRegulatorPLLStandby 0x2
632 #define bRegulator1Standby 0x4
633 #define bPLLPowerUp 0x8
634 #define bDPLLPowerUp 0x10
635 #define bDA10PowerUp 0x20
636 #define bAD7PowerUp 0x200
637 #define bDA6PowerUp 0x2000
638 #define bXtalPowerUp 0x4000
639 #define b40MDClkPowerUP 0x8000
640 #define bDA6DebugMode 0x20000
641 #define bDA6Swing 0x380000
643 #define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */
645 #define b80MClkDelay 0x18000000 /* Useless */
646 #define bAFEWatchDogEnable 0x20000000
648 #define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */
649 #define bXtalCap23 0x3
650 #define bXtalCap92x 0x0f000000
651 #define bXtalCap 0x0f000000
653 #define bIntDifClkEnable 0x400 /* Useless */
654 #define bExtSigClkEnable 0x800
655 #define bBandgapMbiasPowerUp 0x10000
656 #define bAD11SHGain 0xc0000
657 #define bAD11InputRange 0x700000
658 #define bAD11OPCurrent 0x3800000
659 #define bIPathLoopback 0x4000000
660 #define bQPathLoopback 0x8000000
661 #define bAFELoopback 0x10000000
662 #define bDA10Swing 0x7e0
663 #define bDA10Reverse 0x800
664 #define bDAClkSource 0x1000
665 #define bAD7InputRange 0x6000
666 #define bAD7Gain 0x38000
667 #define bAD7OutputCMMode 0x40000
668 #define bAD7InputCMMode 0x380000
669 #define bAD7Current 0xc00000
670 #define bRegulatorAdjust 0x7000000
671 #define bAD11PowerUpAtTx 0x1
672 #define bDA10PSAtTx 0x10
673 #define bAD11PowerUpAtRx 0x100
674 #define bDA10PSAtRx 0x1000
675 #define bCCKRxAGCFormat 0x200
676 #define bPSDFFTSamplepPoint 0xc000
677 #define bPSDAverageNum 0x3000
678 #define bIQPathControl 0xc00
679 #define bPSDFreq 0x3ff
680 #define bPSDAntennaPath 0x30
681 #define bPSDIQSwitch 0x40
682 #define bPSDRxTrigger 0x400000
683 #define bPSDTxTrigger 0x80000000
684 #define bPSDSineToneScale 0x7f000000
685 #define bPSDReport 0xffff
687 /* 3. Page9(0x900) */
688 #define bOFDMTxSC 0x30000000 /* Useless */
690 #define bOFDMTxOn 0x2
691 #define bDebugPage 0xfff /* reset debug page and also HWord, LWord */
692 #define bDebugItem 0xff /* reset debug page and LWord */
694 #define bAntNonHT 0x100
695 #define bAntHT1 0x1000
696 #define bAntHT2 0x10000
697 #define bAntHT1S1 0x100000
698 #define bAntNonHTS1 0x1000000
700 /* 4. PageA(0xA00) */
701 #define bCCKBBMode 0x3 /* Useless */
702 #define bCCKTxPowerSaving 0x80
703 #define bCCKRxPowerSaving 0x40
705 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */
707 #define bCCKScramble 0x8 /* Useless */
708 #define bCCKAntDiversity 0x8000
709 #define bCCKCarrierRecovery 0x4000
710 #define bCCKTxRate 0x3000
711 #define bCCKDCCancel 0x0800
712 #define bCCKISICancel 0x0400
713 #define bCCKMatchFilter 0x0200
714 #define bCCKEqualizer 0x0100
715 #define bCCKPreambleDetect 0x800000
716 #define bCCKFastFalseCCA 0x400000
717 #define bCCKChEstStart 0x300000
718 #define bCCKCCACount 0x080000
719 #define bCCKcs_lim 0x070000
720 #define bCCKBistMode 0x80000000
721 #define bCCKCCAMask 0x40000000
722 #define bCCKTxDACPhase 0x4
723 #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */
724 #define bCCKr_cp_mode0 0x0100
725 #define bCCKTxDCOffset 0xf0
726 #define bCCKRxDCOffset 0xf
727 #define bCCKCCAMode 0xc000
728 #define bCCKFalseCS_lim 0x3f00
729 #define bCCKCS_ratio 0xc00000
730 #define bCCKCorgBit_sel 0x300000
731 #define bCCKPD_lim 0x0f0000
732 #define bCCKNewCCA 0x80000000
733 #define bCCKRxHPofIG 0x8000
734 #define bCCKRxIG 0x7f00
735 #define bCCKLNAPolarity 0x800000
736 #define bCCKRx1stGain 0x7f0000
737 #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */
738 #define bCCKRxAGCSatLevel 0x1f000000
739 #define bCCKRxAGCSatCount 0xe0
740 #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */
741 #define bCCKFixedRxAGC 0x8000
742 /* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */
743 #define bCCKAntennaPolarity 0x2000
744 #define bCCKTxFilterType 0x0c00
745 #define bCCKRxAGCReportType 0x0300
746 #define bCCKRxDAGCEn 0x80000000
747 #define bCCKRxDAGCPeriod 0x20000000
748 #define bCCKRxDAGCSatLevel 0x1f000000
749 #define bCCKTimingRecovery 0x800000
750 #define bCCKTxC0 0x3f0000
751 #define bCCKTxC1 0x3f000000
752 #define bCCKTxC2 0x3f
753 #define bCCKTxC3 0x3f00
754 #define bCCKTxC4 0x3f0000
755 #define bCCKTxC5 0x3f000000
756 #define bCCKTxC6 0x3f
757 #define bCCKTxC7 0x3f00
758 #define bCCKDebugPort 0xff0000
759 #define bCCKDACDebug 0x0f000000
760 #define bCCKFalseAlarmEnable 0x8000
761 #define bCCKFalseAlarmRead 0x4000
762 #define bCCKTRSSI 0x7f
763 #define bCCKRxAGCReport 0xfe
764 #define bCCKRxReport_AntSel 0x80000000
765 #define bCCKRxReport_MFOff 0x40000000
766 #define bCCKRxRxReport_SQLoss 0x20000000
767 #define bCCKRxReport_Pktloss 0x10000000
768 #define bCCKRxReport_Lockedbit 0x08000000
769 #define bCCKRxReport_RateError 0x04000000
770 #define bCCKRxReport_RxRate 0x03000000
771 #define bCCKRxFACounterLower 0xff
772 #define bCCKRxFACounterUpper 0xff000000
773 #define bCCKRxHPAGCStart 0xe000
774 #define bCCKRxHPAGCFinal 0x1c00
775 #define bCCKRxFalseAlarmEnable 0x8000
776 #define bCCKFACounterFreeze 0x4000
777 #define bCCKTxPathSel 0x10000000
778 #define bCCKDefaultRxPath 0xc000000
779 #define bCCKOptionRxPath 0x3000000
781 /* 5. PageC(0xC00) */
782 #define bNumOfSTF 0x3 /* Useless */
783 #define bShift_L 0xc0
793 #define bTRSSIFreq 0x200
794 #define bADCBackoff 0x3000
795 #define bDFIRBackoff 0xc000
796 #define bTRSSILatchPhase 0x10000
797 #define bRxIDCOffset 0xff
798 #define bRxQDCOffset 0xff00
799 #define bRxDFIRMode 0x1800000
800 #define bRxDCNFType 0xe000000
801 #define bRXIQImb_A 0x3ff
802 #define bRXIQImb_B 0xfc00
803 #define bRXIQImb_C 0x3f0000
804 #define bRXIQImb_D 0xffc00000
805 #define bDC_dc_Notch 0x60000
806 #define bRxNBINotch 0x1f000000
808 #define bPD_TH_Opt2 0xc000
809 #define bPWED_TH 0x700
810 #define bIfMF_Win_L 0x800
811 #define bPD_Option 0x1000
812 #define bMF_Win_L 0xe000
813 #define bBW_Search_L 0x30000
814 #define bwin_enh_L 0xc0000
815 #define bBW_TH 0x700000
816 #define bED_TH2 0x3800000
817 #define bBW_option 0x4000000
818 #define bRatio_TH 0x18000000
819 #define bWindow_L 0xe0000000
820 #define bSBD_Option 0x1
821 #define bFrame_TH 0x1c
822 #define bFS_Option 0x60
823 #define bDC_Slope_check 0x80
824 #define bFGuard_Counter_DC_L 0xe00
825 #define bFrame_Weight_Short 0x7000
826 #define bSub_Tune 0xe00000
827 #define bFrame_DC_Length 0xe000000
828 #define bSBD_start_offset 0x30000000
829 #define bFrame_TH_2 0x7
830 #define bFrame_GI2_TH 0x38
831 #define bGI2_Sync_en 0x40
832 #define bSarch_Short_Early 0x300
833 #define bSarch_Short_Late 0xc00
834 #define bSarch_GI2_Late 0x70000
835 #define bCFOAntSum 0x1
837 #define bCFOStartOffset 0xc
838 #define bCFOLookBack 0x70
839 #define bCFOSumWeight 0x80
840 #define bDAGCEnable 0x10000
841 #define bTXIQImb_A 0x3ff
842 #define bTXIQImb_B 0xfc00
843 #define bTXIQImb_C 0x3f0000
844 #define bTXIQImb_D 0xffc00000
845 #define bTxIDCOffset 0xff
846 #define bTxQDCOffset 0xff00
847 #define bTxDFIRMode 0x10000
848 #define bTxPesudoNoiseOn 0x4000000
849 #define bTxPesudoNoise_A 0xff
850 #define bTxPesudoNoise_B 0xff00
851 #define bTxPesudoNoise_C 0xff0000
852 #define bTxPesudoNoise_D 0xff000000
853 #define bCCADropOption 0x20000
854 #define bCCADropThres 0xfff00000
856 #define bEDCCA_L 0xf0
857 #define bLambda_ED 0x300
858 #define bRxInitialGain 0x7f
859 #define bRxAntDivEn 0x80
860 #define bRxAGCAddressForLNA 0x7f00
861 #define bRxHighPowerFlow 0x8000
862 #define bRxAGCFreezeThres 0xc0000
863 #define bRxFreezeStep_AGC1 0x300000
864 #define bRxFreezeStep_AGC2 0xc00000
865 #define bRxFreezeStep_AGC3 0x3000000
866 #define bRxFreezeStep_AGC0 0xc000000
867 #define bRxRssi_Cmp_En 0x10000000
868 #define bRxQuickAGCEn 0x20000000
869 #define bRxAGCFreezeThresMode 0x40000000
870 #define bRxOverFlowCheckType 0x80000000
871 #define bRxAGCShift 0x7f
872 #define bTRSW_Tri_Only 0x80
873 #define bPowerThres 0x300
875 #define bRxAGCTogetherEn 0x2
876 #define bRxAGCMin 0x4
877 #define bRxHP_Ini 0x7
878 #define bRxHP_TRLNA 0x70
879 #define bRxHP_RSSI 0x700
880 #define bRxHP_BBP1 0x7000
881 #define bRxHP_BBP2 0x70000
882 #define bRxHP_BBP3 0x700000
883 #define bRSSI_H 0x7f0000 /* the threshold for high power */
884 #define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */
885 #define bRxSettle_TRSW 0x7
886 #define bRxSettle_LNA 0x38
887 #define bRxSettle_RSSI 0x1c0
888 #define bRxSettle_BBP 0xe00
889 #define bRxSettle_RxHP 0x7000
890 #define bRxSettle_AntSW_RSSI 0x38000
891 #define bRxSettle_AntSW 0xc0000
892 #define bRxProcessTime_DAGC 0x300000
893 #define bRxSettle_HSSI 0x400000
894 #define bRxProcessTime_BBPPW 0x800000
895 #define bRxAntennaPowerShift 0x3000000
896 #define bRSSITableSelect 0xc000000
897 #define bRxHP_Final 0x7000000
898 #define bRxHTSettle_BBP 0x7
899 #define bRxHTSettle_HSSI 0x8
900 #define bRxHTSettle_RxHP 0x70
901 #define bRxHTSettle_BBPPW 0x80
902 #define bRxHTSettle_Idle 0x300
903 #define bRxHTSettle_Reserved 0x1c00
904 #define bRxHTRxHPEn 0x8000
905 #define bRxHTAGCFreezeThres 0x30000
906 #define bRxHTAGCTogetherEn 0x40000
907 #define bRxHTAGCMin 0x80000
908 #define bRxHTAGCEn 0x100000
909 #define bRxHTDAGCEn 0x200000
910 #define bRxHTRxHP_BBP 0x1c00000
911 #define bRxHTRxHP_Final 0xe0000000
912 #define bRxPWRatioTH 0x3
913 #define bRxPWRatioEn 0x4
914 #define bRxMFHold 0x3800
915 #define bRxPD_Delay_TH1 0x38
916 #define bRxPD_Delay_TH2 0x1c0
917 #define bRxPD_DC_COUNT_MAX 0x600
918 /* #define bRxMF_Hold 0x3800 */
919 #define bRxPD_Delay_TH 0x8000
920 #define bRxProcess_Delay 0xf0000
921 #define bRxSearchrange_GI2_Early 0x700000
922 #define bRxFrame_Guard_Counter_L 0x3800000
923 #define bRxSGI_Guard_L 0xc000000
924 #define bRxSGI_Search_L 0x30000000
925 #define bRxSGI_TH 0xc0000000
926 #define bDFSCnt0 0xff
927 #define bDFSCnt1 0xff00
928 #define bDFSFlag 0xf0000
929 #define bMFWeightSum 0x300000
930 #define bMinIdxTH 0x7f000000
931 #define bDAFormat 0x40000
932 #define bTxChEmuEnable 0x01000000
933 #define bTRSWIsolation_A 0x7f
934 #define bTRSWIsolation_B 0x7f00
935 #define bTRSWIsolation_C 0x7f0000
936 #define bTRSWIsolation_D 0x7f000000
937 #define bExtLNAGain 0x7c00
939 /* 6. PageE(0xE00) */
940 #define bSTBCEn 0x4 /* Useless */
941 #define bAntennaMapping 0x10
943 #define bCFOAntSumD 0x200
944 #define bPHYCounterReset 0x8000000
945 #define bCFOReportGet 0x4000000
946 #define bOFDMContinueTx 0x10000000
947 #define bOFDMSingleCarrier 0x20000000
948 #define bOFDMSingleTone 0x40000000
949 /* #define bRxPath1 0x01 */
950 /* #define bRxPath2 0x02 */
951 /* #define bRxPath3 0x04 */
952 /* #define bRxPath4 0x08 */
953 /* #define bTxPath1 0x10 */
954 /* #define bTxPath2 0x20 */
955 #define bHTDetect 0x100
956 #define bCFOEn 0x10000
957 #define bCFOValue 0xfff00000
958 #define bSigTone_Re 0x3f
959 #define bSigTone_Im 0x7f00
960 #define bCounter_CCA 0xffff
961 #define bCounter_ParityFail 0xffff0000
962 #define bCounter_RateIllegal 0xffff
963 #define bCounter_CRC8Fail 0xffff0000
964 #define bCounter_MCSNoSupport 0xffff
965 #define bCounter_FastSync 0xffff
966 #define bShortCFO 0xfff
967 #define bShortCFOTLength 12 /* total */
968 #define bShortCFOFLength 11 /* fraction */
969 #define bLongCFO 0x7ff
970 #define bLongCFOTLength 11
971 #define bLongCFOFLength 11
972 #define bTailCFO 0x1fff
973 #define bTailCFOTLength 13
974 #define bTailCFOFLength 12
975 #define bmax_en_pwdB 0xffff
976 #define bCC_power_dB 0xffff0000
977 #define bnoise_pwdB 0xffff
978 #define bPowerMeasTLength 10
979 #define bPowerMeasFLength 3
980 #define bRx_HT_BW 0x1
983 #define bNB_intf_det_on 0x1
984 #define bIntf_win_len_cfg 0x30
985 #define bNB_Intf_TH_cfg 0x1c0
987 #define bTableSel 0x40
989 #define bRxSNR_A 0xff
990 #define bRxSNR_B 0xff00
991 #define bRxSNR_C 0xff0000
992 #define bRxSNR_D 0xff000000
993 #define bSNREVMTLength 8
994 #define bSNREVMFLength 1
996 #define bCSI2nd 0xff00
997 #define bRxEVM1st 0xff0000
998 #define bRxEVM2nd 0xff000000
1000 #define bPWDB 0xff00
1001 #define bSGIEN 0x10000
1003 #define bSFactorQAM1 0xf /* Useless */
1004 #define bSFactorQAM2 0xf0
1005 #define bSFactorQAM3 0xf00
1006 #define bSFactorQAM4 0xf000
1007 #define bSFactorQAM5 0xf0000
1008 #define bSFactorQAM6 0xf0000
1009 #define bSFactorQAM7 0xf00000
1010 #define bSFactorQAM8 0xf000000
1011 #define bSFactorQAM9 0xf0000000
1012 #define bCSIScheme 0x100000
1014 #define bNoiseLvlTopSet 0x3 /* Useless */
1015 #define bChSmooth 0x4
1016 #define bChSmoothCfg1 0x38
1017 #define bChSmoothCfg2 0x1c0
1018 #define bChSmoothCfg3 0xe00
1019 #define bChSmoothCfg4 0x7000
1020 #define bMRCMode 0x800000
1021 #define bTHEVMCfg 0x7000000
1023 #define bLoopFitType 0x1 /* Useless */
1024 #define bUpdCFO 0x40
1025 #define bUpdCFOOffData 0x80
1026 #define bAdvUpdCFO 0x100
1027 #define bAdvTimeCtrl 0x800
1028 #define bUpdClko 0x1000
1030 #define bTrackingMode 0x8000
1031 #define bPhCmpEnable 0x10000
1032 #define bUpdClkoLTF 0x20000
1033 #define bComChCFO 0x40000
1034 #define bCSIEstiMode 0x80000
1035 #define bAdvUpdEqz 0x100000
1036 #define bUChCfg 0x7000000
1037 #define bUpdEqz 0x8000000
1039 /* Rx Pseduo noise */
1040 #define bRxPesudoNoiseOn 0x20000000 /* Useless */
1041 #define bRxPesudoNoise_A 0xff
1042 #define bRxPesudoNoise_B 0xff00
1043 #define bRxPesudoNoise_C 0xff0000
1044 #define bRxPesudoNoise_D 0xff000000
1045 #define bPesudoNoiseState_A 0xffff
1046 #define bPesudoNoiseState_B 0xffff0000
1047 #define bPesudoNoiseState_C 0xffff
1048 #define bPesudoNoiseState_D 0xffff0000
1052 #define bZebra1_HSSIEnable 0x8 /* Useless */
1053 #define bZebra1_TRxControl 0xc00
1054 #define bZebra1_TRxGainSetting 0x07f
1055 #define bZebra1_RxCorner 0xc00
1056 #define bZebra1_TxChargePump 0x38
1057 #define bZebra1_RxChargePump 0x7
1058 #define bZebra1_ChannelNum 0xf80
1059 #define bZebra1_TxLPFBW 0x400
1060 #define bZebra1_RxLPFBW 0x600
1063 #define bRTL8256RegModeCtrl1 0x100 /* Useless */
1064 #define bRTL8256RegModeCtrl0 0x40
1065 #define bRTL8256_TxLPFBW 0x18
1066 #define bRTL8256_RxLPFBW 0x600
1069 #define bRTL8258_TxLPFBW 0xc /* Useless */
1070 #define bRTL8258_RxLPFBW 0xc00
1071 #define bRTL8258_RSSILPFBW 0xc0
1078 /* byte endable for sb_write */
1079 #define bByte0 0x1 /* Useless */
1087 /* for PutRegsetting & GetRegSetting BitMask */
1088 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
1089 #define bMaskByte1 0xff00
1090 #define bMaskByte2 0xff0000
1091 #define bMaskByte3 0xff000000
1092 #define bMaskHWord 0xffff0000
1093 #define bMaskLWord 0x0000ffff
1094 #define bMaskDWord 0xffffffff
1095 #define bMaskH3Bytes 0xffffff00
1096 #define bMask12Bits 0xfff
1097 #define bMaskH4Bits 0xf0000000
1098 #define bMaskOFDM_D 0xffc00000
1099 #define bMaskCCK 0x3f3f3f3f
1102 #define bEnable 0x1 /* Useless */
1103 #define bDisable 0x0
1105 #define LeftAntenna 0x0 /* Useless */
1106 #define RightAntenna 0x1
1108 #define tCheckTxStatus 500 /* 500ms // Useless */
1109 #define tUpdateRxCounter 100 /* 100ms */
1111 #define rateCCK 0 /* Useless */
1115 /* define Register-End */
1116 #define bPMAC_End 0x1ff /* Useless */
1117 #define bFPGAPHY0_End 0x8ff
1118 #define bFPGAPHY1_End 0x9ff
1119 #define bCCKPHY0_End 0xaff
1120 #define bOFDMPHY0_End 0xcff
1121 #define bOFDMPHY1_End 0xdff
1123 /* define max debug item in each debug page
1124 * #define bMaxItem_FPGA_PHY0 0x9
1125 * #define bMaxItem_FPGA_PHY1 0x3
1126 * #define bMaxItem_PHY_11B 0x16
1127 * #define bMaxItem_OFDM_PHY0 0x29
1128 * #define bMaxItem_OFDM_PHY1 0x0 */
1130 #define bPMACControl 0x0 /* Useless */
1131 #define bWMACControl 0x1
1132 #define bWNICControl 0x2
1134 #define PathA 0x0 /* Useless */