drivers/net/wireless/rockchip_wlan/rtl8723cs/hal/phydm/txbf/haltxbf8814a.c

   1 /* ************************************************************
   2  * Description:
   3  *
   4  * This file is for 8814A TXBF mechanism
   5  *
   6  * ************************************************************ */
   7
   8 #include "mp_precomp.h"
   9 #include "../phydm_precomp.h"
  10
  11 #if (BEAMFORMING_SUPPORT == 1)
  12 #if (RTL8814A_SUPPORT == 1)
  13
  14 boolean
  15 phydm_beamforming_set_iqgen_8814A(
  16         void                    *p_dm_void
  17 )
  18 {
  19         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  20         u8 i = 0;
  21         u16 counter = 0;
  22         u32 rf_mode[4];
  23
  24         for (i = ODM_RF_PATH_A ; i < MAX_RF_PATH ; i++)
  25                 odm_set_rf_reg(p_dm_odm, i, RF_WE_LUT, 0x80000, 0x1);   /*RF mode table write enable*/
  26
  27         while (1) {
  28                 counter++;
  29                 for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++)
  30                         odm_set_rf_reg(p_dm_odm, i, RF_RCK_OS, 0xfffff, 0x18000);       /*Select Rx mode*/
  31
  32                 ODM_delay_us(2);
  33
  34                 for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++)
  35                         rf_mode[i] = odm_get_rf_reg(p_dm_odm, i, RF_RCK_OS, 0xfffff);
  36
  37                 if ((rf_mode[0] == 0x180000) && (rf_mode[1] == 0x180000) && (rf_mode[2] == 0x180000) && (rf_mode[3] == 0x180000))
  38                         break;
  39                 else if (counter == 100) {
  40                         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("iqgen setting fail:8814A\n"));
  41                         return false;
  42                 }
  43         }
  44
  45         for (i = ODM_RF_PATH_A ; i < MAX_RF_PATH ; i++) {
  46                 odm_set_rf_reg(p_dm_odm, i, RF_TXPA_G1, 0xfffff, 0xBE77F); /*Set Table data*/
  47                 odm_set_rf_reg(p_dm_odm, i, RF_TXPA_G2, 0xfffff, 0x226BF); /*Enable TXIQGEN in Rx mode*/
  48         }
  49         odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_TXPA_G2, 0xfffff, 0xE26BF); /*Enable TXIQGEN in Rx mode*/
  50
  51         for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++)
  52                 odm_set_rf_reg(p_dm_odm, i, RF_WE_LUT, 0x80000, 0x0);   /*RF mode table write disable*/
  53
  54         return true;
  55
  56 }
  57
  58
  59
  60 void
  61 hal_txbf_8814a_set_ndpa_rate(
  62         void                    *p_dm_void,
  63         u8      BW,
  64         u8      rate
  65 )
  66 {
  67         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
  68
  69         odm_write_1byte(p_dm_odm, REG_NDPA_OPT_CTRL_8814A, BW);
  70         odm_write_1byte(p_dm_odm, REG_NDPA_RATE_8814A, (u8) rate);
  71
  72 }
  73
  74 #define PHYDM_MEMORY_MAP_BUF_READ       0x8000
  75 #define PHYDM_CTRL_INFO_PAGE                    0x660
  76
  77 void
  78 phydm_data_rate_8814a(
  79         struct PHY_DM_STRUCT                    *p_dm_odm,
  80         u8                              mac_id,
  81         u32                             *data,
  82         u8                              data_len
  83 )
  84 {
  85         u8      i = 0;
  86         u16     x_read_data_addr = 0;
  87
  88         odm_write_2byte(p_dm_odm, REG_PKTBUF_DBG_CTRL_8814A, PHYDM_CTRL_INFO_PAGE);
  89         x_read_data_addr = PHYDM_MEMORY_MAP_BUF_READ + mac_id * 32; /*Ctrl Info: 32Bytes for each macid(n)*/
  90
  91         if ((x_read_data_addr < PHYDM_MEMORY_MAP_BUF_READ) || (x_read_data_addr > 0x8FFF)) {
  92                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("x_read_data_addr(0x%x) is not correct!\n", x_read_data_addr));
  93                 return;
  94         }
  95
  96         /* Read data */
  97         for (i = 0; i < data_len; i++)
  98                 *(data + i) = odm_read_2byte(p_dm_odm, x_read_data_addr + i);
  99
 100 }
 101
 102 void
 103 hal_txbf_8814a_get_tx_rate(
 104         void                    *p_dm_void
 105 )
 106 {
 107         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 108         struct _RT_BEAMFORMING_INFO     *p_beam_info = &p_dm_odm->beamforming_info;
 109         struct _RT_BEAMFORMEE_ENTRY     *p_entry;
 110         u32     tx_rpt_data = 0;
 111         u8      data_rate = 0xFF;
 112
 113         p_entry = &(p_beam_info->beamformee_entry[p_beam_info->beamformee_cur_idx]);
 114
 115         phydm_data_rate_8814a(p_dm_odm, (u8)p_entry->mac_id, &tx_rpt_data, 1);
 116         data_rate = (u8)tx_rpt_data;
 117         data_rate &= 0x7f;   /*Bit7 indicates SGI*/
 118
 119         p_dm_odm->tx_bf_data_rate = data_rate;
 120
 121         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] p_dm_odm->tx_bf_data_rate = 0x%x\n", __func__, p_dm_odm->tx_bf_data_rate));
 122 }
 123
 124 void
 125 hal_txbf_8814a_reset_tx_path(
 126         void                    *p_dm_void,
 127         u8                              idx
 128 )
 129 {
 130         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 131 #if DEV_BUS_TYPE == RT_USB_INTERFACE
 132         struct _RT_BEAMFORMING_INFO     *p_beamforming_info = &p_dm_odm->beamforming_info;
 133         struct _RT_BEAMFORMEE_ENTRY     beamformee_entry;
 134         u8      nr_index = 0, tx_ss = 0;
 135
 136         if (idx < BEAMFORMEE_ENTRY_NUM)
 137                 beamformee_entry = p_beamforming_info->beamformee_entry[idx];
 138         else
 139                 return;
 140
 141         if ((p_dm_odm->last_usb_hub) != (*p_dm_odm->hub_usb_mode)) {
 142                 nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(p_dm_odm), beamformee_entry.comp_steering_num_of_bfer);
 143
 144                 if (*p_dm_odm->hub_usb_mode == 2) {
 145                         if (p_dm_odm->rf_type == ODM_4T4R)
 146                                 tx_ss = 0xf;
 147                         else if (p_dm_odm->rf_type == ODM_3T3R)
 148                                 tx_ss = 0xe;
 149                         else
 150                                 tx_ss = 0x6;
 151                 } else if (*p_dm_odm->hub_usb_mode == 1)        /*USB 2.0 always 2Tx*/
 152                         tx_ss = 0x6;
 153                 else
 154                         tx_ss = 0x6;
 155
 156                 if (tx_ss == 0xf) {
 157                         odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93f);
 158                         odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKDWORD, 0x93f93f0);
 159                 } else if (tx_ss == 0xe) {
 160                         odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93e);
 161                         odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e93e0);
 162                 } else if (tx_ss == 0x6) {
 163                         odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x936);
 164                         odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360);
 165                 }
 166
 167                 if (idx == 0) {
 168                         switch (nr_index) {
 169                         case 0:
 170                                 break;
 171
 172                         case 1:                 /*Nsts = 2      BC*/
 173                                 odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366);              /*tx2path, BC*/
 174                                 break;
 175
 176                         case 2:                 /*Nsts = 3      BCD*/
 177                                 odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee);   /*tx3path, BCD*/
 178                                 break;
 179
 180                         default:                        /*nr>3, same as Case 3*/
 181                                 odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff);   /*tx4path, ABCD*/
 182                                 break;
 183                         }
 184                 } else  {
 185                         switch (nr_index) {
 186                         case 0:
 187                                 break;
 188
 189                         case 1:                 /*Nsts = 2      BC*/
 190                                 odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366);              /*tx2path, BC*/
 191                                 break;
 192
 193                         case 2:                 /*Nsts = 3      BCD*/
 194                                 odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee);   /*tx3path, BCD*/
 195                                 break;
 196
 197                         default:                        /*nr>3, same as Case 3*/
 198                                 odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff);   /*tx4path, ABCD*/
 199                                 break;
 200                         }
 201                 }
 202
 203                 p_dm_odm->last_usb_hub = *p_dm_odm->hub_usb_mode;
 204         } else
 205                 return;
 206 #endif
 207 }
 208
 209
 210 u8
 211 hal_txbf_8814a_get_ntx(
 212         void                    *p_dm_void
 213 )
 214 {
 215         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 216         u8              ntx = 0, tx_ss = 3;
 217
 218 #if DEV_BUS_TYPE == RT_USB_INTERFACE
 219         tx_ss = *p_dm_odm->hub_usb_mode;
 220 #endif
 221         if (tx_ss == 3 || tx_ss == 2) {
 222                 if (p_dm_odm->rf_type == ODM_4T4R)
 223                         ntx = 3;
 224                 else if (p_dm_odm->rf_type == ODM_3T3R)
 225                         ntx = 2;
 226                 else
 227                         ntx = 1;
 228         } else if (tx_ss == 1)  /*USB 2.0 always 2Tx*/
 229                 ntx = 1;
 230         else
 231                 ntx = 1;
 232
 233         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ntx = %d\n", __func__, ntx));
 234         return ntx;
 235 }
 236
 237 u8
 238 hal_txbf_8814a_get_nrx(
 239         void                    *p_dm_void
 240 )
 241 {
 242         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 243         u8                      nrx = 0;
 244
 245         if (p_dm_odm->rf_type == ODM_4T4R)
 246                 nrx = 3;
 247         else if (p_dm_odm->rf_type == ODM_3T3R)
 248                 nrx = 2;
 249         else if (p_dm_odm->rf_type == ODM_2T2R)
 250                 nrx = 1;
 251         else if (p_dm_odm->rf_type == ODM_2T3R)
 252                 nrx = 2;
 253         else if (p_dm_odm->rf_type == ODM_2T4R)
 254                 nrx = 3;
 255         else if (p_dm_odm->rf_type == ODM_1T1R)
 256                 nrx = 0;
 257         else if (p_dm_odm->rf_type == ODM_1T2R)
 258                 nrx = 1;
 259         else
 260                 nrx = 0;
 261
 262         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] nrx = %d\n", __func__, nrx));
 263         return nrx;
 264 }
 265
 266 void
 267 hal_txbf_8814a_rf_mode(
 268         void                    *p_dm_void,
 269         struct _RT_BEAMFORMING_INFO     *p_beamforming_info,
 270         u8                                      idx
 271 )
 272 {
 273         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 274         u8                              i, nr_index = 0;
 275         u8                              tx_ss = 3;              /*default use 3 Tx*/
 276         struct _RT_BEAMFORMEE_ENTRY     beamformee_entry;
 277
 278         if (idx < BEAMFORMEE_ENTRY_NUM)
 279                 beamformee_entry = p_beamforming_info->beamformee_entry[idx];
 280         else
 281                 return;
 282
 283         nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(p_dm_odm), beamformee_entry.comp_steering_num_of_bfer);
 284
 285         if (p_dm_odm->rf_type == ODM_1T1R)
 286                 return;
 287
 288         if (p_beamforming_info->beamformee_su_cnt > 0) {
 289 #if DEV_BUS_TYPE == RT_USB_INTERFACE
 290                 p_dm_odm->last_usb_hub = *p_dm_odm->hub_usb_mode;
 291                 tx_ss = *p_dm_odm->hub_usb_mode;
 292 #endif
 293                 if (tx_ss == 3 || tx_ss == 2) {
 294                         if (p_dm_odm->rf_type == ODM_4T4R)
 295                                 tx_ss = 0xf;
 296                         else if (p_dm_odm->rf_type == ODM_3T3R)
 297                                 tx_ss = 0xe;
 298                         else
 299                                 tx_ss = 0x6;
 300                 } else if (tx_ss == 1)  /*USB 2.0 always 2Tx*/
 301                         tx_ss = 0x6;
 302                 else
 303                         tx_ss = 0x6;
 304
 305                 if (tx_ss == 0xf) {
 306                         odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93f);
 307                         odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKDWORD, 0x93f93f0);
 308                 } else if (tx_ss == 0xe) {
 309                         odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93e);
 310                         odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e93e0);
 311                 } else if (tx_ss == 0x6) {
 312                         odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x936);
 313                         odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360);
 314                 }
 315
 316                 /*for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/
 317                 odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT(28) | BIT29, 0x2);                  /*enable BB TxBF ant mapping register*/
 318                 odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT30, 0x1);                    /*if Nsts > Nc don't apply V matrix*/
 319
 320                 if (idx == 0) {
 321                         switch (nr_index) {
 322                         case 0:
 323                                 break;
 324
 325                         case 1:                 /*Nsts = 2      BC*/
 326                                 odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366);              /*tx2path, BC*/
 327                                 break;
 328
 329                         case 2:                 /*Nsts = 3      BCD*/
 330                                 odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee);   /*tx3path, BCD*/
 331                                 break;
 332
 333                         default:                        /*nr>3, same as Case 3*/
 334                                 odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff);   /*tx4path, ABCD*/
 335
 336                                 break;
 337                         }
 338                 } else {
 339                         switch (nr_index) {
 340                         case 0:
 341                                 break;
 342
 343                         case 1:                 /*Nsts = 2      BC*/
 344                                 odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366);              /*tx2path, BC*/
 345                                 break;
 346
 347                         case 2:                 /*Nsts = 3      BCD*/
 348                                 odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee);   /*tx3path, BCD*/
 349                                 break;
 350
 351                         default:                        /*nr>3, same as Case 3*/
 352                                 odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff);   /*tx4path, ABCD*/
 353                                 break;
 354                         }
 355                 }
 356         }
 357
 358         if ((p_beamforming_info->beamformee_su_cnt == 0) && (p_beamforming_info->beamformer_su_cnt == 0)) {
 359                 odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x932);   /*set tx_path selection for 8814a BFer bug refine*/
 360                 odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e9360);
 361         }
 362 }
 363 #if 0
 364 void
 365 hal_txbf_8814a_download_ndpa(
 366         void                    *p_dm_void,
 367         u8                              idx
 368 )
 369 {
 370         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 371         u8                      u1b_tmp = 0, tmp_reg422 = 0;
 372         u8                      bcn_valid_reg = 0, count = 0, dl_bcn_count = 0;
 373         u16                     head_page = 0x7FE;
 374         boolean                 is_send_beacon = false;
 375         u16                     tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*default reseved 1 page for the IC type which is undefined.*/
 376         struct _RT_BEAMFORMING_INFO     *p_beam_info = &p_dm_odm->beamforming_info;
 377         struct _RT_BEAMFORMEE_ENTRY     *p_beam_entry = p_beam_info->beamformee_entry + idx;
 378         struct _ADAPTER         *adapter = p_dm_odm->adapter;
 379
 380 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 381         *p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = true;
 382 #endif
 383         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
 384
 385         phydm_get_hal_def_var_handler_interface(p_dm_odm, HAL_DEF_TX_PAGE_BOUNDARY, (u16 *)&tx_page_bndy);
 386
 387         /*Set REG_CR bit 8. DMA beacon by SW.*/
 388         u1b_tmp = odm_read_1byte(p_dm_odm, REG_CR_8814A + 1);
 389         odm_write_1byte(p_dm_odm,  REG_CR_8814A + 1, (u1b_tmp | BIT(0)));
 390
 391
 392         /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
 393         tmp_reg422 = odm_read_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8814A + 2);
 394         odm_write_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8814A + 2,  tmp_reg422 & (~BIT(6)));
 395
 396         if (tmp_reg422 & BIT(6)) {
 397                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: There is an adapter is sending beacon.\n", __func__));
 398                 is_send_beacon = true;
 399         }
 400
 401         /*0x204[11:0]   Beacon Head for TXDMA*/
 402         odm_write_2byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A, head_page);
 403
 404         do {
 405                 /*Clear beacon valid check bit.*/
 406                 bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A + 1);
 407                 odm_write_1byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A + 1, (bcn_valid_reg | BIT(7)));
 408
 409                 /*download NDPA rsvd page.*/
 410                 if (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)
 411                         beamforming_send_vht_ndpa_packet(p_dm_odm, p_beam_entry->mac_addr, p_beam_entry->AID, p_beam_entry->sound_bw, BEACON_QUEUE);
 412                 else
 413                         beamforming_send_ht_ndpa_packet(p_dm_odm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE);
 414
 415                 /*check rsvd page download OK.*/
 416                 bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A + 1);
 417                 count = 0;
 418                 while (!(bcn_valid_reg & BIT(7)) && count < 20) {
 419                         count++;
 420                         ODM_delay_ms(10);
 421                         bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A + 2);
 422                 }
 423                 dl_bcn_count++;
 424         } while (!(bcn_valid_reg & BIT(7)) && dl_bcn_count < 5);
 425
 426         if (!(bcn_valid_reg & BIT(7)))
 427                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Download RSVD page failed!\n", __func__));
 428
 429         /*0x204[11:0]   Beacon Head for TXDMA*/
 430         odm_write_2byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A, tx_page_bndy);
 431
 432         /*To make sure that if there exists an adapter which would like to send beacon.*/
 433         /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
 434         /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */
 435         /*the beacon cannot be sent by HW.*/
 436         /*2010.06.23. Added by tynli.*/
 437         if (is_send_beacon)
 438                 odm_write_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422);
 439
 440         /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
 441         /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
 442         u1b_tmp = odm_read_1byte(p_dm_odm, REG_CR_8814A + 1);
 443         odm_write_1byte(p_dm_odm, REG_CR_8814A + 1, (u1b_tmp & (~BIT(0))));
 444
 445         p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;
 446
 447 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 448         *p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = false;
 449 #endif
 450 }
 451
 452 void
 453 hal_txbf_8814a_fw_txbf_cmd(
 454         void                    *p_dm_void
 455 )
 456 {
 457         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 458         u8      idx, period = 0;
 459         u8      PageNum0 = 0xFF, PageNum1 = 0xFF;
 460         u8      u1_tx_bf_parm[3] = {0};
 461         struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info;
 462
 463         for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
 464                 if (p_beam_info->beamformee_entry[idx].is_used && p_beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
 465                         if (p_beam_info->beamformee_entry[idx].is_sound) {
 466                                 PageNum0 = 0xFE;
 467                                 PageNum1 = 0x07;
 468                                 period = (u8)(p_beam_info->beamformee_entry[idx].sound_period);
 469                         } else if (PageNum0 == 0xFF) {
 470                                 PageNum0 = 0xFF; /*stop sounding*/
 471                                 PageNum1 = 0x0F;
 472                         }
 473                 }
 474         }
 475
 476         u1_tx_bf_parm[0] = PageNum0;
 477         u1_tx_bf_parm[1] = PageNum1;
 478         u1_tx_bf_parm[2] = period;
 479         odm_fill_h2c_cmd(p_dm_odm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm);
 480
 481         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD,
 482                 ("[%s] PageNum0 = %d, PageNum1 = %d period = %d\n", __func__, PageNum0, PageNum1, period));
 483 }
 484 #endif
 485 void
 486 hal_txbf_8814a_enter(
 487         void                    *p_dm_void,
 488         u8                              bfer_bfee_idx
 489 )
 490 {
 491         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 492         u8                                      i = 0;
 493         u8                                      bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
 494         u8                                      bfee_idx = (bfer_bfee_idx & 0xF);
 495         struct _RT_BEAMFORMING_INFO     *p_beamforming_info = &p_dm_odm->beamforming_info;
 496         struct _RT_BEAMFORMEE_ENTRY     beamformee_entry;
 497         struct _RT_BEAMFORMER_ENTRY     beamformer_entry;
 498         u16                                     sta_id = 0, csi_param = 0;
 499         u8                                      nc_index = 0, nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0;
 500
 501         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] bfer_idx=%d, bfee_idx=%d\n", __func__, bfer_idx, bfee_idx));
 502         odm_set_mac_reg(p_dm_odm, REG_SND_PTCL_CTRL_8814A, MASKBYTE1 | MASKBYTE2, 0x0202);
 503
 504         if ((p_beamforming_info->beamformer_su_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) {
 505                 beamformer_entry = p_beamforming_info->beamformer_entry[bfer_idx];
 506                 /*Sounding protocol control*/
 507                 odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8814A, 0xDB);
 508
 509                 /*MAC address/Partial AID of Beamformer*/
 510                 if (bfer_idx == 0) {
 511                         for (i = 0; i < 6 ; i++)
 512                                 odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER0_INFO_8814A + i), beamformer_entry.mac_addr[i]);
 513                 } else {
 514                         for (i = 0; i < 6 ; i++)
 515                                 odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER1_INFO_8814A + i), beamformer_entry.mac_addr[i]);
 516                 }
 517
 518                 /*CSI report parameters of Beamformer*/
 519                 nc_index = hal_txbf_8814a_get_nrx(p_dm_odm);    /*for 8814A nrx = 3(4 ant), min=0(1 ant)*/
 520                 nr_index = beamformer_entry.num_of_sounding_dim;        /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/
 521
 522                 grouping = 0;
 523
 524                 /*for ac = 1, for n = 3*/
 525                 if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU)
 526                         codebookinfo = 1;
 527                 else if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_HT_EXPLICIT)
 528                         codebookinfo = 3;
 529
 530                 coefficientsize = 3;
 531
 532                 csi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index));
 533
 534                 if (bfer_idx == 0)
 535                         odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8814A, csi_param);
 536                 else
 537                         odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8814A + 2, csi_param);
 538                 /*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/
 539                 odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8814A + 3, 0x40);
 540
 541         }
 542
 543         if ((p_beamforming_info->beamformee_su_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) {
 544                 beamformee_entry = p_beamforming_info->beamformee_entry[bfee_idx];
 545
 546                 hal_txbf_8814a_rf_mode(p_dm_odm, p_beamforming_info, bfee_idx);
 547
 548                 if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss))
 549                         sta_id = beamformee_entry.mac_id;
 550                 else
 551                         sta_id = beamformee_entry.p_aid;
 552
 553                 /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
 554                 if (bfee_idx == 0) {
 555                         odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8814A, sta_id);
 556                         odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8814A + 3, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8814A + 3) | BIT(4) | BIT(6) | BIT(7));
 557                 } else
 558                         odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8814A + 2, sta_id | BIT(14) | BIT(15) | BIT(12));
 559
 560                 /*CSI report parameters of Beamformee*/
 561                 if (bfee_idx == 0) {
 562                         /*Get BIT24 & BIT25*/
 563                         u8      tmp = odm_read_1byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3) & 0x3;
 564
 565                         odm_write_1byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3, tmp | 0x60);
 566                         odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A, sta_id);
 567                 } else
 568                         odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, sta_id | 0xE200); /*Set BIT25*/
 569
 570                 phydm_beamforming_notify(p_dm_odm);
 571         }
 572
 573 }
 574
 575
 576 void
 577 hal_txbf_8814a_leave(
 578         void                    *p_dm_void,
 579         u8                              idx
 580 )
 581 {
 582         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 583         struct _RT_BEAMFORMING_INFO     *p_beamforming_info = &p_dm_odm->beamforming_info;
 584         struct _RT_BEAMFORMER_ENTRY     beamformer_entry;
 585         struct _RT_BEAMFORMEE_ENTRY     beamformee_entry;
 586
 587         if (idx < BEAMFORMER_ENTRY_NUM) {
 588                 beamformer_entry = p_beamforming_info->beamformer_entry[idx];
 589                 beamformee_entry = p_beamforming_info->beamformee_entry[idx];
 590         } else
 591                 return;
 592
 593         /*Clear P_AID of Beamformee*/
 594         /*Clear MAC address of Beamformer*/
 595         /*Clear Associated Bfmee Sel*/
 596
 597         if (beamformer_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) {
 598                 odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8814A, 0xD8);
 599                 if (idx == 0) {
 600                         odm_write_4byte(p_dm_odm, REG_ASSOCIATED_BFMER0_INFO_8814A, 0);
 601                         odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMER0_INFO_8814A + 4, 0);
 602                         odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8814A, 0);
 603                 } else {
 604                         odm_write_4byte(p_dm_odm, REG_ASSOCIATED_BFMER1_INFO_8814A, 0);
 605                         odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMER1_INFO_8814A + 4, 0);
 606                         odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8814A + 2, 0);
 607                 }
 608         }
 609
 610         if (beamformee_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) {
 611                 hal_txbf_8814a_rf_mode(p_dm_odm, p_beamforming_info, idx);
 612                 if (idx == 0) {
 613                         odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8814A, 0x0);
 614                         odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8814A + 3, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8814A + 3) | BIT(4) | BIT(6) | BIT(7));
 615                         odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A, 0);
 616                 } else {
 617                         odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8814A + 2, 0x0 | BIT(14) | BIT(15) | BIT(12));
 618
 619                         odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, odm_read_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2) & 0x60);
 620                 }
 621         }
 622 }
 623
 624 void
 625 hal_txbf_8814a_status(
 626         void                    *p_dm_void,
 627         u8                              idx
 628 )
 629 {
 630         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 631         u16                                     beam_ctrl_val, tmp_val;
 632         u32                                     beam_ctrl_reg;
 633         struct _RT_BEAMFORMING_INFO     *p_beamforming_info = &p_dm_odm->beamforming_info;
 634         struct _RT_BEAMFORMEE_ENTRY     beamform_entry;
 635
 636         if (idx < BEAMFORMEE_ENTRY_NUM)
 637                 beamform_entry = p_beamforming_info->beamformee_entry[idx];
 638         else
 639                 return;
 640
 641         if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss))
 642                 beam_ctrl_val = beamform_entry.mac_id;
 643         else
 644                 beam_ctrl_val = beamform_entry.p_aid;
 645
 646         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, beamform_entry.beamform_entry_state = %d", __func__, beamform_entry.beamform_entry_state));
 647
 648         if (idx == 0)
 649                 beam_ctrl_reg = REG_TXBF_CTRL_8814A;
 650         else {
 651                 beam_ctrl_reg = REG_TXBF_CTRL_8814A + 2;
 652                 beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15);
 653         }
 654
 655         if ((beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (p_beamforming_info->apply_v_matrix == true)) {
 656                 if (beamform_entry.sound_bw == CHANNEL_WIDTH_20)
 657                         beam_ctrl_val |= BIT(9);
 658                 else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40)
 659                         beam_ctrl_val |= (BIT(9) | BIT(10));
 660                 else if (beamform_entry.sound_bw == CHANNEL_WIDTH_80)
 661                         beam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11));
 662         } else {
 663                 ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, Don't apply Vmatrix",  __func__));
 664                 beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11));
 665         }
 666
 667         odm_write_2byte(p_dm_odm, beam_ctrl_reg, beam_ctrl_val);
 668         /*disable NDP packet use beamforming */
 669         tmp_val = odm_read_2byte(p_dm_odm, REG_TXBF_CTRL_8814A);
 670         odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8814A, tmp_val | BIT(15));
 671
 672 }
 673
 674
 675
 676
 677
 678 void
 679 hal_txbf_8814a_fw_txbf(
 680         void                    *p_dm_void,
 681         u8                              idx
 682 )
 683 {
 684 #if 0
 685         struct PHY_DM_STRUCT    *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
 686         struct _RT_BEAMFORMING_INFO     *p_beam_info = &p_dm_odm->beamforming_info;
 687         struct _RT_BEAMFORMEE_ENTRY     *p_beam_entry = p_beam_info->beamformee_entry + idx;
 688
 689         ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
 690
 691         if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING)
 692                 hal_txbf_8814a_download_ndpa(p_dm_odm, idx);
 693
 694         hal_txbf_8814a_fw_txbf_cmd(p_dm_odm);
 695 #endif
 696 }
 697
 698 #endif  /* (RTL8814A_SUPPORT == 1)*/
 699
 700 #endif