1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
21 /*Image2HeaderVersion: 2.18*/
22 #include "mp_precomp.h"
23 #include "../phydm_precomp.h"
25 #if (RTL8703B_SUPPORT == 1)
28 struct PHY_DM_STRUCT *p_dm_odm,
35 u8 _board_type = ((p_dm_odm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/
36 ((p_dm_odm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/
37 ((p_dm_odm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/
38 ((p_dm_odm->board_type & BIT(6)) >> 6) << 3 | /* _APA */
39 ((p_dm_odm->board_type & BIT(2)) >> 2) << 4; /* _BT*/
41 u32 cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4;
42 u32 driver1 = p_dm_odm->cut_version << 24 |
43 (p_dm_odm->support_interface & 0xF0) << 16 |
44 p_dm_odm->support_platform << 16 |
45 p_dm_odm->package_type << 12 |
46 (p_dm_odm->support_interface & 0x0F) << 8 |
49 u32 driver2 = (p_dm_odm->type_glna & 0xFF) << 0 |
50 (p_dm_odm->type_gpa & 0xFF) << 8 |
51 (p_dm_odm->type_alna & 0xFF) << 16 |
52 (p_dm_odm->type_apa & 0xFF) << 24;
56 u32 driver4 = (p_dm_odm->type_glna & 0xFF00) >> 8 |
57 (p_dm_odm->type_gpa & 0xFF00) |
58 (p_dm_odm->type_alna & 0xFF00) << 8 |
59 (p_dm_odm->type_apa & 0xFF00) << 16;
61 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
62 ("===> check_positive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4));
63 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
64 ("===> check_positive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4));
66 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
67 (" (Platform, Interface) = (0x%X, 0x%X)\n", p_dm_odm->support_platform, p_dm_odm->support_interface));
68 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
69 (" (Board, Package) = (0x%X, 0x%X)\n", p_dm_odm->board_type, p_dm_odm->package_type));
72 /*============== value Defined Check ===============*/
73 /*QFN type [15:12] and cut version [27:24] need to do value check*/
75 if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
77 if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
80 /*=============== Bit Defined Check ================*/
81 /* We don't care [31:28] */
84 driver1 &= 0x00FF0FFF;
86 if ((cond1 & driver1) == cond1) {
89 if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/
92 if ((cond1 & BIT(0)) != 0) /*GLNA*/
93 bit_mask |= 0x000000FF;
94 if ((cond1 & BIT(1)) != 0) /*GPA*/
95 bit_mask |= 0x0000FF00;
96 if ((cond1 & BIT(2)) != 0) /*ALNA*/
97 bit_mask |= 0x00FF0000;
98 if ((cond1 & BIT(3)) != 0) /*APA*/
99 bit_mask |= 0xFF000000;
101 if (((cond2 & bit_mask) == (driver2 & bit_mask)) && ((cond4 & bit_mask) == (driver4 & bit_mask))) /* board_type of each RF path is matched*/
110 struct PHY_DM_STRUCT *p_dm_odm,
111 const u32 condition1,
118 /******************************************************************************
120 ******************************************************************************/
122 u32 array_mp_8703b_agc_tab[] = {
449 odm_read_and_config_mp_8703b_agc_tab(
450 struct PHY_DM_STRUCT *p_dm_odm
455 boolean is_matched = true, is_skipped = false;
456 u32 array_len = sizeof(array_mp_8703b_agc_tab) / sizeof(u32);
457 u32 *array = array_mp_8703b_agc_tab;
459 u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
461 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8703b_agc_tab\n"));
463 while ((i + 1) < array_len) {
467 if (v1 & (BIT(31) | BIT30)) {/*positive & negative condition*/
468 if (v1 & BIT(31)) {/* positive condition*/
469 c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
470 if (c_cond == COND_ENDIF) {/*end*/
473 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n"));
474 } else if (c_cond == COND_ELSE) { /*else*/
475 is_matched = is_skipped ? false : true;
476 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n"));
477 } else {/*if , else if*/
480 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n"));
482 } else if (v1 & BIT(30)) { /*negative condition*/
483 if (is_skipped == false) {
484 if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) {
496 odm_config_bb_agc_8703b(p_dm_odm, v1, MASKDWORD, v2);
503 odm_get_version_mp_8703b_agc_tab(void)
508 /******************************************************************************
510 ******************************************************************************/
512 u32 array_mp_8703b_phy_reg[] = {
719 odm_read_and_config_mp_8703b_phy_reg(
720 struct PHY_DM_STRUCT *p_dm_odm
725 boolean is_matched = true, is_skipped = false;
726 u32 array_len = sizeof(array_mp_8703b_phy_reg) / sizeof(u32);
727 u32 *array = array_mp_8703b_phy_reg;
729 u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
731 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8703b_phy_reg\n"));
733 while ((i + 1) < array_len) {
737 if (v1 & (BIT(31) | BIT30)) {/*positive & negative condition*/
738 if (v1 & BIT(31)) {/* positive condition*/
739 c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
740 if (c_cond == COND_ENDIF) {/*end*/
743 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n"));
744 } else if (c_cond == COND_ELSE) { /*else*/
745 is_matched = is_skipped ? false : true;
746 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n"));
747 } else {/*if , else if*/
750 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n"));
752 } else if (v1 & BIT(30)) { /*negative condition*/
753 if (is_skipped == false) {
754 if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) {
766 odm_config_bb_phy_8703b(p_dm_odm, v1, MASKDWORD, v2);
773 odm_get_version_mp_8703b_phy_reg(void)
778 /******************************************************************************
780 ******************************************************************************/
782 u32 array_mp_8703b_phy_reg_pg[] = {
783 0, 0, 0, 0x00000e08, 0x0000ff00, 0x00003200,
784 0, 0, 0, 0x0000086c, 0xffffff00, 0x32323200,
785 0, 0, 0, 0x00000e00, 0xffffffff, 0x34363636,
786 0, 0, 0, 0x00000e04, 0xffffffff, 0x28303234,
787 0, 0, 0, 0x00000e10, 0xffffffff, 0x30343434,
788 0, 0, 0, 0x00000e14, 0xffffffff, 0x26262830
792 odm_read_and_config_mp_8703b_phy_reg_pg(
793 struct PHY_DM_STRUCT *p_dm_odm
797 u32 array_len = sizeof(array_mp_8703b_phy_reg_pg) / sizeof(u32);
798 u32 *array = array_mp_8703b_phy_reg_pg;
800 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
801 struct _ADAPTER *adapter = p_dm_odm->adapter;
802 HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
804 PlatformZeroMemory(p_hal_data->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT * MAX_BYTES_LINE_HWCONFIG_TXT);
805 p_hal_data->nLinesReadPwrByRate = array_len / 6;
808 ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8703b_phy_reg_pg\n"));
810 p_dm_odm->phy_reg_pg_version = 1;
811 p_dm_odm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE;
813 for (i = 0; i < array_len; i += 6) {
815 u32 v2 = array[i + 1];
816 u32 v3 = array[i + 2];
817 u32 v4 = array[i + 3];
818 u32 v5 = array[i + 4];
819 u32 v6 = array[i + 5];
821 odm_config_bb_phy_reg_pg_8703b(p_dm_odm, v1, v2, v3, v4, v5, v6);
823 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
824 rsprintf((char *)p_hal_data->BufOfLinesPwrByRate[i / 6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,",
825 (v1 == 0 ? "2.4G" : " 5G"), (v2 == 0 ? "A" : "B"), (v3 == 0 ? "1Tx" : "2Tx"), v4, v5, v6);
832 #endif /* end of HWIMG_SUPPORT*/