drivers/net/wireless/rockchip_wlan/rtl8723bu/hal/hal_com.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #define _HAL_COM_C_
  21
  22 #include <drv_types.h>
  23 #include "hal_com_h2c.h"
  24
  25 #include "../hal/OUTSRC/odm_precomp.h"
  26
  27 u8 rtw_hal_data_init(_adapter *padapter)
  28 {
  29         if(is_primary_adapter(padapter))        //if(padapter->isprimary)
  30         {
  31                 padapter->hal_data_sz = sizeof(HAL_DATA_TYPE);
  32                 padapter->HalData = rtw_zvmalloc(padapter->hal_data_sz);
  33                 if(padapter->HalData == NULL){
  34                         DBG_8192C("cant not alloc memory for HAL DATA \n");
  35                         return _FAIL;
  36                 }
  37         }
  38         return _SUCCESS;
  39 }
  40
  41 void rtw_hal_data_deinit(_adapter *padapter)
  42 {
  43         if(is_primary_adapter(padapter))        //if(padapter->isprimary)
  44         {
  45                 if (padapter->HalData)
  46                 {
  47                         #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
  48                         phy_free_filebuf(padapter);
  49                         #endif
  50                         rtw_vmfree(padapter->HalData, padapter->hal_data_sz);
  51                         padapter->HalData = NULL;
  52                         padapter->hal_data_sz = 0;
  53                 }
  54         }
  55 }
  56
  57
  58 void dump_chip_info(HAL_VERSION ChipVersion)
  59 {
  60         int cnt = 0;
  61         u8 buf[128];
  62
  63         if(IS_81XXC(ChipVersion)){
  64                 cnt += sprintf((buf+cnt), "Chip Version Info: %s_", IS_92C_SERIAL(ChipVersion)?"CHIP_8192C":"CHIP_8188C");
  65         }
  66         else if(IS_92D(ChipVersion)){
  67                 cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8192D_");
  68         }
  69         else if(IS_8723_SERIES(ChipVersion)){
  70                 cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8723A_");
  71         }
  72         else if(IS_8188E(ChipVersion)){
  73                 cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8188E_");
  74         }
  75         else if(IS_8812_SERIES(ChipVersion)){
  76                 cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8812_");
  77         }
  78     else if(IS_8192E(ChipVersion)){
  79                 cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8192E_");
  80         }
  81         else if(IS_8821_SERIES(ChipVersion)){
  82                 cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8821_");
  83         }
  84         else if(IS_8723B_SERIES(ChipVersion)){
  85                 cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8723B_");
  86         }
  87
  88         cnt += sprintf((buf+cnt), "%s_", IS_NORMAL_CHIP(ChipVersion)?"Normal_Chip":"Test_Chip");
  89         if(IS_CHIP_VENDOR_TSMC(ChipVersion))
  90                 cnt += sprintf((buf+cnt), "%s_","TSMC");
  91         else if(IS_CHIP_VENDOR_UMC(ChipVersion))
  92                 cnt += sprintf((buf+cnt), "%s_","UMC");
  93         else if(IS_CHIP_VENDOR_SMIC(ChipVersion))
  94                 cnt += sprintf((buf+cnt), "%s_","SMIC");
  95
  96         if(IS_A_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "A_CUT_");
  97         else if(IS_B_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "B_CUT_");
  98         else if(IS_C_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "C_CUT_");
  99         else if(IS_D_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "D_CUT_");
 100         else if(IS_E_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "E_CUT_");
 101         else if(IS_I_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "I_CUT_");
 102         else if(IS_J_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "J_CUT_");
 103         else if(IS_K_CUT(ChipVersion)) cnt += sprintf((buf+cnt), "K_CUT_");
 104         else cnt += sprintf((buf+cnt), "UNKNOWN_CUT(%d)_", ChipVersion.CUTVersion);
 105
 106         if(IS_1T1R(ChipVersion)) cnt += sprintf((buf+cnt), "1T1R_");
 107         else if(IS_1T2R(ChipVersion)) cnt += sprintf((buf+cnt), "1T2R_");
 108         else if(IS_2T2R(ChipVersion)) cnt += sprintf((buf+cnt), "2T2R_");
 109         else cnt += sprintf((buf+cnt), "UNKNOWN_RFTYPE(%d)_", ChipVersion.RFType);
 110
 111         cnt += sprintf((buf+cnt), "RomVer(%d)\n", ChipVersion.ROMVer);
 112
 113         DBG_871X("%s", buf);
 114 }
 115
 116
 117 #define EEPROM_CHANNEL_PLAN_BY_HW_MASK  0x80
 118
 119 /*
 120  * Description:
 121  *      Use hardware(efuse), driver parameter(registry) and default channel plan
 122  *      to decide which one should be used.
 123  *
 124  * Parameters:
 125  *      padapter                        pointer of adapter
 126  *      hw_channel_plan         channel plan from HW (efuse/eeprom)
 127  *                                              BIT[7] software configure mode; 0:Enable, 1:disable
 128  *                                              BIT[6:0] Channel Plan
 129  *      sw_channel_plan         channel plan from SW (registry/module param)
 130  *      def_channel_plan        channel plan used when HW/SW both invalid
 131  *      AutoLoadFail            efuse autoload fail or not
 132  *
 133  * Return:
 134  *      Final channel plan decision
 135  *
 136  */
 137 u8
 138 hal_com_config_channel_plan(
 139         IN      PADAPTER        padapter,
 140         IN      u8                      hw_channel_plan,
 141         IN      u8                      sw_channel_plan,
 142         IN      u8                      def_channel_plan,
 143         IN      BOOLEAN         AutoLoadFail
 144         )
 145 {
 146         PHAL_DATA_TYPE  pHalData;
 147         u8 hwConfig;
 148         u8 chnlPlan;
 149
 150
 151         pHalData = GET_HAL_DATA(padapter);
 152         pHalData->bDisableSWChannelPlan = _FALSE;
 153         chnlPlan = def_channel_plan;
 154
 155         if (0xFF == hw_channel_plan)
 156                 AutoLoadFail = _TRUE;
 157
 158         if (_FALSE == AutoLoadFail)
 159         {
 160                 u8 hw_chnlPlan;
 161
 162                 hw_chnlPlan = hw_channel_plan & (~EEPROM_CHANNEL_PLAN_BY_HW_MASK);
 163                 if (rtw_is_channel_plan_valid(hw_chnlPlan))
 164                 {
 165 #ifndef CONFIG_SW_CHANNEL_PLAN
 166                         if (hw_channel_plan & EEPROM_CHANNEL_PLAN_BY_HW_MASK)
 167                                 pHalData->bDisableSWChannelPlan = _TRUE;
 168 #endif // !CONFIG_SW_CHANNEL_PLAN
 169
 170                         chnlPlan = hw_chnlPlan;
 171                 }
 172         }
 173
 174         if ((_FALSE == pHalData->bDisableSWChannelPlan)
 175                 && rtw_is_channel_plan_valid(sw_channel_plan))
 176         {
 177                 chnlPlan = sw_channel_plan;
 178         }
 179
 180         return chnlPlan;
 181 }
 182
 183 BOOLEAN
 184 HAL_IsLegalChannel(
 185         IN      PADAPTER        Adapter,
 186         IN      u32                     Channel
 187         )
 188 {
 189         BOOLEAN bLegalChannel = _TRUE;
 190
 191         if (Channel > 14) {
 192                 if(IsSupported5G(Adapter->registrypriv.wireless_mode) == _FALSE) {
 193                         bLegalChannel = _FALSE;
 194                         DBG_871X("Channel > 14 but wireless_mode do not support 5G\n");
 195                 }
 196         } else if ((Channel <= 14) && (Channel >=1)){
 197                 if(IsSupported24G(Adapter->registrypriv.wireless_mode) == _FALSE) {
 198                         bLegalChannel = _FALSE;
 199                         DBG_871X("(Channel <= 14) && (Channel >=1) but wireless_mode do not support 2.4G\n");
 200                 }
 201         } else {
 202                 bLegalChannel = _FALSE;
 203                 DBG_871X("Channel is Invalid !!!\n");
 204         }
 205
 206         return bLegalChannel;
 207 }
 208
 209 u8      MRateToHwRate(u8 rate)
 210 {
 211         u8      ret = DESC_RATE1M;
 212
 213         switch(rate)
 214         {
 215                 case MGN_1M:                ret = DESC_RATE1M;  break;
 216                 case MGN_2M:                ret = DESC_RATE2M;  break;
 217                 case MGN_5_5M:              ret = DESC_RATE5_5M;        break;
 218                 case MGN_11M:               ret = DESC_RATE11M; break;
 219                 case MGN_6M:                ret = DESC_RATE6M;  break;
 220                 case MGN_9M:                ret = DESC_RATE9M;  break;
 221                 case MGN_12M:               ret = DESC_RATE12M; break;
 222                 case MGN_18M:               ret = DESC_RATE18M; break;
 223                 case MGN_24M:               ret = DESC_RATE24M; break;
 224                 case MGN_36M:               ret = DESC_RATE36M; break;
 225                 case MGN_48M:               ret = DESC_RATE48M; break;
 226                 case MGN_54M:               ret = DESC_RATE54M; break;
 227
 228                 case MGN_MCS0:              ret = DESC_RATEMCS0;        break;
 229                 case MGN_MCS1:              ret = DESC_RATEMCS1;        break;
 230                 case MGN_MCS2:              ret = DESC_RATEMCS2;        break;
 231                 case MGN_MCS3:              ret = DESC_RATEMCS3;        break;
 232                 case MGN_MCS4:              ret = DESC_RATEMCS4;        break;
 233                 case MGN_MCS5:              ret = DESC_RATEMCS5;        break;
 234                 case MGN_MCS6:              ret = DESC_RATEMCS6;        break;
 235                 case MGN_MCS7:              ret = DESC_RATEMCS7;        break;
 236                 case MGN_MCS8:              ret = DESC_RATEMCS8;        break;
 237                 case MGN_MCS9:              ret = DESC_RATEMCS9;        break;
 238                 case MGN_MCS10:         ret = DESC_RATEMCS10;   break;
 239                 case MGN_MCS11:         ret = DESC_RATEMCS11;   break;
 240                 case MGN_MCS12:         ret = DESC_RATEMCS12;   break;
 241                 case MGN_MCS13:         ret = DESC_RATEMCS13;   break;
 242                 case MGN_MCS14:         ret = DESC_RATEMCS14;   break;
 243                 case MGN_MCS15:         ret = DESC_RATEMCS15;   break;
 244                 case MGN_MCS16:             ret = DESC_RATEMCS16;       break;
 245                 case MGN_MCS17:             ret = DESC_RATEMCS17;       break;
 246                 case MGN_MCS18:             ret = DESC_RATEMCS18;       break;
 247                 case MGN_MCS19:             ret = DESC_RATEMCS19;       break;
 248                 case MGN_MCS20:         ret = DESC_RATEMCS20;   break;
 249                 case MGN_MCS21:         ret = DESC_RATEMCS21;   break;
 250                 case MGN_MCS22:         ret = DESC_RATEMCS22;   break;
 251                 case MGN_MCS23:         ret = DESC_RATEMCS23;   break;
 252                 case MGN_MCS24:         ret = DESC_RATEMCS24;   break;
 253                 case MGN_MCS25:         ret = DESC_RATEMCS25;   break;
 254                 case MGN_MCS26:             ret = DESC_RATEMCS26;       break;
 255                 case MGN_MCS27:             ret = DESC_RATEMCS27;       break;
 256                 case MGN_MCS28:             ret = DESC_RATEMCS28;       break;
 257                 case MGN_MCS29:             ret = DESC_RATEMCS29;       break;
 258                 case MGN_MCS30:         ret = DESC_RATEMCS30;   break;
 259                 case MGN_MCS31:         ret = DESC_RATEMCS31;   break;
 260
 261                 case MGN_VHT1SS_MCS0:   ret = DESC_RATEVHTSS1MCS0;      break;
 262                 case MGN_VHT1SS_MCS1:   ret = DESC_RATEVHTSS1MCS1;      break;
 263                 case MGN_VHT1SS_MCS2:   ret = DESC_RATEVHTSS1MCS2;      break;
 264                 case MGN_VHT1SS_MCS3:   ret = DESC_RATEVHTSS1MCS3;      break;
 265                 case MGN_VHT1SS_MCS4:   ret = DESC_RATEVHTSS1MCS4;      break;
 266                 case MGN_VHT1SS_MCS5:   ret = DESC_RATEVHTSS1MCS5;      break;
 267                 case MGN_VHT1SS_MCS6:   ret = DESC_RATEVHTSS1MCS6;      break;
 268                 case MGN_VHT1SS_MCS7:   ret = DESC_RATEVHTSS1MCS7;      break;
 269                 case MGN_VHT1SS_MCS8:   ret = DESC_RATEVHTSS1MCS8;      break;
 270                 case MGN_VHT1SS_MCS9:   ret = DESC_RATEVHTSS1MCS9;      break;
 271                 case MGN_VHT2SS_MCS0:   ret = DESC_RATEVHTSS2MCS0;      break;
 272                 case MGN_VHT2SS_MCS1:   ret = DESC_RATEVHTSS2MCS1;      break;
 273                 case MGN_VHT2SS_MCS2:   ret = DESC_RATEVHTSS2MCS2;      break;
 274                 case MGN_VHT2SS_MCS3:   ret = DESC_RATEVHTSS2MCS3;      break;
 275                 case MGN_VHT2SS_MCS4:   ret = DESC_RATEVHTSS2MCS4;      break;
 276                 case MGN_VHT2SS_MCS5:   ret = DESC_RATEVHTSS2MCS5;      break;
 277                 case MGN_VHT2SS_MCS6:   ret = DESC_RATEVHTSS2MCS6;      break;
 278                 case MGN_VHT2SS_MCS7:   ret = DESC_RATEVHTSS2MCS7;      break;
 279                 case MGN_VHT2SS_MCS8:   ret = DESC_RATEVHTSS2MCS8;      break;
 280                 case MGN_VHT2SS_MCS9:   ret = DESC_RATEVHTSS2MCS9;      break;
 281                 case MGN_VHT3SS_MCS0:   ret = DESC_RATEVHTSS3MCS0;      break;
 282                 case MGN_VHT3SS_MCS1:   ret = DESC_RATEVHTSS3MCS1;      break;
 283                 case MGN_VHT3SS_MCS2:   ret = DESC_RATEVHTSS3MCS2;      break;
 284                 case MGN_VHT3SS_MCS3:   ret = DESC_RATEVHTSS3MCS3;      break;
 285                 case MGN_VHT3SS_MCS4:   ret = DESC_RATEVHTSS3MCS4;      break;
 286                 case MGN_VHT3SS_MCS5:   ret = DESC_RATEVHTSS3MCS5;      break;
 287                 case MGN_VHT3SS_MCS6:   ret = DESC_RATEVHTSS3MCS6;      break;
 288                 case MGN_VHT3SS_MCS7:   ret = DESC_RATEVHTSS3MCS7;      break;
 289                 case MGN_VHT3SS_MCS8:   ret = DESC_RATEVHTSS3MCS8;      break;
 290                 case MGN_VHT3SS_MCS9:   ret = DESC_RATEVHTSS3MCS9;      break;
 291                 case MGN_VHT4SS_MCS0:   ret = DESC_RATEVHTSS4MCS0;      break;
 292                 case MGN_VHT4SS_MCS1:   ret = DESC_RATEVHTSS4MCS1;      break;
 293                 case MGN_VHT4SS_MCS2:   ret = DESC_RATEVHTSS4MCS2;      break;
 294                 case MGN_VHT4SS_MCS3:   ret = DESC_RATEVHTSS4MCS3;      break;
 295                 case MGN_VHT4SS_MCS4:   ret = DESC_RATEVHTSS4MCS4;      break;
 296                 case MGN_VHT4SS_MCS5:   ret = DESC_RATEVHTSS4MCS5;      break;
 297                 case MGN_VHT4SS_MCS6:   ret = DESC_RATEVHTSS4MCS6;      break;
 298                 case MGN_VHT4SS_MCS7:   ret = DESC_RATEVHTSS4MCS7;      break;
 299                 case MGN_VHT4SS_MCS8:   ret = DESC_RATEVHTSS4MCS8;      break;
 300                 case MGN_VHT4SS_MCS9:   ret = DESC_RATEVHTSS4MCS9;      break;
 301                 default:                break;
 302         }
 303
 304         return ret;
 305 }
 306
 307 u8      HwRateToMRate(u8 rate)
 308 {
 309         u8      ret_rate = MGN_1M;
 310
 311         switch(rate)
 312         {
 313
 314                 case DESC_RATE1M:                   ret_rate = MGN_1M;          break;
 315                 case DESC_RATE2M:                   ret_rate = MGN_2M;          break;
 316                 case DESC_RATE5_5M:             ret_rate = MGN_5_5M;    break;
 317                 case DESC_RATE11M:                  ret_rate = MGN_11M;         break;
 318                 case DESC_RATE6M:                   ret_rate = MGN_6M;          break;
 319                 case DESC_RATE9M:                   ret_rate = MGN_9M;          break;
 320                 case DESC_RATE12M:                  ret_rate = MGN_12M;         break;
 321                 case DESC_RATE18M:                  ret_rate = MGN_18M;         break;
 322                 case DESC_RATE24M:                  ret_rate = MGN_24M;         break;
 323                 case DESC_RATE36M:                  ret_rate = MGN_36M;         break;
 324                 case DESC_RATE48M:                  ret_rate = MGN_48M;         break;
 325                 case DESC_RATE54M:                  ret_rate = MGN_54M;         break;
 326                 case DESC_RATEMCS0:             ret_rate = MGN_MCS0;    break;
 327                 case DESC_RATEMCS1:             ret_rate = MGN_MCS1;    break;
 328                 case DESC_RATEMCS2:             ret_rate = MGN_MCS2;    break;
 329                 case DESC_RATEMCS3:             ret_rate = MGN_MCS3;    break;
 330                 case DESC_RATEMCS4:             ret_rate = MGN_MCS4;    break;
 331                 case DESC_RATEMCS5:             ret_rate = MGN_MCS5;    break;
 332                 case DESC_RATEMCS6:             ret_rate = MGN_MCS6;    break;
 333                 case DESC_RATEMCS7:             ret_rate = MGN_MCS7;    break;
 334                 case DESC_RATEMCS8:             ret_rate = MGN_MCS8;    break;
 335                 case DESC_RATEMCS9:             ret_rate = MGN_MCS9;    break;
 336                 case DESC_RATEMCS10:        ret_rate = MGN_MCS10;       break;
 337                 case DESC_RATEMCS11:        ret_rate = MGN_MCS11;       break;
 338                 case DESC_RATEMCS12:        ret_rate = MGN_MCS12;       break;
 339                 case DESC_RATEMCS13:        ret_rate = MGN_MCS13;       break;
 340                 case DESC_RATEMCS14:        ret_rate = MGN_MCS14;       break;
 341                 case DESC_RATEMCS15:        ret_rate = MGN_MCS15;       break;
 342                 case DESC_RATEMCS16:        ret_rate = MGN_MCS16;       break;
 343                 case DESC_RATEMCS17:        ret_rate = MGN_MCS17;       break;
 344                 case DESC_RATEMCS18:        ret_rate = MGN_MCS18;       break;
 345                 case DESC_RATEMCS19:        ret_rate = MGN_MCS19;       break;
 346                 case DESC_RATEMCS20:        ret_rate = MGN_MCS20;       break;
 347                 case DESC_RATEMCS21:        ret_rate = MGN_MCS21;       break;
 348                 case DESC_RATEMCS22:        ret_rate = MGN_MCS22;       break;
 349                 case DESC_RATEMCS23:        ret_rate = MGN_MCS23;       break;
 350                 case DESC_RATEMCS24:        ret_rate = MGN_MCS24;       break;
 351                 case DESC_RATEMCS25:        ret_rate = MGN_MCS25;       break;
 352                 case DESC_RATEMCS26:        ret_rate = MGN_MCS26;       break;
 353                 case DESC_RATEMCS27:        ret_rate = MGN_MCS27;       break;
 354                 case DESC_RATEMCS28:        ret_rate = MGN_MCS28;       break;
 355                 case DESC_RATEMCS29:        ret_rate = MGN_MCS29;       break;
 356                 case DESC_RATEMCS30:        ret_rate = MGN_MCS30;       break;
 357                 case DESC_RATEMCS31:        ret_rate = MGN_MCS31;       break;
 358                 case DESC_RATEVHTSS1MCS0:       ret_rate = MGN_VHT1SS_MCS0;             break;
 359                 case DESC_RATEVHTSS1MCS1:       ret_rate = MGN_VHT1SS_MCS1;             break;
 360                 case DESC_RATEVHTSS1MCS2:       ret_rate = MGN_VHT1SS_MCS2;             break;
 361                 case DESC_RATEVHTSS1MCS3:       ret_rate = MGN_VHT1SS_MCS3;             break;
 362                 case DESC_RATEVHTSS1MCS4:       ret_rate = MGN_VHT1SS_MCS4;             break;
 363                 case DESC_RATEVHTSS1MCS5:       ret_rate = MGN_VHT1SS_MCS5;             break;
 364                 case DESC_RATEVHTSS1MCS6:       ret_rate = MGN_VHT1SS_MCS6;             break;
 365                 case DESC_RATEVHTSS1MCS7:       ret_rate = MGN_VHT1SS_MCS7;             break;
 366                 case DESC_RATEVHTSS1MCS8:       ret_rate = MGN_VHT1SS_MCS8;             break;
 367                 case DESC_RATEVHTSS1MCS9:       ret_rate = MGN_VHT1SS_MCS9;             break;
 368                 case DESC_RATEVHTSS2MCS0:       ret_rate = MGN_VHT2SS_MCS0;             break;
 369                 case DESC_RATEVHTSS2MCS1:       ret_rate = MGN_VHT2SS_MCS1;             break;
 370                 case DESC_RATEVHTSS2MCS2:       ret_rate = MGN_VHT2SS_MCS2;             break;
 371                 case DESC_RATEVHTSS2MCS3:       ret_rate = MGN_VHT2SS_MCS3;             break;
 372                 case DESC_RATEVHTSS2MCS4:       ret_rate = MGN_VHT2SS_MCS4;             break;
 373                 case DESC_RATEVHTSS2MCS5:       ret_rate = MGN_VHT2SS_MCS5;             break;
 374                 case DESC_RATEVHTSS2MCS6:       ret_rate = MGN_VHT2SS_MCS6;             break;
 375                 case DESC_RATEVHTSS2MCS7:       ret_rate = MGN_VHT2SS_MCS7;             break;
 376                 case DESC_RATEVHTSS2MCS8:       ret_rate = MGN_VHT2SS_MCS8;             break;
 377                 case DESC_RATEVHTSS2MCS9:       ret_rate = MGN_VHT2SS_MCS9;             break;
 378                 case DESC_RATEVHTSS3MCS0:       ret_rate = MGN_VHT3SS_MCS0;             break;
 379                 case DESC_RATEVHTSS3MCS1:       ret_rate = MGN_VHT3SS_MCS1;             break;
 380                 case DESC_RATEVHTSS3MCS2:       ret_rate = MGN_VHT3SS_MCS2;             break;
 381                 case DESC_RATEVHTSS3MCS3:       ret_rate = MGN_VHT3SS_MCS3;             break;
 382                 case DESC_RATEVHTSS3MCS4:       ret_rate = MGN_VHT3SS_MCS4;             break;
 383                 case DESC_RATEVHTSS3MCS5:       ret_rate = MGN_VHT3SS_MCS5;             break;
 384                 case DESC_RATEVHTSS3MCS6:       ret_rate = MGN_VHT3SS_MCS6;             break;
 385                 case DESC_RATEVHTSS3MCS7:       ret_rate = MGN_VHT3SS_MCS7;             break;
 386                 case DESC_RATEVHTSS3MCS8:       ret_rate = MGN_VHT3SS_MCS8;             break;
 387                 case DESC_RATEVHTSS3MCS9:       ret_rate = MGN_VHT3SS_MCS9;             break;
 388                 case DESC_RATEVHTSS4MCS0:       ret_rate = MGN_VHT4SS_MCS0;             break;
 389                 case DESC_RATEVHTSS4MCS1:       ret_rate = MGN_VHT4SS_MCS1;             break;
 390                 case DESC_RATEVHTSS4MCS2:       ret_rate = MGN_VHT4SS_MCS2;             break;
 391                 case DESC_RATEVHTSS4MCS3:       ret_rate = MGN_VHT4SS_MCS3;             break;
 392                 case DESC_RATEVHTSS4MCS4:       ret_rate = MGN_VHT4SS_MCS4;             break;
 393                 case DESC_RATEVHTSS4MCS5:       ret_rate = MGN_VHT4SS_MCS5;             break;
 394                 case DESC_RATEVHTSS4MCS6:       ret_rate = MGN_VHT4SS_MCS6;             break;
 395                 case DESC_RATEVHTSS4MCS7:       ret_rate = MGN_VHT4SS_MCS7;             break;
 396                 case DESC_RATEVHTSS4MCS8:       ret_rate = MGN_VHT4SS_MCS8;             break;
 397                 case DESC_RATEVHTSS4MCS9:       ret_rate = MGN_VHT4SS_MCS9;             break;
 398
 399                 default:
 400                         DBG_871X("HwRateToMRate(): Non supported Rate [%x]!!!\n",rate );
 401                         break;
 402         }
 403
 404         return ret_rate;
 405 }
 406
 407 void    HalSetBrateCfg(
 408         IN PADAPTER             Adapter,
 409         IN u8                   *mBratesOS,
 410         OUT u16                 *pBrateCfg)
 411 {
 412         u8      i, is_brate, brate;
 413
 414         for(i=0;i<NDIS_802_11_LENGTH_RATES_EX;i++)
 415         {
 416                 is_brate = mBratesOS[i] & IEEE80211_BASIC_RATE_MASK;
 417                 brate = mBratesOS[i] & 0x7f;
 418
 419                 if( is_brate )
 420                 {
 421                         switch(brate)
 422                         {
 423                                 case IEEE80211_CCK_RATE_1MB:    *pBrateCfg |= RATE_1M;  break;
 424                                 case IEEE80211_CCK_RATE_2MB:    *pBrateCfg |= RATE_2M;  break;
 425                                 case IEEE80211_CCK_RATE_5MB:    *pBrateCfg |= RATE_5_5M;break;
 426                                 case IEEE80211_CCK_RATE_11MB:   *pBrateCfg |= RATE_11M; break;
 427                                 case IEEE80211_OFDM_RATE_6MB:   *pBrateCfg |= RATE_6M;  break;
 428                                 case IEEE80211_OFDM_RATE_9MB:   *pBrateCfg |= RATE_9M;  break;
 429                                 case IEEE80211_OFDM_RATE_12MB:  *pBrateCfg |= RATE_12M; break;
 430                                 case IEEE80211_OFDM_RATE_18MB:  *pBrateCfg |= RATE_18M; break;
 431                                 case IEEE80211_OFDM_RATE_24MB:  *pBrateCfg |= RATE_24M; break;
 432                                 case IEEE80211_OFDM_RATE_36MB:  *pBrateCfg |= RATE_36M; break;
 433                                 case IEEE80211_OFDM_RATE_48MB:  *pBrateCfg |= RATE_48M; break;
 434                                 case IEEE80211_OFDM_RATE_54MB:  *pBrateCfg |= RATE_54M; break;
 435                         }
 436                 }
 437         }
 438 }
 439
 440 static VOID
 441 _OneOutPipeMapping(
 442         IN      PADAPTER        pAdapter
 443         )
 444 {
 445         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(pAdapter);
 446
 447         pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO
 448         pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];//VI
 449         pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[0];//BE
 450         pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];//BK
 451
 452         pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN
 453         pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT
 454         pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH
 455         pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD
 456 }
 457
 458 static VOID
 459 _TwoOutPipeMapping(
 460         IN      PADAPTER        pAdapter,
 461         IN      BOOLEAN         bWIFICfg
 462         )
 463 {
 464         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(pAdapter);
 465
 466         if(bWIFICfg){ //WMM
 467
 468                 //      BK,     BE,     VI,     VO,     BCN,    CMD,MGT,HIGH,HCCA
 469                 //{  0,         1,      0,      1,      0,      0,      0,      0,              0       };
 470                 //0:ep_0 num, 1:ep_1 num
 471
 472                 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[1];//VO
 473                 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];//VI
 474                 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];//BE
 475                 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];//BK
 476
 477                 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN
 478                 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT
 479                 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH
 480                 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD
 481
 482         }
 483         else{//typical setting
 484
 485
 486                 //BK,   BE,     VI,     VO,     BCN,    CMD,MGT,HIGH,HCCA
 487                 //{  1,         1,      0,      0,      0,      0,      0,      0,              0       };
 488                 //0:ep_0 num, 1:ep_1 num
 489
 490                 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO
 491                 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];//VI
 492                 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];//BE
 493                 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];//BK
 494
 495                 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN
 496                 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT
 497                 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH
 498                 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD
 499
 500         }
 501
 502 }
 503
 504 static VOID _ThreeOutPipeMapping(
 505         IN      PADAPTER        pAdapter,
 506         IN      BOOLEAN         bWIFICfg
 507         )
 508 {
 509         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(pAdapter);
 510
 511         if(bWIFICfg){//for WMM
 512
 513                 //      BK,     BE,     VI,     VO,     BCN,    CMD,MGT,HIGH,HCCA
 514                 //{  1,         2,      1,      0,      0,      0,      0,      0,              0       };
 515                 //0:H, 1:N, 2:L
 516
 517                 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO
 518                 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];//VI
 519                 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];//BE
 520                 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];//BK
 521
 522                 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN
 523                 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT
 524                 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH
 525                 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD
 526
 527         }
 528         else{//typical setting
 529
 530
 531                 //      BK,     BE,     VI,     VO,     BCN,    CMD,MGT,HIGH,HCCA
 532                 //{  2,         2,      1,      0,      0,      0,      0,      0,              0       };
 533                 //0:H, 1:N, 2:L
 534
 535                 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO
 536                 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];//VI
 537                 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];//BE
 538                 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];//BK
 539
 540                 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN
 541                 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT
 542                 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH
 543                 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD
 544         }
 545
 546 }
 547 static VOID _FourOutPipeMapping(
 548         IN      PADAPTER        pAdapter,
 549         IN      BOOLEAN         bWIFICfg
 550         )
 551 {
 552         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(pAdapter);
 553
 554         if(bWIFICfg){//for WMM
 555
 556                 //      BK,     BE,     VI,     VO,     BCN,    CMD,MGT,HIGH,HCCA
 557                 //{  1,         2,      1,      0,      0,      0,      0,      0,              0       };
 558                 //0:H, 1:N, 2:L ,3:E
 559
 560                 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO
 561                 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];//VI
 562                 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];//BE
 563                 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];//BK
 564
 565                 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN
 566                 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT
 567                 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[3];//HIGH
 568                 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD
 569
 570         }
 571         else{//typical setting
 572
 573
 574                 //      BK,     BE,     VI,     VO,     BCN,    CMD,MGT,HIGH,HCCA
 575                 //{  2,         2,      1,      0,      0,      0,      0,      0,              0       };
 576                 //0:H, 1:N, 2:L
 577
 578                 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO
 579                 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];//VI
 580                 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];//BE
 581                 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];//BK
 582
 583                 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN
 584                 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT
 585                 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[3];//HIGH
 586                 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD
 587         }
 588
 589 }
 590 BOOLEAN
 591 Hal_MappingOutPipe(
 592         IN      PADAPTER        pAdapter,
 593         IN      u8              NumOutPipe
 594         )
 595 {
 596         struct registry_priv *pregistrypriv = &pAdapter->registrypriv;
 597
 598         BOOLEAN  bWIFICfg = (pregistrypriv->wifi_spec) ?_TRUE:_FALSE;
 599
 600         BOOLEAN result = _TRUE;
 601
 602         switch(NumOutPipe)
 603         {
 604                 case 2:
 605                         _TwoOutPipeMapping(pAdapter, bWIFICfg);
 606                         break;
 607                 case 3:
 608                 case 4:
 609                         _ThreeOutPipeMapping(pAdapter, bWIFICfg);
 610                         break;
 611                 case 1:
 612                         _OneOutPipeMapping(pAdapter);
 613                         break;
 614                 default:
 615                         result = _FALSE;
 616                         break;
 617         }
 618
 619         return result;
 620
 621 }
 622
 623 void hal_init_macaddr(_adapter *adapter)
 624 {
 625         rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, adapter->eeprompriv.mac_addr);
 626 #ifdef  CONFIG_CONCURRENT_MODE
 627         if (adapter->pbuddy_adapter)
 628                 rtw_hal_set_hwreg(adapter->pbuddy_adapter, HW_VAR_MAC_ADDR, adapter->pbuddy_adapter->eeprompriv.mac_addr);
 629 #endif
 630 }
 631
 632 void rtw_init_hal_com_default_value(PADAPTER Adapter)
 633 {
 634         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(Adapter);
 635
 636         pHalData->AntDetection = 1;
 637 }
 638
 639 /*
 640 * C2H event format:
 641 * Field  TRIGGER                CONTENT    CMD_SEQ      CMD_LEN          CMD_ID
 642 * BITS   [127:120]      [119:16]      [15:8]              [7:4]            [3:0]
 643 */
 644
 645 void c2h_evt_clear(_adapter *adapter)
 646 {
 647         rtw_write8(adapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE);
 648 }
 649
 650 s32 c2h_evt_read(_adapter *adapter, u8 *buf)
 651 {
 652         s32 ret = _FAIL;
 653         struct c2h_evt_hdr *c2h_evt;
 654         int i;
 655         u8 trigger;
 656
 657         if (buf == NULL)
 658                 goto exit;
 659
 660 #if defined(CONFIG_RTL8192C) || defined(CONFIG_RTL8192D) || defined(CONFIG_RTL8723A) || defined (CONFIG_RTL8188E)
 661
 662         trigger = rtw_read8(adapter, REG_C2HEVT_CLEAR);
 663
 664         if (trigger == C2H_EVT_HOST_CLOSE) {
 665                 goto exit; /* Not ready */
 666         } else if (trigger != C2H_EVT_FW_CLOSE) {
 667                 goto clear_evt; /* Not a valid value */
 668         }
 669
 670         c2h_evt = (struct c2h_evt_hdr *)buf;
 671
 672         _rtw_memset(c2h_evt, 0, 16);
 673
 674         *buf = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL);
 675         *(buf+1) = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 1);
 676
 677         RT_PRINT_DATA(_module_hal_init_c_, _drv_info_, "c2h_evt_read(): ",
 678                 &c2h_evt , sizeof(c2h_evt));
 679
 680         if (0) {
 681                 DBG_871X("%s id:%u, len:%u, seq:%u, trigger:0x%02x\n", __func__
 682                         , c2h_evt->id, c2h_evt->plen, c2h_evt->seq, trigger);
 683         }
 684
 685         /* Read the content */
 686         for (i = 0; i < c2h_evt->plen; i++)
 687                 c2h_evt->payload[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + sizeof(*c2h_evt) + i);
 688
 689         RT_PRINT_DATA(_module_hal_init_c_, _drv_info_, "c2h_evt_read(): Command Content:\n",
 690                 c2h_evt->payload, c2h_evt->plen);
 691
 692         ret = _SUCCESS;
 693
 694 clear_evt:
 695         /*
 696         * Clear event to notify FW we have read the command.
 697         * If this field isn't clear, the FW won't update the next command message.
 698         */
 699         c2h_evt_clear(adapter);
 700 #endif
 701 exit:
 702         return ret;
 703 }
 704
 705 /*
 706 * C2H event format:
 707 * Field    TRIGGER    CMD_LEN    CONTENT    CMD_SEQ    CMD_ID
 708 * BITS    [127:120]   [119:112]    [111:16]          [15:8]         [7:0]
 709 */
 710 s32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf)
 711 {
 712         s32 ret = _FAIL;
 713         struct c2h_evt_hdr_88xx *c2h_evt;
 714         int i;
 715         u8 trigger;
 716
 717         if (buf == NULL)
 718                 goto exit;
 719
 720 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8723B)
 721
 722         trigger = rtw_read8(adapter, REG_C2HEVT_CLEAR);
 723
 724         if (trigger == C2H_EVT_HOST_CLOSE) {
 725                 goto exit; /* Not ready */
 726         } else if (trigger != C2H_EVT_FW_CLOSE) {
 727                 goto clear_evt; /* Not a valid value */
 728         }
 729
 730         c2h_evt = (struct c2h_evt_hdr_88xx *)buf;
 731
 732         _rtw_memset(c2h_evt, 0, 16);
 733
 734         c2h_evt->id = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL);
 735         c2h_evt->seq = rtw_read8(adapter, REG_C2HEVT_CMD_SEQ_88XX);
 736         c2h_evt->plen = rtw_read8(adapter, REG_C2HEVT_CMD_LEN_88XX);
 737
 738         RT_PRINT_DATA(_module_hal_init_c_, _drv_info_, "c2h_evt_read(): ",
 739                 &c2h_evt , sizeof(c2h_evt));
 740
 741         if (0) {
 742                 DBG_871X("%s id:%u, len:%u, seq:%u, trigger:0x%02x\n", __func__
 743                         , c2h_evt->id, c2h_evt->plen, c2h_evt->seq, trigger);
 744         }
 745
 746         /* Read the content */
 747         for (i = 0; i < c2h_evt->plen; i++)
 748                 c2h_evt->payload[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i);
 749
 750         RT_PRINT_DATA(_module_hal_init_c_, _drv_info_, "c2h_evt_read(): Command Content:\n",
 751                 c2h_evt->payload, c2h_evt->plen);
 752
 753         ret = _SUCCESS;
 754
 755 clear_evt:
 756         /*
 757         * Clear event to notify FW we have read the command.
 758         * If this field isn't clear, the FW won't update the next command message.
 759         */
 760         c2h_evt_clear(adapter);
 761 #endif
 762 exit:
 763         return ret;
 764 }
 765
 766
 767 u8  rtw_hal_networktype_to_raid(_adapter *adapter, struct sta_info *psta)
 768 {
 769         if(IS_NEW_GENERATION_IC(adapter)){
 770                 return networktype_to_raid_ex(adapter,psta);
 771         }
 772         else{
 773                 return networktype_to_raid(adapter,psta);
 774         }
 775
 776 }
 777 u8 rtw_get_mgntframe_raid(_adapter *adapter,unsigned char network_type)
 778 {
 779
 780         u8 raid;
 781         if(IS_NEW_GENERATION_IC(adapter)){
 782
 783                 raid = (network_type & WIRELESS_11B)    ?RATEID_IDX_B
 784                                                                                         :RATEID_IDX_G;
 785         }
 786         else{
 787                 raid = (network_type & WIRELESS_11B)    ?RATR_INX_WIRELESS_B
 788                                                                                         :RATR_INX_WIRELESS_G;
 789         }
 790         return raid;
 791 }
 792
 793 void rtw_hal_update_sta_rate_mask(PADAPTER padapter, struct sta_info *psta)
 794 {
 795         u8      i, rf_type, limit;
 796         u32     tx_ra_bitmap;
 797
 798         if(psta == NULL)
 799         {
 800                 return;
 801         }
 802
 803         tx_ra_bitmap = 0;
 804
 805         //b/g mode ra_bitmap
 806         for (i=0; i<sizeof(psta->bssrateset); i++)
 807         {
 808                 if (psta->bssrateset[i])
 809                         tx_ra_bitmap |= rtw_get_bit_value_from_ieee_value(psta->bssrateset[i]&0x7f);
 810         }
 811
 812 #ifdef CONFIG_80211N_HT
 813 #ifdef CONFIG_80211AC_VHT
 814         //AC mode ra_bitmap
 815         if(psta->vhtpriv.vht_option)
 816         {
 817                 tx_ra_bitmap |= (rtw_vht_rate_to_bitmap(psta->vhtpriv.vht_mcs_map) << 12);
 818         }
 819         else
 820 #endif //CONFIG_80211AC_VHT
 821         {
 822                 //n mode ra_bitmap
 823                 if(psta->htpriv.ht_option)
 824                 {
 825                         rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
 826                         if(rf_type == RF_2T2R)
 827                                 limit=16;// 2R
 828                         else
 829                                 limit=8;//  1R
 830
 831                         for (i=0; i<limit; i++) {
 832                                 if (psta->htpriv.ht_cap.supp_mcs_set[i/8] & BIT(i%8))
 833                                         tx_ra_bitmap |= BIT(i+12);
 834                         }
 835                 }
 836         }
 837 #endif //CONFIG_80211N_HT
 838
 839         psta->ra_mask = tx_ra_bitmap;
 840         psta->init_rate = get_highest_rate_idx(tx_ra_bitmap)&0x3f;
 841 }
 842
 843 void hw_var_port_switch(_adapter *adapter)
 844 {
 845 #ifdef CONFIG_CONCURRENT_MODE
 846 #ifdef CONFIG_RUNTIME_PORT_SWITCH
 847 /*
 848 0x102: MSR
 849 0x550: REG_BCN_CTRL
 850 0x551: REG_BCN_CTRL_1
 851 0x55A: REG_ATIMWND
 852 0x560: REG_TSFTR
 853 0x568: REG_TSFTR1
 854 0x570: REG_ATIMWND_1
 855 0x610: REG_MACID
 856 0x618: REG_BSSID
 857 0x700: REG_MACID1
 858 0x708: REG_BSSID1
 859 */
 860
 861         int i;
 862         u8 msr;
 863         u8 bcn_ctrl;
 864         u8 bcn_ctrl_1;
 865         u8 atimwnd[2];
 866         u8 atimwnd_1[2];
 867         u8 tsftr[8];
 868         u8 tsftr_1[8];
 869         u8 macid[6];
 870         u8 bssid[6];
 871         u8 macid_1[6];
 872         u8 bssid_1[6];
 873
 874         u8 iface_type;
 875
 876         msr = rtw_read8(adapter, MSR);
 877         bcn_ctrl = rtw_read8(adapter, REG_BCN_CTRL);
 878         bcn_ctrl_1 = rtw_read8(adapter, REG_BCN_CTRL_1);
 879
 880         for (i=0; i<2; i++)
 881                 atimwnd[i] = rtw_read8(adapter, REG_ATIMWND+i);
 882         for (i=0; i<2; i++)
 883                 atimwnd_1[i] = rtw_read8(adapter, REG_ATIMWND_1+i);
 884
 885         for (i=0; i<8; i++)
 886                 tsftr[i] = rtw_read8(adapter, REG_TSFTR+i);
 887         for (i=0; i<8; i++)
 888                 tsftr_1[i] = rtw_read8(adapter, REG_TSFTR1+i);
 889
 890         for (i=0; i<6; i++)
 891                 macid[i] = rtw_read8(adapter, REG_MACID+i);
 892
 893         for (i=0; i<6; i++)
 894                 bssid[i] = rtw_read8(adapter, REG_BSSID+i);
 895
 896         for (i=0; i<6; i++)
 897                 macid_1[i] = rtw_read8(adapter, REG_MACID1+i);
 898
 899         for (i=0; i<6; i++)
 900                 bssid_1[i] = rtw_read8(adapter, REG_BSSID1+i);
 901
 902 #ifdef DBG_RUNTIME_PORT_SWITCH
 903         DBG_871X(FUNC_ADPT_FMT" before switch\n"
 904                 "msr:0x%02x\n"
 905                 "bcn_ctrl:0x%02x\n"
 906                 "bcn_ctrl_1:0x%02x\n"
 907                 "atimwnd:0x%04x\n"
 908                 "atimwnd_1:0x%04x\n"
 909                 "tsftr:%llu\n"
 910                 "tsftr1:%llu\n"
 911                 "macid:"MAC_FMT"\n"
 912                 "bssid:"MAC_FMT"\n"
 913                 "macid_1:"MAC_FMT"\n"
 914                 "bssid_1:"MAC_FMT"\n"
 915                 , FUNC_ADPT_ARG(adapter)
 916                 , msr
 917                 , bcn_ctrl
 918                 , bcn_ctrl_1
 919                 , *((u16*)atimwnd)
 920                 , *((u16*)atimwnd_1)
 921                 , *((u64*)tsftr)
 922                 , *((u64*)tsftr_1)
 923                 , MAC_ARG(macid)
 924                 , MAC_ARG(bssid)
 925                 , MAC_ARG(macid_1)
 926                 , MAC_ARG(bssid_1)
 927         );
 928 #endif /* DBG_RUNTIME_PORT_SWITCH */
 929
 930         /* disable bcn function, disable update TSF  */
 931         rtw_write8(adapter, REG_BCN_CTRL, (bcn_ctrl & (~EN_BCN_FUNCTION)) | DIS_TSF_UDT);
 932         rtw_write8(adapter, REG_BCN_CTRL_1, (bcn_ctrl_1 & (~EN_BCN_FUNCTION)) | DIS_TSF_UDT);
 933
 934         /* switch msr */
 935         msr = (msr&0xf0) |((msr&0x03) << 2) | ((msr&0x0c) >> 2);
 936         rtw_write8(adapter, MSR, msr);
 937
 938         /* write port0 */
 939         rtw_write8(adapter, REG_BCN_CTRL, bcn_ctrl_1 & ~EN_BCN_FUNCTION);
 940         for (i=0; i<2; i++)
 941                 rtw_write8(adapter, REG_ATIMWND+i, atimwnd_1[i]);
 942         for (i=0; i<8; i++)
 943                 rtw_write8(adapter, REG_TSFTR+i, tsftr_1[i]);
 944         for (i=0; i<6; i++)
 945                 rtw_write8(adapter, REG_MACID+i, macid_1[i]);
 946         for (i=0; i<6; i++)
 947                 rtw_write8(adapter, REG_BSSID+i, bssid_1[i]);
 948
 949         /* write port1 */
 950         rtw_write8(adapter, REG_BCN_CTRL_1, bcn_ctrl & ~EN_BCN_FUNCTION);
 951         for (i=0; i<2; i++)
 952                 rtw_write8(adapter, REG_ATIMWND_1+1, atimwnd[i]);
 953         for (i=0; i<8; i++)
 954                 rtw_write8(adapter, REG_TSFTR1+i, tsftr[i]);
 955         for (i=0; i<6; i++)
 956                 rtw_write8(adapter, REG_MACID1+i, macid[i]);
 957         for (i=0; i<6; i++)
 958                 rtw_write8(adapter, REG_BSSID1+i, bssid[i]);
 959
 960         /* write bcn ctl */
 961 #ifdef CONFIG_BT_COEXIST
 962 #if defined(CONFIG_RTL8723A) || defined(CONFIG_RTL8723B)
 963         // always enable port0 beacon function for PSTDMA
 964         bcn_ctrl_1 |= EN_BCN_FUNCTION;
 965         // always disable port1 beacon function for PSTDMA
 966         bcn_ctrl &= ~EN_BCN_FUNCTION;
 967 #endif
 968 #endif
 969         rtw_write8(adapter, REG_BCN_CTRL, bcn_ctrl_1);
 970         rtw_write8(adapter, REG_BCN_CTRL_1, bcn_ctrl);
 971
 972         if (adapter->iface_type == IFACE_PORT0) {
 973                 adapter->iface_type = IFACE_PORT1;
 974                 adapter->pbuddy_adapter->iface_type = IFACE_PORT0;
 975                 DBG_871X_LEVEL(_drv_always_, "port switch - port0("ADPT_FMT"), port1("ADPT_FMT")\n",
 976                         ADPT_ARG(adapter->pbuddy_adapter), ADPT_ARG(adapter));
 977         } else {
 978                 adapter->iface_type = IFACE_PORT0;
 979                 adapter->pbuddy_adapter->iface_type = IFACE_PORT1;
 980                 DBG_871X_LEVEL(_drv_always_, "port switch - port0("ADPT_FMT"), port1("ADPT_FMT")\n",
 981                         ADPT_ARG(adapter), ADPT_ARG(adapter->pbuddy_adapter));
 982         }
 983
 984 #ifdef DBG_RUNTIME_PORT_SWITCH
 985         msr = rtw_read8(adapter, MSR);
 986         bcn_ctrl = rtw_read8(adapter, REG_BCN_CTRL);
 987         bcn_ctrl_1 = rtw_read8(adapter, REG_BCN_CTRL_1);
 988
 989         for (i=0; i<2; i++)
 990                 atimwnd[i] = rtw_read8(adapter, REG_ATIMWND+i);
 991         for (i=0; i<2; i++)
 992                 atimwnd_1[i] = rtw_read8(adapter, REG_ATIMWND_1+i);
 993
 994         for (i=0; i<8; i++)
 995                 tsftr[i] = rtw_read8(adapter, REG_TSFTR+i);
 996         for (i=0; i<8; i++)
 997                 tsftr_1[i] = rtw_read8(adapter, REG_TSFTR1+i);
 998
 999         for (i=0; i<6; i++)
1000                 macid[i] = rtw_read8(adapter, REG_MACID+i);
1001
1002         for (i=0; i<6; i++)
1003                 bssid[i] = rtw_read8(adapter, REG_BSSID+i);
1004
1005         for (i=0; i<6; i++)
1006                 macid_1[i] = rtw_read8(adapter, REG_MACID1+i);
1007
1008         for (i=0; i<6; i++)
1009                 bssid_1[i] = rtw_read8(adapter, REG_BSSID1+i);
1010
1011         DBG_871X(FUNC_ADPT_FMT" after switch\n"
1012                 "msr:0x%02x\n"
1013                 "bcn_ctrl:0x%02x\n"
1014                 "bcn_ctrl_1:0x%02x\n"
1015                 "atimwnd:%u\n"
1016                 "atimwnd_1:%u\n"
1017                 "tsftr:%llu\n"
1018                 "tsftr1:%llu\n"
1019                 "macid:"MAC_FMT"\n"
1020                 "bssid:"MAC_FMT"\n"
1021                 "macid_1:"MAC_FMT"\n"
1022                 "bssid_1:"MAC_FMT"\n"
1023                 , FUNC_ADPT_ARG(adapter)
1024                 , msr
1025                 , bcn_ctrl
1026                 , bcn_ctrl_1
1027                 , *((u16*)atimwnd)
1028                 , *((u16*)atimwnd_1)
1029                 , *((u64*)tsftr)
1030                 , *((u64*)tsftr_1)
1031                 , MAC_ARG(macid)
1032                 , MAC_ARG(bssid)
1033                 , MAC_ARG(macid_1)
1034                 , MAC_ARG(bssid_1)
1035         );
1036 #endif /* DBG_RUNTIME_PORT_SWITCH */
1037
1038 #endif /* CONFIG_RUNTIME_PORT_SWITCH */
1039 #endif /* CONFIG_CONCURRENT_MODE */
1040 }
1041
1042 void SetHwReg(_adapter *adapter, u8 variable, u8 *val)
1043 {
1044         HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1045         DM_ODM_T *odm = &(hal_data->odmpriv);
1046
1047 _func_enter_;
1048
1049         switch (variable) {
1050         case HW_VAR_PORT_SWITCH:
1051                 hw_var_port_switch(adapter);
1052                 break;
1053         case HW_VAR_INIT_RTS_RATE:
1054         {
1055                 u16 brate_cfg = *((u16*)val);
1056                 u8 rate_index = 0;
1057                 HAL_VERSION *hal_ver = &hal_data->VersionID;
1058
1059                 if (IS_81XXC(*hal_ver) ||IS_92D(*hal_ver) || IS_8723_SERIES(*hal_ver) || IS_8188E(*hal_ver)) {
1060
1061                         while (brate_cfg > 0x1) {
1062                                 brate_cfg = (brate_cfg >> 1);
1063                                 rate_index++;
1064                         }
1065                         rtw_write8(adapter, REG_INIRTS_RATE_SEL, rate_index);
1066                 } else {
1067                         rtw_warn_on(1);
1068                 }
1069         }
1070                 break;
1071         case HW_VAR_SEC_CFG:
1072         {
1073                 #if defined(CONFIG_CONCURRENT_MODE) && !defined(DYNAMIC_CAMID_ALLOC)
1074                 // enable tx enc and rx dec engine, and no key search for MC/BC
1075                 rtw_write8(adapter, REG_SECCFG, SCR_NoSKMC|SCR_RxDecEnable|SCR_TxEncEnable);
1076                 #elif defined(DYNAMIC_CAMID_ALLOC)
1077                 u16 reg_scr;
1078
1079                 reg_scr = rtw_read16(adapter, REG_SECCFG);
1080                 rtw_write16(adapter, REG_SECCFG, reg_scr|SCR_CHK_KEYID|SCR_RxDecEnable|SCR_TxEncEnable);
1081                 #else
1082                 rtw_write8(adapter, REG_SECCFG, *((u8*)val));
1083                 #endif
1084         }
1085                 break;
1086         case HW_VAR_SEC_DK_CFG:
1087         {
1088                 struct security_priv *sec = &adapter->securitypriv;
1089                 u8 reg_scr = rtw_read8(adapter, REG_SECCFG);
1090
1091                 if (val) /* Enable default key related setting */
1092                 {
1093                         reg_scr |= SCR_TXBCUSEDK;
1094                         if (sec->dot11AuthAlgrthm != dot11AuthAlgrthm_8021X)
1095                                 reg_scr |= (SCR_RxUseDK|SCR_TxUseDK);
1096                 }
1097                 else /* Disable default key related setting */
1098                 {
1099                         reg_scr &= ~(SCR_RXBCUSEDK|SCR_TXBCUSEDK|SCR_RxUseDK|SCR_TxUseDK);
1100                 }
1101
1102                 rtw_write8(adapter, REG_SECCFG, reg_scr);
1103         }
1104                 break;
1105         case HW_VAR_DM_FLAG:
1106                 odm->SupportAbility = *((u32*)val);
1107                 break;
1108         case HW_VAR_DM_FUNC_OP:
1109                 if (*((u8*)val) == _TRUE) {
1110                         /* save dm flag */
1111                         odm->BK_SupportAbility = odm->SupportAbility;
1112                 } else {
1113                         /* restore dm flag */
1114                         odm->SupportAbility = odm->BK_SupportAbility;
1115                 }
1116                 break;
1117         case HW_VAR_DM_FUNC_SET:
1118                 if(*((u32*)val) == DYNAMIC_ALL_FUNC_ENABLE){
1119                         struct dm_priv  *dm = &hal_data->dmpriv;
1120                         dm->DMFlag = dm->InitDMFlag;
1121                         odm->SupportAbility = dm->InitODMFlag;
1122                 } else {
1123                         odm->SupportAbility |= *((u32 *)val);
1124                 }
1125                 break;
1126         case HW_VAR_DM_FUNC_CLR:
1127                 /*
1128                 * input is already a mask to clear function
1129                 * don't invert it again! George,Lucas@20130513
1130                 */
1131                 odm->SupportAbility &= *((u32 *)val);
1132                 break;
1133         default:
1134                 if (0)
1135                 DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" variable(%d) not defined!\n",
1136                         FUNC_ADPT_ARG(adapter), variable);
1137                 break;
1138         }
1139
1140 _func_exit_;
1141 }
1142
1143 void GetHwReg(_adapter *adapter, u8 variable, u8 *val)
1144 {
1145         HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1146         DM_ODM_T *odm = &(hal_data->odmpriv);
1147
1148 _func_enter_;
1149
1150         switch (variable) {
1151         case HW_VAR_BASIC_RATE:
1152                 *((u16*)val) = hal_data->BasicRateSet;
1153                 break;
1154         case HW_VAR_DM_FLAG:
1155                 *((u32*)val) = odm->SupportAbility;
1156                 break;
1157         case HW_VAR_RF_TYPE:
1158                 *((u8*)val) = hal_data->rf_type;
1159                 break;
1160         default:
1161                 if (0)
1162                 DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" variable(%d) not defined!\n",
1163                         FUNC_ADPT_ARG(adapter), variable);
1164                 break;
1165         }
1166
1167 _func_exit_;
1168 }
1169
1170
1171
1172
1173 u8
1174 SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value)
1175 {
1176         HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1177         DM_ODM_T *odm = &(hal_data->odmpriv);
1178         u8 bResult = _SUCCESS;
1179
1180         switch(variable) {
1181         case HW_DEF_FA_CNT_DUMP:
1182                 //ODM_COMP_COMMON
1183                 if(*((u8*)value))
1184                         odm->DebugComponents |= (ODM_COMP_DIG |ODM_COMP_FA_CNT);
1185                 else
1186                         odm->DebugComponents &= ~(ODM_COMP_DIG |ODM_COMP_FA_CNT);
1187                 break;
1188         case HAL_DEF_DBG_RX_INFO_DUMP:
1189                 {
1190                         PFALSE_ALARM_STATISTICS FalseAlmCnt = &(odm->FalseAlmCnt);
1191                         pDIG_T  pDM_DigTable = &odm->DM_DigTable;
1192
1193                         DBG_871X("============ Rx Info dump ===================\n");
1194                         DBG_871X("bLinked = %d, RSSI_Min = %d(%%), CurrentIGI = 0x%x \n",
1195                                 odm->bLinked, odm->RSSI_Min, pDM_DigTable->CurIGValue);
1196                         DBG_871X("Cnt_Cck_fail = %d, Cnt_Ofdm_fail = %d, Total False Alarm = %d\n",
1197                                 FalseAlmCnt->Cnt_Cck_fail, FalseAlmCnt->Cnt_Ofdm_fail, FalseAlmCnt->Cnt_all);
1198
1199                         if(odm->bLinked){
1200                                 DBG_871X("RxRate = %s, RSSI_A = %d(%%), RSSI_B = %d(%%)\n",
1201                                         HDATA_RATE(odm->RxRate), odm->RSSI_A, odm->RSSI_B);
1202
1203                                 #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
1204                                 rtw_dump_raw_rssi_info(adapter);
1205                                 #endif
1206                         }
1207                 }
1208                 break;
1209         case HW_DEF_ODM_DBG_FLAG:
1210                 ODM_CmnInfoUpdate(odm, ODM_CMNINFO_DBG_COMP, *((u8Byte*)value));
1211                 break;
1212         case HW_DEF_ODM_DBG_LEVEL:
1213                 ODM_CmnInfoUpdate(odm, ODM_CMNINFO_DBG_LEVEL, *((u4Byte*)value));
1214                 break;
1215         case HAL_DEF_DBG_DM_FUNC:
1216         {
1217                 u8 dm_func = *((u8*)value);
1218                 struct dm_priv *dm = &hal_data->dmpriv;
1219
1220                 if(dm_func == 0){ //disable all dynamic func
1221                         odm->SupportAbility = DYNAMIC_FUNC_DISABLE;
1222                         DBG_8192C("==> Disable all dynamic function...\n");
1223                 }
1224                 else if(dm_func == 1){//disable DIG
1225                         odm->SupportAbility  &= (~DYNAMIC_BB_DIG);
1226                         DBG_8192C("==> Disable DIG...\n");
1227                 }
1228                 else if(dm_func == 2){//disable High power
1229                         odm->SupportAbility  &= (~DYNAMIC_BB_DYNAMIC_TXPWR);
1230                 }
1231                 else if(dm_func == 3){//disable tx power tracking
1232                         odm->SupportAbility  &= (~DYNAMIC_RF_CALIBRATION);
1233                         DBG_8192C("==> Disable tx power tracking...\n");
1234                 }
1235                 else if(dm_func == 4){//disable BT coexistence
1236                         dm->DMFlag &= (~DYNAMIC_FUNC_BT);
1237                 }
1238                 else if(dm_func == 5){//disable antenna diversity
1239                         odm->SupportAbility  &= (~DYNAMIC_BB_ANT_DIV);
1240                 }
1241                 else if(dm_func == 6){//turn on all dynamic func
1242                         if(!(odm->SupportAbility  & DYNAMIC_BB_DIG)) {
1243                                 DIG_T   *pDigTable = &odm->DM_DigTable;
1244                                 pDigTable->CurIGValue= rtw_read8(adapter, 0xc50);
1245                         }
1246                         dm->DMFlag |= DYNAMIC_FUNC_BT;
1247                         odm->SupportAbility = DYNAMIC_ALL_FUNC_ENABLE;
1248                         DBG_8192C("==> Turn on all dynamic function...\n");
1249                 }
1250         }
1251                 break;
1252         case HAL_DEF_DBG_DUMP_RXPKT:
1253                 hal_data->bDumpRxPkt = *((u8*)value);
1254                 break;
1255         case HAL_DEF_DBG_DUMP_TXPKT:
1256                 hal_data->bDumpTxPkt = *((u8*)value);
1257                 break;
1258         case HAL_DEF_ANT_DETECT:
1259                 hal_data->AntDetection = *((u8 *)value);
1260                 break;
1261         default:
1262                 DBG_871X_LEVEL(_drv_always_, "%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __FUNCTION__, variable);
1263                 bResult = _FAIL;
1264                 break;
1265         }
1266
1267         return bResult;
1268 }
1269
1270 u8
1271 GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value)
1272 {
1273         HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
1274         DM_ODM_T *odm = &(hal_data->odmpriv);
1275         u8 bResult = _SUCCESS;
1276
1277         switch(variable) {
1278                 case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
1279                         {
1280                                 struct mlme_priv *pmlmepriv;
1281                                 struct sta_priv *pstapriv;
1282                                 struct sta_info *psta;
1283
1284                                 pmlmepriv = &adapter->mlmepriv;
1285                                 pstapriv = &adapter->stapriv;
1286                                 psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress);
1287                                 if (psta)
1288                                 {
1289                                         *((int*)value) = psta->rssi_stat.UndecoratedSmoothedPWDB;
1290                                 }
1291                         }
1292                         break;
1293                 case HW_DEF_ODM_DBG_FLAG:
1294                         *((u8Byte*)value) = odm->DebugComponents;
1295                         break;
1296                 case HW_DEF_ODM_DBG_LEVEL:
1297                         *((u4Byte*)value) = odm->DebugLevel;
1298                         break;
1299                 case HAL_DEF_DBG_DM_FUNC:
1300                         *(( u32*)value) =hal_data->odmpriv.SupportAbility;
1301                         break;
1302                 case HAL_DEF_DBG_DUMP_RXPKT:
1303                         *((u8*)value) = hal_data->bDumpRxPkt;
1304                         break;
1305                 case HAL_DEF_DBG_DUMP_TXPKT:
1306                         *((u8*)value) = hal_data->bDumpTxPkt;
1307                         break;
1308                 case HAL_DEF_ANT_DETECT:
1309                         *((u8 *)value) = hal_data->AntDetection;
1310                         break;
1311                 case HAL_DEF_MACID_SLEEP:
1312                         *(u8*)value = _FALSE;
1313                         break;
1314                 case HAL_DEF_TX_PAGE_SIZE:
1315                         *(( u32*)value) = PAGE_SIZE_128;
1316                         break;
1317                 default:
1318                         DBG_871X_LEVEL(_drv_always_, "%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __FUNCTION__, variable);
1319                         bResult = _FAIL;
1320                         break;
1321         }
1322
1323         return bResult;
1324 }
1325
1326 void GetHalODMVar(
1327         PADAPTER                                Adapter,
1328         HAL_ODM_VARIABLE                eVariable,
1329         PVOID                                   pValue1,
1330         PVOID                                   pValue2)
1331 {
1332         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1333         PDM_ODM_T podmpriv = &pHalData->odmpriv;
1334         switch(eVariable){
1335 #if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR)
1336                 case HAL_ODM_NOISE_MONITOR:
1337                         {
1338                                 u8 chan = *(u8*)pValue1;
1339                                 *(s16 *)pValue2 = pHalData->noise[chan];
1340                                 #ifdef DBG_NOISE_MONITOR
1341                                 DBG_8192C("### Noise monitor chan(%d)-noise:%d (dBm) ###\n",
1342                                         chan,pHalData->noise[chan]);
1343                                 #endif
1344
1345                         }
1346                         break;
1347 #endif//#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
1348                 default:
1349                         break;
1350         }
1351 }
1352
1353 void SetHalODMVar(
1354         PADAPTER                                Adapter,
1355         HAL_ODM_VARIABLE                eVariable,
1356         PVOID                                   pValue1,
1357         BOOLEAN                                 bSet)
1358 {
1359         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1360         PDM_ODM_T podmpriv = &pHalData->odmpriv;
1361         //_irqL irqL;
1362         switch(eVariable){
1363                 case HAL_ODM_STA_INFO:
1364                         {
1365                                 struct sta_info *psta = (struct sta_info *)pValue1;
1366                                 if(bSet){
1367                                         DBG_8192C("### Set STA_(%d) info ###\n",psta->mac_id);
1368                                         ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS,psta->mac_id,psta);
1369                                 }
1370                                 else{
1371                                         DBG_8192C("### Clean STA_(%d) info ###\n",psta->mac_id);
1372                                         //_enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL);
1373                                         ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS,psta->mac_id,NULL);
1374
1375                                         //_exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL);
1376                                     }
1377                         }
1378                         break;
1379                 case HAL_ODM_P2P_STATE:
1380                                 ODM_CmnInfoUpdate(podmpriv,ODM_CMNINFO_WIFI_DIRECT,bSet);
1381                         break;
1382                 case HAL_ODM_WIFI_DISPLAY_STATE:
1383                                 ODM_CmnInfoUpdate(podmpriv,ODM_CMNINFO_WIFI_DISPLAY,bSet);
1384                         break;
1385                 #if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR)
1386                 case HAL_ODM_NOISE_MONITOR:
1387                         {
1388                                 struct noise_info *pinfo = (struct noise_info *)pValue1;
1389
1390                                 #ifdef DBG_NOISE_MONITOR
1391                                 DBG_8192C("### Noise monitor chan(%d)-bPauseDIG:%d,IGIValue:0x%02x,max_time:%d (ms) ###\n",
1392                                         pinfo->chan,pinfo->bPauseDIG,pinfo->IGIValue,pinfo->max_time);
1393                                 #endif
1394
1395                                 pHalData->noise[pinfo->chan] = ODM_InbandNoise_Monitor(podmpriv,pinfo->bPauseDIG,pinfo->IGIValue,pinfo->max_time);
1396                                 DBG_871X("chan_%d, noise = %d (dBm)\n",pinfo->chan,pHalData->noise[pinfo->chan]);
1397                                 #ifdef DBG_NOISE_MONITOR
1398                                 DBG_871X("noise_a = %d, noise_b = %d  noise_all:%d \n",
1399                                         podmpriv->noise_level.noise[ODM_RF_PATH_A],
1400                                         podmpriv->noise_level.noise[ODM_RF_PATH_B],
1401                                         podmpriv->noise_level.noise_all);
1402                                 #endif
1403                         }
1404                         break;
1405                 #endif//#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
1406
1407                 default:
1408                         break;
1409         }
1410 }
1411
1412
1413 BOOLEAN
1414 eqNByte(
1415         u8*     str1,
1416         u8*     str2,
1417         u32     num
1418         )
1419 {
1420         if(num==0)
1421                 return _FALSE;
1422         while(num>0)
1423         {
1424                 num--;
1425                 if(str1[num]!=str2[num])
1426                         return _FALSE;
1427         }
1428         return _TRUE;
1429 }
1430
1431 //
1432 //      Description:
1433 //              Return TRUE if chTmp is represent for hex digit and
1434 //              FALSE otherwise.
1435 //
1436 //
1437 BOOLEAN
1438 IsHexDigit(
1439         IN              char            chTmp
1440 )
1441 {
1442         if( (chTmp >= '0' && chTmp <= '9') ||
1443                 (chTmp >= 'a' && chTmp <= 'f') ||
1444                 (chTmp >= 'A' && chTmp <= 'F') )
1445         {
1446                 return _TRUE;
1447         }
1448         else
1449         {
1450                 return _FALSE;
1451         }
1452 }
1453
1454
1455 //
1456 //      Description:
1457 //              Translate a character to hex digit.
1458 //
1459 u32
1460 MapCharToHexDigit(
1461         IN              char            chTmp
1462 )
1463 {
1464         if(chTmp >= '0' && chTmp <= '9')
1465                 return (chTmp - '0');
1466         else if(chTmp >= 'a' && chTmp <= 'f')
1467                 return (10 + (chTmp - 'a'));
1468         else if(chTmp >= 'A' && chTmp <= 'F')
1469                 return (10 + (chTmp - 'A'));
1470         else
1471                 return 0;
1472 }
1473
1474
1475
1476 //
1477 //      Description:
1478 //              Parse hex number from the string pucStr.
1479 //
1480 BOOLEAN
1481 GetHexValueFromString(
1482         IN              char*                   szStr,
1483         IN OUT  u32*                    pu4bVal,
1484         IN OUT  u32*                    pu4bMove
1485 )
1486 {
1487         char*           szScan = szStr;
1488
1489         // Check input parameter.
1490         if(szStr == NULL || pu4bVal == NULL || pu4bMove == NULL)
1491         {
1492                 DBG_871X("GetHexValueFromString(): Invalid inpur argumetns! szStr: %p, pu4bVal: %p, pu4bMove: %p\n", szStr, pu4bVal, pu4bMove);
1493                 return _FALSE;
1494         }
1495
1496         // Initialize output.
1497         *pu4bMove = 0;
1498         *pu4bVal = 0;
1499
1500         // Skip leading space.
1501         while(  *szScan != '\0' &&
1502                         (*szScan == ' ' || *szScan == '\t') )
1503         {
1504                 szScan++;
1505                 (*pu4bMove)++;
1506         }
1507
1508         // Skip leading '0x' or '0X'.
1509         if(*szScan == '0' && (*(szScan+1) == 'x' || *(szScan+1) == 'X'))
1510         {
1511                 szScan += 2;
1512                 (*pu4bMove) += 2;
1513         }
1514
1515         // Check if szScan is now pointer to a character for hex digit,
1516         // if not, it means this is not a valid hex number.
1517         if(!IsHexDigit(*szScan))
1518         {
1519                 return _FALSE;
1520         }
1521
1522         // Parse each digit.
1523         do
1524         {
1525                 (*pu4bVal) <<= 4;
1526                 *pu4bVal += MapCharToHexDigit(*szScan);
1527
1528                 szScan++;
1529                 (*pu4bMove)++;
1530         } while(IsHexDigit(*szScan));
1531
1532         return _TRUE;
1533 }
1534
1535 BOOLEAN
1536 GetFractionValueFromString(
1537         IN              char*                   szStr,
1538         IN OUT  u8*                             pInteger,
1539         IN OUT  u8*                             pFraction,
1540         IN OUT  u32*                    pu4bMove
1541 )
1542 {
1543         char    *szScan = szStr;
1544
1545         // Initialize output.
1546         *pu4bMove = 0;
1547         *pInteger = 0;
1548         *pFraction = 0;
1549
1550         // Skip leading space.
1551         while ( *szScan != '\0' &&      (*szScan == ' ' || *szScan == '\t') ) {
1552                 ++szScan;
1553                 ++(*pu4bMove);
1554         }
1555
1556         // Parse each digit.
1557         do {
1558                 (*pInteger) *= 10;
1559                 *pInteger += ( *szScan - '0' );
1560
1561                 ++szScan;
1562                 ++(*pu4bMove);
1563
1564                 if ( *szScan == '.' )
1565                 {
1566                         ++szScan;
1567                         ++(*pu4bMove);
1568
1569                         if ( *szScan < '0' || *szScan > '9' )
1570                                 return _FALSE;
1571                         else {
1572                                 *pFraction = *szScan - '0';
1573                                 ++szScan;
1574                                 ++(*pu4bMove);
1575                                 return _TRUE;
1576                         }
1577                 }
1578         } while(*szScan >= '0' && *szScan <= '9');
1579
1580         return _TRUE;
1581 }
1582
1583 //
1584 //      Description:
1585 //              Return TRUE if szStr is comment out with leading "//".
1586 //
1587 BOOLEAN
1588 IsCommentString(
1589         IN              char                    *szStr
1590 )
1591 {
1592         if(*szStr == '/' && *(szStr+1) == '/')
1593         {
1594                 return _TRUE;
1595         }
1596         else
1597         {
1598                 return _FALSE;
1599         }
1600 }
1601
1602 BOOLEAN
1603 GetU1ByteIntegerFromStringInDecimal(
1604         IN              char*   Str,
1605         IN OUT  u8*             pInt
1606         )
1607 {
1608         u16 i = 0;
1609         *pInt = 0;
1610
1611         while ( Str[i] != '\0' )
1612         {
1613                 if ( Str[i] >= '0' && Str[i] <= '9' )
1614                 {
1615                         *pInt *= 10;
1616                         *pInt += ( Str[i] - '0' );
1617                 }
1618                 else
1619                 {
1620                         return _FALSE;
1621                 }
1622                 ++i;
1623         }
1624
1625         return _TRUE;
1626 }
1627
1628 // <20121004, Kordan> For example,
1629 // ParseQualifiedString(inString, 0, outString, '[', ']') gets "Kordan" from a string "Hello [Kordan]".
1630 // If RightQualifier does not exist, it will hang on in the while loop
1631 BOOLEAN
1632 ParseQualifiedString(
1633     IN          char*   In,
1634     IN OUT      u32*    Start,
1635     OUT         char*   Out,
1636     IN          char            LeftQualifier,
1637     IN          char            RightQualifier
1638     )
1639 {
1640         u32     i = 0, j = 0;
1641         char    c = In[(*Start)++];
1642
1643         if (c != LeftQualifier)
1644                 return _FALSE;
1645
1646         i = (*Start);
1647         while ((c = In[(*Start)++]) != RightQualifier)
1648                 ; // find ']'
1649         j = (*Start) - 2;
1650         strncpy((char *)Out, (const char*)(In+i), j-i+1);
1651
1652         return _TRUE;
1653 }
1654
1655 BOOLEAN
1656 isAllSpaceOrTab(
1657         u8*     data,
1658         u8      size
1659         )
1660 {
1661         u8      cnt = 0, NumOfSpaceAndTab = 0;
1662
1663         while( size > cnt )
1664         {
1665                 if ( data[cnt] == ' ' || data[cnt] == '\t' || data[cnt] == '\0' )
1666                         ++NumOfSpaceAndTab;
1667
1668                 ++cnt;
1669         }
1670
1671         return size == NumOfSpaceAndTab;
1672 }
1673
1674
1675 void rtw_hal_check_rxfifo_full(_adapter *adapter)
1676 {
1677         struct dvobj_priv *psdpriv = adapter->dvobj;
1678         struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
1679         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(adapter);
1680         int save_cnt=_FALSE;
1681
1682         //switch counter to RX fifo
1683         if(IS_81XXC(pHalData->VersionID) || IS_92D(pHalData->VersionID)
1684                 || IS_8188E(pHalData->VersionID) || IS_8723_SERIES(pHalData->VersionID)
1685                 || IS_8812_SERIES(pHalData->VersionID) || IS_8821_SERIES(pHalData->VersionID))
1686         {
1687                 rtw_write8(adapter, REG_RXERR_RPT+3, rtw_read8(adapter, REG_RXERR_RPT+3)|0xa0);
1688                 save_cnt = _TRUE;
1689         }
1690         else if(IS_8723B_SERIES(pHalData->VersionID) || IS_8192E(pHalData->VersionID))
1691         {
1692                 //printk("8723b or 8192e , MAC_667 set 0xf0\n");
1693                 rtw_write8(adapter, REG_RXERR_RPT+3, rtw_read8(adapter, REG_RXERR_RPT+3)|0xf0);
1694                 save_cnt = _TRUE;
1695         }
1696         //todo: other chips
1697
1698         if(save_cnt)
1699         {
1700                 //rtw_write8(adapter, REG_RXERR_RPT+3, rtw_read8(adapter, REG_RXERR_RPT+3)|0xa0);
1701                 pdbgpriv->dbg_rx_fifo_last_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow;
1702                 pdbgpriv->dbg_rx_fifo_curr_overflow = rtw_read16(adapter, REG_RXERR_RPT);
1703                 pdbgpriv->dbg_rx_fifo_diff_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow-pdbgpriv->dbg_rx_fifo_last_overflow;
1704         }
1705 }
1706
1707 void linked_info_dump(_adapter *padapter,u8 benable)
1708 {
1709         struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
1710
1711         if(padapter->bLinkInfoDump == benable)
1712                 return;
1713
1714         DBG_871X("%s %s \n",__FUNCTION__,(benable)?"enable":"disable");
1715
1716         if(benable){
1717                 #ifdef CONFIG_LPS
1718                 pwrctrlpriv->org_power_mgnt = pwrctrlpriv->power_mgnt;//keep org value
1719                 rtw_pm_set_lps(padapter,PS_MODE_ACTIVE);
1720                 #endif
1721
1722                 #ifdef CONFIG_IPS
1723                 pwrctrlpriv->ips_org_mode = pwrctrlpriv->ips_mode;//keep org value
1724                 rtw_pm_set_ips(padapter,IPS_NONE);
1725                 #endif
1726         }
1727         else{
1728                 #ifdef CONFIG_IPS
1729                 rtw_pm_set_ips(padapter, pwrctrlpriv->ips_org_mode);
1730                 #endif // CONFIG_IPS
1731
1732                 #ifdef CONFIG_LPS
1733                 rtw_pm_set_lps(padapter, pwrctrlpriv->ips_org_mode);
1734                 #endif // CONFIG_LPS
1735         }
1736         padapter->bLinkInfoDump = benable ;
1737 }
1738
1739 #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
1740 void rtw_get_raw_rssi_info(void *sel, _adapter *padapter)
1741 {
1742         u8 isCCKrate,rf_path;
1743         PHAL_DATA_TYPE  pHalData =  GET_HAL_DATA(padapter);
1744         struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
1745
1746         DBG_871X_SEL_NL(sel,"RxRate = %s, PWDBALL = %d(%%), rx_pwr_all = %d(dBm)\n",
1747                         HDATA_RATE(psample_pkt_rssi->data_rate), psample_pkt_rssi->pwdball, psample_pkt_rssi->pwr_all);
1748         isCCKrate = (psample_pkt_rssi->data_rate <= DESC_RATE11M)?TRUE :FALSE;
1749
1750         if(isCCKrate)
1751                 psample_pkt_rssi->mimo_singal_strength[0] = psample_pkt_rssi->pwdball;
1752
1753         for(rf_path = 0;rf_path<pHalData->NumTotalRFPath;rf_path++)
1754         {
1755                 DBG_871X_SEL_NL(sel,"RF_PATH_%d=>singal_strength:%d(%%),singal_quality:%d(%%)\n"
1756                         ,rf_path,psample_pkt_rssi->mimo_singal_strength[rf_path],psample_pkt_rssi->mimo_singal_quality[rf_path]);
1757
1758                 if(!isCCKrate){
1759                         DBG_871X_SEL_NL(sel,"\trx_ofdm_pwr:%d(dBm),rx_ofdm_snr:%d(dB)\n",
1760                         psample_pkt_rssi->ofdm_pwr[rf_path],psample_pkt_rssi->ofdm_snr[rf_path]);
1761                 }
1762         }
1763 }
1764
1765 void rtw_dump_raw_rssi_info(_adapter *padapter)
1766 {
1767         u8 isCCKrate,rf_path;
1768         PHAL_DATA_TYPE  pHalData =  GET_HAL_DATA(padapter);
1769         struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
1770         DBG_871X("============ RAW Rx Info dump ===================\n");
1771         DBG_871X("RxRate = %s, PWDBALL = %d(%%), rx_pwr_all = %d(dBm)\n",
1772                         HDATA_RATE(psample_pkt_rssi->data_rate), psample_pkt_rssi->pwdball, psample_pkt_rssi->pwr_all);
1773
1774         isCCKrate = (psample_pkt_rssi->data_rate <= DESC_RATE11M)?TRUE :FALSE;
1775
1776         if(isCCKrate)
1777                 psample_pkt_rssi->mimo_singal_strength[0] = psample_pkt_rssi->pwdball;
1778
1779         for(rf_path = 0;rf_path<pHalData->NumTotalRFPath;rf_path++)
1780         {
1781                 DBG_871X("RF_PATH_%d=>singal_strength:%d(%%),singal_quality:%d(%%)"
1782                         ,rf_path,psample_pkt_rssi->mimo_singal_strength[rf_path],psample_pkt_rssi->mimo_singal_quality[rf_path]);
1783
1784                 if(!isCCKrate){
1785                         printk(",rx_ofdm_pwr:%d(dBm),rx_ofdm_snr:%d(dB)\n",
1786                         psample_pkt_rssi->ofdm_pwr[rf_path],psample_pkt_rssi->ofdm_snr[rf_path]);
1787                 }else{
1788                         printk("\n");
1789                 }
1790         }
1791 }
1792
1793 void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe)
1794 {
1795         u8 isCCKrate,rf_path;
1796         PHAL_DATA_TYPE  pHalData =  GET_HAL_DATA(padapter);
1797         struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
1798
1799         PODM_PHY_INFO_T pPhyInfo  = (PODM_PHY_INFO_T)(&pattrib->phy_info);
1800         struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
1801
1802         psample_pkt_rssi->data_rate = pattrib->data_rate;
1803         isCCKrate = (pattrib->data_rate <= DESC_RATE11M)?TRUE :FALSE;
1804
1805         psample_pkt_rssi->pwdball = pPhyInfo->RxPWDBAll;
1806         psample_pkt_rssi->pwr_all = pPhyInfo->RecvSignalPower;
1807
1808         for(rf_path = 0;rf_path<pHalData->NumTotalRFPath;rf_path++)
1809         {
1810                 psample_pkt_rssi->mimo_singal_strength[rf_path] = pPhyInfo->RxMIMOSignalStrength[rf_path];
1811                 psample_pkt_rssi->mimo_singal_quality[rf_path] = pPhyInfo->RxMIMOSignalQuality[rf_path];
1812                 if(!isCCKrate){
1813                         psample_pkt_rssi->ofdm_pwr[rf_path] = pPhyInfo->RxPwr[rf_path];
1814                         psample_pkt_rssi->ofdm_snr[rf_path] = pPhyInfo->RxSNR[rf_path];
1815                 }
1816         }
1817 }
1818 #endif
1819
1820 #ifdef CONFIG_EFUSE_CONFIG_FILE
1821 int check_phy_efuse_tx_power_info_valid(PADAPTER padapter) {
1822         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1823         u8* pContent = pEEPROM->efuse_eeprom_data;
1824         int index = 0;
1825         u16 tx_index_offset = 0x0000;
1826
1827         switch(padapter->chip_type) {
1828                 case RTL8723B:
1829                         tx_index_offset = EEPROM_TX_PWR_INX_8723B;
1830                 break;
1831                 case RTL8188E:
1832                         tx_index_offset = EEPROM_TX_PWR_INX_88E;
1833                 break;
1834                 case RTL8192E:
1835                         tx_index_offset = EEPROM_TX_PWR_INX_8192E;
1836                 break;
1837                 default:
1838                         tx_index_offset = 0x0010;
1839                 break;
1840         }
1841         for (index = 0 ; index < 12 ; index++) {
1842                 if (pContent[tx_index_offset + index] == 0xFF) {
1843                         return _FALSE;
1844                 } else {
1845                         DBG_871X("0x%02x ,", pContent[EEPROM_TX_PWR_INX_88E+index]);
1846                 }
1847         }
1848         DBG_871X("\n");
1849         return _TRUE;
1850 }
1851
1852 int check_phy_efuse_macaddr_info_valid(PADAPTER padapter) {
1853
1854         u8 val = 0;
1855         u16 addr_offset = 0x0000;
1856
1857         switch(padapter->chip_type) {
1858                 case RTL8723B:
1859                         if (padapter->interface_type == RTW_USB) {
1860                                 addr_offset = EEPROM_MAC_ADDR_8723BU;
1861                                 DBG_871X("%s: interface is USB\n", __func__);
1862                         } else if (padapter->interface_type == RTW_SDIO) {
1863                                 addr_offset = EEPROM_MAC_ADDR_8723BS;
1864                                 DBG_871X("%s: interface is SDIO\n", __func__);
1865                         } else if (padapter->interface_type == RTW_PCIE) {
1866                                 addr_offset = EEPROM_MAC_ADDR_8723BE;
1867                                 DBG_871X("%s: interface is PCIE\n", __func__);
1868                         } else if (padapter->interface_type == RTW_GSPI) {
1869                                 //addr_offset = EEPROM_MAC_ADDR_8723BS;
1870                                 DBG_871X("%s: interface is GSPI\n", __func__);
1871                         }
1872                 break;
1873                 case RTL8188E:
1874                         if (padapter->interface_type == RTW_USB) {
1875                                 addr_offset = EEPROM_MAC_ADDR_88EU;
1876                                 DBG_871X("%s: interface is USB\n", __func__);
1877                         } else if (padapter->interface_type == RTW_SDIO) {
1878                                 addr_offset = EEPROM_MAC_ADDR_88ES;
1879                                 DBG_871X("%s: interface is SDIO\n", __func__);
1880                         } else if (padapter->interface_type == RTW_PCIE) {
1881                                 addr_offset = EEPROM_MAC_ADDR_88EE;
1882                                 DBG_871X("%s: interface is PCIE\n", __func__);
1883                         } else if (padapter->interface_type == RTW_GSPI) {
1884                                 //addr_offset = EEPROM_MAC_ADDR_8723BS;
1885                                 DBG_871X("%s: interface is GSPI\n", __func__);
1886                         }
1887                 break;
1888         }
1889
1890         if (addr_offset == 0x0000) {
1891                 DBG_871X("phy efuse MAC addr offset is 0!!\n");
1892                 return _FALSE;
1893         } else {
1894                 rtw_efuse_map_read(padapter, addr_offset, 1, &val);
1895         }
1896
1897         if (val == 0xFF) {
1898                 return _FALSE;
1899         } else {
1900                 DBG_871X("phy efuse with valid MAC addr\n");
1901                 return _TRUE;
1902         }
1903 }
1904
1905 u32 Hal_readPGDataFromConfigFile(
1906         PADAPTER        padapter,
1907         struct file *fp)
1908 {
1909         u32 i;
1910         mm_segment_t fs;
1911         u8 temp[3];
1912         loff_t pos = 0;
1913         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1914         u8      *PROMContent = pEEPROM->efuse_eeprom_data;
1915
1916         temp[2] = 0; // add end of string '\0'
1917
1918         fs = get_fs();
1919         set_fs(KERNEL_DS);
1920
1921         for (i = 0 ; i < HWSET_MAX_SIZE ; i++) {
1922                 vfs_read(fp, temp, 2, &pos);
1923                 PROMContent[i] = simple_strtoul(temp, NULL, 16);
1924                 if ((i % EFUSE_FILE_COLUMN_NUM) == (EFUSE_FILE_COLUMN_NUM - 1)) {
1925                         //Filter the lates space char.
1926                         vfs_read(fp, temp, 1, &pos);
1927                         if (strchr(temp, ' ') == NULL) {
1928                                 pos--;
1929                                 vfs_read(fp, temp, 2, &pos);
1930                         }
1931                 } else {
1932                         pos += 1; // Filter the space character
1933                 }
1934         }
1935
1936         set_fs(fs);
1937         pEEPROM->bloadfile_fail_flag = _FALSE;
1938
1939 #ifdef CONFIG_DEBUG
1940         DBG_871X("Efuse configure file:\n");
1941         for (i=0; i<HWSET_MAX_SIZE; i++)
1942         {
1943                 if (i % 16 == 0)
1944                         printk("\n");
1945
1946                 printk("%02X ", PROMContent[i]);
1947         }
1948         printk("\n");
1949 #endif
1950
1951         return _SUCCESS;
1952 }
1953
1954 void Hal_ReadMACAddrFromFile(
1955         PADAPTER                padapter,
1956         struct file *fp)
1957 {
1958         u32 i;
1959         mm_segment_t fs;
1960         u8 source_addr[18];
1961         loff_t pos = 0;
1962         u32     curtime = rtw_get_current_time();
1963         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1964         u8 *head, *end;
1965
1966         _rtw_memset(source_addr, 0, 18);
1967         _rtw_memset(pEEPROM->mac_addr, 0, ETH_ALEN);
1968
1969         fs = get_fs();
1970         set_fs(KERNEL_DS);
1971
1972         DBG_871X("wifi mac address:\n");
1973         vfs_read(fp, source_addr, 18, &pos);
1974         source_addr[17] = ':';
1975
1976         head = end = source_addr;
1977         for (i=0; i<ETH_ALEN; i++) {
1978                 while (end && (*end != ':') )
1979                         end++;
1980
1981                 if (end && (*end == ':') )
1982                         *end = '\0';
1983
1984                 pEEPROM->mac_addr[i] = simple_strtoul(head, NULL, 16 );
1985
1986                 if (end) {
1987                         end++;
1988                         head = end;
1989                 }
1990         }
1991
1992         set_fs(fs);
1993         pEEPROM->bloadmac_fail_flag = _FALSE;
1994
1995         if (rtw_check_invalid_mac_address(pEEPROM->mac_addr) == _TRUE) {
1996 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,33))
1997                 get_random_bytes(pEEPROM->mac_addr, ETH_ALEN);
1998                 pEEPROM->mac_addr[0] = 0x00;
1999                 pEEPROM->mac_addr[1] = 0xe0;
2000                 pEEPROM->mac_addr[2] = 0x4c;
2001 #else
2002                 pEEPROM->mac_addr[0] = 0x00;
2003                 pEEPROM->mac_addr[1] = 0xe0;
2004                 pEEPROM->mac_addr[2] = 0x4c;
2005                 pEEPROM->mac_addr[3] = (u8)(curtime & 0xff) ;
2006                 pEEPROM->mac_addr[4] = (u8)((curtime>>8) & 0xff) ;
2007                 pEEPROM->mac_addr[5] = (u8)((curtime>>16) & 0xff) ;
2008 #endif
2009                 DBG_871X("MAC Address from wifimac error is invalid, assign random MAC !!!\n");
2010         }
2011
2012         DBG_871X("%s: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
2013                         __func__, pEEPROM->mac_addr[0], pEEPROM->mac_addr[1],
2014                         pEEPROM->mac_addr[2], pEEPROM->mac_addr[3],
2015                         pEEPROM->mac_addr[4], pEEPROM->mac_addr[5]);
2016 }
2017
2018 void Hal_GetPhyEfuseMACAddr(PADAPTER padapter, u8* mac_addr) {
2019         int i = 0;
2020         u16 addr_offset = 0x0000;
2021
2022         switch(padapter->chip_type) {
2023                 case RTL8723B:
2024                         if (padapter->interface_type == RTW_USB) {
2025                                 addr_offset = EEPROM_MAC_ADDR_8723BU;
2026                                 DBG_871X("%s: interface is USB\n", __func__);
2027                         } else if (padapter->interface_type == RTW_SDIO) {
2028                                 addr_offset = EEPROM_MAC_ADDR_8723BS;
2029                                 DBG_871X("%s: interface is SDIO\n", __func__);
2030                         } else if (padapter->interface_type == RTW_PCIE) {
2031                                 addr_offset = EEPROM_MAC_ADDR_8723BE;
2032                                 DBG_871X("%s: interface is PCIE\n", __func__);
2033                         } else if (padapter->interface_type == RTW_GSPI){
2034                                 //addr_offset = EEPROM_MAC_ADDR_8723BS;
2035                                 DBG_871X("%s: interface is GSPI\n", __func__);
2036                         }
2037                 break;
2038                 case RTL8188E:
2039                         if (padapter->interface_type == RTW_USB) {
2040                                 addr_offset = EEPROM_MAC_ADDR_88EU;
2041                                 DBG_871X("%s: interface is USB\n", __func__);
2042                         } else if (padapter->interface_type == RTW_SDIO) {
2043                                 addr_offset = EEPROM_MAC_ADDR_88ES;
2044                                 DBG_871X("%s: interface is SDIO\n", __func__);
2045                         } else if (padapter->interface_type == RTW_PCIE) {
2046                                 addr_offset = EEPROM_MAC_ADDR_88EE;
2047                                 DBG_871X("%s: interface is PCIE\n", __func__);
2048                         } else if (padapter->interface_type == RTW_GSPI){
2049                                 //addr_offset = EEPROM_MAC_ADDR_8723BS;
2050                                 DBG_871X("%s: interface is GSPI\n", __func__);
2051                         }
2052                 break;
2053         }
2054
2055         rtw_efuse_map_read(padapter, addr_offset, ETH_ALEN, mac_addr);
2056
2057         if (rtw_check_invalid_mac_address(mac_addr) == _TRUE) {
2058 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,33))
2059                 get_random_bytes(mac_addr, ETH_ALEN);
2060                 mac_addr[0] = 0x00;
2061                 mac_addr[1] = 0xe0;
2062                 mac_addr[2] = 0x4c;
2063 #else
2064                 mac_addr[0] = 0x00;
2065                 mac_addr[1] = 0xe0;
2066                 mac_addr[2] = 0x4c;
2067                 mac_addr[3] = (u8)(curtime & 0xff) ;
2068                 mac_addr[4] = (u8)((curtime>>8) & 0xff) ;
2069                 mac_addr[5] = (u8)((curtime>>16) & 0xff) ;
2070 #endif
2071                 DBG_871X("MAC Address from phy efuse error, assign random MAC !!!\n");
2072         }
2073
2074         DBG_871X("%s: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
2075                         __func__, mac_addr[0], mac_addr[1], mac_addr[2],
2076                         mac_addr[3], mac_addr[4], mac_addr[5]);
2077 }
2078 #endif //CONFIG_EFUSE_CONFIG_FILE
2079
2080 #ifdef CONFIG_RF_GAIN_OFFSET
2081 u32 Array_kfreemap[] = {
2082 0x08,0xe,
2083 0x06,0xc,
2084 0x04,0xa,
2085 0x02,0x8,
2086 0x00,0x6,
2087 0x03,0x4,
2088 0x05,0x2,
2089 0x07,0x0,
2090 0x09,0x0,
2091 0x0c,0x0,
2092 };
2093
2094 void rtw_bb_rf_gain_offset(_adapter *padapter)
2095 {
2096         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);
2097         u8              value = padapter->eeprompriv.EEPROMRFGainOffset;
2098         u8              tmp = 0x3e;
2099         u32     res,i=0;
2100         u4Byte     ArrayLen    = sizeof(Array_kfreemap)/sizeof(u32);
2101         pu4Byte    Array           = Array_kfreemap;
2102         u4Byte v1=0,v2=0,GainValue,target=0;
2103         //DBG_871X("+%s value: 0x%02x+\n", __func__, value);
2104 #if defined(CONFIG_RTL8723A)
2105         if (value & BIT0) {
2106                 DBG_871X("Offset RF Gain.\n");
2107                 DBG_871X("Offset RF Gain.  padapter->eeprompriv.EEPROMRFGainVal=0x%x\n",padapter->eeprompriv.EEPROMRFGainVal);
2108                 if(padapter->eeprompriv.EEPROMRFGainVal != 0xff){
2109                         res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0xd, 0xffffffff);
2110                         DBG_871X("Offset RF Gain. reg 0xd=0x%x\n",res);
2111                         res &= 0xfff87fff;
2112
2113                         res |= (padapter->eeprompriv.EEPROMRFGainVal & 0x0f)<< 15;
2114                         DBG_871X("Offset RF Gain.        reg 0xd=0x%x\n",res);
2115
2116                         rtw_hal_write_rfreg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET_CCK, RF_GAIN_OFFSET_MASK, res);
2117
2118                         res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0xe, 0xffffffff);
2119                         DBG_871X("Offset RF Gain. reg 0xe=0x%x\n",res);
2120                         res &= 0xfffffff0;
2121
2122                         res |= (padapter->eeprompriv.EEPROMRFGainVal & 0x0f);
2123                         DBG_871X("Offset RF Gain.        reg 0xe=0x%x\n",res);
2124
2125                         rtw_hal_write_rfreg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET_OFDM, RF_GAIN_OFFSET_MASK, res);
2126                 }
2127                 else
2128                 {
2129                         DBG_871X("Offset RF Gain.  padapter->eeprompriv.EEPROMRFGainVal=0x%x    != 0xff, didn't run Kfree\n",padapter->eeprompriv.EEPROMRFGainVal);
2130                 }
2131         } else {
2132                 DBG_871X("Using the default RF gain.\n");
2133         }
2134 #elif defined(CONFIG_RTL8723B)
2135         if (value & BIT4) {
2136                 DBG_871X("Offset RF Gain.\n");
2137                 DBG_871X("Offset RF Gain.  padapter->eeprompriv.EEPROMRFGainVal=0x%x\n",padapter->eeprompriv.EEPROMRFGainVal);
2138
2139                 if(padapter->eeprompriv.EEPROMRFGainVal != 0xff){
2140                         if (pHalData->ant_path == ODM_RF_PATH_A)
2141                                 GainValue=(padapter->eeprompriv.EEPROMRFGainVal & 0x0f);
2142                         else
2143                                 GainValue=(padapter->eeprompriv.EEPROMRFGainVal & 0xf0)>>4;
2144                         DBG_871X("Ant PATH_%d GainValue Offset = 0x%x\n",(pHalData->ant_path == ODM_RF_PATH_A) ? (ODM_RF_PATH_A) : (ODM_RF_PATH_B),GainValue);
2145
2146                         for (i = 0; i < ArrayLen; i += 2 )
2147                         {
2148                                 v1 = Array[i];
2149                                 v2 = Array[i+1];
2150                                 if ( v1 == GainValue ) {
2151                                                 DBG_871X("Offset RF Gain. got v1 =0x%x ,v2 =0x%x \n",v1,v2);
2152                                                 target=v2;
2153                                                 break;
2154                                  }
2155                         }
2156                         DBG_871X("padapter->eeprompriv.EEPROMRFGainVal=0x%x ,Gain offset Target Value=0x%x\n",padapter->eeprompriv.EEPROMRFGainVal,target);
2157
2158                         res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff);
2159                         DBG_871X("Offset RF Gain. before reg 0x7f=0x%08x\n",res);
2160                         PHY_SetRFReg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, BIT18|BIT17|BIT16|BIT15, target);
2161                         res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff);
2162
2163                         DBG_871X("Offset RF Gain. After reg 0x7f=0x%08x\n",res);
2164
2165                 } else {
2166
2167                         DBG_871X("Offset RF Gain.  padapter->eeprompriv.EEPROMRFGainVal=0x%x    != 0xff, didn't run Kfree\n",padapter->eeprompriv.EEPROMRFGainVal);
2168                 }
2169         } else {
2170                 DBG_871X("Using the default RF gain.\n");
2171         }
2172
2173 #elif defined(CONFIG_RTL8188E)
2174         if (value & BIT4) {
2175                 DBG_871X("8188ES Offset RF Gain.\n");
2176                 DBG_871X("8188ES Offset RF Gain. EEPROMRFGainVal=0x%x\n",
2177                                 padapter->eeprompriv.EEPROMRFGainVal);
2178
2179                 if (padapter->eeprompriv.EEPROMRFGainVal != 0xff) {
2180                         res = rtw_hal_read_rfreg(padapter, RF_PATH_A,
2181                                         REG_RF_BB_GAIN_OFFSET, 0xffffffff);
2182
2183                         DBG_871X("Offset RF Gain. reg 0x55=0x%x\n",res);
2184                         res &= 0xfff87fff;
2185
2186                         res |= (padapter->eeprompriv.EEPROMRFGainVal & 0x0f) << 15;
2187                         DBG_871X("Offset RF Gain. res=0x%x\n",res);
2188
2189                         rtw_hal_write_rfreg(padapter, RF_PATH_A,
2190                                         REG_RF_BB_GAIN_OFFSET,
2191                                         RF_GAIN_OFFSET_MASK, res);
2192                 } else {
2193                         DBG_871X("Offset RF Gain. EEPROMRFGainVal=0x%x == 0xff, didn't run Kfree\n",
2194                                         padapter->eeprompriv.EEPROMRFGainVal);
2195                 }
2196         } else {
2197                 DBG_871X("Using the default RF gain.\n");
2198         }
2199 #else
2200         if (!(value & 0x01)) {
2201                 //DBG_871X("Offset RF Gain.\n");
2202                 res = rtw_hal_read_rfreg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, 0xffffffff);
2203                 value &= tmp;
2204                 res = value << 14;
2205                 rtw_hal_write_rfreg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, RF_GAIN_OFFSET_MASK, res);
2206         } else {
2207                 DBG_871X("Using the default RF gain.\n");
2208         }
2209 #endif
2210
2211 }
2212 #endif //CONFIG_RF_GAIN_OFFSET
2213
2214 //To avoid RX affect TX throughput
2215 void dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer)
2216 {
2217         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
2218         struct mlme_priv                *pmlmepriv = &(padapter->mlmepriv);
2219         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);
2220 #ifdef CONFIG_USB_RX_AGGREGATION
2221         if(IS_HARDWARE_TYPE_8821U(padapter) )//|| IS_HARDWARE_TYPE_8192EU(padapter))
2222         {
2223                 //This AGG_PH_TH only for UsbRxAggMode == USB_RX_AGG_USB
2224                 if((pHalData->UsbRxAggMode == USB_RX_AGG_USB) && (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE))
2225                 {
2226                         if(pdvobjpriv->traffic_stat.cur_tx_tp > 2 && pdvobjpriv->traffic_stat.cur_rx_tp < 30)
2227                                 rtw_write16(padapter, REG_RXDMA_AGG_PG_TH,0x1010);
2228                         else
2229                                 rtw_write16(padapter, REG_RXDMA_AGG_PG_TH,0x2005); //dmc agg th 20K
2230
2231                         //DBG_871X("TX_TP=%u, RX_TP=%u \n", pdvobjpriv->traffic_stat.cur_tx_tp, pdvobjpriv->traffic_stat.cur_rx_tp);
2232                 }
2233         }
2234 #endif
2235 }
2236