1 /******************************************************************************
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3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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5 * This program is free software; you can redistribute it and/or modify it
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6 * under the terms of version 2 of the GNU General Public License as
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7 * published by the Free Software Foundation.
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9 * This program is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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14 * You should have received a copy of the GNU General Public License along with
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15 * this program; if not, write to the Free Software Foundation, Inc.,
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16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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19 ******************************************************************************/
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21 //============================================================
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23 //============================================================
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25 #include "odm_precomp.h"
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29 ODM_InitDebugSetting(
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30 IN PDM_ODM_T pDM_Odm
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33 pDM_Odm->DebugLevel = ODM_DBG_LOUD;
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35 pDM_Odm->DebugComponents =
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40 // ODM_COMP_RA_MASK |
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41 // ODM_COMP_DYNAMIC_TXPWR |
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42 // ODM_COMP_FA_CNT |
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43 // ODM_COMP_RSSI_MONITOR |
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44 // ODM_COMP_CCK_PD |
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45 // ODM_COMP_ANT_DIV |
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46 // ODM_COMP_PWR_SAVE |
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47 // ODM_COMP_PWR_TRAIN |
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48 // ODM_COMP_RATE_ADAPTIVE |
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49 // ODM_COMP_PATH_DIV |
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50 // ODM_COMP_DYNAMIC_PRICCA |
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53 // ODM_COMP_CFO_TRACKING |
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56 // ODM_COMP_EDCA_TURBO |
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57 // ODM_COMP_EARLY_MODE |
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59 // ODM_COMP_TX_PWR_TRACK |
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60 // ODM_COMP_RX_GAIN_TRACK |
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61 // ODM_COMP_CALIBRATION |
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63 // ODM_COMP_COMMON |
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71 /*------------------Declare variable-----------------------
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72 // Define debug flag array for common debug print macro. */
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73 u4Byte ODM_DBGP_Type[ODM_DBGP_TYPE_MAX];
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75 /* Define debug print header for every service module. */
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76 ODM_DBGP_HEAD_T ODM_DBGP_Head;
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79 /*-----------------------------------------------------------------------------
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80 * Function: DBGP_Flag_Init
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82 * Overview: Refresh all debug print control flag content to zero.
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92 * 10/20/2006 MHC Create Version 0.
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94 *---------------------------------------------------------------------------*/
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95 extern void ODM_DBGP_Flag_Init(void)
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99 for (i = 0; i < ODM_DBGP_TYPE_MAX; i++)
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101 ODM_DBGP_Type[i] = 0;
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104 #ifndef ADSL_AP_BUILD_WORKAROUND
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106 // 2010/06/02 MH Free build driver can not out any debug message!!!
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107 // Init Debug flag enable condition
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109 ODM_DBGP_Type[FINIT] = \
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116 ODM_DBGP_Type[FDM] = \
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125 ODM_DBGP_Type[FIOCTL] = \
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127 // IOCTL_IRP_DETAIL |
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128 // IOCTL_IRP_STATISTICS |
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129 // IOCTL_IRP_HANDLE |
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130 // IOCTL_BT_HCICMD |
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131 // IOCTL_BT_HCICMD_DETAIL |
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132 // IOCTL_BT_HCICMD_EXT |
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133 // IOCTL_BT_EVENT |
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134 // IOCTL_BT_EVENT_DETAIL |
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135 // IOCTL_BT_EVENT_PERIODICAL |
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136 // IOCTL_BT_TX_ACLDATA |
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137 // IOCTL_BT_TX_ACLDATA_DETAIL |
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138 // IOCTL_BT_RX_ACLDATA |
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139 // IOCTL_BT_RX_ACLDATA_DETAIL |
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143 // IOCTL_CALLBACK_FUN |
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144 // IOCTL_PARSE_BT_PKT |
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147 ODM_DBGP_Type[FBT] = \
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151 ODM_DBGP_Type[FEEPROM] = \
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154 // EFUSE_READ_ALL |
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155 // EFUSE_ANALYSIS |
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156 // EFUSE_PG_DETAIL |
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159 ODM_DBGP_Type[FDBG_CTRL] = \
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160 // DBG_CTRL_TRACE |
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161 // DBG_CTRL_INBAND_NOISE |
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164 // 2011/07/20 MH Add for short cut
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165 ODM_DBGP_Type[FSHORT_CUT] = \
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172 /* Define debug header of every service module. */
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173 //ODM_DBGP_Head.pMANS = "\n\r[MANS] ";
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174 //ODM_DBGP_Head.pRTOS = "\n\r[RTOS] ";
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175 //ODM_DBGP_Head.pALM = "\n\r[ALM] ";
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176 //ODM_DBGP_Head.pPEM = "\n\r[PEM] ";
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177 //ODM_DBGP_Head.pCMPK = "\n\r[CMPK] ";
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178 //ODM_DBGP_Head.pRAPD = "\n\r[RAPD] ";
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179 //ODM_DBGP_Head.pTXPB = "\n\r[TXPB] ";
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180 //ODM_DBGP_Head.pQUMG = "\n\r[QUMG] ";
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182 } /* DBGP_Flag_Init */
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188 u4Byte GlobalDebugLevel = DBG_LOUD;
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190 // 2009/06/22 MH Allow Fre build to print none debug info at init time.
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193 u8Byte GlobalDebugComponents = \
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197 // COMP_OID_QUERY |
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210 // COMP_AUTHENTICATOR |
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228 // COMP_DUALMACSWITCH |
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229 // COMP_EASY_CONCURRENT |
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231 //1!!!!!!!!!!!!!!!!!!!!!!!!!!!
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232 //1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
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233 //1!!!!!!!!!!!!!!!!!!!!!!!!!!!
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236 // COMP_POWER_TRACKING |
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237 // COMP_RX_REORDER |
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244 // COMP_MESH_INTERWORKING |
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249 // COMP_BB_POWERSAVING |
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261 u8Byte GlobalDebugComponents = 0;
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264 #if (RT_PLATFORM==PLATFORM_LINUX)
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265 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
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266 EXPORT_SYMBOL(GlobalDebugComponents);
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267 EXPORT_SYMBOL(GlobalDebugLevel);
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271 /*------------------Declare variable-----------------------
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272 // Define debug flag array for common debug print macro. */
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273 u4Byte DBGP_Type[DBGP_TYPE_MAX];
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275 /* Define debug print header for every service module. */
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276 DBGP_HEAD_T DBGP_Head;
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279 /*-----------------------------------------------------------------------------
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280 * Function: DBGP_Flag_Init
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282 * Overview: Refresh all debug print control flag content to zero.
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292 * 10/20/2006 MHC Create Version 0.
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294 *---------------------------------------------------------------------------*/
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295 extern void DBGP_Flag_Init(void)
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299 for (i = 0; i < DBGP_TYPE_MAX; i++)
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305 // 2010/06/02 MH Free build driver can not out any debug message!!!
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306 // Init Debug flag enable condition
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308 DBGP_Type[FINIT] = \
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324 DBGP_Type[FIOCTL] = \
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326 // IOCTL_IRP_DETAIL |
\r
327 // IOCTL_IRP_STATISTICS |
\r
328 // IOCTL_IRP_HANDLE |
\r
329 // IOCTL_BT_HCICMD |
\r
330 // IOCTL_BT_HCICMD_DETAIL |
\r
331 // IOCTL_BT_HCICMD_EXT |
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332 // IOCTL_BT_EVENT |
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333 // IOCTL_BT_EVENT_DETAIL |
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334 // IOCTL_BT_EVENT_PERIODICAL |
\r
335 // IOCTL_BT_TX_ACLDATA |
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336 // IOCTL_BT_TX_ACLDATA_DETAIL |
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337 // IOCTL_BT_RX_ACLDATA |
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338 // IOCTL_BT_RX_ACLDATA_DETAIL |
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342 // IOCTL_CALLBACK_FUN |
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343 // IOCTL_PARSE_BT_PKT |
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350 DBGP_Type[FEEPROM] = \
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353 // EFUSE_READ_ALL |
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354 // EFUSE_ANALYSIS |
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355 // EFUSE_PG_DETAIL |
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358 DBGP_Type[FDBG_CTRL] = \
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359 // DBG_CTRL_TRACE |
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360 // DBG_CTRL_INBAND_NOISE |
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363 // 2011/07/20 MH Add for short cut
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364 DBGP_Type[FSHORT_CUT] = \
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370 /* Define debug header of every service module. */
\r
371 DBGP_Head.pMANS = "\n\r[MANS] ";
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372 DBGP_Head.pRTOS = "\n\r[RTOS] ";
\r
373 DBGP_Head.pALM = "\n\r[ALM] ";
\r
374 DBGP_Head.pPEM = "\n\r[PEM] ";
\r
375 DBGP_Head.pCMPK = "\n\r[CMPK] ";
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376 DBGP_Head.pRAPD = "\n\r[RAPD] ";
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377 DBGP_Head.pTXPB = "\n\r[TXPB] ";
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378 DBGP_Head.pQUMG = "\n\r[QUMG] ";
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380 } /* DBGP_Flag_Init */
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383 /*-----------------------------------------------------------------------------
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384 * Function: DBG_PrintAllFlag
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386 * Overview: Print All debug flag
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396 * 12/10/2008 MHC Create Version 0.
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398 *---------------------------------------------------------------------------*/
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399 extern void DBG_PrintAllFlag(void)
\r
401 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 0 FQoS\n"));
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402 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 1 FTX\n"));
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403 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 2 FRX\n"));
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404 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 3 FSEC\n"));
\r
405 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 4 FMGNT\n"));
\r
406 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 5 FMLME\n"));
\r
407 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 6 FRESOURCE\n"));
\r
408 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 7 FBEACON\n"));
\r
409 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 8 FISR\n"));
\r
410 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 9 FPHY\n"));
\r
411 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 11 FMP\n"));
\r
412 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 12 FPWR\n"));
\r
413 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 13 FDM\n"));
\r
414 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 14 FDBG_CTRL\n"));
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415 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 15 FC2H\n"));
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416 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 16 FBT\n"));
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417 } // DBG_PrintAllFlag
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420 extern void DBG_PrintAllComp(void)
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424 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("GlobalDebugComponents Definition\n"));
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425 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT0 COMP_TRACE\n"));
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426 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT1 COMP_DBG\n"));
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427 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT2 COMP_INIT\n"));
\r
428 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT3 COMP_OID_QUERY\n"));
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429 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT4 COMP_OID_SET\n"));
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430 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT5 COMP_RECV\n"));
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431 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT6 COMP_SEND\n"));
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432 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT7 COMP_IO\n"));
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433 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT8 COMP_POWER\n"));
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434 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT9 COMP_MLME\n"));
\r
435 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT10 COMP_SCAN\n"));
\r
436 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT11 COMP_SYSTEM\n"));
\r
437 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT12 COMP_SEC\n"));
\r
438 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT13 COMP_AP\n"));
\r
439 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT14 COMP_TURBO\n"));
\r
440 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT15 COMP_QOS\n"));
\r
441 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT16 COMP_AUTHENTICATOR\n"));
\r
442 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT17 COMP_BEACON\n"));
\r
443 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT18 COMP_BEACON\n"));
\r
444 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT19 COMP_RATE\n"));
\r
445 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT20 COMP_EVENTS\n"));
\r
446 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT21 COMP_FPGA\n"));
\r
447 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT22 COMP_RM\n"));
\r
448 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT23 COMP_MP\n"));
\r
449 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT24 COMP_RXDESC\n"));
\r
450 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT25 COMP_CKIP\n"));
\r
451 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT26 COMP_DIG\n"));
\r
452 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT27 COMP_TXAGC\n"));
\r
453 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT28 COMP_HIPWR\n"));
\r
454 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT29 COMP_HALDM\n"));
\r
455 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT30 COMP_RSNA\n"));
\r
456 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT31 COMP_INDIC\n"));
\r
457 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT32 COMP_LED\n"));
\r
458 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT33 COMP_RF\n"));
\r
459 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT34 COMP_HT\n"));
\r
460 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT35 COMP_POWER_TRACKING\n"));
\r
461 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT36 COMP_POWER_TRACKING\n"));
\r
462 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT37 COMP_AMSDU\n"));
\r
463 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT38 COMP_WPS\n"));
\r
464 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT39 COMP_RATR\n"));
\r
465 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT40 COMP_RESET\n"));
\r
466 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT41 COMP_CMD\n"));
\r
467 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT42 COMP_EFUSE\n"));
\r
468 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT43 COMP_MESH_INTERWORKING\n"));
\r
469 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT43 COMP_CCX\n"));
\r
471 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("GlobalDebugComponents = %"i64fmt"x\n", GlobalDebugComponents));
\r
472 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("Enable DBG COMP ="));
\r
473 for (i = 0; i < 64; i++)
\r
475 if (GlobalDebugComponents & ((u8Byte)0x1 << i) )
\r
477 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT%02d |\n", i));
\r
480 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("\n"));
\r
482 } // DBG_PrintAllComp
\r
485 /*-----------------------------------------------------------------------------
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486 * Function: DBG_PrintFlagEvent
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488 * Overview: Print dedicated debug flag event
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498 * 12/10/2008 MHC Create Version 0.
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500 *---------------------------------------------------------------------------*/
\r
501 extern void DBG_PrintFlagEvent(u1Byte DbgFlag)
\r
506 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 QoS_INIT\n"));
\r
507 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 QoS_VISTA\n"));
\r
511 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 TX_DESC\n"));
\r
512 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 TX_DESC_TID\n"));
\r
516 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 RX_DATA\n"));
\r
517 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 RX_PHY_STS\n"));
\r
518 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 RX_PHY_SS\n"));
\r
519 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 3 RX_PHY_SQ\n"));
\r
520 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 4 RX_PHY_ASTS\n"));
\r
521 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 5 RX_ERR_LEN\n"));
\r
522 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 6 RX_DEFRAG\n"));
\r
523 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 7 RX_ERR_RATE\n"));
\r
527 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("NA\n"));
\r
531 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("NA\n"));
\r
535 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 MEDIA_STS\n"));
\r
536 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 LINK_STS\n"));
\r
540 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 OS_CHK\n"));
\r
544 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 BCN_SHOW\n"));
\r
545 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 BCN_PEER\n"));
\r
549 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 ISR_CHK\n"));
\r
553 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 PHY_BBR\n"));
\r
554 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 PHY_BBW\n"));
\r
555 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 PHY_RFR\n"));
\r
556 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 3 PHY_RFW\n"));
\r
557 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 4 PHY_MACR\n"));
\r
558 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 5 PHY_MACW\n"));
\r
559 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 6 PHY_ALLR\n"));
\r
560 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 7 PHY_ALLW\n"));
\r
561 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 8 PHY_TXPWR\n"));
\r
565 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 MP_RX\n"));
\r
569 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 EEPROM_W\n"));
\r
570 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 EFUSE_PG\n"));
\r
574 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 LPS\n"));
\r
575 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 IPS\n"));
\r
576 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 PWRSW\n"));
\r
577 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 3 PWRHW\n"));
\r
578 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 4 PWRHAL\n"));
\r
582 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 WA_IOT\n"));
\r
583 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 DM_PWDB\n"));
\r
584 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 DM_Monitor\n"));
\r
585 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 3 DM_DIG\n"));
\r
589 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 DBG_CTRL_TRACE\n"));
\r
590 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 DBG_CTRL_INBAND_NOISE\n"));
\r
594 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 C2H_Summary\n"));
\r
595 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 C2H_PacketData\n"));
\r
596 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 C2H_ContentData\n"));
\r
600 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 BT_TRACE\n"));
\r
601 ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 BT_RFPoll\n"));
\r
608 } // DBG_PrintFlagEvent
\r
611 extern void DBG_DumpMem(const u1Byte DbgComp,
\r
612 const u1Byte DbgLevel,
\r
618 for (i=0;i<((Len>>3) + 1);i++)
\r
620 ODM_RT_TRACE(pDM_Odm,DbgComp, DbgLevel, ("%02X %02X %02X %02X %02X %02X %02X %02X\n",
\r
621 *(pMem+(i*8)), *(pMem+(i*8+1)), *(pMem+(i*8+2)), *(pMem+(i*8+3)),
\r
622 *(pMem+(i*8+4)), *(pMem+(i*8+5)), *(pMem+(i*8+6)), *(pMem+(i*8+7))));
\r