1 /******************************************************************************
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3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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5 * This program is free software; you can redistribute it and/or modify it
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6 * under the terms of version 2 of the GNU General Public License as
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7 * published by the Free Software Foundation.
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9 * This program is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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14 * You should have received a copy of the GNU General Public License along with
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15 * this program; if not, write to the Free Software Foundation, Inc.,
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16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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18 *******************************************************************************/
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19 #ifndef __RTL8812A_SPEC_H__
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20 #define __RTL8812A_SPEC_H__
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22 #include <drv_conf.h>
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25 //============================================================
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26 // 8812 Regsiter offset definition
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27 //============================================================
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29 //============================================================
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31 //============================================================
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33 //-----------------------------------------------------
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35 // 0x0000h ~ 0x00FFh System Configuration
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37 //-----------------------------------------------------
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38 #define REG_HSIMR_8812 0x0058
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39 #define REG_HSISR_8812 0x005c
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40 #define REG_GPIO_EXT_CTRL 0x0060
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41 #define REG_GPIO_STATUS_8812 0x006C
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42 #define REG_SDIO_CTRL_8812 0x0070
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43 #define REG_OPT_CTRL_8812 0x0074
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44 #define REG_RF_B_CTRL_8812 0x0076
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45 #define REG_FW_DRV_MSG_8812 0x0088
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46 #define REG_HMEBOX_E2_E3_8812 0x008C
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47 #define REG_HIMR0_8812 0x00B0
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48 #define REG_HISR0_8812 0x00B4
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49 #define REG_HIMR1_8812 0x00B8
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50 #define REG_HISR1_8812 0x00BC
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51 #define REG_EFUSE_BURN_GNT_8812 0x00CF
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52 #define REG_SYS_CFG1_8812 0x00FC
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54 //-----------------------------------------------------
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56 // 0x0100h ~ 0x01FFh MACTOP General Configuration
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58 //-----------------------------------------------------
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59 #define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL)
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60 #define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+2)
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61 #define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+3)
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63 #define REG_RSVD3_8812 0x0168
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64 #define REG_C2HEVT_CMD_SEQ_88XX 0x01A1
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65 #define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2
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66 #define REG_C2HEVT_CMD_LEN_88XX 0x01AE
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68 #define REG_HMEBOX_EXT0_8812 0x01F0
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69 #define REG_HMEBOX_EXT1_8812 0x01F4
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70 #define REG_HMEBOX_EXT2_8812 0x01F8
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71 #define REG_HMEBOX_EXT3_8812 0x01FC
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73 //-----------------------------------------------------
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75 // 0x0200h ~ 0x027Fh TXDMA Configuration
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77 //-----------------------------------------------------
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78 #define REG_DWBCN0_CTRL_8812 REG_TDECTRL
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79 #define REG_DWBCN1_CTRL_8812 0x0228
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81 //-----------------------------------------------------
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83 // 0x0280h ~ 0x02FFh RXDMA Configuration
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85 //-----------------------------------------------------
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86 #define REG_RXDMA_CONTROL_8812 0x0286 // Control the RX DMA.
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87 #define REG_RXDMA_PRO_8812 0x0290
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88 #define REG_EARLY_MODE_CONTROL_8812 0x02BC
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89 #define REG_RSVD5_8812 0x02F0
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90 #define REG_RSVD6_8812 0x02F4
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91 #define REG_RSVD7_8812 0x02F8
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92 #define REG_RSVD8_8812 0x02FC
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95 //-----------------------------------------------------
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97 // 0x0300h ~ 0x03FFh PCIe
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99 //-----------------------------------------------------
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100 #define REG_DBI_WDATA_8812 0x0348 // DBI Write Data
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101 #define REG_DBI_RDATA_8812 0x034C // DBI Read Data
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102 #define REG_DBI_ADDR_8812 0x0350 // DBI Address
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103 #define REG_DBI_FLAG_8812 0x0352 // DBI Read/Write Flag
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104 #define REG_MDIO_WDATA_8812 0x0354 // MDIO for Write PCIE PHY
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105 #define REG_MDIO_RDATA_8812 0x0356 // MDIO for Reads PCIE PHY
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106 #define REG_MDIO_CTL_8812 0x0358 // MDIO for Control
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107 #define REG_PCIE_MULTIFET_CTRL_8812 0x036A //PCIE Multi-Fethc Control
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109 //-----------------------------------------------------
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111 // 0x0400h ~ 0x047Fh Protocol Configuration
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113 //-----------------------------------------------------
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114 #define REG_TXBF_CTRL_8812 0x042C
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115 #define REG_ARFR0_8812 0x0444
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116 #define REG_ARFR1_8812 0x044C
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117 #define REG_CCK_CHECK_8812 0x0454
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118 #define REG_AMPDU_MAX_TIME_8812 0x0456
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119 #define REG_TXPKTBUF_BCNQ_BDNY1_8812 0x0457
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121 #define REG_AMPDU_MAX_LENGTH_8812 0x0458
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122 #define REG_TXPKTBUF_WMAC_LBK_BF_HD_8812 0x045D
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123 #define REG_NDPA_OPT_CTRL_8812 0x045F
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124 #define REG_DATA_SC_8812 0x0483
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125 #define REG_ARFR2_8812 0x048C
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126 #define REG_ARFR3_8812 0x0494
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127 #define REG_TXRPT_START_OFFSET 0x04AC
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128 #define REG_AMPDU_BURST_MODE_8812 0x04BC
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129 #define REG_HT_SINGLE_AMPDU_8812 0x04C7
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130 #define REG_MACID_PKT_DROP0_8812 0x04D0
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132 //-----------------------------------------------------
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134 // 0x0500h ~ 0x05FFh EDCA Configuration
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136 //-----------------------------------------------------
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137 #define REG_CTWND_8812 0x0572
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138 #define REG_SECONDARY_CCA_CTRL_8812 0x0577
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139 #define REG_SCH_TXCMD_8812 0x05F8
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141 //-----------------------------------------------------
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143 // 0x0600h ~ 0x07FFh WMAC Configuration
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145 //-----------------------------------------------------
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146 #define REG_MAC_CR_8812 0x0600
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148 #define REG_MAC_TX_SM_STATE_8812 0x06B4
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151 #define REG_BFMER0_INFO_8812 0x06E4
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152 #define REG_BFMER1_INFO_8812 0x06EC
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153 #define REG_CSI_RPT_PARAM_BW20_8812 0x06F4
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154 #define REG_CSI_RPT_PARAM_BW40_8812 0x06F8
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155 #define REG_CSI_RPT_PARAM_BW80_8812 0x06FC
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158 #define REG_BFMEE_SEL_8812 0x0714
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159 #define REG_SND_PTCL_CTRL_8812 0x0718
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162 //-----------------------------------------------------
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164 // Redifine register definition for compatibility
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166 //-----------------------------------------------------
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168 // TODO: use these definition when using REG_xxx naming rule.
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169 // NOTE: DO NOT Remove these definition. Use later.
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170 #define ISR_8812 REG_HISR0_8812
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172 //----------------------------------------------------------------------------
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173 // 8195 IMR/ISR bits (offset 0xB0, 8bits)
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174 //----------------------------------------------------------------------------
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175 #define IMR_DISABLED_8812 0
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176 // IMR DW0(0x00B0-00B3) Bit 0-31
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177 #define IMR_TIMER2_8812 BIT31 // Timeout interrupt 2
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178 #define IMR_TIMER1_8812 BIT30 // Timeout interrupt 1
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179 #define IMR_PSTIMEOUT_8812 BIT29 // Power Save Time Out Interrupt
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180 #define IMR_GTINT4_8812 BIT28 // When GTIMER4 expires, this bit is set to 1
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181 #define IMR_GTINT3_8812 BIT27 // When GTIMER3 expires, this bit is set to 1
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182 #define IMR_TXBCN0ERR_8812 BIT26 // Transmit Beacon0 Error
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183 #define IMR_TXBCN0OK_8812 BIT25 // Transmit Beacon0 OK
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184 #define IMR_TSF_BIT32_TOGGLE_8812 BIT24 // TSF Timer BIT32 toggle indication interrupt
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185 #define IMR_BCNDMAINT0_8812 BIT20 // Beacon DMA Interrupt 0
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186 #define IMR_BCNDERR0_8812 BIT16 // Beacon Queue DMA OK0
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187 #define IMR_HSISR_IND_ON_INT_8812 BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1)
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188 #define IMR_BCNDMAINT_E_8812 BIT14 // Beacon DMA Interrupt Extension for Win7
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189 #define IMR_ATIMEND_8812 BIT12 // CTWidnow End or ATIM Window End
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190 #define IMR_C2HCMD_8812 BIT10 // CPU to Host Command INT Status, Write 1 clear
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191 #define IMR_CPWM2_8812 BIT9 // CPU power Mode exchange INT Status, Write 1 clear
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192 #define IMR_CPWM_8812 BIT8 // CPU power Mode exchange INT Status, Write 1 clear
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193 #define IMR_HIGHDOK_8812 BIT7 // High Queue DMA OK
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194 #define IMR_MGNTDOK_8812 BIT6 // Management Queue DMA OK
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195 #define IMR_BKDOK_8812 BIT5 // AC_BK DMA OK
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196 #define IMR_BEDOK_8812 BIT4 // AC_BE DMA OK
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197 #define IMR_VIDOK_8812 BIT3 // AC_VI DMA OK
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198 #define IMR_VODOK_8812 BIT2 // AC_VO DMA OK
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199 #define IMR_RDU_8812 BIT1 // Rx Descriptor Unavailable
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200 #define IMR_ROK_8812 BIT0 // Receive DMA OK
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202 // IMR DW1(0x00B4-00B7) Bit 0-31
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203 #define IMR_BCNDMAINT7_8812 BIT27 // Beacon DMA Interrupt 7
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204 #define IMR_BCNDMAINT6_8812 BIT26 // Beacon DMA Interrupt 6
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205 #define IMR_BCNDMAINT5_8812 BIT25 // Beacon DMA Interrupt 5
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206 #define IMR_BCNDMAINT4_8812 BIT24 // Beacon DMA Interrupt 4
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207 #define IMR_BCNDMAINT3_8812 BIT23 // Beacon DMA Interrupt 3
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208 #define IMR_BCNDMAINT2_8812 BIT22 // Beacon DMA Interrupt 2
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209 #define IMR_BCNDMAINT1_8812 BIT21 // Beacon DMA Interrupt 1
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210 #define IMR_BCNDOK7_8812 BIT20 // Beacon Queue DMA OK Interrup 7
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211 #define IMR_BCNDOK6_8812 BIT19 // Beacon Queue DMA OK Interrup 6
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212 #define IMR_BCNDOK5_8812 BIT18 // Beacon Queue DMA OK Interrup 5
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213 #define IMR_BCNDOK4_8812 BIT17 // Beacon Queue DMA OK Interrup 4
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214 #define IMR_BCNDOK3_8812 BIT16 // Beacon Queue DMA OK Interrup 3
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215 #define IMR_BCNDOK2_8812 BIT15 // Beacon Queue DMA OK Interrup 2
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216 #define IMR_BCNDOK1_8812 BIT14 // Beacon Queue DMA OK Interrup 1
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217 #define IMR_ATIMEND_E_8812 BIT13 // ATIM Window End Extension for Win7
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218 #define IMR_TXERR_8812 BIT11 // Tx Error Flag Interrupt Status, write 1 clear.
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219 #define IMR_RXERR_8812 BIT10 // Rx Error Flag INT Status, Write 1 clear
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220 #define IMR_TXFOVW_8812 BIT9 // Transmit FIFO Overflow
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221 #define IMR_RXFOVW_8812 BIT8 // Receive FIFO Overflow
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224 #ifdef CONFIG_PCI_HCI
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225 //#define IMR_RX_MASK (IMR_ROK_8812|IMR_RDU_8812|IMR_RXFOVW_8812)
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226 #define IMR_TX_MASK (IMR_VODOK_8812|IMR_VIDOK_8812|IMR_BEDOK_8812|IMR_BKDOK_8812|IMR_MGNTDOK_8812|IMR_HIGHDOK_8812)
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228 #define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8812 | IMR_TXBCN0OK_8812 | IMR_TXBCN0ERR_8812 | IMR_BCNDERR0_8812)
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230 #define RT_AC_INT_MASKS (IMR_VIDOK_8812 | IMR_VODOK_8812 | IMR_BEDOK_8812|IMR_BKDOK_8812)
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234 //============================================================================
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235 // Regsiter Bit and Content definition
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236 //============================================================================
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238 //2 ACMHWCTRL 0x05C0
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239 #define AcmHw_HwEn_8812 BIT(0)
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240 #define AcmHw_VoqEn_8812 BIT(1)
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241 #define AcmHw_ViqEn_8812 BIT(2)
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242 #define AcmHw_BeqEn_8812 BIT(3)
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243 #define AcmHw_VoqStatus_8812 BIT(5)
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244 #define AcmHw_ViqStatus_8812 BIT(6)
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245 #define AcmHw_BeqStatus_8812 BIT(7)
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247 #endif //__RTL8188E_SPEC_H__
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249 #ifdef CONFIG_RTL8821A
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250 #include "rtl8821a_spec.h"
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251 #endif // CONFIG_RTL8821A
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