1 /******************************************************************************
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3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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5 * This program is free software; you can redistribute it and/or modify it
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6 * under the terms of version 2 of the GNU General Public License as
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7 * published by the Free Software Foundation.
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9 * This program is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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14 * You should have received a copy of the GNU General Public License along with
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15 * this program; if not, write to the Free Software Foundation, Inc.,
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16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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18 *******************************************************************************/
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19 #ifndef __RTL8723B_SPEC_H__
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20 #define __RTL8723B_SPEC_H__
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22 #include <drv_conf.h>
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25 #define HAL_NAV_UPPER_UNIT_8723B 128 // micro-second
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27 //-----------------------------------------------------
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29 // 0x0000h ~ 0x00FFh System Configuration
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31 //-----------------------------------------------------
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32 #define REG_RSV_CTRL_8723B 0x001C // 3 Byte
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33 #define REG_BT_WIFI_ANTENNA_SWITCH_8723B 0x0038
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34 #define REG_HSISR_8723B 0x005c
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35 #define REG_PAD_CTRL1_8723B 0x0064
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36 #define REG_AFE_CTRL_4_8723B 0x0078
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37 #define REG_HMEBOX_DBG_0_8723B 0x0088
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38 #define REG_HMEBOX_DBG_1_8723B 0x008A
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39 #define REG_HMEBOX_DBG_2_8723B 0x008C
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40 #define REG_HMEBOX_DBG_3_8723B 0x008E
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41 #define REG_HIMR0_8723B 0x00B0
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42 #define REG_HISR0_8723B 0x00B4
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43 #define REG_HIMR1_8723B 0x00B8
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44 #define REG_HISR1_8723B 0x00BC
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45 #define REG_PMC_DBG_CTRL2_8723B 0x00CC
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47 //-----------------------------------------------------
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49 // 0x0100h ~ 0x01FFh MACTOP General Configuration
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51 //-----------------------------------------------------
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52 #define REG_C2HEVT_CMD_ID_8723B 0x01A0
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53 #define REG_C2HEVT_CMD_LEN_8723B 0x01AE
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54 #define REG_WOWLAN_WAKE_REASON 0x01C7
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55 #define REG_WOWLAN_GTK_DBG1 0x630
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56 #define REG_WOWLAN_GTK_DBG2 0x634
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58 #define REG_HMEBOX_EXT0_8723B 0x01F0
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59 #define REG_HMEBOX_EXT1_8723B 0x01F4
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60 #define REG_HMEBOX_EXT2_8723B 0x01F8
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61 #define REG_HMEBOX_EXT3_8723B 0x01FC
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63 //-----------------------------------------------------
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65 // 0x0200h ~ 0x027Fh TXDMA Configuration
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67 //-----------------------------------------------------
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69 //-----------------------------------------------------
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71 // 0x0280h ~ 0x02FFh RXDMA Configuration
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73 //-----------------------------------------------------
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74 #define REG_RXDMA_CONTROL_8723B 0x0286 // Control the RX DMA.
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75 #define REG_RXDMA_MODE_CTRL_8723B 0x0290
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77 //-----------------------------------------------------
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79 // 0x0300h ~ 0x03FFh PCIe
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81 //-----------------------------------------------------
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82 #define REG_PCIE_CTRL_REG_8723B 0x0300
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83 #define REG_INT_MIG_8723B 0x0304 // Interrupt Migration
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84 #define REG_BCNQ_DESA_8723B 0x0308 // TX Beacon Descriptor Address
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85 #define REG_HQ_DESA_8723B 0x0310 // TX High Queue Descriptor Address
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86 #define REG_MGQ_DESA_8723B 0x0318 // TX Manage Queue Descriptor Address
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87 #define REG_VOQ_DESA_8723B 0x0320 // TX VO Queue Descriptor Address
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88 #define REG_VIQ_DESA_8723B 0x0328 // TX VI Queue Descriptor Address
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89 #define REG_BEQ_DESA_8723B 0x0330 // TX BE Queue Descriptor Address
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90 #define REG_BKQ_DESA_8723B 0x0338 // TX BK Queue Descriptor Address
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91 #define REG_RX_DESA_8723B 0x0340 // RX Queue Descriptor Address
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92 #define REG_DBI_WDATA_8723B 0x0348 // DBI Write Data
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93 #define REG_DBI_RDATA_8723B 0x034C // DBI Read Data
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94 #define REG_DBI_ADDR_8723B 0x0350 // DBI Address
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95 #define REG_DBI_FLAG_8723B 0x0352 // DBI Read/Write Flag
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96 #define REG_MDIO_WDATA_8723B 0x0354 // MDIO for Write PCIE PHY
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97 #define REG_MDIO_RDATA_8723B 0x0356 // MDIO for Reads PCIE PHY
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98 #define REG_MDIO_CTL_8723B 0x0358 // MDIO for Control
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99 #define REG_DBG_SEL_8723B 0x0360 // Debug Selection Register
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100 #define REG_PCIE_HRPWM_8723B 0x0361 //PCIe RPWM
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101 #define REG_PCIE_HCPWM_8723B 0x0363 //PCIe CPWM
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102 #define REG_PCIE_MULTIFET_CTRL_8723B 0x036A //PCIE Multi-Fethc Control
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104 //-----------------------------------------------------
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106 // 0x0400h ~ 0x047Fh Protocol Configuration
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108 //-----------------------------------------------------
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109 #define REG_TXPKTBUF_BCNQ_BDNY_8723B 0x0424
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110 #define REG_TXPKTBUF_MGQ_BDNY_8723B 0x0425
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111 #define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B 0x045D
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112 #ifdef CONFIG_WOWLAN
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113 #define REG_TXPKTBUF_IV_LOW 0x0484
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114 #define REG_TXPKTBUF_IV_HIGH 0x0488
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116 #define REG_AMPDU_BURST_MODE_8723B 0x04BC
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118 //-----------------------------------------------------
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120 // 0x0500h ~ 0x05FFh EDCA Configuration
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122 //-----------------------------------------------------
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123 #define REG_SECONDARY_CCA_CTRL_8723B 0x0577
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125 //-----------------------------------------------------
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127 // 0x0600h ~ 0x07FFh WMAC Configuration
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129 //-----------------------------------------------------
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132 //============================================================
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133 // SDIO Bus Specification
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134 //============================================================
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136 //-----------------------------------------------------
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137 // SDIO CMD Address Mapping
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138 //-----------------------------------------------------
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140 //-----------------------------------------------------
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141 // I/O bus domain (Host)
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142 //-----------------------------------------------------
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144 //-----------------------------------------------------
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146 //-----------------------------------------------------
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147 #define SDIO_REG_HCPWM1_8723B 0x025 // HCI Current Power Mode 1
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150 //============================================================================
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151 // 8723 Regsiter Bit and Content definition
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152 //============================================================================
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155 // interrupt mask which needs to clear
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156 #define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\
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157 HSISR_SPS_OCP_INT |\
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162 //-----------------------------------------------------
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164 // 0x0100h ~ 0x01FFh MACTOP General Configuration
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166 //-----------------------------------------------------
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169 //-----------------------------------------------------
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171 // 0x0200h ~ 0x027Fh TXDMA Configuration
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173 //-----------------------------------------------------
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175 //-----------------------------------------------------
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177 // 0x0280h ~ 0x02FFh RXDMA Configuration
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179 //-----------------------------------------------------
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180 #define BIT_USB_RXDMA_AGG_EN BIT(31)
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181 #define RXDMA_AGG_MODE_EN BIT(1)
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183 #ifdef CONFIG_WOWLAN
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184 #define RXPKT_RELEASE_POLL BIT(16)
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185 #define RXDMA_IDLE BIT(17)
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186 #define RW_RELEASE_EN BIT(18)
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189 //-----------------------------------------------------
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191 // 0x0400h ~ 0x047Fh Protocol Configuration
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193 //-----------------------------------------------------
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195 //----------------------------------------------------------------------------
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196 // 8723B REG_CCK_CHECK (offset 0x454)
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197 //----------------------------------------------------------------------------
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198 #define BIT_BCN_PORT_SEL BIT5
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200 //-----------------------------------------------------
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202 // 0x0500h ~ 0x05FFh EDCA Configuration
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204 //-----------------------------------------------------
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206 //-----------------------------------------------------
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208 // 0x0600h ~ 0x07FFh WMAC Configuration
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210 //-----------------------------------------------------
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211 #ifdef CONFIG_RF_GAIN_OFFSET
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213 #ifdef CONFIG_RTL8723B
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214 #define EEPROM_RF_GAIN_OFFSET 0xC1
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217 #define EEPROM_RF_GAIN_VAL 0x1F6
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218 #endif //CONFIG_RF_GAIN_OFFSET
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221 //----------------------------------------------------------------------------
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222 // 8195 IMR/ISR bits (offset 0xB0, 8bits)
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223 //----------------------------------------------------------------------------
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224 #define IMR_DISABLED_8723B 0
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225 // IMR DW0(0x00B0-00B3) Bit 0-31
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226 #define IMR_TIMER2_8723B BIT31 // Timeout interrupt 2
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227 #define IMR_TIMER1_8723B BIT30 // Timeout interrupt 1
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228 #define IMR_PSTIMEOUT_8723B BIT29 // Power Save Time Out Interrupt
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229 #define IMR_GTINT4_8723B BIT28 // When GTIMER4 expires, this bit is set to 1
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230 #define IMR_GTINT3_8723B BIT27 // When GTIMER3 expires, this bit is set to 1
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231 #define IMR_TXBCN0ERR_8723B BIT26 // Transmit Beacon0 Error
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232 #define IMR_TXBCN0OK_8723B BIT25 // Transmit Beacon0 OK
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233 #define IMR_TSF_BIT32_TOGGLE_8723B BIT24 // TSF Timer BIT32 toggle indication interrupt
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234 #define IMR_BCNDMAINT0_8723B BIT20 // Beacon DMA Interrupt 0
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235 #define IMR_BCNDERR0_8723B BIT16 // Beacon Queue DMA OK0
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236 #define IMR_HSISR_IND_ON_INT_8723B BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1)
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237 #define IMR_BCNDMAINT_E_8723B BIT14 // Beacon DMA Interrupt Extension for Win7
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238 #define IMR_ATIMEND_8723B BIT12 // CTWidnow End or ATIM Window End
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239 #define IMR_C2HCMD_8723B BIT10 // CPU to Host Command INT Status, Write 1 clear
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240 #define IMR_CPWM2_8723B BIT9 // CPU power Mode exchange INT Status, Write 1 clear
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241 #define IMR_CPWM_8723B BIT8 // CPU power Mode exchange INT Status, Write 1 clear
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242 #define IMR_HIGHDOK_8723B BIT7 // High Queue DMA OK
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243 #define IMR_MGNTDOK_8723B BIT6 // Management Queue DMA OK
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244 #define IMR_BKDOK_8723B BIT5 // AC_BK DMA OK
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245 #define IMR_BEDOK_8723B BIT4 // AC_BE DMA OK
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246 #define IMR_VIDOK_8723B BIT3 // AC_VI DMA OK
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247 #define IMR_VODOK_8723B BIT2 // AC_VO DMA OK
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248 #define IMR_RDU_8723B BIT1 // Rx Descriptor Unavailable
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249 #define IMR_ROK_8723B BIT0 // Receive DMA OK
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251 // IMR DW1(0x00B4-00B7) Bit 0-31
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252 #define IMR_BCNDMAINT7_8723B BIT27 // Beacon DMA Interrupt 7
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253 #define IMR_BCNDMAINT6_8723B BIT26 // Beacon DMA Interrupt 6
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254 #define IMR_BCNDMAINT5_8723B BIT25 // Beacon DMA Interrupt 5
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255 #define IMR_BCNDMAINT4_8723B BIT24 // Beacon DMA Interrupt 4
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256 #define IMR_BCNDMAINT3_8723B BIT23 // Beacon DMA Interrupt 3
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257 #define IMR_BCNDMAINT2_8723B BIT22 // Beacon DMA Interrupt 2
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258 #define IMR_BCNDMAINT1_8723B BIT21 // Beacon DMA Interrupt 1
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259 #define IMR_BCNDOK7_8723B BIT20 // Beacon Queue DMA OK Interrup 7
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260 #define IMR_BCNDOK6_8723B BIT19 // Beacon Queue DMA OK Interrup 6
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261 #define IMR_BCNDOK5_8723B BIT18 // Beacon Queue DMA OK Interrup 5
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262 #define IMR_BCNDOK4_8723B BIT17 // Beacon Queue DMA OK Interrup 4
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263 #define IMR_BCNDOK3_8723B BIT16 // Beacon Queue DMA OK Interrup 3
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264 #define IMR_BCNDOK2_8723B BIT15 // Beacon Queue DMA OK Interrup 2
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265 #define IMR_BCNDOK1_8723B BIT14 // Beacon Queue DMA OK Interrup 1
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266 #define IMR_ATIMEND_E_8723B BIT13 // ATIM Window End Extension for Win7
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267 #define IMR_TXERR_8723B BIT11 // Tx Error Flag Interrupt Status, write 1 clear.
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268 #define IMR_RXERR_8723B BIT10 // Rx Error Flag INT Status, Write 1 clear
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269 #define IMR_TXFOVW_8723B BIT9 // Transmit FIFO Overflow
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270 #define IMR_RXFOVW_8723B BIT8 // Receive FIFO Overflow
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272 #ifdef CONFIG_PCI_HCI
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273 //#define IMR_RX_MASK (IMR_ROK_8723B|IMR_RDU_8723B|IMR_RXFOVW_8723B)
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274 #define IMR_TX_MASK (IMR_VODOK_8723B|IMR_VIDOK_8723B|IMR_BEDOK_8723B|IMR_BKDOK_8723B|IMR_MGNTDOK_8723B|IMR_HIGHDOK_8723B)
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276 #define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8723B | IMR_TXBCN0OK_8723B | IMR_TXBCN0ERR_8723B | IMR_BCNDERR0_8723B)
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278 #define RT_AC_INT_MASKS (IMR_VIDOK_8723B | IMR_VODOK_8723B | IMR_BEDOK_8723B|IMR_BKDOK_8723B)
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283 #ifdef CONFIG_USB_HCI
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284 //should be renamed and moved to another file
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285 typedef enum _BOARD_TYPE_8192CUSB{
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286 BOARD_USB_DONGLE = 0, // USB dongle
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287 BOARD_USB_High_PA = 1, // USB dongle with high power PA
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288 BOARD_MINICARD = 2, // Minicard
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289 BOARD_USB_SOLO = 3, // USB solo-Slim module
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290 BOARD_USB_COMBO = 4, // USB Combo-Slim module
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291 } BOARD_TYPE_8723BUSB, *PBOARD_TYPE_8723BUSB;
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