drivers/net/wireless/rockchip_wlan/rtl8189es/include/rtl8192e_spec.h

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *\r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *******************************************************************************/\r
  19 #ifndef __RTL8192E_SPEC_H__\r
  20 #define __RTL8192E_SPEC_H__\r
  21 \r
  22 #include <drv_conf.h>\r
  23 \r
  24 \r
  25 //============================================================\r
  26 //       8192E Regsiter offset definition\r
  27 //============================================================\r
  28 \r
  29 //============================================================\r
  30 //\r
  31 //============================================================\r
  32 \r
  33 //-----------------------------------------------------\r
  34 //\r
  35 //      0x0000h ~ 0x00FFh       System Configuration\r
  36 //\r
  37 //-----------------------------------------------------\r
  38 #define REG_AFE_CTRL1_8192E                     0x0024\r
  39 #define REG_AFE_CTRL2_8192E                     0x0028\r
  40 #define REG_AFE_CTRL3_8192E                     0x002c\r
  41 \r
  42 \r
  43 #define REG_SDIO_CTRL_8192E                     0x0070\r
  44 #define REG_OPT_CTRL_8192E                              0x0074\r
  45 #define REG_RF_B_CTRL_8192E                     0x0076\r
  46 #define REG_AFE_CTRL4_8192E                     0x0078 \r
  47 #define REG_LDO_SWR_CTRL                                0x007C\r
  48 #define REG_FW_DRV_MSG_8192E                    0x0088\r
  49 #define REG_HMEBOX_E2_E3_8192E          0x008C\r
  50 #define REG_HIMR0_8192E                         0x00B0\r
  51 #define REG_HISR0_8192E                                 0x00B4\r
  52 #define REG_HIMR1_8192E                                 0x00B8\r
  53 #define REG_HISR1_8192E                                 0x00BC\r
  54 \r
  55 #define REG_SYS_CFG1_8192E                              0x00F0\r
  56 #define REG_SYS_CFG2_8192E                              0x00FC \r
  57 //-----------------------------------------------------\r
  58 //\r
  59 //      0x0100h ~ 0x01FFh       MACTOP General Configuration\r
  60 //\r
  61 //-----------------------------------------------------\r
  62 #define REG_PKTBUF_DBG_ADDR                     (REG_PKTBUF_DBG_CTRL)\r
  63 #define REG_RXPKTBUF_DBG                                (REG_PKTBUF_DBG_CTRL+2)\r
  64 #define REG_TXPKTBUF_DBG                                (REG_PKTBUF_DBG_CTRL+3)\r
  65 #define REG_WOWLAN_WAKE_REASON          REG_MCUTST_WOWLAN\r
  66 \r
  67 #define REG_RSVD3_8192E                                 0x0168\r
  68 #define REG_C2HEVT_CMD_SEQ_88XX         0x01A1\r
  69 #define REG_C2hEVT_CMD_CONTENT_88XX     0x01A2\r
  70 #define REG_C2HEVT_CMD_LEN_88XX         0x01AE\r
  71 \r
  72 #define REG_HMEBOX_EXT0_8192E                   0x01F0\r
  73 #define REG_HMEBOX_EXT1_8192E                   0x01F4\r
  74 #define REG_HMEBOX_EXT2_8192E                   0x01F8\r
  75 #define REG_HMEBOX_EXT3_8192E                   0x01FC\r
  76 \r
  77 //-----------------------------------------------------\r
  78 //\r
  79 //      0x0200h ~ 0x027Fh       TXDMA Configuration\r
  80 //\r
  81 //-----------------------------------------------------\r
  82 \r
  83 //-----------------------------------------------------\r
  84 //\r
  85 //      0x0280h ~ 0x02FFh       RXDMA Configuration\r
  86 //\r
  87 //-----------------------------------------------------\r
  88 #define REG_RXDMA_8192E                                 0x0290\r
  89 #define REG_EARLY_MODE_CONTROL_8192E            0x02BC\r
  90 \r
  91 #define REG_RSVD5_8192E                                 0x02F0\r
  92 #define REG_RSVD6_8192E                                 0x02F4\r
  93 #define REG_RSVD7_8192E                                 0x02F8\r
  94 #define REG_RSVD8_8192E                                 0x02FC\r
  95 \r
  96 //-----------------------------------------------------\r
  97 //\r
  98 //      0x0300h ~ 0x03FFh       PCIe\r
  99 //\r
 100 //-----------------------------------------------------\r
 101 #define REG_PCIE_MULTIFET_CTRL_8192E    0x036A  //PCIE Multi-Fethc Control\r
 102 \r
 103 //-----------------------------------------------------\r
 104 //\r
 105 //      0x0400h ~ 0x047Fh       Protocol Configuration\r
 106 //\r
 107 //-----------------------------------------------------\r
 108 #define REG_TXBF_CTRL_8192E                             0x042C\r
 109 #define REG_ARFR1_8192E                                 0x044C\r
 110 #define REG_CCK_CHECK_8192E                             0x0454\r
 111 #define REG_AMPDU_MAX_TIME_8192E                        0x0456\r
 112 #define REG_BCNQ1_BDNY_8192E                            0x0457\r
 113 \r
 114 #define REG_AMPDU_MAX_LENGTH_8192E      0x0458\r
 115 #define REG_NDPA_OPT_CTRL_8192E         0x045F\r
 116 #define REG_DATA_SC_8192E                               0x0483\r
 117 #define REG_TXRPT_START_OFFSET                  0x04AC\r
 118 #define REG_AMPDU_BURST_MODE_8192E      0x04BC\r
 119 #define REG_HT_SINGLE_AMPDU_8192E               0x04C7\r
 120 #define REG_MACID_PKT_DROP0_8192E               0x04D0\r
 121 \r
 122 //-----------------------------------------------------\r
 123 //\r
 124 //      0x0500h ~ 0x05FFh       EDCA Configuration\r
 125 //\r
 126 //-----------------------------------------------------\r
 127 #define REG_CTWND_8192E                                 0x0572\r
 128 #define REG_SECONDARY_CCA_CTRL_8192E    0x0577\r
 129 #define REG_SCH_TXCMD_8192E                     0x05F8\r
 130 \r
 131 //-----------------------------------------------------\r
 132 //\r
 133 //      0x0600h ~ 0x07FFh       WMAC Configuration\r
 134 //\r
 135 //-----------------------------------------------------\r
 136 #define REG_MAC_CR_8192E                                0x0600\r
 137 \r
 138 #define REG_MAC_TX_SM_STATE_8192E               0x06B4\r
 139 \r
 140 // Power\r
 141 #define REG_BFMER0_INFO_8192E                   0x06E4\r
 142 #define REG_BFMER1_INFO_8192E                   0x06EC\r
 143 #define REG_CSI_RPT_PARAM_BW20_8192E    0x06F4\r
 144 #define REG_CSI_RPT_PARAM_BW40_8192E    0x06F8\r
 145 #define REG_CSI_RPT_PARAM_BW80_8192E    0x06FC\r
 146 \r
 147 // Hardware Port 2\r
 148 #define REG_BFMEE_SEL_8192E                             0x0714\r
 149 #define REG_SND_PTCL_CTRL_8192E         0x0718\r
 150 \r
 151 \r
 152 //-----------------------------------------------------\r
 153 //\r
 154 //      Redifine register definition for compatibility\r
 155 //\r
 156 //-----------------------------------------------------\r
 157 \r
 158 // TODO: use these definition when using REG_xxx naming rule.\r
 159 // NOTE: DO NOT Remove these definition. Use later.\r
 160 #define ISR_8192E                                                       REG_HISR0_8192E\r
 161 \r
 162 //----------------------------------------------------------------------------\r
 163 //       8192E IMR/ISR bits                                             (offset 0xB0,  8bits)\r
 164 //----------------------------------------------------------------------------\r
 165 #define IMR_DISABLED_8192E                                      0\r
 166 // IMR DW0(0x00B0-00B3) Bit 0-31\r
 167 #define IMR_TIMER2_8192E                                        BIT31           // Timeout interrupt 2\r
 168 #define IMR_TIMER1_8192E                                        BIT30           // Timeout interrupt 1  \r
 169 #define IMR_PSTIMEOUT_8192E                             BIT29           // Power Save Time Out Interrupt\r
 170 #define IMR_GTINT4_8192E                                        BIT28           // When GTIMER4 expires, this bit is set to 1   \r
 171 #define IMR_GTINT3_8192E                                        BIT27           // When GTIMER3 expires, this bit is set to 1   \r
 172 #define IMR_TXBCN0ERR_8192E                             BIT26           // Transmit Beacon0 Error                       \r
 173 #define IMR_TXBCN0OK_8192E                                      BIT25           // Transmit Beacon0 OK                  \r
 174 #define IMR_TSF_BIT32_TOGGLE_8192E              BIT24           // TSF Timer BIT32 toggle indication interrupt                  \r
 175 #define IMR_BCNDMAINT0_8192E                            BIT20           // Beacon DMA Interrupt 0                       \r
 176 #define IMR_BCNDERR0_8192E                                      BIT16           // Beacon Queue DMA OK0                 \r
 177 #define IMR_HSISR_IND_ON_INT_8192E              BIT15           // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1)\r
 178 #define IMR_BCNDMAINT_E_8192E                           BIT14           // Beacon DMA Interrupt Extension for Win7                      \r
 179 #define IMR_ATIMEND_8192E                                       BIT12           // CTWidnow End or ATIM Window End\r
 180 #define IMR_C2HCMD_8192E                                        BIT10           // CPU to Host Command INT Status, Write 1 clear        \r
 181 #define IMR_CPWM2_8192E                                 BIT9                    // CPU power Mode exchange INT Status, Write 1 clear    \r
 182 #define IMR_CPWM_8192E                                          BIT8                    // CPU power Mode exchange INT Status, Write 1 clear    \r
 183 #define IMR_HIGHDOK_8192E                                       BIT7                    // High Queue DMA OK    \r
 184 #define IMR_MGNTDOK_8192E                                       BIT6                    // Management Queue DMA OK      \r
 185 #define IMR_BKDOK_8192E                                 BIT5                    // AC_BK DMA OK         \r
 186 #define IMR_BEDOK_8192E                                 BIT4                    // AC_BE DMA OK \r
 187 #define IMR_VIDOK_8192E                                 BIT3                    // AC_VI DMA OK         \r
 188 #define IMR_VODOK_8192E                                 BIT2                    // AC_VO DMA OK \r
 189 #define IMR_RDU_8192E                                           BIT1                    // Rx Descriptor Unavailable    \r
 190 #define IMR_ROK_8192E                                           BIT0                    // Receive DMA OK\r
 191 \r
 192 // IMR DW1(0x00B4-00B7) Bit 0-31\r
 193 #define IMR_BCNDMAINT7_8192E                            BIT27           // Beacon DMA Interrupt 7\r
 194 #define IMR_BCNDMAINT6_8192E                            BIT26           // Beacon DMA Interrupt 6\r
 195 #define IMR_BCNDMAINT5_8192E                            BIT25           // Beacon DMA Interrupt 5\r
 196 #define IMR_BCNDMAINT4_8192E                            BIT24           // Beacon DMA Interrupt 4\r
 197 #define IMR_BCNDMAINT3_8192E                            BIT23           // Beacon DMA Interrupt 3\r
 198 #define IMR_BCNDMAINT2_8192E                            BIT22           // Beacon DMA Interrupt 2\r
 199 #define IMR_BCNDMAINT1_8192E                            BIT21           // Beacon DMA Interrupt 1\r
 200 #define IMR_BCNDOK7_8192E                                       BIT20           // Beacon Queue DMA OK Interrup 7\r
 201 #define IMR_BCNDOK6_8192E                                       BIT19           // Beacon Queue DMA OK Interrup 6\r
 202 #define IMR_BCNDOK5_8192E                                       BIT18           // Beacon Queue DMA OK Interrup 5\r
 203 #define IMR_BCNDOK4_8192E                                       BIT17           // Beacon Queue DMA OK Interrup 4\r
 204 #define IMR_BCNDOK3_8192E                                       BIT16           // Beacon Queue DMA OK Interrup 3\r
 205 #define IMR_BCNDOK2_8192E                                       BIT15           // Beacon Queue DMA OK Interrup 2\r
 206 #define IMR_BCNDOK1_8192E                                       BIT14           // Beacon Queue DMA OK Interrup 1\r
 207 #define IMR_ATIMEND_E_8192E                             BIT13           // ATIM Window End Extension for Win7\r
 208 #define IMR_TXERR_8192E                                 BIT11           // Tx Error Flag Interrupt Status, write 1 clear.\r
 209 #define IMR_RXERR_8192E                                 BIT10           // Rx Error Flag INT Status, Write 1 clear\r
 210 #define IMR_TXFOVW_8192E                                        BIT9                    // Transmit FIFO Overflow\r
 211 #define IMR_RXFOVW_8192E                                        BIT8                    // Receive FIFO Overflow\r
 212 \r
 213 //----------------------------------------------------------------------------\r
 214 //       8192E Auto LLT bits                                            (offset 0x224,  8bits)\r
 215 //----------------------------------------------------------------------------\r
 216 //224 REG_AUTO_LLT\r
 217 // move to hal_com_reg.h\r
 218 \r
 219 //----------------------------------------------------------------------------\r
 220 //       8192E Auto LLT bits                                            (offset 0x290,  32bits)\r
 221 //----------------------------------------------------------------------------\r
 222 #define BIT_DMA_MODE                    BIT1\r
 223 #define BIT_USB_RXDMA_AGG_EN    BIT31\r
 224 \r
 225 //----------------------------------------------------------------------------\r
 226 //       8192E REG_SYS_CFG1                                             (offset 0xF0,  32bits)\r
 227 //----------------------------------------------------------------------------\r
 228 #define BIT_SPSLDO_SEL                  BIT24\r
 229 \r
 230 \r
 231 //----------------------------------------------------------------------------\r
 232 //       8192E REG_CCK_CHECK                                            (offset 0x454,  8bits)\r
 233 //----------------------------------------------------------------------------\r
 234 #define BIT_BCN_PORT_SEL                BIT5\r
 235 \r
 236 //============================================================================\r
 237 //       Regsiter Bit and Content definition \r
 238 //============================================================================\r
 239 \r
 240 //2 ACMHWCTRL 0x05C0\r
 241 #define AcmHw_HwEn_8192E                                BIT(0)\r
 242 #define AcmHw_VoqEn_8192E                               BIT(1)\r
 243 #define AcmHw_ViqEn_8192E                               BIT(2)\r
 244 #define AcmHw_BeqEn_8192E                               BIT(3)\r
 245 #define AcmHw_VoqStatus_8192E                   BIT(5)\r
 246 #define AcmHw_ViqStatus_8192E                   BIT(6)\r
 247 #define AcmHw_BeqStatus_8192E                   BIT(7)\r
 248 \r
 249 \r
 250 \r
 251 \r
 252 #endif //__RTL8192E_SPEC_H__\r
 253 \r