1 /******************************************************************************
3 * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
20 #ifndef __GSPI_OPS_H__
21 #define __GSPI_OPS_H__
23 /* follwing defination is based on
24 * GSPI spec of RTL8723, we temp
25 * suppose that it will be the same
26 * for diff chips of GSPI, if not
27 * we should move it to HAL folder */
28 #define SPI_LOCAL_DOMAIN 0x0
29 #define WLAN_IOREG_DOMAIN 0x8
30 #define FW_FIFO_DOMAIN 0x4
31 #define TX_HIQ_DOMAIN 0xc
32 #define TX_MIQ_DOMAIN 0xd
33 #define TX_LOQ_DOMAIN 0xe
34 #define RX_RXFIFO_DOMAIN 0x1f
36 //IO Bus domain address mapping
37 #define DEFUALT_OFFSET 0x0
38 #define SPI_LOCAL_OFFSET 0x10250000
39 #define WLAN_IOREG_OFFSET 0x10260000
40 #define FW_FIFO_OFFSET 0x10270000
41 #define TX_HIQ_OFFSET 0x10310000
42 #define TX_MIQ_OFFSET 0x1032000
43 #define TX_LOQ_OFFSET 0x10330000
44 #define RX_RXOFF_OFFSET 0x10340000
47 #define SPI_REG_TX_CTRL 0x0000 // SPI Tx Control
48 #define SPI_REG_STATUS_RECOVERY 0x0004
49 #define SPI_REG_INT_TIMEOUT 0x0006
50 #define SPI_REG_HIMR 0x0014 // SPI Host Interrupt Mask
51 #define SPI_REG_HISR 0x0018 // SPI Host Interrupt Service Routine
52 #define SPI_REG_RX0_REQ_LEN 0x001C // RXDMA Request Length
53 #define SPI_REG_FREE_TXPG 0x0020 // Free Tx Buffer Page
54 #define SPI_REG_HCPWM1 0x0024 // HCI Current Power Mode 1
55 #define SPI_REG_HCPWM2 0x0026 // HCI Current Power Mode 2
56 #define SPI_REG_HTSFR_INFO 0x0030 // HTSF Informaion
57 #define SPI_REG_HRPWM1 0x0080 // HCI Request Power Mode 1
58 #define SPI_REG_HRPWM2 0x0082 // HCI Request Power Mode 2
59 #define SPI_REG_HPS_CLKR 0x0084 // HCI Power Save Clock
60 #define SPI_REG_HSUS_CTRL 0x0086 // SPI HCI Suspend Control
61 #define SPI_REG_HIMR_ON 0x0090 //SPI Host Extension Interrupt Mask Always
62 #define SPI_REG_HISR_ON 0x0091 //SPI Host Extension Interrupt Status Always
63 #define SPI_REG_CFG 0x00F0 //SPI Configuration Register
65 #define SPI_TX_CTRL (SPI_REG_TX_CTRL |SPI_LOCAL_OFFSET)
66 #define SPI_STATUS_RECOVERY (SPI_REG_STATUS_RECOVERY |SPI_LOCAL_OFFSET)
67 #define SPI_INT_TIMEOUT (SPI_REG_INT_TIMEOUT |SPI_LOCAL_OFFSET)
68 #define SPI_HIMR (SPI_REG_HIMR |SPI_LOCAL_OFFSET)
69 #define SPI_HISR (SPI_REG_HISR |SPI_LOCAL_OFFSET)
70 #define SPI_RX0_REQ_LEN_1_BYTE (SPI_REG_RX0_REQ_LEN |SPI_LOCAL_OFFSET)
71 #define SPI_FREE_TXPG (SPI_REG_FREE_TXPG |SPI_LOCAL_OFFSET)
73 #define SPI_HIMR_DISABLED 0
75 //SPI HIMR MASK diff with SDIO
76 #define SPI_HISR_RX_REQUEST BIT(0)
77 #define SPI_HISR_AVAL BIT(1)
78 #define SPI_HISR_TXERR BIT(2)
79 #define SPI_HISR_RXERR BIT(3)
80 #define SPI_HISR_TXFOVW BIT(4)
81 #define SPI_HISR_RXFOVW BIT(5)
82 #define SPI_HISR_TXBCNOK BIT(6)
83 #define SPI_HISR_TXBCNERR BIT(7)
84 #define SPI_HISR_BCNERLY_INT BIT(16)
85 #define SPI_HISR_ATIMEND BIT(17)
86 #define SPI_HISR_ATIMEND_E BIT(18)
87 #define SPI_HISR_CTWEND BIT(19)
88 #define SPI_HISR_C2HCMD BIT(20)
89 #define SPI_HISR_CPWM1 BIT(21)
90 #define SPI_HISR_CPWM2 BIT(22)
91 #define SPI_HISR_HSISR_IND BIT(23)
92 #define SPI_HISR_GTINT3_IND BIT(24)
93 #define SPI_HISR_GTINT4_IND BIT(25)
94 #define SPI_HISR_PSTIMEOUT BIT(26)
95 #define SPI_HISR_OCPINT BIT(27)
96 #define SPI_HISR_TSF_BIT32_TOGGLE BIT(29)
98 #define MASK_SPI_HISR_CLEAR (SPI_HISR_TXERR |\
107 SPI_HISR_HSISR_IND |\
108 SPI_HISR_GTINT3_IND |\
109 SPI_HISR_GTINT4_IND |\
110 SPI_HISR_PSTIMEOUT |\
113 #define REG_LEN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 0, 8, x)//(x<<(unsigned int)24)
114 #define REG_ADDR_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x)//(x<<(unsigned int)16)
115 #define REG_DOMAIN_ID_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)//(x<<(unsigned int)0)
116 #define REG_FUN_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)//(x<<(unsigned int)5)
117 #define REG_RW_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)//(x<<(unsigned int)7)
119 #define FIFO_LEN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 0, 16, x)//(x<<(unsigned int)24)
120 //#define FIFO_ADDR_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x)//(x<<(unsigned int)16)
121 #define FIFO_DOMAIN_ID_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)//(x<<(unsigned int)0)
122 #define FIFO_FUN_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)//(x<<(unsigned int)5)
123 #define FIFO_RW_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)//(x<<(unsigned int)7)
127 #define GET_STATUS_PUB_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 24, 8)
128 #define GET_STATUS_HI_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 18, 6)
129 #define GET_STATUS_MID_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 12, 6)
130 #define GET_STATUS_LOW_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 6, 6)
131 #define GET_STATUS_HISR_HI6BIT(status) LE_BITS_TO_4BYTE(status, 0, 6)
134 #define GET_STATUS_HISR_MID8BIT(status) LE_BITS_TO_4BYTE(status + 4, 24, 8)
135 #define GET_STATUS_HISR_LOW8BIT(status) LE_BITS_TO_4BYTE(status + 4, 16, 8)
136 #define GET_STATUS_ERROR(status) LE_BITS_TO_4BYTE(status + 4, 17, 1)
137 #define GET_STATUS_INT(status) LE_BITS_TO_4BYTE(status + 4, 16, 1)
138 #define GET_STATUS_RX_LENGTH(status) LE_BITS_TO_4BYTE(status + 4, 0, 16)
141 #define RXDESC_SIZE 24
144 struct spi_more_data {
145 unsigned long more_data;
149 #ifdef CONFIG_RTL8723A
150 void rtl8723as_set_hal_ops(PADAPTER padapter);
151 #define set_hal_ops rtl8723as_set_hal_ops
154 #ifdef CONFIG_RTL8188E
155 void rtl8188es_set_hal_ops(PADAPTER padapter);
156 #define set_hal_ops rtl8188es_set_hal_ops
158 extern void spi_set_chip_endian(PADAPTER padapter);
159 extern void spi_set_intf_ops(_adapter *padapter,struct _io_ops *pops);
160 extern void spi_set_chip_endian(PADAPTER padapter);
161 extern void InitInterrupt8723ASdio(PADAPTER padapter);
162 extern void InitSysInterrupt8723ASdio(PADAPTER padapter);
163 extern void EnableInterrupt8723ASdio(PADAPTER padapter);
164 extern void DisableInterrupt8723ASdio(PADAPTER padapter);
165 extern void spi_int_hdl(PADAPTER padapter);
166 extern u8 HalQueryTxBufferStatus8723ASdio(PADAPTER padapter);
167 extern void InitInterrupt8188ESdio(PADAPTER padapter);
168 extern void EnableInterrupt8188ESdio(PADAPTER padapter);
169 extern void DisableInterrupt8188ESdio(PADAPTER padapter);
170 #ifdef CONFIG_RTL8723B
171 extern void InitInterrupt8723BSdio(PADAPTER padapter);
172 extern void InitSysInterrupt8723BSdio(PADAPTER padapter);
173 extern void EnableInterrupt8723BSdio(PADAPTER padapter);
174 extern void DisableInterrupt8723BSdio(PADAPTER padapter);
175 extern u8 HalQueryTxBufferStatus8723BSdio(PADAPTER padapter);
178 #endif //__GSPI_OPS_H__