drivers/net/wireless/rockchip_wlan/rtl8189es/include/Hal8188EPhyCfg.h

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *\r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *\r
  19  ******************************************************************************/\r
  20 #ifndef __INC_HAL8188EPHYCFG_H__\r
  21 #define __INC_HAL8188EPHYCFG_H__\r
  22 \r
  23 \r
  24 /*--------------------------Define Parameters-------------------------------*/\r
  25 #define LOOP_LIMIT                              5\r
  26 #define MAX_STALL_TIME                  50              //us\r
  27 #define AntennaDiversityValue           0x80    //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80)\r
  28 #define MAX_TXPWR_IDX_NMODE_92S 63\r
  29 #define Reset_Cnt_Limit                 3\r
  30 \r
  31 #ifdef CONFIG_PCI_HCI\r
  32 #define MAX_AGGR_NUM    0x0B\r
  33 #else\r
  34 #define MAX_AGGR_NUM    0x07\r
  35 #endif // CONFIG_PCI_HCI\r
  36 \r
  37 \r
  38 /*--------------------------Define Parameters-------------------------------*/\r
  39 \r
  40 \r
  41 /*------------------------------Define structure----------------------------*/ \r
  42 \r
  43 #define MAX_PG_GROUP 13\r
  44 \r
  45 #define MAX_TX_COUNT_8188E                      1\r
  46 \r
  47 /* BB/RF related */\r
  48 \r
  49 \r
  50 /*------------------------------Define structure----------------------------*/ \r
  51 \r
  52 \r
  53 /*------------------------Export global variable----------------------------*/\r
  54 /*------------------------Export global variable----------------------------*/\r
  55 \r
  56 \r
  57 /*------------------------Export Marco Definition---------------------------*/\r
  58 /*------------------------Export Marco Definition---------------------------*/\r
  59 \r
  60 \r
  61 /*--------------------------Exported Function prototype---------------------*/\r
  62 //\r
  63 // BB and RF register read/write\r
  64 //\r
  65 u32     PHY_QueryBBReg8188E(    IN      PADAPTER        Adapter,\r
  66                                                                 IN      u32             RegAddr,\r
  67                                                                 IN      u32             BitMask );\r
  68 void    PHY_SetBBReg8188E(      IN      PADAPTER        Adapter,\r
  69                                                                 IN      u32             RegAddr,\r
  70                                                                 IN      u32             BitMask,\r
  71                                                                 IN      u32             Data    );\r
  72 u32     PHY_QueryRFReg8188E(    IN      PADAPTER        Adapter,\r
  73                                                                 IN      u8                              eRFPath,\r
  74                                                                 IN      u32                             RegAddr,\r
  75                                                                 IN      u32                             BitMask );\r
  76 void    PHY_SetRFReg8188E(      IN      PADAPTER                Adapter,\r
  77                                                                 IN      u8                              eRFPath,\r
  78                                                                 IN      u32                             RegAddr,\r
  79                                                                 IN      u32                             BitMask,\r
  80                                                                 IN      u32                             Data    );\r
  81 \r
  82 //\r
  83 // Initialization related function\r
  84 //\r
  85 /* MAC/BB/RF HAL config */\r
  86 int     PHY_MACConfig8188E(IN   PADAPTER        Adapter );\r
  87 int     PHY_BBConfig8188E(IN    PADAPTER        Adapter );\r
  88 int     PHY_RFConfig8188E(IN    PADAPTER        Adapter );\r
  89 \r
  90 /* RF config */\r
  91 int     rtl8188e_PHY_ConfigRFWithParaFile(IN PADAPTER Adapter, IN u8 * pFileName, u8 eRFPath);\r
  92 \r
  93 /* Read initi reg value for tx power setting. */\r
  94 void    rtl8192c_PHY_GetHWRegOriginalValue(     IN      PADAPTER                Adapter );\r
  95 \r
  96 //\r
  97 // RF Power setting\r
  98 //\r
  99 //extern        BOOLEAN PHY_SetRFPowerState(IN  PADAPTER                        Adapter, \r
 100 //                                                                      IN      RT_RF_POWER_STATE       eRFPowerState);\r
 101 \r
 102 //\r
 103 // BB TX Power R/W\r
 104 //\r
 105 void    PHY_GetTxPowerLevel8188E(       IN      PADAPTER                Adapter,\r
 106                                                                                         OUT s32*                powerlevel      );\r
 107 void    PHY_SetTxPowerLevel8188E(       IN      PADAPTER                Adapter,\r
 108                                                                                         IN      u8                      channel );\r
 109 BOOLEAN PHY_UpdateTxPowerDbm8188E(      IN      PADAPTER        Adapter,\r
 110                                                                                         IN      int             powerInDbm      );\r
 111 \r
 112 VOID\r
 113 PHY_SetTxPowerIndex_8188E(\r
 114         IN      PADAPTER                        Adapter,\r
 115         IN      u32                                     PowerIndex,\r
 116         IN      u8                                      RFPath, \r
 117         IN      u8                                      Rate\r
 118         );\r
 119 \r
 120 u8\r
 121 PHY_GetTxPowerIndex_8188E(\r
 122         IN      PADAPTER                pAdapter,\r
 123         IN      u8                              RFPath,\r
 124         IN      u8                              Rate,   \r
 125         IN      CHANNEL_WIDTH   BandWidth,      \r
 126         IN      u8                              Channel\r
 127         );\r
 128 \r
 129 //\r
 130 // Switch bandwidth for 8192S\r
 131 //\r
 132 //extern        void    PHY_SetBWModeCallback8192C(     IN      PRT_TIMER               pTimer  );\r
 133 void    PHY_SetBWMode8188E(     IN      PADAPTER                        pAdapter,\r
 134                                                                         IN      CHANNEL_WIDTH   ChnlWidth,\r
 135                                                                         IN      unsigned char   Offset  );\r
 136 \r
 137 //\r
 138 // Set FW CMD IO for 8192S.\r
 139 //\r
 140 //extern        BOOLEAN HalSetIO8192C(  IN      PADAPTER                        Adapter,\r
 141 //                                                                      IN      IO_TYPE                         IOType);\r
 142 \r
 143 //\r
 144 // Set A2 entry to fw for 8192S\r
 145 //\r
 146 extern  void FillA2Entry8192C(          IN      PADAPTER                        Adapter,\r
 147                                                                                 IN      u8                              index,\r
 148                                                                                 IN      u8*                             val);\r
 149 \r
 150 \r
 151 //\r
 152 // channel switch related funciton\r
 153 //\r
 154 //extern        void    PHY_SwChnlCallback8192C(        IN      PRT_TIMER               pTimer  );\r
 155 void    PHY_SwChnl8188E(        IN      PADAPTER                pAdapter,\r
 156                                                                         IN      u8                      channel );\r
 157 \r
 158 VOID\r
 159 PHY_SetSwChnlBWMode8188E(\r
 160         IN      PADAPTER                        Adapter,\r
 161         IN      u8                                      channel,\r
 162         IN      CHANNEL_WIDTH   Bandwidth,\r
 163         IN      u8                                      Offset40,\r
 164         IN      u8                                      Offset80\r
 165 );\r
 166 \r
 167 //\r
 168 // BB/MAC/RF other monitor API\r
 169 //\r
 170 void    PHY_SetMonitorMode8192C(IN      PADAPTER        pAdapter,\r
 171                                                                                 IN      BOOLEAN         bEnableMonitorMode      );\r
 172 \r
 173 BOOLEAN PHY_CheckIsLegalRfPath8192C(IN  PADAPTER        pAdapter,\r
 174                                                                                         IN      u32             eRFPath );\r
 175 \r
 176 VOID PHY_SetRFPathSwitch_8188E(IN       PADAPTER        pAdapter, IN    BOOLEAN         bMain);\r
 177 \r
 178 extern  VOID\r
 179 PHY_SwitchEphyParameter(\r
 180         IN      PADAPTER                        Adapter\r
 181         );\r
 182 \r
 183 extern  VOID\r
 184 PHY_EnableHostClkReq(\r
 185         IN      PADAPTER                        Adapter\r
 186         );\r
 187 \r
 188 BOOLEAN\r
 189 SetAntennaConfig92C(\r
 190         IN      PADAPTER        Adapter,\r
 191         IN      u8              DefaultAnt      \r
 192         );\r
 193 \r
 194 VOID\r
 195 storePwrIndexDiffRateOffset(\r
 196         IN      PADAPTER        Adapter,\r
 197         IN      u32             RegAddr,\r
 198         IN      u32             BitMask,\r
 199         IN      u32             Data\r
 200         );\r
 201 /*--------------------------Exported Function prototype---------------------*/\r
 202 \r
 203 //\r
 204 // Initialization related function\r
 205 //\r
 206 /* MAC/BB/RF HAL config */\r
 207 //extern s32 PHY_MACConfig8723(PADAPTER padapter);\r
 208 //s32 PHY_BBConfig8723(PADAPTER padapter);\r
 209 //s32 PHY_RFConfig8723(PADAPTER padapter);\r
 210 \r
 211 \r
 212 \r
 213 //==================================================================\r
 214 // Note: If SIC_ENABLE under PCIE, because of the slow operation\r
 215 //      you should \r
 216 //      2) "#define RTL8723_FPGA_VERIFICATION   1"                              in Precomp.h.WlanE.Windows\r
 217 //      3) "#define RTL8190_Download_Firmware_From_Header       0"      in Precomp.h.WlanE.Windows if needed.\r
 218 //\r
 219 #if (RTL8188E_SUPPORT == 1) && (RTL8188E_FPGA_TRUE_PHY_VERIFICATION == 1)\r
 220 #define SIC_ENABLE                              1\r
 221 #define SIC_HW_SUPPORT          1\r
 222 #else\r
 223 #define SIC_ENABLE                              0\r
 224 #define SIC_HW_SUPPORT          0\r
 225 #endif\r
 226 //==================================================================\r
 227 \r
 228 \r
 229 #define SIC_MAX_POLL_CNT                5\r
 230 \r
 231 #if(SIC_HW_SUPPORT == 1)\r
 232 #define SIC_CMD_READY                   0\r
 233 #define SIC_CMD_PREWRITE                0x1\r
 234 #if(RTL8188E_SUPPORT == 1)\r
 235 #define SIC_CMD_WRITE                   0x40\r
 236 #define SIC_CMD_PREREAD         0x2\r
 237 #define SIC_CMD_READ                    0x80\r
 238 #define SIC_CMD_INIT                    0xf0\r
 239 #define SIC_INIT_VAL                    0xff\r
 240 \r
 241 #define SIC_INIT_REG                    0x1b7\r
 242 #define SIC_CMD_REG                     0x1EB           // 1byte\r
 243 #define SIC_ADDR_REG                    0x1E8           // 1b4~1b5, 2 bytes\r
 244 #define SIC_DATA_REG                    0x1EC           // 1b0~1b3\r
 245 #else\r
 246 #define SIC_CMD_WRITE                   0x11\r
 247 #define SIC_CMD_PREREAD         0x2\r
 248 #define SIC_CMD_READ                    0x12\r
 249 #define SIC_CMD_INIT                    0x1f\r
 250 #define SIC_INIT_VAL                    0xff\r
 251 \r
 252 #define SIC_INIT_REG                    0x1b7\r
 253 #define SIC_CMD_REG                     0x1b6           // 1byte\r
 254 #define SIC_ADDR_REG                    0x1b4           // 1b4~1b5, 2 bytes\r
 255 #define SIC_DATA_REG                    0x1b0           // 1b0~1b3\r
 256 #endif\r
 257 #else\r
 258 #define SIC_CMD_READY                   0\r
 259 #define SIC_CMD_WRITE                   1\r
 260 #define SIC_CMD_READ                    2\r
 261 \r
 262 #if(RTL8188E_SUPPORT == 1)\r
 263 #define SIC_CMD_REG                     0x1EB           // 1byte\r
 264 #define SIC_ADDR_REG                    0x1E8           // 1b9~1ba, 2 bytes\r
 265 #define SIC_DATA_REG                    0x1EC           // 1bc~1bf\r
 266 #else\r
 267 #define SIC_CMD_REG                     0x1b8           // 1byte\r
 268 #define SIC_ADDR_REG                    0x1b9           // 1b9~1ba, 2 bytes\r
 269 #define SIC_DATA_REG                    0x1bc           // 1bc~1bf\r
 270 #endif\r
 271 #endif\r
 272 \r
 273 #if(SIC_ENABLE == 1)\r
 274 VOID SIC_Init(IN PADAPTER Adapter);\r
 275 #endif\r
 276 \r
 277 \r
 278 #endif  // __INC_HAL8192CPHYCFG_H\r
 279 \r