drivers/net/wireless/rockchip_wlan/rtl8189es/hal/rtl8188e/rtl8188e_mp.c

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *\r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *\r
  19  ******************************************************************************/\r
  20 #define _RTL8188E_MP_C_\r
  21 #ifdef CONFIG_MP_INCLUDED\r
  22 \r
  23 #include <drv_types.h>\r
  24 #include <rtw_mp.h>\r
  25 \r
  26 #include <rtl8188e_hal.h>\r
  27 #include <rtl8188e_dm.h>\r
  28 \r
  29 \r
  30 s32 Hal_SetPowerTracking(PADAPTER padapter, u8 enable)\r
  31 {\r
  32         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);\r
  33         \r
  34         struct dm_priv  *pdmpriv = &pHalData->dmpriv;\r
  35         PDM_ODM_T               pDM_Odm = &(pHalData->odmpriv);\r
  36 \r
  37 \r
  38         if (!netif_running(padapter->pnetdev)) {\r
  39                 RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: interface not opened!\n"));\r
  40                 return _FAIL;\r
  41         }\r
  42 \r
  43         if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {\r
  44                 RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: not in MP mode!\n"));\r
  45                 return _FAIL;\r
  46         }\r
  47 \r
  48         if (enable)\r
  49         {\r
  50                         pDM_Odm->RFCalibrateInfo.bTXPowerTracking = _TRUE;\r
  51         }\r
  52         else\r
  53                 pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit= _FALSE;\r
  54 \r
  55         return _SUCCESS;\r
  56 }\r
  57 \r
  58 void Hal_GetPowerTracking(PADAPTER padapter, u8 *enable)\r
  59 {\r
  60         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);\r
  61         \r
  62         struct dm_priv  *pdmpriv = &pHalData->dmpriv;\r
  63         PDM_ODM_T               pDM_Odm = &(pHalData->odmpriv);\r
  64 \r
  65 \r
  66         *enable = pDM_Odm->RFCalibrateInfo.TxPowerTrackControl;\r
  67 }\r
  68 \r
  69 static void Hal_disable_dm(PADAPTER padapter)\r
  70 {\r
  71         u8 v8;\r
  72         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);\r
  73 \r
  74         struct dm_priv  *pdmpriv = &pHalData->dmpriv;\r
  75         PDM_ODM_T               pDM_Odm = &(pHalData->odmpriv);\r
  76 \r
  77 \r
  78         //3 1. disable firmware dynamic mechanism\r
  79         // disable Power Training, Rate Adaptive\r
  80         v8 = rtw_read8(padapter, REG_BCN_CTRL);\r
  81         v8 &= ~EN_BCN_FUNCTION;\r
  82         rtw_write8(padapter, REG_BCN_CTRL, v8);\r
  83 \r
  84         //3 2. disable driver dynamic mechanism\r
  85         // disable Dynamic Initial Gain\r
  86         // disable High Power\r
  87         // disable Power Tracking\r
  88         Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE);\r
  89 \r
  90         // enable APK, LCK and IQK but disable power tracking\r
  91         pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _FALSE;\r
  92         Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _TRUE);\r
  93 }\r
  94 \r
  95 /*-----------------------------------------------------------------------------\r
  96  * Function:    mpt_SwitchRfSetting\r
  97  *\r
  98  * Overview:    Change RF Setting when we siwthc channel/rate/BW for MP.\r
  99  *\r
 100  * Input:       IN      PADAPTER                                pAdapter\r
 101  *\r
 102  * Output:      NONE\r
 103  *\r
 104  * Return:      NONE\r
 105  *\r
 106  * Revised History:\r
 107  * When                 Who             Remark\r
 108  * 01/08/2009   MHC             Suggestion from SD3 Willis for 92S series.\r
 109  * 01/09/2009   MHC             Add CCK modification for 40MHZ. Suggestion from SD3.\r
 110  *\r
 111  *---------------------------------------------------------------------------*/\r
 112 void Hal_mpt_SwitchRfSetting(PADAPTER pAdapter)\r
 113 {       \r
 114         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
 115         struct mp_priv  *pmp = &pAdapter->mppriv;\r
 116         u1Byte                          ChannelToSw = pmp->channel;\r
 117         ULONG                           ulRateIdx = pmp->rateidx;\r
 118         ULONG                           ulbandwidth = pmp->bandwidth;\r
 119         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(pAdapter);     \r
 120 \r
 121         // <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.\r
 122         if (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) &&\r
 123                 (ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M))\r
 124         {\r
 125                 pmp->MptCtx.backup0x52_RF_A = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0);\r
 126                 pmp->MptCtx.backup0x52_RF_B = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0);\r
 127                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xD);\r
 128                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xD);\r
 129         }\r
 130         else if (IS_HARDWARE_TYPE_8188E(pAdapter))\r
 131         {\r
 132                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, pmp->MptCtx.backup0x52_RF_A);\r
 133                 PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, pmp->MptCtx.backup0x52_RF_B);\r
 134         }\r
 135 \r
 136         return ;\r
 137 }\r
 138 /*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/\r
 139 \r
 140 /*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/\r
 141 void Hal_MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)\r
 142 {\r
 143         u32             TempVal = 0, TempVal2 = 0, TempVal3 = 0;\r
 144         u32             CurrCCKSwingVal = 0, CCKSwingIndex = 12;\r
 145         u8              i;\r
 146         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
 147 \r
 148 \r
 149         // get current cck swing value and check 0xa22 & 0xa23 later to match the table.\r
 150         CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);\r
 151 \r
 152         if (!bInCH14)\r
 153         {\r
 154                 // Readback the current bb cck swing value and compare with the table to\r
 155                 // get the current swing index\r
 156                 for (i = 0; i < CCK_TABLE_SIZE; i++)\r
 157                 {\r
 158                         if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) &&\r
 159                                 (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch1_Ch13[i][1]))\r
 160                         {\r
 161                                 CCKSwingIndex = i;\r
 162 //                              RT_TRACE(COMP_INIT, DBG_LOUD,("Ch1~13, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",\r
 163 //                                      (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex));\r
 164                                 break;\r
 165                         }\r
 166                 }\r
 167 \r
 168                 //Write 0xa22 0xa23\r
 169                 TempVal = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][0] +\r
 170                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][1]<<8) ;\r
 171 \r
 172 \r
 173                 //Write 0xa24 ~ 0xa27\r
 174                 TempVal2 = 0;\r
 175                 TempVal2 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][2] +\r
 176                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][3]<<8) +\r
 177                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][4]<<16 )+\r
 178                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][5]<<24);\r
 179 \r
 180                 //Write 0xa28  0xa29\r
 181                 TempVal3 = 0;\r
 182                 TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] +\r
 183                                 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7]<<8) ;\r
 184         }\r
 185         else\r
 186         {\r
 187                 for (i = 0; i < CCK_TABLE_SIZE; i++)\r
 188                 {\r
 189                         if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch14[i][0]) &&\r
 190                                 (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch14[i][1]))\r
 191                         {\r
 192                                 CCKSwingIndex = i;\r
 193 //                              RT_TRACE(COMP_INIT, DBG_LOUD,("Ch14, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",\r
 194 //                                      (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex));\r
 195                                 break;\r
 196                         }\r
 197                 }\r
 198 \r
 199                 //Write 0xa22 0xa23\r
 200                 TempVal = CCKSwingTable_Ch14[CCKSwingIndex][0] +\r
 201                                 (CCKSwingTable_Ch14[CCKSwingIndex][1]<<8) ;\r
 202 \r
 203                 //Write 0xa24 ~ 0xa27\r
 204                 TempVal2 = 0;\r
 205                 TempVal2 = CCKSwingTable_Ch14[CCKSwingIndex][2] +\r
 206                                 (CCKSwingTable_Ch14[CCKSwingIndex][3]<<8) +\r
 207                                 (CCKSwingTable_Ch14[CCKSwingIndex][4]<<16 )+\r
 208                                 (CCKSwingTable_Ch14[CCKSwingIndex][5]<<24);\r
 209 \r
 210                 //Write 0xa28  0xa29\r
 211                 TempVal3 = 0;\r
 212                 TempVal3 = CCKSwingTable_Ch14[CCKSwingIndex][6] +\r
 213                                 (CCKSwingTable_Ch14[CCKSwingIndex][7]<<8) ;\r
 214         }\r
 215 \r
 216         write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);\r
 217         write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);\r
 218         write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);\r
 219 }\r
 220 \r
 221 void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven)\r
 222 {\r
 223         s32             TempCCk;\r
 224         u8              CCK_index, CCK_index_old=0;\r
 225         u8              Action = 0;     //0: no action, 1: even->odd, 2:odd->even\r
 226         u8              TimeOut = 100;\r
 227         s32             i = 0;\r
 228         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 229         PMPT_CONTEXT    pMptCtx = &pAdapter->mppriv.MptCtx;\r
 230 \r
 231         struct dm_priv  *pdmpriv = &pHalData->dmpriv;\r
 232         PDM_ODM_T               pDM_Odm = &(pHalData->odmpriv);\r
 233 \r
 234 \r
 235         if (!IS_92C_SERIAL(pHalData->VersionID))\r
 236                 return;\r
 237 #if 0\r
 238         while(PlatformAtomicExchange(&Adapter->IntrCCKRefCount, TRUE) == TRUE)\r
 239         {\r
 240                 PlatformSleepUs(100);\r
 241                 TimeOut--;\r
 242                 if(TimeOut <= 0)\r
 243                 {\r
 244                         RTPRINT(FINIT, INIT_TxPower,\r
 245                          ("!!!MPT_CCKTxPowerAdjustbyIndex Wait for check CCK gain index too long!!!\n" ));\r
 246                         break;\r
 247                 }\r
 248         }\r
 249 #endif\r
 250         if (beven && !pMptCtx->bMptIndexEven)   //odd->even\r
 251         {\r
 252                 Action = 2;\r
 253                 pMptCtx->bMptIndexEven = _TRUE;\r
 254         }\r
 255         else if (!beven && pMptCtx->bMptIndexEven)      //even->odd\r
 256         {\r
 257                 Action = 1;\r
 258                 pMptCtx->bMptIndexEven = _FALSE;\r
 259         }\r
 260 \r
 261         if (Action != 0)\r
 262         {\r
 263                 //Query CCK default setting From 0xa24\r
 264                 TempCCk = read_bbreg(pAdapter, rCCK0_TxFilter2, bMaskDWord) & bMaskCCK;\r
 265                 for (i = 0; i < CCK_TABLE_SIZE; i++)\r
 266                 {\r
 267                         if (pDM_Odm->RFCalibrateInfo.bCCKinCH14)\r
 268                         {\r
 269                                 if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch14[i][2], 4) == _TRUE)\r
 270                                 {\r
 271                                         CCK_index_old = (u8) i;\r
 272 //                                      RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: Initial reg0x%x = 0x%lx, CCK_index=0x%x, ch 14 %d\n",\r
 273 //                                              rCCK0_TxFilter2, TempCCk, CCK_index_old, pHalData->bCCKinCH14));\r
 274                                         break;\r
 275                                 }\r
 276                         }\r
 277                         else\r
 278                         {\r
 279                                 if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch1_Ch13[i][2], 4) == _TRUE)\r
 280                                 {\r
 281                                         CCK_index_old = (u8) i;\r
 282 //                                      RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: Initial reg0x%x = 0x%lx, CCK_index=0x%x, ch14 %d\n",\r
 283 //                                              rCCK0_TxFilter2, TempCCk, CCK_index_old, pHalData->bCCKinCH14));\r
 284                                         break;\r
 285                                 }\r
 286                         }\r
 287                 }\r
 288 \r
 289                 if (Action == 1) {\r
 290                         if (CCK_index_old == 0)\r
 291                                 CCK_index_old = 1;\r
 292                         CCK_index = CCK_index_old - 1;\r
 293                 } else {\r
 294                         CCK_index = CCK_index_old + 1;\r
 295                 }\r
 296 \r
 297                 if (CCK_index == CCK_TABLE_SIZE) {\r
 298                         CCK_index = CCK_TABLE_SIZE -1;\r
 299                         RT_TRACE(_module_mp_, _drv_info_, ("CCK_index == CCK_TABLE_SIZE\n"));\r
 300                 }\r
 301 \r
 302 //              RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: new CCK_index=0x%x\n",\r
 303 //                       CCK_index));\r
 304 \r
 305                 //Adjust CCK according to gain index\r
 306                 if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) {\r
 307                         rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch1_Ch13[CCK_index][0]);\r
 308                         rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch1_Ch13[CCK_index][1]);\r
 309                         rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch1_Ch13[CCK_index][2]);\r
 310                         rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch1_Ch13[CCK_index][3]);\r
 311                         rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch1_Ch13[CCK_index][4]);\r
 312                         rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch1_Ch13[CCK_index][5]);\r
 313                         rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch1_Ch13[CCK_index][6]);\r
 314                         rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch1_Ch13[CCK_index][7]);\r
 315                 } else {\r
 316                         rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch14[CCK_index][0]);\r
 317                         rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch14[CCK_index][1]);\r
 318                         rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch14[CCK_index][2]);\r
 319                         rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch14[CCK_index][3]);\r
 320                         rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch14[CCK_index][4]);\r
 321                         rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch14[CCK_index][5]);\r
 322                         rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch14[CCK_index][6]);\r
 323                         rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch14[CCK_index][7]);\r
 324                 }\r
 325         }\r
 326 #if 0\r
 327         RTPRINT(FINIT, INIT_TxPower,\r
 328         ("MPT_CCKTxPowerAdjustbyIndex 0xa20=%x\n", PlatformEFIORead4Byte(Adapter, 0xa20)));\r
 329 \r
 330         PlatformAtomicExchange(&Adapter->IntrCCKRefCount, FALSE);\r
 331 #endif\r
 332 }\r
 333 /*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/\r
 334 \r
 335 /*\r
 336  * SetChannel\r
 337  * Description\r
 338  *      Use H2C command to change channel,\r
 339  *      not only modify rf register, but also other setting need to be done.\r
 340  */\r
 341 void Hal_SetChannel(PADAPTER pAdapter)\r
 342 {\r
 343 #if 0\r
 344         struct mp_priv *pmp = &pAdapter->mppriv;\r
 345 \r
 346 //      SelectChannel(pAdapter, pmp->channel);\r
 347         set_channel_bwmode(pAdapter, pmp->channel, pmp->channel_offset, pmp->bandwidth);\r
 348 #else\r
 349         u8              eRFPath;\r
 350 \r
 351         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 352         struct mp_priv  *pmp = &pAdapter->mppriv;\r
 353         struct dm_priv  *pdmpriv = &pHalData->dmpriv;\r
 354         PDM_ODM_T               pDM_Odm = &(pHalData->odmpriv);\r
 355         \r
 356         u8              channel = pmp->channel;\r
 357         u8              bandwidth = pmp->bandwidth;\r
 358         u8              rate = pmp->rateidx;\r
 359 \r
 360 \r
 361         // set RF channel register\r
 362         for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++)\r
 363         {\r
 364                 if(IS_HARDWARE_TYPE_8192D(pAdapter))\r
 365                         _write_rfreg(pAdapter, eRFPath, ODM_CHANNEL, 0xFF, channel);\r
 366                 else\r
 367                         _write_rfreg(pAdapter, eRFPath, ODM_CHANNEL, 0x3FF, channel);\r
 368         }\r
 369         Hal_mpt_SwitchRfSetting(pAdapter);\r
 370 \r
 371         SelectChannel(pAdapter, channel);\r
 372 \r
 373         if (pHalData->CurrentChannel == 14 && !pDM_Odm->RFCalibrateInfo.bCCKinCH14) {\r
 374                 pDM_Odm->RFCalibrateInfo.bCCKinCH14 = _TRUE;\r
 375                 Hal_MPT_CCKTxPowerAdjust(pAdapter, pDM_Odm->RFCalibrateInfo.bCCKinCH14);\r
 376         }\r
 377         else if (pHalData->CurrentChannel != 14 && pDM_Odm->RFCalibrateInfo.bCCKinCH14) {\r
 378                 pDM_Odm->RFCalibrateInfo.bCCKinCH14 = _FALSE;\r
 379                 Hal_MPT_CCKTxPowerAdjust(pAdapter, pDM_Odm->RFCalibrateInfo.bCCKinCH14);\r
 380         }\r
 381 \r
 382 #endif\r
 383 }\r
 384 \r
 385 /*\r
 386  * Notice\r
 387  *      Switch bandwitdth may change center frequency(channel)\r
 388  */\r
 389 void Hal_SetBandwidth(PADAPTER pAdapter)\r
 390 {\r
 391         struct mp_priv *pmp = &pAdapter->mppriv;\r
 392 \r
 393 \r
 394         SetBWMode(pAdapter, pmp->bandwidth, pmp->prime_channel_offset);\r
 395         Hal_mpt_SwitchRfSetting(pAdapter);\r
 396 }\r
 397 \r
 398 void Hal_SetCCKTxPower(PADAPTER pAdapter, u8 *TxPower)\r
 399 {\r
 400         u32 tmpval = 0;\r
 401 \r
 402 \r
 403         // rf-A cck tx power\r
 404         write_bbreg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, TxPower[RF_PATH_A]);\r
 405         tmpval = (TxPower[RF_PATH_A]<<16) | (TxPower[RF_PATH_A]<<8) | TxPower[RF_PATH_A];\r
 406         write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);\r
 407 \r
 408         // rf-B cck tx power\r
 409         write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, TxPower[RF_PATH_B]);\r
 410         tmpval = (TxPower[RF_PATH_B]<<16) | (TxPower[RF_PATH_B]<<8) | TxPower[RF_PATH_B];\r
 411         write_bbreg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);\r
 412 \r
 413         RT_TRACE(_module_mp_, _drv_notice_,\r
 414                  ("-SetCCKTxPower: A[0x%02x] B[0x%02x]\n",\r
 415                   TxPower[RF_PATH_A], TxPower[RF_PATH_B]));\r
 416 }\r
 417 \r
 418 void Hal_SetOFDMTxPower(PADAPTER pAdapter, u8 *TxPower)\r
 419 {\r
 420         u32 TxAGC = 0;\r
 421         u8 tmpval = 0;\r
 422         PMPT_CONTEXT    pMptCtx = &pAdapter->mppriv.MptCtx;\r
 423         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 424 \r
 425 \r
 426         // HT Tx-rf(A)\r
 427         tmpval = TxPower[RF_PATH_A];\r
 428         TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval;\r
 429 \r
 430         write_bbreg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);\r
 431         write_bbreg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);\r
 432         write_bbreg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);\r
 433         write_bbreg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);\r
 434         write_bbreg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);\r
 435         write_bbreg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);\r
 436 \r
 437         // HT Tx-rf(B)\r
 438         tmpval = TxPower[RF_PATH_B];\r
 439         TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval;\r
 440 \r
 441         write_bbreg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);\r
 442         write_bbreg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);\r
 443         write_bbreg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);\r
 444         write_bbreg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);\r
 445         write_bbreg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);\r
 446         write_bbreg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);\r
 447 \r
 448 }\r
 449 \r
 450 void Hal_SetAntennaPathPower(PADAPTER pAdapter)\r
 451 {\r
 452         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
 453         u8 TxPowerLevel[MAX_RF_PATH_NUMS];\r
 454         u8 rfPath;\r
 455 \r
 456         TxPowerLevel[RF_PATH_A] = pAdapter->mppriv.txpoweridx;\r
 457         TxPowerLevel[RF_PATH_B] = pAdapter->mppriv.txpoweridx_b;\r
 458 \r
 459         switch (pAdapter->mppriv.antenna_tx)\r
 460         {\r
 461                 case ANTENNA_A:\r
 462                 default:\r
 463                         rfPath = RF_PATH_A;\r
 464                         break;\r
 465                 case ANTENNA_B:\r
 466                         rfPath = RF_PATH_B;\r
 467                         break;\r
 468                 case ANTENNA_C:\r
 469                         rfPath = RF_PATH_C;\r
 470                         break;\r
 471         }\r
 472 \r
 473         switch (pHalData->rf_chip)\r
 474         {\r
 475                 case RF_8225:\r
 476                 case RF_8256:\r
 477                 case RF_6052:\r
 478                         Hal_SetCCKTxPower(pAdapter, TxPowerLevel);\r
 479                         if (pAdapter->mppriv.rateidx < MPT_RATE_6M)     // CCK rate\r
 480                                 Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);\r
 481                         Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);\r
 482                         break;\r
 483 \r
 484                 default:\r
 485                         break;\r
 486         }\r
 487 }\r
 488 \r
 489 void Hal_SetTxPower(PADAPTER pAdapter)\r
 490 {\r
 491         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
 492         u8 TxPower = pAdapter->mppriv.txpoweridx;\r
 493         u8 TxPowerLevel[MAX_RF_PATH_NUMS];\r
 494         u8 rf, rfPath;\r
 495 \r
 496         for (rf = 0; rf < MAX_RF_PATH_NUMS; rf++) {\r
 497                 TxPowerLevel[rf] = TxPower;\r
 498         }\r
 499 \r
 500         switch (pAdapter->mppriv.antenna_tx)\r
 501         {\r
 502                 case ANTENNA_A:\r
 503                 default:\r
 504                         rfPath = RF_PATH_A;\r
 505                         break;\r
 506                 case ANTENNA_B:\r
 507                         rfPath = RF_PATH_B;\r
 508                         break;\r
 509                 case ANTENNA_C:\r
 510                         rfPath = RF_PATH_C;\r
 511                         break;\r
 512         }\r
 513 \r
 514         switch (pHalData->rf_chip)\r
 515         {\r
 516                 // 2008/09/12 MH Test only !! We enable the TX power tracking for MP!!!!!\r
 517                 // We should call normal driver API later!!\r
 518                 case RF_8225:\r
 519                 case RF_8256:\r
 520                 case RF_6052:\r
 521                         Hal_SetCCKTxPower(pAdapter, TxPowerLevel);\r
 522                         if (pAdapter->mppriv.rateidx < MPT_RATE_6M)     // CCK rate\r
 523                                 Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);\r
 524                         Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);\r
 525                         break;\r
 526 \r
 527                 default:\r
 528                         break;\r
 529         }\r
 530 \r
 531 //      SetCCKTxPower(pAdapter, TxPower);\r
 532 //      SetOFDMTxPower(pAdapter, TxPower);\r
 533 }\r
 534 \r
 535 void Hal_SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset)\r
 536 {\r
 537         u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D,tmpAGC;\r
 538 \r
 539         TxAGCOffset_B = (ulTxAGCOffset&0x000000ff);\r
 540         TxAGCOffset_C = ((ulTxAGCOffset&0x0000ff00)>>8);\r
 541         TxAGCOffset_D = ((ulTxAGCOffset&0x00ff0000)>>16);\r
 542 \r
 543         tmpAGC = (TxAGCOffset_D<<8 | TxAGCOffset_C<<4 | TxAGCOffset_B);\r
 544         write_bbreg(pAdapter, rFPGA0_TxGainStage,\r
 545                         (bXBTxAGC|bXCTxAGC|bXDTxAGC), tmpAGC);\r
 546 }\r
 547 \r
 548 void Hal_SetDataRate(PADAPTER pAdapter)\r
 549 {\r
 550         Hal_mpt_SwitchRfSetting(pAdapter);\r
 551 }\r
 552 \r
 553 void Hal_SetAntenna(PADAPTER pAdapter)\r
 554 {\r
 555         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 556 \r
 557         R_ANTENNA_SELECT_OFDM *p_ofdm_tx;       /* OFDM Tx register */\r
 558         R_ANTENNA_SELECT_CCK *p_cck_txrx;\r
 559 \r
 560         u8      r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;\r
 561         u8      chgTx = 0, chgRx = 0;\r
 562         u32     r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;\r
 563 \r
 564 \r
 565         p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val;\r
 566         p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val;\r
 567 \r
 568         p_ofdm_tx->r_ant_ht1    = 0x1;\r
 569         p_ofdm_tx->r_ant_ht2    = 0x2;  // Second TX RF path is A\r
 570         p_ofdm_tx->r_ant_non_ht = 0x3;  // 0x1+0x2=0x3\r
 571 \r
 572         switch (pAdapter->mppriv.antenna_tx)\r
 573         {\r
 574                 case ANTENNA_A:\r
 575                         p_ofdm_tx->r_tx_antenna         = 0x1;\r
 576                         r_ofdm_tx_en_val                = 0x1;\r
 577                         p_ofdm_tx->r_ant_l              = 0x1;\r
 578                         p_ofdm_tx->r_ant_ht_s1          = 0x1;\r
 579                         p_ofdm_tx->r_ant_non_ht_s1      = 0x1;\r
 580                         p_cck_txrx->r_ccktx_enable      = 0x8;\r
 581                         chgTx = 1;\r
 582 \r
 583                         // From SD3 Willis suggestion !!! Set RF A=TX and B as standby\r
 584 //                      if (IS_HARDWARE_TYPE_8192S(pAdapter))\r
 585                         {\r
 586                         write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);\r
 587                         write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);\r
 588                         r_ofdm_tx_en_val                = 0x3;\r
 589 \r
 590                         // Power save\r
 591                         //cosa r_ant_select_ofdm_val = 0x11111111;\r
 592 \r
 593                         // We need to close RFB by SW control\r
 594                         if (pHalData->rf_type == RF_2T2R)\r
 595                         {\r
 596                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);\r
 597                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);\r
 598                                 PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);\r
 599                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);\r
 600                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);\r
 601                         }\r
 602                         }\r
 603                         break;\r
 604 \r
 605                 case ANTENNA_B:\r
 606                         p_ofdm_tx->r_tx_antenna         = 0x2;\r
 607                         r_ofdm_tx_en_val                = 0x2;\r
 608                         p_ofdm_tx->r_ant_l              = 0x2;\r
 609                         p_ofdm_tx->r_ant_ht_s1          = 0x2;\r
 610                         p_ofdm_tx->r_ant_non_ht_s1      = 0x2;\r
 611                         p_cck_txrx->r_ccktx_enable      = 0x4;\r
 612                         chgTx = 1;\r
 613 \r
 614                         // From SD3 Willis suggestion !!! Set RF A as standby\r
 615                         //if (IS_HARDWARE_TYPE_8192S(pAdapter))\r
 616                         {\r
 617                         PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);\r
 618                         PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);\r
 619 //                      r_ofdm_tx_en_val                = 0x3;\r
 620 \r
 621                         // Power save\r
 622                         //cosa r_ant_select_ofdm_val = 0x22222222;\r
 623 \r
 624                         // 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.\r
 625                         // 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control\r
 626                         if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R)\r
 627                         {\r
 628                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);\r
 629                                 PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);\r
 630                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);\r
 631 //                              PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);\r
 632                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);\r
 633                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);\r
 634                         }\r
 635                         }\r
 636                 break;\r
 637 \r
 638                 case ANTENNA_AB:        // For 8192S\r
 639                         p_ofdm_tx->r_tx_antenna         = 0x3;\r
 640                         r_ofdm_tx_en_val                = 0x3;\r
 641                         p_ofdm_tx->r_ant_l              = 0x3;\r
 642                         p_ofdm_tx->r_ant_ht_s1          = 0x3;\r
 643                         p_ofdm_tx->r_ant_non_ht_s1      = 0x3;\r
 644                         p_cck_txrx->r_ccktx_enable      = 0xC;\r
 645                         chgTx = 1;\r
 646 \r
 647                         // From SD3 Willis suggestion !!! Set RF B as standby\r
 648                         //if (IS_HARDWARE_TYPE_8192S(pAdapter))\r
 649                         {\r
 650                         PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);\r
 651                         PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);\r
 652 \r
 653                         // Disable Power save\r
 654                         //cosa r_ant_select_ofdm_val = 0x3321333;\r
 655 #if 0\r
 656                         // 2008/10/31 MH From SD3 Willi's suggestion. We must read RFA 2T table.\r
 657                         if ((pHalData->VersionID == VERSION_8192S_ACUT)) // For RTL8192SU A-Cut only, by Roger, 2008.11.07.\r
 658                         {\r
 659                                 mpt_RFConfigFromPreParaArrary(pAdapter, 1, RF_PATH_A);\r
 660                         }\r
 661 #endif\r
 662                         // 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control\r
 663                         if (pHalData->rf_type == RF_2T2R)\r
 664                         {\r
 665                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);\r
 666                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);\r
 667 //                              PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);\r
 668                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);\r
 669                                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);\r
 670                         }\r
 671                         }\r
 672                         break;\r
 673 \r
 674                 default:\r
 675                         break;\r
 676         }\r
 677 \r
 678         //\r
 679         // r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D\r
 680         // r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D\r
 681         // r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D\r
 682         //\r
 683         switch (pAdapter->mppriv.antenna_rx)\r
 684         {\r
 685                 case ANTENNA_A:\r
 686                         r_rx_antenna_ofdm               = 0x1;  // A\r
 687                         p_cck_txrx->r_cckrx_enable      = 0x0;  // default: A\r
 688                         p_cck_txrx->r_cckrx_enable_2    = 0x0;  // option: A\r
 689                         chgRx = 1;\r
 690                         break;\r
 691 \r
 692                 case ANTENNA_B:\r
 693                         r_rx_antenna_ofdm               = 0x2;  // B\r
 694                         p_cck_txrx->r_cckrx_enable      = 0x1;  // default: B\r
 695                         p_cck_txrx->r_cckrx_enable_2    = 0x1;  // option: B\r
 696                         chgRx = 1;\r
 697                         break;\r
 698 \r
 699                 case ANTENNA_AB:\r
 700                         r_rx_antenna_ofdm               = 0x3;  // AB\r
 701                         p_cck_txrx->r_cckrx_enable      = 0x0;  // default:A\r
 702                         p_cck_txrx->r_cckrx_enable_2    = 0x1;  // option:B\r
 703                         chgRx = 1;\r
 704                         break;\r
 705 \r
 706                 default:\r
 707                         break;\r
 708         }\r
 709 \r
 710         if (chgTx && chgRx)\r
 711         {\r
 712                 switch(pHalData->rf_chip)\r
 713                 {\r
 714                         case RF_8225:\r
 715                         case RF_8256:\r
 716                         case RF_6052:\r
 717                                 //r_ant_sel_cck_val = r_ant_select_cck_val;\r
 718                                 PHY_SetBBReg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val);       //OFDM Tx\r
 719                                 PHY_SetBBReg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val);            //OFDM Tx\r
 720                                 PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm);    //OFDM Rx\r
 721                                 PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm);    //OFDM Rx\r
 722                                 PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);//r_ant_sel_cck_val);                //CCK TxRx\r
 723 \r
 724                                 break;\r
 725 \r
 726                         default:\r
 727                                 break;\r
 728                 }\r
 729         }\r
 730 \r
 731         RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));\r
 732 }\r
 733 \r
 734 s32 Hal_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)\r
 735 {\r
 736         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
 737 \r
 738 \r
 739         if (!netif_running(pAdapter->pnetdev)) {\r
 740                 RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter! Fail: interface not opened!\n"));\r
 741                 return _FAIL;\r
 742         }\r
 743 \r
 744         if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {\r
 745                 RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter: Fail! not in MP mode!\n"));\r
 746                 return _FAIL;\r
 747         }\r
 748 \r
 749         target_ther &= 0xff;\r
 750         if (target_ther < 0x07)\r
 751                 target_ther = 0x07;\r
 752         else if (target_ther > 0x1d)\r
 753                 target_ther = 0x1d;\r
 754 \r
 755         pHalData->EEPROMThermalMeter = target_ther;\r
 756 \r
 757         return _SUCCESS;\r
 758 }\r
 759 \r
 760 void Hal_TriggerRFThermalMeter(PADAPTER pAdapter)\r
 761 {\r
 762   \r
 763         _write_rfreg( pAdapter, RF_PATH_A , RF_T_METER_88E , BIT17 |BIT16 , 0x03 );\r
 764 \r
 765 //      RT_TRACE(_module_mp_,_drv_alert_, ("TriggerRFThermalMeter() finished.\n" ));\r
 766 }\r
 767 \r
 768 u8 Hal_ReadRFThermalMeter(PADAPTER pAdapter)\r
 769 {\r
 770         u32 ThermalValue = 0;\r
 771 \r
 772         //ThermalValue = _read_rfreg(pAdapter, RF_PATH_A, RF_T_METER, 0x1F);    // 0x24: RF Reg[4:0]\r
 773 \r
 774         ThermalValue = _read_rfreg(pAdapter, RF_PATH_A, RF_T_METER_88E, 0xfc00);\r
 775         \r
 776 //      RT_TRACE(_module_mp_, _drv_alert_, ("ThermalValue = 0x%x\n", ThermalValue));\r
 777         return (u8)ThermalValue;\r
 778 }\r
 779 \r
 780 void Hal_GetThermalMeter(PADAPTER pAdapter, u8 *value)\r
 781 {\r
 782 #if 0\r
 783         fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);\r
 784         rtw_msleep_os(1000);\r
 785         fw_cmd_data(pAdapter, value, 1);\r
 786         *value &= 0xFF;\r
 787 #else\r
 788 \r
 789         Hal_TriggerRFThermalMeter(pAdapter);\r
 790         rtw_msleep_os(1000);\r
 791         *value = Hal_ReadRFThermalMeter(pAdapter);\r
 792 #endif\r
 793 }\r
 794 \r
 795 void Hal_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)\r
 796 {\r
 797     HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
 798         pAdapter->mppriv.MptCtx.bSingleCarrier = bStart;\r
 799         if (bStart)// Start Single Carrier.\r
 800         {\r
 801                 RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleCarrierTx: test start\n"));\r
 802                 // 1. if OFDM block on?\r
 803                 if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))\r
 804                         write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);//set OFDM block on\r
 805 \r
 806                 {\r
 807                 // 2. set CCK test mode off, set to CCK normal mode\r
 808                 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);\r
 809                 // 3. turn on scramble setting\r
 810                 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);\r
 811          }\r
 812                 // 4. Turn On Single Carrier Tx and turn off the other test modes.\r
 813                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);\r
 814                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable);\r
 815                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);\r
 816 #ifdef CONFIG_RTL8192C\r
 817                 // 5. Disable TX power saving at STF & LLTF\r
 818                 write_bbreg(pAdapter, rOFDM1_LSTF, BIT22, 1);\r
 819 #endif\r
 820                 //for dynamic set Power index.\r
 821                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);\r
 822                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);\r
 823                 \r
 824         }\r
 825         else// Stop Single Carrier.\r
 826         {\r
 827                 RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleCarrierTx: test stop\n"));\r
 828 \r
 829                 // Turn off all test modes.\r
 830                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);\r
 831                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);\r
 832                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);\r
 833 #ifdef CONFIG_RTL8192C\r
 834                 // Cancel disable TX power saving at STF&LLTF\r
 835                 write_bbreg(pAdapter, rOFDM1_LSTF, BIT22, 0);\r
 836 #endif\r
 837                 //Delay 10 ms //delay_ms(10);\r
 838                 rtw_msleep_os(10);\r
 839 \r
 840                 //BB Reset\r
 841                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);\r
 842                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);\r
 843 \r
 844                 //Stop for dynamic set Power index.\r
 845                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);\r
 846                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);\r
 847                 \r
 848         }\r
 849 }\r
 850 \r
 851 \r
 852 void Hal_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)\r
 853 {\r
 854         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 855         BOOLEAN         is92C = IS_92C_SERIAL(pHalData->VersionID);\r
 856 \r
 857         u8 rfPath;\r
 858         u32              reg58 = 0x0;\r
 859         switch (pAdapter->mppriv.antenna_tx)\r
 860         {\r
 861                 case ANTENNA_A:\r
 862                 default:\r
 863                         rfPath = RF_PATH_A;\r
 864                         break;\r
 865                 case ANTENNA_B:\r
 866                         rfPath = RF_PATH_B;\r
 867                         break;\r
 868                 case ANTENNA_C:\r
 869                         rfPath = RF_PATH_C;\r
 870                         break;\r
 871         }\r
 872 \r
 873         pAdapter->mppriv.MptCtx.bSingleTone = bStart;\r
 874         if (bStart)// Start Single Tone.\r
 875         {\r
 876                 RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleToneTx: test start\n"));\r
 877                 {   // <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)\r
 878             if (IS_HARDWARE_TYPE_8188E(pAdapter)) \r
 879             {\r
 880                 reg58 = PHY_QueryRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask);\r
 881                 reg58 &= 0xFFFFFFF0;\r
 882                 reg58 += 2;\r
 883                 PHY_SetRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask, reg58);\r
 884             }\r
 885                 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);\r
 886                 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);\r
 887         }\r
 888 \r
 889                 if (is92C)\r
 890                  {\r
 891                         _write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x01);\r
 892                         rtw_usleep_os(100);\r
 893                         if (rfPath == RF_PATH_A)\r
 894                                 write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x10000); // PAD all on.\r
 895                         else if (rfPath == RF_PATH_B)\r
 896                                 write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x10000); // PAD all on.\r
 897                         write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); // PAD all on.\r
 898                         rtw_usleep_os(100);\r
 899                 } \r
 900                 else\r
 901                 {\r
 902                         write_rfreg(pAdapter, rfPath, 0x21, 0xd4000);\r
 903                         rtw_usleep_os(100);\r
 904                         write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); // PAD all on.\r
 905                         rtw_usleep_os(100);\r
 906                 }\r
 907 \r
 908                 //for dynamic set Power index.\r
 909                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);\r
 910                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);\r
 911                 \r
 912         }\r
 913         else// Stop Single Tone.\r
 914         {\r
 915                         RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleToneTx: test stop\n"));\r
 916                         \r
 917                 {   // <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)\r
 918             // <20120326, Kordan> Only in single tone mode. (asked by Edlu)\r
 919             if (IS_HARDWARE_TYPE_8188E(pAdapter)) \r
 920             {\r
 921                 reg58 = PHY_QueryRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask);\r
 922                 reg58 &= 0xFFFFFFF0;\r
 923                 PHY_SetRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask, reg58);\r
 924             }\r
 925         \r
 926                 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);\r
 927                 write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);\r
 928                 }\r
 929                 if (is92C) {\r
 930                         _write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x00);\r
 931                         rtw_usleep_os(100);\r
 932                         write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x32d75); // PAD all on.\r
 933                         write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x32d75); // PAD all on.\r
 934                         rtw_usleep_os(100);\r
 935                 } else {\r
 936                         write_rfreg(pAdapter, rfPath, 0x21, 0x54000);\r
 937                         rtw_usleep_os(100);\r
 938                         write_rfreg(pAdapter, rfPath, 0x00, 0x30000); // PAD all on.\r
 939                         rtw_usleep_os(100);\r
 940                 }\r
 941 \r
 942                 //Stop for dynamic set Power index.\r
 943                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);\r
 944                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);\r
 945                 \r
 946         }\r
 947         \r
 948 }\r
 949 \r
 950 \r
 951 \r
 952 void Hal_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)\r
 953 {\r
 954         pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart;\r
 955         if (bStart) // Start Carrier Suppression.\r
 956         {\r
 957                 RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test start\n"));\r
 958                 //if(pMgntInfo->dot11CurrentWirelessMode == WIRELESS_MODE_B)\r
 959                 if (pAdapter->mppriv.rateidx <= MPT_RATE_11M)\r
 960                   {\r
 961                         // 1. if CCK block on?\r
 962                         if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))\r
 963                                 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);//set CCK block on\r
 964 \r
 965                         //Turn Off All Test Mode\r
 966                         write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);\r
 967                         write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);\r
 968                         write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);\r
 969 \r
 970                         write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);    //transmit mode\r
 971                         write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0);  //turn off scramble setting\r
 972 \r
 973                         //Set CCK Tx Test Rate\r
 974                         //PHY_SetBBReg(pAdapter, rCCK0_System, bCCKTxRate, pMgntInfo->ForcedDataRate);\r
 975                         write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0);    //Set FTxRate to 1Mbps\r
 976                 }\r
 977 \r
 978                 //for dynamic set Power index.\r
 979                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);\r
 980                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);\r
 981                 \r
 982         }\r
 983         else// Stop Carrier Suppression.\r
 984         {\r
 985                 RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test stop\n"));\r
 986                 //if(pMgntInfo->dot11CurrentWirelessMode == WIRELESS_MODE_B)\r
 987                 if (pAdapter->mppriv.rateidx <= MPT_RATE_11M ) {\r
 988                         write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);    //normal mode\r
 989                         write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1);  //turn on scramble setting\r
 990 \r
 991                         //BB Reset\r
 992                         write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);\r
 993                         write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);\r
 994                 }\r
 995 \r
 996                 //Stop for dynamic set Power index.\r
 997                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);\r
 998                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);\r
 999                 \r
1000         }\r
1001         //DbgPrint("\n MPT_ProSetCarrierSupp() is finished. \n");\r
1002 }\r
1003 \r
1004 void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart)\r
1005 {\r
1006         u32 cckrate;\r
1007 \r
1008         if (bStart)\r
1009         {\r
1010                 RT_TRACE(_module_mp_, _drv_alert_,\r
1011                          ("SetCCKContinuousTx: test start\n"));\r
1012 \r
1013                 // 1. if CCK block on?\r
1014                 if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))\r
1015                         write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);//set CCK block on\r
1016 \r
1017                 //Turn Off All Test Mode\r
1018                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);\r
1019                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);\r
1020                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);\r
1021                 //Set CCK Tx Test Rate\r
1022                 #if 0\r
1023                 switch(pAdapter->mppriv.rateidx)\r
1024                 {\r
1025                         case 2:\r
1026                                 cckrate = 0;\r
1027                                 break;\r
1028                         case 4:\r
1029                                 cckrate = 1;\r
1030                                 break;\r
1031                         case 11:\r
1032                                 cckrate = 2;\r
1033                                 break;\r
1034                         case 22:\r
1035                                 cckrate = 3;\r
1036                                 break;\r
1037                         default:\r
1038                                 cckrate = 0;\r
1039                                 break;\r
1040                 }\r
1041                 #else\r
1042                 cckrate  = pAdapter->mppriv.rateidx;\r
1043                 #endif\r
1044                 write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);\r
1045                 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);   //transmit mode\r
1046                 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);     //turn on scramble setting\r
1047 \r
1048 #ifdef CONFIG_RTL8192C\r
1049                 // Patch for CCK 11M waveform\r
1050                 if (cckrate == MPT_RATE_1M)\r
1051                         write_bbreg(pAdapter, 0xA71, BIT(6), bDisable);\r
1052                 else\r
1053                         write_bbreg(pAdapter, 0xA71, BIT(6), bEnable);\r
1054 #endif\r
1055                 //for dynamic set Power index.\r
1056                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);\r
1057                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);\r
1058 \r
1059         }\r
1060         else {\r
1061                 RT_TRACE(_module_mp_, _drv_info_,\r
1062                          ("SetCCKContinuousTx: test stop\n"));\r
1063 \r
1064                 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);   //normal mode\r
1065                 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);     //turn on scramble setting\r
1066 \r
1067                 //BB Reset\r
1068                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);\r
1069                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);\r
1070 \r
1071                 //Stop for dynamic set Power index.\r
1072                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);\r
1073                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);\r
1074         }\r
1075 \r
1076         pAdapter->mppriv.MptCtx.bCckContTx = bStart;\r
1077         pAdapter->mppriv.MptCtx.bOfdmContTx = _FALSE;\r
1078 }/* mpt_StartCckContTx */\r
1079 \r
1080 void Hal_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart)\r
1081 {\r
1082     HAL_DATA_TYPE       *pHalData = GET_HAL_DATA(pAdapter);\r
1083 \r
1084         if (bStart) {\r
1085                 RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test start\n"));\r
1086                 // 1. if OFDM block on?\r
1087                 if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))\r
1088                         write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);//set OFDM block on\r
1089         {\r
1090 \r
1091                 // 2. set CCK test mode off, set to CCK normal mode\r
1092                 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);\r
1093 \r
1094                 // 3. turn on scramble setting\r
1095                 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);\r
1096         }\r
1097                 // 4. Turn On Continue Tx and turn off the other test modes.\r
1098                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable);\r
1099                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);\r
1100                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);\r
1101 \r
1102                 //for dynamic set Power index.\r
1103                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);\r
1104                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);\r
1105                 \r
1106         } else {\r
1107                 RT_TRACE(_module_mp_,_drv_info_, ("SetOFDMContinuousTx: test stop\n"));\r
1108                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);\r
1109                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);\r
1110                 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);\r
1111                 //Delay 10 ms\r
1112                 rtw_msleep_os(10);\r
1113                 //BB Reset\r
1114                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);\r
1115                 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);\r
1116 \r
1117                 //Stop for dynamic set Power index.\r
1118                 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);\r
1119                 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);\r
1120         }\r
1121 \r
1122         pAdapter->mppriv.MptCtx.bCckContTx = _FALSE;\r
1123         pAdapter->mppriv.MptCtx.bOfdmContTx = bStart;\r
1124 }/* mpt_StartOfdmContTx */\r
1125 \r
1126 void Hal_SetContinuousTx(PADAPTER pAdapter, u8 bStart)\r
1127 {\r
1128 #if 0\r
1129         // ADC turn off [bit24-21] adc port0 ~ port1\r
1130         if (bStart) {\r
1131                 write_bbreg(pAdapter, rRx_Wait_CCCA, read_bbreg(pAdapter, rRx_Wait_CCCA) & 0xFE1FFFFF);\r
1132                 rtw_usleep_os(100);\r
1133         }\r
1134 #endif\r
1135         RT_TRACE(_module_mp_, _drv_info_,\r
1136                  ("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx));\r
1137 \r
1138         pAdapter->mppriv.MptCtx.bStartContTx = bStart;\r
1139         if (pAdapter->mppriv.rateidx <= MPT_RATE_11M)\r
1140         {\r
1141                 Hal_SetCCKContinuousTx(pAdapter, bStart);\r
1142         }\r
1143         else if ((pAdapter->mppriv.rateidx >= MPT_RATE_6M) &&\r
1144                  (pAdapter->mppriv.rateidx <= MPT_RATE_MCS15))\r
1145         {\r
1146                 Hal_SetOFDMContinuousTx(pAdapter, bStart);\r
1147         }\r
1148 #if 0\r
1149         // ADC turn on [bit24-21] adc port0 ~ port1\r
1150         if (!bStart) {\r
1151                 write_bbreg(pAdapter, rRx_Wait_CCCA, read_bbreg(pAdapter, rRx_Wait_CCCA) | 0x01E00000);\r
1152         }\r
1153 #endif\r
1154 }\r
1155 \r
1156 #endif // CONFIG_MP_INCLUDE\r
1157 \r