1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
23 #include "../odm_precomp.h"
25 #if (RTL8188E_SUPPORT == 1)
28 odm_ConfigRFReg_8188E(
32 IN ODM_RF_RADIO_PATH_E RF_PATH,
38 #ifdef CONFIG_LONG_DELAY_ISSUE
44 else if (Addr == 0xfd)
48 else if (Addr == 0xfc)
52 else if (Addr == 0xfb)
56 else if (Addr == 0xfa)
60 else if (Addr == 0xf9)
66 ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
67 // Add 1us delay between BB/RF register setting.
74 odm_ConfigRF_RadioA_8188E(
80 u4Byte content = 0x1000; // RF_Content: radioa_txt
81 u4Byte maskforPhySet= (u4Byte)(content&0xE000);
83 odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet);
85 ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data));
89 odm_ConfigRF_RadioB_8188E(
95 u4Byte content = 0x1001; // RF_Content: radiob_txt
96 u4Byte maskforPhySet= (u4Byte)(content&0xE000);
98 odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet);
100 ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data));
106 IN PDM_ODM_T pDM_Odm,
111 ODM_Write1Byte(pDM_Odm, Addr, Data);
112 ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data));
116 odm_ConfigBB_AGC_8188E(
117 IN PDM_ODM_T pDM_Odm,
123 ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
124 // Add 1us delay between BB/RF register setting.
127 ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data));
131 odm_ConfigBB_PHY_REG_PG_8188E(
132 IN PDM_ODM_T pDM_Odm,
142 #ifdef CONFIG_LONG_DELAY_ISSUE
148 else if (Addr == 0xfd){
151 else if (Addr == 0xfc){
154 else if (Addr == 0xfb){
157 else if (Addr == 0xfa){
160 else if (Addr == 0xf9){
164 ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data));
166 #if !(DM_ODM_SUPPORT_TYPE&ODM_AP)
167 PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data);
173 odm_ConfigBB_TXPWR_LMT_8188E(
174 IN PDM_ODM_T pDM_Odm,
175 IN pu1Byte Regulation,
177 IN pu1Byte Bandwidth,
178 IN pu1Byte RateSection,
181 IN pu1Byte PowerLimit
184 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
185 PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band,
186 Bandwidth, RateSection, RfPath, Channel, PowerLimit);
187 #elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
188 PHY_SetTxPowerLimit(pDM_Odm->Adapter, Regulation, Band,
189 Bandwidth, RateSection, RfPath, Channel, PowerLimit);
194 odm_ConfigBB_PHY_8188E(
195 IN PDM_ODM_T pDM_Odm,
202 #ifdef CONFIG_LONG_DELAY_ISSUE
208 else if (Addr == 0xfd){
211 else if (Addr == 0xfc){
214 else if (Addr == 0xfb){
217 else if (Addr == 0xfa){
220 else if (Addr == 0xf9){
225 pDM_Odm->RFCalibrateInfo.RegA24 = Data;
226 ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
228 // Add 1us delay between BB/RF register setting.
230 ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data));