drivers/net/wireless/rockchip_wlan/rtl8189es/hal/OUTSRC/odm.h

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *                                        \r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *\r
  19  ******************************************************************************/\r
  20 \r
  21 \r
  22 #ifndef __HALDMOUTSRC_H__\r
  23 #define __HALDMOUTSRC_H__\r
  24 \r
  25 //============================================================\r
  26 // Definition \r
  27 //============================================================\r
  28 //\r
  29 // 2011/09/22 MH Define all team supprt ability.\r
  30 //\r
  31 \r
  32 //\r
  33 // 2011/09/22 MH Define for all teams. Please Define the constan in your precomp header.\r
  34 //\r
  35 //#define               DM_ODM_SUPPORT_AP                       0\r
  36 //#define               DM_ODM_SUPPORT_ADSL                     0\r
  37 //#define               DM_ODM_SUPPORT_CE                       0\r
  38 //#define               DM_ODM_SUPPORT_MP                       1\r
  39 \r
  40 //\r
  41 // 2011/09/28 MH Define ODM SW team support flag.\r
  42 //\r
  43 \r
  44 \r
  45 \r
  46 //\r
  47 // Antenna Switch Relative Definition.\r
  48 //\r
  49 \r
  50 //\r
  51 // 20100503 Joseph:\r
  52 // Add new function SwAntDivCheck8192C().\r
  53 // This is the main function of Antenna diversity function before link.\r
  54 // Mainly, it just retains last scan result and scan again.\r
  55 // After that, it compares the scan result to see which one gets better RSSI.\r
  56 // It selects antenna with better receiving power and returns better scan result.\r
  57 //\r
  58 #define TP_MODE         0\r
  59 #define RSSI_MODE               1\r
  60 #define TRAFFIC_LOW     0\r
  61 #define TRAFFIC_HIGH    1\r
  62 \r
  63 \r
  64 //============================================================\r
  65 //3 Tx Power Tracking\r
  66 //3============================================================\r
  67 #define         DPK_DELTA_MAPPING_NUM   13\r
  68 #define         index_mapping_HP_NUM    15      \r
  69 #define OFDM_TABLE_SIZE         43\r
  70 #define CCK_TABLE_SIZE                  33\r
  71 #define TXSCALE_TABLE_SIZE              37\r
  72 #define TXPWR_TRACK_TABLE_SIZE  30\r
  73 #define DELTA_SWINGIDX_SIZE     30\r
  74 #define BAND_NUM                                4\r
  75 \r
  76 //============================================================\r
  77 //3 PSD Handler\r
  78 //3============================================================\r
  79 \r
  80 #define AFH_PSD         1       //0:normal PSD scan, 1: only do 20 pts PSD\r
  81 #define MODE_40M                0       //0:20M, 1:40M\r
  82 #define PSD_TH2         3  \r
  83 #define PSD_CHMIN               20   // Minimum channel number for BT AFH\r
  84 #define SIR_STEP_SIZE   3\r
  85 #define   Smooth_Size_1         5\r
  86 #define Smooth_TH_1     3\r
  87 #define   Smooth_Size_2         10\r
  88 #define Smooth_TH_2     4\r
  89 #define   Smooth_Size_3         20\r
  90 #define Smooth_TH_3     4\r
  91 #define   Smooth_Step_Size 5\r
  92 #define Adaptive_SIR    1\r
  93 #if(RTL8723_FPGA_VERIFICATION == 1)\r
  94 #define PSD_RESCAN              1\r
  95 #else\r
  96 #define PSD_RESCAN              4\r
  97 #endif\r
  98 #define PSD_SCAN_INTERVAL       700 //ms\r
  99 \r
 100 \r
 101 \r
 102 //8723A High Power IGI Setting\r
 103 #define         DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22\r
 104 #define                 DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28\r
 105 #define         DM_DIG_HIGH_PWR_THRESHOLD       0x3a\r
 106 #define         DM_DIG_LOW_PWR_THRESHOLD        0x14\r
 107 \r
 108 //ANT Test\r
 109 #define                 ANTTESTALL              0x00            //Ant A or B will be Testing   \r
 110 #define         ANTTESTA                0x01            //Ant A will be Testing \r
 111 #define         ANTTESTB                0x02            //Ant B will be testing\r
 112 \r
 113 // LPS define\r
 114 #define DM_DIG_FA_TH0_LPS                               4 //-> 4 in lps\r
 115 #define DM_DIG_FA_TH1_LPS                               15 //-> 15 lps\r
 116 #define DM_DIG_FA_TH2_LPS                               30 //-> 30 lps\r
 117 #define RSSI_OFFSET_DIG                                 0x05;\r
 118 \r
 119 \r
 120 \r
 121 //for 8723A Ant Definition--2012--06--07 due to different IC may be different ANT define\r
 122 #define         MAIN_ANT                1               //Ant A or Ant Main\r
 123 #define         AUX_ANT         2               //AntB or Ant Aux\r
 124 #define         MAX_ANT         3               // 3 for AP using\r
 125 \r
 126 \r
 127 //Antenna Diversity Type\r
 128 #define SW_ANTDIV       0\r
 129 #define HW_ANTDIV       1\r
 130 //============================================================\r
 131 // structure and define\r
 132 //============================================================\r
 133 \r
 134 //\r
 135 // 2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement.\r
 136 // We need to remove to other position???\r
 137 //\r
 138 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))\r
 139 typedef         struct rtl8192cd_priv {\r
 140         u1Byte          temp;\r
 141 \r
 142 }rtl8192cd_priv, *prtl8192cd_priv;\r
 143 #endif\r
 144 \r
 145 \r
 146 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
 147 typedef         struct _ADAPTER{\r
 148         u1Byte          temp;\r
 149         #ifdef AP_BUILD_WORKAROUND\r
 150         HAL_DATA_TYPE*          temp2;\r
 151         prtl8192cd_priv         priv;\r
 152         #endif\r
 153 }ADAPTER, *PADAPTER;\r
 154 #endif\r
 155 \r
 156 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)\r
 157 \r
 158 typedef         struct _WLAN_STA{\r
 159         u1Byte          temp;\r
 160 } WLAN_STA, *PRT_WLAN_STA;\r
 161 \r
 162 #endif\r
 163 \r
 164 typedef struct _Dynamic_Initial_Gain_Threshold_\r
 165 {\r
 166         u1Byte          Dig_Enable_Flag;\r
 167         u1Byte          Dig_Ext_Port_Stage;\r
 168         \r
 169         int                     RssiLowThresh;\r
 170         int                     RssiHighThresh;\r
 171 \r
 172         u4Byte          FALowThresh;\r
 173         u4Byte          FAHighThresh;\r
 174 \r
 175         u1Byte          CurSTAConnectState;\r
 176         u1Byte          PreSTAConnectState;\r
 177         u1Byte          CurMultiSTAConnectState;\r
 178 \r
 179         u1Byte          PreIGValue;\r
 180         u1Byte          CurIGValue;\r
 181         u1Byte          BT30_CurIGI;\r
 182         u1Byte          BackupIGValue;\r
 183 \r
 184         s1Byte          BackoffVal;\r
 185         s1Byte          BackoffVal_range_max;\r
 186         s1Byte          BackoffVal_range_min;\r
 187         u1Byte          rx_gain_range_max;\r
 188         u1Byte          rx_gain_range_min;\r
 189         u1Byte          Rssi_val_min;\r
 190 \r
 191         u1Byte          PreCCK_CCAThres;\r
 192         u1Byte          CurCCK_CCAThres;\r
 193         u1Byte          PreCCKPDState;\r
 194         u1Byte          CurCCKPDState;\r
 195 \r
 196         u1Byte          LargeFAHit;\r
 197         u1Byte          ForbiddenIGI;\r
 198         u4Byte          Recover_cnt;\r
 199 \r
 200         u1Byte          DIG_Dynamic_MIN_0;\r
 201         u1Byte          DIG_Dynamic_MIN_1;\r
 202         BOOLEAN         bMediaConnect_0;\r
 203         BOOLEAN         bMediaConnect_1;\r
 204 \r
 205         u4Byte          AntDiv_RSSI_max;\r
 206         u4Byte          RSSI_max;\r
 207 }DIG_T,*pDIG_T;\r
 208 \r
 209 typedef struct _Dynamic_Power_Saving_\r
 210 {\r
 211         u1Byte          PreCCAState;\r
 212         u1Byte          CurCCAState;\r
 213 \r
 214         u1Byte          PreRFState;\r
 215         u1Byte          CurRFState;\r
 216 \r
 217         int                 Rssi_val_min;\r
 218         \r
 219         u1Byte          initialize;\r
 220         u4Byte          Reg874,RegC70,Reg85C,RegA74;\r
 221         \r
 222 }PS_T,*pPS_T;\r
 223 \r
 224 typedef struct _FALSE_ALARM_STATISTICS{\r
 225         u4Byte  Cnt_Parity_Fail;\r
 226         u4Byte  Cnt_Rate_Illegal;\r
 227         u4Byte  Cnt_Crc8_fail;\r
 228         u4Byte  Cnt_Mcs_fail;\r
 229         u4Byte  Cnt_Ofdm_fail;\r
 230         u4Byte  Cnt_Cck_fail;\r
 231         u4Byte  Cnt_all;\r
 232         u4Byte  Cnt_Fast_Fsync;\r
 233         u4Byte  Cnt_SB_Search_fail;\r
 234         u4Byte  Cnt_OFDM_CCA;\r
 235         u4Byte  Cnt_CCK_CCA;\r
 236         u4Byte  Cnt_CCA_all;\r
 237         u4Byte  Cnt_BW_USC;     //Gary\r
 238         u4Byte  Cnt_BW_LSC;     //Gary\r
 239 }FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;\r
 240 \r
 241 typedef struct _Dynamic_Primary_CCA{\r
 242         u1Byte          PriCCA_flag;\r
 243         u1Byte          intf_flag;\r
 244         u1Byte          intf_type;  \r
 245         u1Byte          DupRTS_flag;\r
 246         u1Byte          Monitor_flag;\r
 247         u1Byte          CH_offset;\r
 248         u1Byte                  MF_state;\r
 249 }Pri_CCA_T, *pPri_CCA_T;\r
 250 \r
 251 typedef struct _Rate_Adaptive_Table_{\r
 252         u1Byte          firstconnect;\r
 253 }RA_T, *pRA_T;\r
 254 \r
 255 typedef struct _RX_High_Power_\r
 256 {\r
 257         u1Byte          RXHP_flag;\r
 258         u1Byte          PSD_func_trigger;\r
 259         u1Byte          PSD_bitmap_RXHP[80];\r
 260         u1Byte          Pre_IGI;\r
 261         u1Byte          Cur_IGI;\r
 262         u1Byte          Pre_pw_th;\r
 263         u1Byte          Cur_pw_th;\r
 264         BOOLEAN         First_time_enter;\r
 265         BOOLEAN         RXHP_enable;\r
 266         u1Byte          TP_Mode;\r
 267         RT_TIMER        PSDTimer;\r
 268 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)    \r
 269         #if USE_WORKITEM\r
 270         RT_WORK_ITEM            PSDTimeWorkitem;\r
 271         #endif\r
 272 #endif\r
 273 \r
 274 }RXHP_T, *pRXHP_T;\r
 275         \r
 276 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE))\r
 277 #define ASSOCIATE_ENTRY_NUM                                     32 // Max size of AsocEntry[].\r
 278 #define ODM_ASSOCIATE_ENTRY_NUM                         ASSOCIATE_ENTRY_NUM\r
 279 \r
 280 #elif(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
 281 #define ASSOCIATE_ENTRY_NUM                                     NUM_STAT\r
 282 #define ODM_ASSOCIATE_ENTRY_NUM                         ASSOCIATE_ENTRY_NUM+1\r
 283 \r
 284 #else\r
 285 //\r
 286 // 2012/01/12 MH Revise for compatiable with other SW team. \r
 287 // 0 is for STA 1-n is for AP clients.\r
 288 //\r
 289 #define ODM_ASSOCIATE_ENTRY_NUM                         ASSOCIATE_ENTRY_NUM+1// Default port only one\r
 290 #endif\r
 291 \r
 292 //#ifdef CONFIG_ANTENNA_DIVERSITY\r
 293 // This indicates two different the steps. \r
 294 // In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air.\r
 295 // In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK\r
 296 // with original RSSI to determine if it is necessary to switch antenna.\r
 297 #define SWAW_STEP_PEAK          0\r
 298 #define SWAW_STEP_DETERMINE     1\r
 299 \r
 300 #define TP_MODE         0\r
 301 #define RSSI_MODE               1\r
 302 #define TRAFFIC_LOW     0\r
 303 #define TRAFFIC_HIGH    1\r
 304 #define TRAFFIC_UltraLOW        2\r
 305 \r
 306 typedef struct _SW_Antenna_Switch_\r
 307 {\r
 308         u1Byte          Double_chk_flag;\r
 309         u1Byte          try_flag;\r
 310         s4Byte          PreRSSI;\r
 311         u1Byte          CurAntenna;\r
 312         u1Byte          PreAntenna;\r
 313         u1Byte          RSSI_Trying;\r
 314         u1Byte          TestMode;\r
 315         u1Byte          bTriggerAntennaSwitch;\r
 316         u1Byte          SelectAntennaMap;\r
 317         u1Byte          RSSI_target;    \r
 318         u1Byte          reset_idx;\r
 319 \r
 320         // Before link Antenna Switch check\r
 321         u1Byte          SWAS_NoLink_State;\r
 322         u4Byte          SWAS_NoLink_BK_Reg860;\r
 323         u4Byte          SWAS_NoLink_BK_Reg92c;\r
 324         BOOLEAN         ANTA_ON;        //To indicate Ant A is or not\r
 325         BOOLEAN         ANTB_ON;        //To indicate Ant B is on or not\r
 326         u1Byte          Ant5G;\r
 327         u1Byte          Ant2G;\r
 328 \r
 329         s4Byte          RSSI_sum_A;\r
 330         s4Byte          RSSI_sum_B;\r
 331         s4Byte          RSSI_cnt_A;\r
 332         s4Byte          RSSI_cnt_B;\r
 333 \r
 334         u8Byte          lastTxOkCnt;\r
 335         u8Byte          lastRxOkCnt;\r
 336         u8Byte          TXByteCnt_A;\r
 337         u8Byte          TXByteCnt_B;\r
 338         u8Byte          RXByteCnt_A;\r
 339         u8Byte          RXByteCnt_B;\r
 340         u1Byte          TrafficLoad;\r
 341         u1Byte          Train_time;\r
 342         u1Byte          Train_time_flag;\r
 343         RT_TIMER        SwAntennaSwitchTimer;\r
 344         RT_TIMER        SwAntennaSwitchTimer_8723B;\r
 345 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)    \r
 346         #if USE_WORKITEM\r
 347         RT_WORK_ITEM                    SwAntennaSwitchWorkitem;\r
 348         RT_WORK_ITEM                    SwAntennaSwitchWorkitem_8723B;\r
 349         #endif\r
 350 #endif\r
 351 /* CE Platform use\r
 352 #ifdef CONFIG_SW_ANTENNA_DIVERSITY\r
 353         _timer SwAntennaSwitchTimer; \r
 354         u8Byte lastTxOkCnt;\r
 355         u8Byte lastRxOkCnt;\r
 356         u8Byte TXByteCnt_A;\r
 357         u8Byte TXByteCnt_B;\r
 358         u8Byte RXByteCnt_A;\r
 359         u8Byte RXByteCnt_B;\r
 360         u1Byte DoubleComfirm;\r
 361         u1Byte TrafficLoad;\r
 362         //SW Antenna Switch\r
 363 \r
 364 \r
 365 #endif\r
 366 */\r
 367 #ifdef CONFIG_HW_ANTENNA_DIVERSITY\r
 368         //Hybrid Antenna Diversity\r
 369         u4Byte          CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM+1];\r
 370         u4Byte          CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM+1];\r
 371         u4Byte          OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM+1];\r
 372         u4Byte          OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM+1];\r
 373         u4Byte          RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM+1];\r
 374         u4Byte          RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM+1];\r
 375         u1Byte          TxAnt[ASSOCIATE_ENTRY_NUM+1];\r
 376         u1Byte          TargetSTA;\r
 377         u1Byte          antsel;\r
 378         u1Byte          RxIdleAnt;\r
 379 \r
 380 #endif\r
 381         \r
 382 }SWAT_T, *pSWAT_T;\r
 383 //#endif\r
 384 \r
 385 typedef struct _EDCA_TURBO_\r
 386 {\r
 387         BOOLEAN bCurrentTurboEDCA;\r
 388         BOOLEAN bIsCurRDLState;\r
 389 \r
 390         #if(DM_ODM_SUPPORT_TYPE == ODM_CE       )\r
 391         u4Byte  prv_traffic_idx; // edca turbo\r
 392         #endif\r
 393 \r
 394 }EDCA_T,*pEDCA_T;\r
 395 \r
 396 typedef struct _ODM_RATE_ADAPTIVE\r
 397 {\r
 398         u1Byte                          Type;                           // DM_Type_ByFW/DM_Type_ByDriver\r
 399         u1Byte                          LdpcThres;                      // if RSSI > LdpcThres => switch from LPDC to BCC\r
 400         BOOLEAN                         bUseLdpc;\r
 401         BOOLEAN                         bLowerRtsRate;\r
 402         u1Byte                          HighRSSIThresh;         // if RSSI > HighRSSIThresh     => RATRState is DM_RATR_STA_HIGH\r
 403         u1Byte                          LowRSSIThresh;          // if RSSI <= LowRSSIThresh     => RATRState is DM_RATR_STA_LOW\r
 404         u1Byte                          RATRState;                      // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW\r
 405 \r
 406 } ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE;\r
 407 \r
 408 \r
 409 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
 410 \r
 411 \r
 412 #ifdef ADSL_AP_BUILD_WORKAROUND\r
 413 #define MAX_TOLERANCE                   5\r
 414 #define IQK_DELAY_TIME                  1               //ms\r
 415 #endif\r
 416 \r
 417 //\r
 418 // Indicate different AP vendor for IOT issue.\r
 419 //\r
 420 typedef enum _HT_IOT_PEER\r
 421 {\r
 422         HT_IOT_PEER_UNKNOWN                     = 0,\r
 423         HT_IOT_PEER_REALTEK                     = 1,\r
 424         HT_IOT_PEER_REALTEK_92SE                = 2,\r
 425         HT_IOT_PEER_BROADCOM            = 3,\r
 426         HT_IOT_PEER_RALINK                      = 4,\r
 427         HT_IOT_PEER_ATHEROS                     = 5,\r
 428         HT_IOT_PEER_CISCO                               = 6,\r
 429         HT_IOT_PEER_MERU                                = 7,    \r
 430         HT_IOT_PEER_MARVELL                     = 8,\r
 431         HT_IOT_PEER_REALTEK_SOFTAP      = 9,// peer is RealTek SOFT_AP, by Bohn, 2009.12.17\r
 432         HT_IOT_PEER_SELF_SOFTAP                 = 10, // Self is SoftAP\r
 433         HT_IOT_PEER_AIRGO                               = 11,\r
 434         HT_IOT_PEER_INTEL                               = 12, \r
 435         HT_IOT_PEER_RTK_APCLIENT                = 13, \r
 436         HT_IOT_PEER_REALTEK_81XX                = 14,   \r
 437         HT_IOT_PEER_REALTEK_WOW                 = 15,   \r
 438         HT_IOT_PEER_MAX                                 = 16\r
 439 }HT_IOT_PEER_E, *PHTIOT_PEER_E;\r
 440 #endif//#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
 441 \r
 442 \r
 443 \r
 444 #define IQK_MAC_REG_NUM         4\r
 445 #define IQK_ADDA_REG_NUM                16\r
 446 #define IQK_BB_REG_NUM_MAX      10\r
 447 #if (RTL8192D_SUPPORT==1) \r
 448 #define IQK_BB_REG_NUM          10\r
 449 #else\r
 450 #define IQK_BB_REG_NUM          9\r
 451 #endif\r
 452 #define HP_THERMAL_NUM          8\r
 453 \r
 454 #define AVG_THERMAL_NUM         8\r
 455 #define IQK_Matrix_REG_NUM      8\r
 456 #define IQK_Matrix_Settings_NUM 14+24+21 // Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G\r
 457 \r
 458 #define         DM_Type_ByFW                    0\r
 459 #define         DM_Type_ByDriver                1\r
 460 \r
 461 //\r
 462 // Declare for common info\r
 463 //\r
 464 #define MAX_PATH_NUM_92CS               2\r
 465 #define MAX_PATH_NUM_8188E              1\r
 466 #define MAX_PATH_NUM_8192E              2\r
 467 #define MAX_PATH_NUM_8723B              1\r
 468 #define MAX_PATH_NUM_8812A              2\r
 469 #define MAX_PATH_NUM_8821A              1\r
 470 \r
 471 #define IQK_THRESHOLD                   8\r
 472 \r
 473 typedef struct _ODM_Phy_Status_Info_\r
 474 {\r
 475         //\r
 476         // Be care, if you want to add any element please insert between \r
 477         // RxPWDBAll & SignalStrength.\r
 478         //\r
 479 #if (DM_ODM_SUPPORT_TYPE &  (ODM_WIN))\r
 480         u4Byte          RxPWDBAll;      \r
 481 #else\r
 482         u1Byte          RxPWDBAll;      \r
 483 #endif\r
 484 \r
 485         u1Byte          SignalQuality;                  // in 0-100 index. \r
 486         s1Byte          RxMIMOSignalQuality[4]; //per-path's EVM\r
 487         u1Byte          RxMIMOEVMdbm[4];                //per-path's EVM dbm\r
 488 \r
 489         u1Byte          RxMIMOSignalStrength[4];// in 0~100 index\r
 490 \r
 491         u2Byte          Cfo_short[4];                   // per-path's Cfo_short\r
 492         u2Byte          Cfo_tail[4];                    // per-path's Cfo_tail\r
 493         \r
 494 #if (DM_ODM_SUPPORT_TYPE &  (ODM_WIN|ODM_CE))\r
 495         s1Byte          RxPower;                                // in dBm Translate from PWdB\r
 496         s1Byte          RecvSignalPower;                // Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures.\r
 497         u1Byte          BTRxRSSIPercentage;     \r
 498         u1Byte          SignalStrength;                 // in 0-100 index.\r
 499  \r
 500         s1Byte          RxPwr[4];                               //per-path's pwdb\r
 501 #endif\r
 502         u1Byte          RxSNR[4];                               //per-path's SNR        \r
 503         u1Byte          BandWidth;\r
 504         u1Byte          btCoexPwrAdjust;\r
 505 }ODM_PHY_INFO_T,*PODM_PHY_INFO_T;\r
 506 \r
 507 \r
 508 typedef struct _ODM_Per_Pkt_Info_\r
 509 {\r
 510         //u1Byte                Rate;   \r
 511         u1Byte          DataRate;\r
 512         u1Byte          StationID;\r
 513         BOOLEAN         bPacketMatchBSSID;\r
 514         BOOLEAN         bPacketToSelf;\r
 515         BOOLEAN         bPacketBeacon;\r
 516 }ODM_PACKET_INFO_T,*PODM_PACKET_INFO_T;\r
 517 \r
 518 \r
 519 typedef struct _ODM_Phy_Dbg_Info_\r
 520 {\r
 521         //ODM Write,debug info\r
 522         s1Byte          RxSNRdB[4];\r
 523         u8Byte          NumQryPhyStatus;\r
 524         u8Byte          NumQryPhyStatusCCK;\r
 525         u8Byte          NumQryPhyStatusOFDM;\r
 526         u1Byte          NumQryBeaconPkt;\r
 527         //Others\r
 528         s4Byte          RxEVM[4];       \r
 529         \r
 530 }ODM_PHY_DBG_INFO_T;\r
 531 \r
 532 \r
 533 typedef struct _ODM_Mac_Status_Info_\r
 534 {\r
 535         u1Byte  test;\r
 536         \r
 537 }ODM_MAC_INFO;\r
 538 \r
 539 \r
 540 typedef enum tag_Dynamic_ODM_Support_Ability_Type\r
 541 {\r
 542         // BB Team\r
 543         ODM_DIG                         = 0x00000001,\r
 544         ODM_HIGH_POWER          = 0x00000002,\r
 545         ODM_CCK_CCA_TH          = 0x00000004,\r
 546         ODM_FA_STATISTICS               = 0x00000008,\r
 547         ODM_RAMASK                      = 0x00000010,\r
 548         ODM_RSSI_MONITOR                = 0x00000020,\r
 549         ODM_SW_ANTDIV           = 0x00000040,\r
 550         ODM_HW_ANTDIV           = 0x00000080,\r
 551         ODM_BB_PWRSV                    = 0x00000100,\r
 552         ODM_2TPATHDIV                   = 0x00000200,\r
 553         ODM_1TPATHDIV                   = 0x00000400,\r
 554         ODM_PSD2AFH                     = 0x00000800\r
 555 }ODM_Ability_E;\r
 556 \r
 557 //\r
 558 // 2011/20/20 MH For MP driver RT_WLAN_STA =  STA_INFO_T\r
 559 // Please declare below ODM relative info in your STA info structure.\r
 560 //\r
 561 #if 1\r
 562 typedef         struct _ODM_STA_INFO{\r
 563         // Driver Write\r
 564         BOOLEAN         bUsed;                          // record the sta status link or not?\r
 565         //u1Byte                WirelessMode;           // \r
 566         u1Byte          IOTPeer;                        // Enum value.  HT_IOT_PEER_E\r
 567 \r
 568         // ODM Write\r
 569         //1 PHY_STATUS_INFO\r
 570         u1Byte          RSSI_Path[4];           // \r
 571         u1Byte          RSSI_Ave;\r
 572         u1Byte          RXEVM[4];\r
 573         u1Byte          RXSNR[4];\r
 574 \r
 575         // ODM Write\r
 576         //1 TX_INFO (may changed by IC)\r
 577         //TX_INFO_T             pTxInfo;                                // Define in IC folder. Move lower layer.\r
 578 #if 0\r
 579         u1Byte          ANTSEL_A;                       //in Jagar: 4bit; others: 2bit\r
 580         u1Byte          ANTSEL_B;                       //in Jagar: 4bit; others: 2bit\r
 581         u1Byte          ANTSEL_C;                       //only in Jagar: 4bit\r
 582         u1Byte          ANTSEL_D;                       //only in Jagar: 4bit\r
 583         u1Byte          TX_ANTL;                        //not in Jagar: 2bit\r
 584         u1Byte          TX_ANT_HT;                      //not in Jagar: 2bit\r
 585         u1Byte          TX_ANT_CCK;                     //not in Jagar: 2bit\r
 586         u1Byte          TXAGC_A;                        //not in Jagar: 4bit\r
 587         u1Byte          TXAGC_B;                        //not in Jagar: 4bit\r
 588         u1Byte          TXPWR_OFFSET;           //only in Jagar: 3bit\r
 589         u1Byte          TX_ANT;                         //only in Jagar: 4bit for TX_ANTL/TX_ANTHT/TX_ANT_CCK\r
 590 #endif\r
 591 \r
 592         //\r
 593         //      Please use compile flag to disabe the strcutrue for other IC except 88E.\r
 594         //      Move To lower layer.\r
 595         //\r
 596         // ODM Write Wilson will handle this part(said by Luke.Lee)\r
 597         //TX_RPT_T              pTxRpt;                         // Define in IC folder. Move lower layer.\r
 598 #if 0   \r
 599         //1 For 88E RA (don't redefine the naming)\r
 600         u1Byte          rate_id;\r
 601         u1Byte          rate_SGI;\r
 602         u1Byte          rssi_sta_ra;\v\r
 603         u1Byte          SGI_enable;\r
 604         u1Byte          Decision_rate;\r
 605         u1Byte          Pre_rate;\r
 606         u1Byte          Active;\r
 607 \r
 608         // Driver write Wilson handle.\r
 609         //1 TX_RPT (don't redefine the naming)\r
 610         u2Byte          RTY[4];                         // ???\r
 611         u2Byte          TOTAL;                          // ???\r
 612         u2Byte          DROP;                           // ???\r
 613         //\r
 614         // Please use compile flag to disabe the strcutrue for other IC except 88E.\r
 615         //\r
 616 #endif\r
 617 \r
 618 }ODM_STA_INFO_T, *PODM_STA_INFO_T;\r
 619 #endif\r
 620 \r
 621 //\r
 622 // 2011/10/20 MH Define Common info enum for all team.\r
 623 //\r
 624 typedef enum _ODM_Common_Info_Definition\r
 625 {\r
 626 //-------------REMOVED CASE-----------//\r
 627         //ODM_CMNINFO_CCK_HP,\r
 628         //ODM_CMNINFO_RFPATH_ENABLE,            // Define as ODM write???       \r
 629         //ODM_CMNINFO_BT_COEXIST,                               // ODM_BT_COEXIST_E\r
 630         //ODM_CMNINFO_OP_MODE,                          // ODM_OPERATION_MODE_E\r
 631 //-------------REMOVED CASE-----------//\r
 632 \r
 633         //\r
 634         // Fixed value:\r
 635         //\r
 636 \r
 637         //-----------HOOK BEFORE REG INIT-----------//\r
 638         ODM_CMNINFO_PLATFORM = 0,\r
 639         ODM_CMNINFO_ABILITY,                                    // ODM_ABILITY_E\r
 640         ODM_CMNINFO_INTERFACE,                          // ODM_INTERFACE_E\r
 641         ODM_CMNINFO_MP_TEST_CHIP,\r
 642         ODM_CMNINFO_IC_TYPE,                                    // ODM_IC_TYPE_E\r
 643         ODM_CMNINFO_CUT_VER,                                    // ODM_CUT_VERSION_E\r
 644         ODM_CMNINFO_FAB_VER,                                    // ODM_FAB_E\r
 645         ODM_CMNINFO_RF_TYPE,                                    // ODM_RF_PATH_E or ODM_RF_TYPE_E?\r
 646         ODM_CMNINFO_RFE_TYPE, \r
 647         ODM_CMNINFO_BOARD_TYPE,                         // ODM_BOARD_TYPE_E\r
 648         ODM_CMNINFO_PACKAGE_TYPE,\r
 649         ODM_CMNINFO_EXT_LNA,                                    // TRUE\r
 650         ODM_CMNINFO_5G_EXT_LNA, \r
 651         ODM_CMNINFO_EXT_PA,\r
 652         ODM_CMNINFO_5G_EXT_PA,\r
 653         ODM_CMNINFO_GPA,\r
 654         ODM_CMNINFO_APA,\r
 655         ODM_CMNINFO_GLNA,\r
 656         ODM_CMNINFO_ALNA,\r
 657         ODM_CMNINFO_EXT_TRSW,\r
 658         ODM_CMNINFO_PATCH_ID,                           //CUSTOMER ID\r
 659         ODM_CMNINFO_BINHCT_TEST,\r
 660         ODM_CMNINFO_BWIFI_TEST,\r
 661         ODM_CMNINFO_SMART_CONCURRENT,\r
 662         //-----------HOOK BEFORE REG INIT-----------//  \r
 663 \r
 664 \r
 665         //\r
 666         // Dynamic value:\r
 667         //\r
 668 //--------- POINTER REFERENCE-----------//\r
 669         ODM_CMNINFO_MAC_PHY_MODE,                       // ODM_MAC_PHY_MODE_E\r
 670         ODM_CMNINFO_TX_UNI,\r
 671         ODM_CMNINFO_RX_UNI,\r
 672         ODM_CMNINFO_WM_MODE,                            // ODM_WIRELESS_MODE_E\r
 673         ODM_CMNINFO_BAND,                                       // ODM_BAND_TYPE_E\r
 674         ODM_CMNINFO_SEC_CHNL_OFFSET,            // ODM_SEC_CHNL_OFFSET_E\r
 675         ODM_CMNINFO_SEC_MODE,                           // ODM_SECURITY_E\r
 676         ODM_CMNINFO_BW,                                         // ODM_BW_E\r
 677         ODM_CMNINFO_CHNL,\r
 678         ODM_CMNINFO_FORCED_RATE,\r
 679         \r
 680         ODM_CMNINFO_DMSP_GET_VALUE,\r
 681         ODM_CMNINFO_BUDDY_ADAPTOR,\r
 682         ODM_CMNINFO_DMSP_IS_MASTER,\r
 683         ODM_CMNINFO_SCAN,\r
 684         ODM_CMNINFO_POWER_SAVING,\r
 685         ODM_CMNINFO_ONE_PATH_CCA,                       // ODM_CCA_PATH_E\r
 686         ODM_CMNINFO_DRV_STOP,\r
 687         ODM_CMNINFO_PNP_IN,\r
 688         ODM_CMNINFO_INIT_ON,\r
 689         ODM_CMNINFO_ANT_TEST,\r
 690         ODM_CMNINFO_NET_CLOSED,\r
 691         ODM_CMNINFO_MP_MODE,\r
 692         //ODM_CMNINFO_RTSTA_AID,                                // For win driver only?\r
 693         ODM_CMNINFO_FORCED_IGI_LB,\r
 694 //--------- POINTER REFERENCE-----------//\r
 695 \r
 696 //------------CALL BY VALUE-------------//\r
 697         ODM_CMNINFO_WIFI_DIRECT,\r
 698         ODM_CMNINFO_WIFI_DISPLAY,\r
 699         ODM_CMNINFO_LINK_IN_PROGRESS,                   \r
 700         ODM_CMNINFO_LINK,\r
 701         ODM_CMNINFO_STATION_STATE,\r
 702         ODM_CMNINFO_RSSI_MIN,\r
 703         ODM_CMNINFO_DBG_COMP,                           // u8Byte\r
 704         ODM_CMNINFO_DBG_LEVEL,                          // u4Byte\r
 705         ODM_CMNINFO_RA_THRESHOLD_HIGH,          // u1Byte\r
 706         ODM_CMNINFO_RA_THRESHOLD_LOW,           // u1Byte\r
 707         ODM_CMNINFO_RF_ANTENNA_TYPE,            // u1Byte\r
 708         ODM_CMNINFO_BT_DISABLED,\r
 709         ODM_CMNINFO_BT_HS_CONNECT_PROCESS,\r
 710         ODM_CMNINFO_BT_HS_RSSI,\r
 711         ODM_CMNINFO_BT_OPERATION,\r
 712         ODM_CMNINFO_BT_LIMITED_DIG,                                     //Need to Limited Dig or not\r
 713         ODM_CMNINFO_BT_DISABLE_EDCA,\r
 714 //------------CALL BY VALUE-------------//\r
 715 \r
 716         //\r
 717         // Dynamic ptr array hook itms.\r
 718         //\r
 719         ODM_CMNINFO_STA_STATUS,\r
 720         ODM_CMNINFO_PHY_STATUS,\r
 721         ODM_CMNINFO_MAC_STATUS,\r
 722         \r
 723         ODM_CMNINFO_MAX,\r
 724 \r
 725 \r
 726 }ODM_CMNINFO_E;\r
 727 \r
 728 //\r
 729 // 2011/10/20 MH Define ODM support ability.  ODM_CMNINFO_ABILITY\r
 730 //\r
 731 typedef enum _ODM_Support_Ability_Definition\r
 732 {\r
 733         //\r
 734         // BB ODM section BIT 0-15\r
 735         //\r
 736         ODM_BB_DIG                                      = BIT0,\r
 737         ODM_BB_RA_MASK                          = BIT1,\r
 738         ODM_BB_DYNAMIC_TXPWR            = BIT2,\r
 739         ODM_BB_FA_CNT                                   = BIT3,\r
 740         ODM_BB_RSSI_MONITOR                     = BIT4,\r
 741         ODM_BB_CCK_PD                                   = BIT5,\r
 742         ODM_BB_ANT_DIV                          = BIT6,\r
 743         ODM_BB_PWR_SAVE                         = BIT7,\r
 744         ODM_BB_PWR_TRAIN                                = BIT8,\r
 745         ODM_BB_RATE_ADAPTIVE                    = BIT9,\r
 746         ODM_BB_PATH_DIV                         = BIT10,\r
 747         ODM_BB_PSD                                      = BIT11,\r
 748         ODM_BB_RXHP                                     = BIT12,\r
 749         ODM_BB_ADAPTIVITY                               = BIT13,\r
 750         ODM_BB_DYNAMIC_ATC                      = BIT14,\r
 751         \r
 752         //\r
 753         // MAC DM section BIT 16-23\r
 754         //\r
 755         ODM_MAC_EDCA_TURBO                      = BIT16,\r
 756         ODM_MAC_EARLY_MODE                      = BIT17,\r
 757         \r
 758         //\r
 759         // RF ODM section BIT 24-31\r
 760         //\r
 761         ODM_RF_TX_PWR_TRACK                     = BIT24,\r
 762         ODM_RF_RX_GAIN_TRACK                    = BIT25,\r
 763         ODM_RF_CALIBRATION                              = BIT26,\r
 764         \r
 765 }ODM_ABILITY_E;\r
 766 \r
 767 //      ODM_CMNINFO_INTERFACE\r
 768 typedef enum tag_ODM_Support_Interface_Definition\r
 769 {\r
 770         ODM_ITRF_PCIE   =       0x1,\r
 771         ODM_ITRF_USB    =       0x2,\r
 772         ODM_ITRF_SDIO   =       0x4,\r
 773         ODM_ITRF_ALL    =       0x7,\r
 774 }ODM_INTERFACE_E;\r
 775 \r
 776 // ODM_CMNINFO_IC_TYPE\r
 777 typedef enum tag_ODM_Support_IC_Type_Definition\r
 778 {\r
 779         ODM_RTL8192S    =       BIT0,\r
 780         ODM_RTL8192C    =       BIT1,\r
 781         ODM_RTL8192D    =       BIT2,\r
 782         ODM_RTL8723A    =       BIT3,\r
 783         ODM_RTL8188E    =       BIT4,\r
 784         ODM_RTL8812     =       BIT5,\r
 785         ODM_RTL8821     =       BIT6,\r
 786         ODM_RTL8192E    =       BIT7,   \r
 787         ODM_RTL8723B    =       BIT8,\r
 788         ODM_RTL8813A    =       BIT9,   \r
 789         ODM_RTL8881A    =       BIT10\r
 790 }ODM_IC_TYPE_E;\r
 791 \r
 792 #define ODM_IC_11N_SERIES               (ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B)\r
 793 #define ODM_IC_11AC_SERIES              (ODM_RTL8812|ODM_RTL8821|ODM_RTL8813A|ODM_RTL8881A)\r
 794 \r
 795 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)\r
 796 #ifdef RTK_AC_SUPPORT\r
 797 #define ODM_IC_11AC_SERIES_SUPPORT              1\r
 798 #else\r
 799 #define ODM_IC_11AC_SERIES_SUPPORT              0\r
 800 #endif\r
 801 #else\r
 802 #define ODM_IC_11AC_SERIES_SUPPORT              1\r
 803 #endif\r
 804 \r
 805 //ODM_CMNINFO_CUT_VER\r
 806 typedef enum tag_ODM_Cut_Version_Definition\r
 807 {\r
 808         ODM_CUT_A               =       0,\r
 809         ODM_CUT_B               =       1,\r
 810         ODM_CUT_C               =       2,\r
 811         ODM_CUT_D               =       3,\r
 812         ODM_CUT_E               =       4,\r
 813         ODM_CUT_F               =       5,\r
 814 \r
 815         ODM_CUT_I               =       8,\r
 816         ODM_CUT_TEST    =       15,\r
 817 }ODM_CUT_VERSION_E;\r
 818 \r
 819 // ODM_CMNINFO_FAB_VER\r
 820 typedef enum tag_ODM_Fab_Version_Definition\r
 821 {\r
 822         ODM_TSMC        =       0,\r
 823         ODM_UMC         =       1,\r
 824 }ODM_FAB_E;\r
 825 \r
 826 // ODM_CMNINFO_RF_TYPE\r
 827 //\r
 828 // For example 1T2R (A+AB = BIT0|BIT4|BIT5)\r
 829 //\r
 830 typedef enum tag_ODM_RF_Path_Bit_Definition\r
 831 {\r
 832         ODM_RF_TX_A     =       BIT0,\r
 833         ODM_RF_TX_B     =       BIT1,\r
 834         ODM_RF_TX_C     =       BIT2,\r
 835         ODM_RF_TX_D     =       BIT3,\r
 836         ODM_RF_RX_A     =       BIT4,\r
 837         ODM_RF_RX_B     =       BIT5,\r
 838         ODM_RF_RX_C     =       BIT6,\r
 839         ODM_RF_RX_D     =       BIT7,\r
 840 }ODM_RF_PATH_E;\r
 841 \r
 842 \r
 843 typedef enum tag_ODM_RF_Type_Definition\r
 844 {\r
 845         ODM_1T1R        =       0,\r
 846         ODM_1T2R        =       1,\r
 847         ODM_2T2R        =       2,\r
 848         ODM_2T3R        =       3,\r
 849         ODM_2T4R        =       4,\r
 850         ODM_3T3R        =       5,\r
 851         ODM_3T4R        =       6,\r
 852         ODM_4T4R        =       7,\r
 853 }ODM_RF_TYPE_E;\r
 854 \r
 855 \r
 856 //\r
 857 // ODM Dynamic common info value definition\r
 858 //\r
 859 \r
 860 //typedef enum _MACPHY_MODE_8192D{\r
 861 //      SINGLEMAC_SINGLEPHY,\r
 862 //      DUALMAC_DUALPHY,\r
 863 //      DUALMAC_SINGLEPHY,\r
 864 //}MACPHY_MODE_8192D,*PMACPHY_MODE_8192D;\r
 865 // Above is the original define in MP driver. Please use the same define. THX.\r
 866 typedef enum tag_ODM_MAC_PHY_Mode_Definition\r
 867 {\r
 868         ODM_SMSP        = 0,\r
 869         ODM_DMSP        = 1,\r
 870         ODM_DMDP        = 2,\r
 871 }ODM_MAC_PHY_MODE_E;\r
 872 \r
 873 \r
 874 typedef enum tag_BT_Coexist_Definition\r
 875 {       \r
 876         ODM_BT_BUSY             = 1,\r
 877         ODM_BT_ON                       = 2,\r
 878         ODM_BT_OFF              = 3,\r
 879         ODM_BT_NONE             = 4,\r
 880 }ODM_BT_COEXIST_E;\r
 881 \r
 882 // ODM_CMNINFO_OP_MODE\r
 883 typedef enum tag_Operation_Mode_Definition\r
 884 {\r
 885         ODM_NO_LINK             = BIT0,\r
 886         ODM_LINK                        = BIT1,\r
 887         ODM_SCAN                        = BIT2,\r
 888         ODM_POWERSAVE   = BIT3,\r
 889         ODM_AP_MODE             = BIT4,\r
 890         ODM_CLIENT_MODE = BIT5,\r
 891         ODM_AD_HOC              = BIT6,\r
 892         ODM_WIFI_DIRECT = BIT7,\r
 893         ODM_WIFI_DISPLAY        = BIT8,\r
 894 }ODM_OPERATION_MODE_E;\r
 895 \r
 896 // ODM_CMNINFO_WM_MODE\r
 897 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_CE))\r
 898 typedef enum tag_Wireless_Mode_Definition\r
 899 {\r
 900         ODM_WM_UNKNOW     = 0x0,\r
 901         ODM_WM_B                  = BIT0,\r
 902         ODM_WM_G                  = BIT1,\r
 903         ODM_WM_A                  = BIT2,\r
 904         ODM_WM_N24G           = BIT3,\r
 905         ODM_WM_N5G             = BIT4,\r
 906         ODM_WM_AUTO           = BIT5,\r
 907         ODM_WM_AC                = BIT6,\r
 908 }ODM_WIRELESS_MODE_E;\r
 909 #else\r
 910 typedef enum tag_Wireless_Mode_Definition\r
 911 {\r
 912         ODM_WM_UNKNOWN  = 0x00,\r
 913         ODM_WM_A                        = BIT0,\r
 914         ODM_WM_B                        = BIT1,\r
 915         ODM_WM_G                        = BIT2,\r
 916         ODM_WM_AUTO             = BIT3,\r
 917         ODM_WM_N24G             = BIT4,\r
 918         ODM_WM_N5G              = BIT5,\r
 919         ODM_WM_AC_5G    = BIT6,\r
 920         ODM_WM_AC_24G   = BIT7,\r
 921         ODM_WM_AC_ONLY          = BIT8,\r
 922         ODM_WM_MAX              = BIT9\r
 923 }ODM_WIRELESS_MODE_E;\r
 924 #endif\r
 925 \r
 926 // ODM_CMNINFO_BAND\r
 927 typedef enum tag_Band_Type_Definition\r
 928 {\r
 929     ODM_BAND_2_4G = 0,\r
 930     ODM_BAND_5G,\r
 931     ODM_BAND_ON_BOTH,\r
 932     ODM_BANDMAX\r
 933 \r
 934 }ODM_BAND_TYPE_E;\r
 935 \r
 936 // ODM_CMNINFO_SEC_CHNL_OFFSET\r
 937 typedef enum tag_Secondary_Channel_Offset_Definition\r
 938 {\r
 939         ODM_DONT_CARE   = 0,\r
 940         ODM_BELOW               = 1,\r
 941         ODM_ABOVE                       = 2\r
 942 }ODM_SEC_CHNL_OFFSET_E;\r
 943 \r
 944 // ODM_CMNINFO_SEC_MODE\r
 945 typedef enum tag_Security_Definition\r
 946 {\r
 947         ODM_SEC_OPEN                    = 0,\r
 948         ODM_SEC_WEP40           = 1,\r
 949         ODM_SEC_TKIP                    = 2,\r
 950         ODM_SEC_RESERVE                 = 3,\r
 951         ODM_SEC_AESCCMP                 = 4,\r
 952         ODM_SEC_WEP104          = 5,\r
 953         ODM_WEP_WPA_MIXED    = 6, // WEP + WPA\r
 954         ODM_SEC_SMS4                    = 7,\r
 955 }ODM_SECURITY_E;\r
 956 \r
 957 // ODM_CMNINFO_BW\r
 958 typedef enum tag_Bandwidth_Definition\r
 959 {       \r
 960         ODM_BW20M               = 0,\r
 961         ODM_BW40M               = 1,\r
 962         ODM_BW80M               = 2,\r
 963         ODM_BW160M              = 3,\r
 964         ODM_BW10M               = 4,\r
 965 }ODM_BW_E;\r
 966 \r
 967 \r
 968 // ODM_CMNINFO_BOARD_TYPE\r
 969 // For non-AC-series IC , ODM_BOARD_5G_EXT_PA and ODM_BOARD_5G_EXT_LNA are ignored\r
 970 // For AC-series IC, external PA & LNA can be indivisuallly added on 2.4G and/or 5G \r
 971 typedef enum tag_Board_Definition\r
 972 {\r
 973     ODM_BOARD_DEFAULT   = 0,      // The DEFAULT case.\r
 974     ODM_BOARD_MINICARD  = BIT(0), // 0 = non-mini card, 1= mini card.\r
 975     ODM_BOARD_SLIM      = BIT(1), // 0 = non-slim card, 1 = slim card\r
 976     ODM_BOARD_BT        = BIT(2), // 0 = without BT card, 1 = with BT\r
 977     ODM_BOARD_EXT_PA    = BIT(3), // 0 = no 2G ext-PA, 1 = existing 2G ext-PA\r
 978     ODM_BOARD_EXT_LNA   = BIT(4), // 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA\r
 979     ODM_BOARD_EXT_TRSW  = BIT(5), // 0 = no ext-TRSW, 1 = existing ext-TRSW\r
 980     ODM_BOARD_EXT_PA_5G = BIT(6), // 0 = no 5G ext-PA, 1 = existing 5G ext-PA\r
 981     ODM_BOARD_EXT_LNA_5G= BIT(7), // 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA\r
 982 }ODM_BOARD_TYPE_E;\r
 983 \r
 984 typedef enum tag_ODM_Package_Definition\r
 985 {\r
 986     ODM_PACKAGE_DEFAULT          = 0,     \r
 987     ODM_PACKAGE_QFN68        = BIT(0), \r
 988     ODM_PACKAGE_TFBGA90      = BIT(1), \r
 989     ODM_PACKAGE_TFBGA79      = BIT(2),  \r
 990 }ODM_Package_TYPE_E;\r
 991 \r
 992 typedef enum tag_ODM_TYPE_GPA_Definition\r
 993 {\r
 994     TYPE_GPA0 = 0,        \r
 995     TYPE_GPA1 = BIT(1)|BIT(0)\r
 996 }ODM_TYPE_GPA_E;\r
 997 \r
 998 typedef enum tag_ODM_TYPE_APA_Definition\r
 999 {\r
1000     TYPE_APA0 = 0,        \r
1001     TYPE_APA1 = BIT(1)|BIT(0)\r
1002 }ODM_TYPE_APA_E;\r
1003 \r
1004 typedef enum tag_ODM_TYPE_GLNA_Definition\r
1005 {\r
1006     TYPE_GLNA0 = 0,       \r
1007     TYPE_GLNA1 = BIT(2)|BIT(0),\r
1008     TYPE_GLNA2 = BIT(3)|BIT(1),\r
1009     TYPE_GLNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0)\r
1010 }ODM_TYPE_GLNA_E;\r
1011 \r
1012 typedef enum tag_ODM_TYPE_ALNA_Definition\r
1013 {\r
1014     TYPE_ALNA0 = 0,       \r
1015     TYPE_ALNA1 = BIT(2)|BIT(0),\r
1016     TYPE_ALNA2 = BIT(3)|BIT(1),\r
1017     TYPE_ALNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0)\r
1018 }ODM_TYPE_ALNA_E;\r
1019 \r
1020 // ODM_CMNINFO_ONE_PATH_CCA\r
1021 typedef enum tag_CCA_Path\r
1022 {\r
1023         ODM_CCA_2R                      = 0,\r
1024         ODM_CCA_1R_A            = 1,\r
1025         ODM_CCA_1R_B            = 2,\r
1026 }ODM_CCA_PATH_E;\r
1027 \r
1028 \r
1029 typedef struct _ODM_RA_Info_\r
1030 {\r
1031         u1Byte RateID;\r
1032         u4Byte RateMask;\r
1033         u4Byte RAUseRate;\r
1034         u1Byte RateSGI;\r
1035         u1Byte RssiStaRA;\r
1036         u1Byte PreRssiStaRA;\r
1037         u1Byte SGIEnable;\r
1038         u1Byte DecisionRate;\r
1039         u1Byte PreRate;\r
1040         u1Byte HighestRate;\r
1041         u1Byte LowestRate;\r
1042         u4Byte NscUp;\r
1043         u4Byte NscDown;\r
1044         u2Byte RTY[5];\r
1045         u4Byte TOTAL;\r
1046         u2Byte DROP;\r
1047         u1Byte Active;\r
1048         u2Byte RptTime;\r
1049         u1Byte RAWaitingCounter;\r
1050         u1Byte RAPendingCounter;        \r
1051 #if 1 //POWER_TRAINING_ACTIVE == 1 // For compile  pass only~!\r
1052         u1Byte PTActive;  // on or off\r
1053         u1Byte PTTryState;  // 0 trying state, 1 for decision state\r
1054         u1Byte PTStage;  // 0~6\r
1055         u1Byte PTStopCount; //Stop PT counter\r
1056         u1Byte PTPreRate;  // if rate change do PT\r
1057         u1Byte PTPreRssi; // if RSSI change 5% do PT\r
1058         u1Byte PTModeSS;  // decide whitch rate should do PT\r
1059         u1Byte RAstage;  // StageRA, decide how many times RA will be done between PT\r
1060         u1Byte PTSmoothFactor;\r
1061 #endif\r
1062 } ODM_RA_INFO_T,*PODM_RA_INFO_T;\r
1063 \r
1064 typedef struct _IQK_MATRIX_REGS_SETTING{\r
1065         BOOLEAN         bIQKDone;\r
1066         s4Byte          Value[3][IQK_Matrix_REG_NUM];\r
1067         BOOLEAN         bBWIqkResultSaved[3];   \r
1068 }IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING;\r
1069 \r
1070 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
1071 typedef struct _PathDiv_Parameter_define_\r
1072 {\r
1073         u4Byte org_5g_RegE30;\r
1074         u4Byte org_5g_RegC14;\r
1075         u4Byte org_5g_RegCA0;\r
1076         u4Byte swt_5g_RegE30;\r
1077         u4Byte swt_5g_RegC14;\r
1078         u4Byte swt_5g_RegCA0;\r
1079         //for 2G IQK information\r
1080         u4Byte org_2g_RegC80;\r
1081         u4Byte org_2g_RegC4C;\r
1082         u4Byte org_2g_RegC94;\r
1083         u4Byte org_2g_RegC14;\r
1084         u4Byte org_2g_RegCA0;\r
1085 \r
1086         u4Byte swt_2g_RegC80;\r
1087         u4Byte swt_2g_RegC4C;\r
1088         u4Byte swt_2g_RegC94;\r
1089         u4Byte swt_2g_RegC14;\r
1090         u4Byte swt_2g_RegCA0;\r
1091 }PATHDIV_PARA,*pPATHDIV_PARA;\r
1092 #endif\r
1093 \r
1094 \r
1095 typedef struct ODM_RF_Calibration_Structure\r
1096 {\r
1097         //for tx power tracking\r
1098         \r
1099         u4Byte  RegA24; // for TempCCK\r
1100         s4Byte  RegE94;\r
1101         s4Byte  RegE9C;\r
1102         s4Byte  RegEB4;\r
1103         s4Byte  RegEBC; \r
1104 \r
1105         u1Byte          TXPowercount;\r
1106         BOOLEAN bTXPowerTrackingInit; \r
1107         BOOLEAN bTXPowerTracking;\r
1108         u1Byte          TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default\r
1109         u1Byte          TM_Trigger;\r
1110         u1Byte          InternalPA5G[2];        //pathA / pathB\r
1111         \r
1112         u1Byte          ThermalMeter[2];    // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1\r
1113         u1Byte          ThermalValue;\r
1114         u1Byte          ThermalValue_LCK;\r
1115         u1Byte          ThermalValue_IQK;\r
1116         u1Byte  ThermalValue_DPK;               \r
1117         u1Byte  ThermalValue_AVG[AVG_THERMAL_NUM];\r
1118         u1Byte  ThermalValue_AVG_index;         \r
1119         u1Byte  ThermalValue_RxGain;\r
1120         u1Byte  ThermalValue_Crystal;\r
1121         u1Byte  ThermalValue_DPKstore;\r
1122         u1Byte  ThermalValue_DPKtrack;\r
1123         BOOLEAN TxPowerTrackingInProgress;\r
1124         \r
1125         BOOLEAN bReloadtxpowerindex;    \r
1126         u1Byte  bRfPiEnable;\r
1127         u4Byte  TXPowerTrackingCallbackCnt; //cosa add for debug\r
1128 \r
1129 \r
1130         //------------------------- Tx power Tracking -------------------------//\r
1131         u1Byte  bCCKinCH14;\r
1132         u1Byte  CCK_index;\r
1133         u1Byte  OFDM_index[MAX_RF_PATH];\r
1134         s1Byte  PowerIndexOffset[MAX_RF_PATH];\r
1135         s1Byte  DeltaPowerIndex[MAX_RF_PATH];\r
1136         s1Byte  DeltaPowerIndexLast[MAX_RF_PATH];       \r
1137         BOOLEAN bTxPowerChanged;\r
1138                 \r
1139         u1Byte  ThermalValue_HP[HP_THERMAL_NUM];\r
1140         u1Byte  ThermalValue_HP_index;\r
1141         IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];\r
1142         BOOLEAN bNeedIQK;\r
1143         BOOLEAN bIQKInProgress; \r
1144         u1Byte  Delta_IQK;\r
1145         u1Byte  Delta_LCK;\r
1146         s1Byte  BBSwingDiff2G, BBSwingDiff5G; // Unit: dB\r
1147     u1Byte  DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE];\r
1148     u1Byte  DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE];\r
1149     u1Byte  DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE];\r
1150     u1Byte  DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE];\r
1151     u1Byte  DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE];\r
1152     u1Byte  DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE];\r
1153     u1Byte  DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE];\r
1154     u1Byte  DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE];\r
1155     u1Byte  DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE];\r
1156     u1Byte  DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE];\r
1157     u1Byte  DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE];\r
1158     u1Byte  DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE];\r
1159     u1Byte  DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE];\r
1160     u1Byte  DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE];\r
1161     \r
1162         //--------------------------------------------------------------------//        \r
1163         \r
1164         //for IQK       \r
1165         u4Byte  RegC04;\r
1166         u4Byte  Reg874;\r
1167         u4Byte  RegC08;\r
1168         u4Byte  RegB68;\r
1169         u4Byte  RegB6C;\r
1170         u4Byte  Reg870;\r
1171         u4Byte  Reg860;\r
1172         u4Byte  Reg864;\r
1173         \r
1174         BOOLEAN bIQKInitialized;\r
1175         BOOLEAN bLCKInProgress;\r
1176         BOOLEAN bAntennaDetected;\r
1177         u4Byte  ADDA_backup[IQK_ADDA_REG_NUM];\r
1178         u4Byte  IQK_MAC_backup[IQK_MAC_REG_NUM];\r
1179         u4Byte  IQK_BB_backup_recover[9];\r
1180         u4Byte  IQK_BB_backup[IQK_BB_REG_NUM];  \r
1181 \r
1182         //for APK\r
1183         u4Byte  APKoutput[2][2]; //path A/B; output1_1a/output1_2a\r
1184         u1Byte  bAPKdone;\r
1185         u1Byte  bAPKThermalMeterIgnore;\r
1186         u1Byte  bDPdone;\r
1187         u1Byte  bDPPathAOK;\r
1188         u1Byte  bDPPathBOK;\r
1189 \r
1190         u4Byte  TxIQC_8723B[2][3][2]; // { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}\r
1191         u4Byte  RxIQC_8723B[2][2][2]; // { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}}\r
1192         u4Byte  TxLOK[2];\r
1193 \r
1194 }ODM_RF_CAL_T,*PODM_RF_CAL_T;\r
1195 //\r
1196 // ODM Dynamic common info value definition\r
1197 //\r
1198 \r
1199 typedef struct _FAST_ANTENNA_TRAINNING_\r
1200 {\r
1201         u1Byte  Bssid[6];\r
1202         u1Byte  antsel_rx_keep_0;\r
1203         u1Byte  antsel_rx_keep_1;\r
1204         u1Byte  antsel_rx_keep_2;\r
1205         u4Byte  antSumRSSI[7];\r
1206         u4Byte  antRSSIcnt[7];\r
1207         u4Byte  antAveRSSI[7];\r
1208         u1Byte  FAT_State;\r
1209         u4Byte  TrainIdx;\r
1210         u1Byte  antsel_a[ODM_ASSOCIATE_ENTRY_NUM];\r
1211         u1Byte  antsel_b[ODM_ASSOCIATE_ENTRY_NUM];\r
1212         u1Byte  antsel_c[ODM_ASSOCIATE_ENTRY_NUM];\r
1213         u4Byte  MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];\r
1214         u4Byte  AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];\r
1215         u4Byte  MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];\r
1216         u4Byte  AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];\r
1217         u1Byte  RxIdleAnt;\r
1218         BOOLEAN bBecomeLinked;\r
1219         u4Byte  MinMaxRSSI;\r
1220         u1Byte  idx_AntDiv_counter_2G;\r
1221         u1Byte  idx_AntDiv_counter_5G;\r
1222         u4Byte  AntDiv_2G_5G;\r
1223         u4Byte    CCK_counter_main;\r
1224         u4Byte    CCK_counter_aux;      \r
1225         u4Byte    OFDM_counter_main;\r
1226         u4Byte    OFDM_counter_aux;     \r
1227 \r
1228 }FAT_T,*pFAT_T;\r
1229 \r
1230 typedef enum _FAT_STATE\r
1231 {\r
1232         FAT_NORMAL_STATE                        = 0,\r
1233         FAT_TRAINING_STATE              = 1,\r
1234 }FAT_STATE_E, *PFAT_STATE_E;\r
1235 \r
1236 typedef enum _ANT_DIV_TYPE\r
1237 {\r
1238         NO_ANTDIV                       = 0xFF, \r
1239         CG_TRX_HW_ANTDIV                = 0x01,\r
1240         CGCS_RX_HW_ANTDIV       = 0x02,\r
1241         FIXED_HW_ANTDIV         = 0x03,\r
1242         CG_TRX_SMART_ANTDIV     = 0x04,\r
1243         CGCS_RX_SW_ANTDIV       = 0x05,\r
1244         S0S1_SW_ANTDIV          = 0x06 //8723B intrnal switch S0 S1\r
1245 }ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E;\r
1246 \r
1247 typedef struct _ODM_PATH_DIVERSITY_\r
1248 {\r
1249         u1Byte  RespTxPath;\r
1250         u1Byte  PathSel[ODM_ASSOCIATE_ENTRY_NUM];\r
1251         u4Byte  PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM];\r
1252         u4Byte  PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM];\r
1253         u4Byte  PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM];\r
1254         u4Byte  PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM];\r
1255 }PATHDIV_T, *pPATHDIV_T;\r
1256 \r
1257 \r
1258 typedef enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE{\r
1259         PHY_REG_PG_RELATIVE_VALUE = 0,\r
1260         PHY_REG_PG_EXACT_VALUE = 1\r
1261 } PHY_REG_PG_TYPE;\r
1262 \r
1263 \r
1264 //\r
1265 // Antenna detection information from single tone mechanism, added by Roger, 2012.11.27.\r
1266 //\r
1267 typedef struct _ANT_DETECTED_INFO{\r
1268         BOOLEAN                 bAntDetected;\r
1269         u4Byte                  dBForAntA;\r
1270         u4Byte                  dBForAntB;\r
1271         u4Byte                  dBForAntO;\r
1272 }ANT_DETECTED_INFO, *PANT_DETECTED_INFO;\r
1273 \r
1274 //\r
1275 // 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration.\r
1276 //\r
1277 #if(DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
1278 #if (RT_PLATFORM != PLATFORM_LINUX)\r
1279 typedef \r
1280 #endif\r
1281 struct DM_Out_Source_Dynamic_Mechanism_Structure\r
1282 #else// for AP,ADSL,CE Team\r
1283 typedef  struct DM_Out_Source_Dynamic_Mechanism_Structure\r
1284 #endif\r
1285 {\r
1286         //RT_TIMER      FastAntTrainingTimer;\r
1287         //\r
1288         //      Add for different team use temporarily\r
1289         //\r
1290         PADAPTER                Adapter;                // For CE/NIC team\r
1291         prtl8192cd_priv priv;                   // For AP/ADSL team\r
1292         // WHen you use Adapter or priv pointer, you must make sure the pointer is ready.\r
1293         BOOLEAN                 odm_ready;\r
1294 \r
1295 #if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))\r
1296         rtl8192cd_priv          fake_priv;\r
1297 #endif\r
1298 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
1299         // ADSL_AP_BUILD_WORKAROUND\r
1300         ADAPTER                 fake_adapter;\r
1301 #endif\r
1302         \r
1303         PHY_REG_PG_TYPE         PhyRegPgValueType;\r
1304         u1Byte                          PhyRegPgVersion;\r
1305 \r
1306         u8Byte                  DebugComponents;\r
1307         u4Byte                  DebugLevel;\r
1308         \r
1309         u8Byte                  NumQryPhyStatusAll;     //CCK + OFDM\r
1310         u8Byte                  LastNumQryPhyStatusAll; \r
1311         u8Byte                  RxPWDBAve;\r
1312         u8Byte                  RxPWDBAve_final;\r
1313         BOOLEAN                 MPDIG_2G;               //off MPDIG\r
1314         u1Byte                  Times_2G;\r
1315         \r
1316 //------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------//\r
1317         BOOLEAN                 bCckHighPower; \r
1318         u1Byte                  RFPathRxEnable;         // ODM_CMNINFO_RFPATH_ENABLE\r
1319         u1Byte                  ControlChannel;\r
1320 //------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------//\r
1321 \r
1322 //--------REMOVED COMMON INFO----------//\r
1323         //u1Byte                                PseudoMacPhyMode;\r
1324         //BOOLEAN                       *BTCoexist;\r
1325         //BOOLEAN                       PseudoBtCoexist;\r
1326         //u1Byte                                OPMode;\r
1327         //BOOLEAN                       bAPMode;\r
1328         //BOOLEAN                       bClientMode;\r
1329         //BOOLEAN                       bAdHocMode;\r
1330         //BOOLEAN                       bSlaveOfDMSP;\r
1331 //--------REMOVED COMMON INFO----------//\r
1332 \r
1333 \r
1334 //1  COMMON INFORMATION\r
1335 \r
1336         //\r
1337         // Init Value\r
1338         //\r
1339 //-----------HOOK BEFORE REG INIT-----------//  \r
1340         // ODM Platform info AP/ADSL/CE/MP = 1/2/3/4\r
1341         u1Byte                  SupportPlatform;                \r
1342         // ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K\r
1343         u4Byte                  SupportAbility;\r
1344         // ODM PCIE/USB/SDIO = 1/2/3\r
1345         u1Byte                  SupportInterface;                       \r
1346         // ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/...\r
1347         u4Byte                  SupportICType;  \r
1348         // Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/...\r
1349         u1Byte                  CutVersion;\r
1350         // Fab Version TSMC/UMC = 0/1\r
1351         u1Byte                  FabVersion;\r
1352         // RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/...\r
1353         u1Byte                  RFType;\r
1354         u1Byte                  RFEType;        \r
1355         // Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/...\r
1356         u1Byte                  BoardType;\r
1357         u1Byte                  PackageType;\r
1358         u1Byte                  TypeGLNA;\r
1359         u1Byte                  TypeGPA;\r
1360         u1Byte                  TypeALNA;\r
1361         u1Byte                  TypeAPA;\r
1362         // with external LNA  NO/Yes = 0/1\r
1363         u1Byte                  ExtLNA;\r
1364         u1Byte                  ExtLNA5G;\r
1365         // with external PA  NO/Yes = 0/1\r
1366         u1Byte                  ExtPA;\r
1367         u1Byte                  ExtPA5G;\r
1368         // with external TRSW  NO/Yes = 0/1\r
1369         u1Byte                  ExtTRSW;\r
1370         u1Byte                  PatchID; //Customer ID\r
1371         BOOLEAN                 bInHctTest;\r
1372         BOOLEAN                 bWIFITest;\r
1373 \r
1374         BOOLEAN                 bDualMacSmartConcurrent;\r
1375         u4Byte                  BK_SupportAbility;\r
1376         u1Byte                  AntDivType;\r
1377 //-----------HOOK BEFORE REG INIT-----------//  \r
1378 \r
1379         //\r
1380         // Dynamic Value\r
1381         //      \r
1382 //--------- POINTER REFERENCE-----------//\r
1383 \r
1384         u1Byte                  u1Byte_temp;\r
1385         BOOLEAN                 BOOLEAN_temp;\r
1386         PADAPTER                PADAPTER_temp;\r
1387         \r
1388         // MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2\r
1389         u1Byte                  *pMacPhyMode;\r
1390         //TX Unicast byte count\r
1391         u8Byte                  *pNumTxBytesUnicast;\r
1392         //RX Unicast byte count\r
1393         u8Byte                  *pNumRxBytesUnicast;\r
1394         // Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3\r
1395         u1Byte                  *pWirelessMode; //ODM_WIRELESS_MODE_E\r
1396         // Frequence band 2.4G/5G = 0/1\r
1397         u1Byte                  *pBandType;\r
1398         // Secondary channel offset don't_care/below/above = 0/1/2\r
1399         u1Byte                  *pSecChOffset;\r
1400         // Security mode Open/WEP/AES/TKIP = 0/1/2/3\r
1401         u1Byte                  *pSecurity;\r
1402         // BW info 20M/40M/80M = 0/1/2\r
1403         u1Byte                  *pBandWidth;\r
1404         // Central channel location Ch1/Ch2/....\r
1405         u1Byte                  *pChannel;      //central channel number\r
1406         BOOLEAN                 DPK_Done;\r
1407         // Common info for 92D DMSP\r
1408         \r
1409         BOOLEAN                 *pbGetValueFromOtherMac;\r
1410         PADAPTER                *pBuddyAdapter;\r
1411         BOOLEAN                 *pbMasterOfDMSP; //MAC0: master, MAC1: slave\r
1412         // Common info for Status\r
1413         BOOLEAN                 *pbScanInProcess;\r
1414         BOOLEAN                 *pbPowerSaving;\r
1415         // CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E.\r
1416         u1Byte                  *pOnePathCCA;\r
1417         //pMgntInfo->AntennaTest\r
1418         u1Byte                  *pAntennaTest;\r
1419         BOOLEAN                 *pbNet_closed;\r
1420         u1Byte                  *mp_mode;\r
1421         //u1Byte                        *pAidMap;\r
1422         u1Byte                  *pu1ForcedIgiLb;\r
1423 //--------- POINTER REFERENCE-----------//\r
1424         pu2Byte                 pForcedDataRate;\r
1425 //------------CALL BY VALUE-------------//\r
1426         BOOLEAN                 bLinkInProcess;\r
1427         BOOLEAN                 bWIFI_Direct;\r
1428         BOOLEAN                 bWIFI_Display;\r
1429         BOOLEAN                 bLinked;\r
1430 \r
1431         BOOLEAN                 bsta_state;\r
1432         u1Byte                  RSSI_Min;       \r
1433         u1Byte          InterfaceIndex; // Add for 92D  dual MAC: 0--Mac0 1--Mac1\r
1434         BOOLEAN         bIsMPChip;\r
1435         BOOLEAN                 bOneEntryOnly;\r
1436         // Common info for BTDM\r
1437         BOOLEAN                 bBtDisabled;                    // BT is disabled\r
1438         BOOLEAN                 bBtConnectProcess;      // BT HS is under connection progress.\r
1439         u1Byte                  btHsRssi;                               // BT HS mode wifi rssi value.\r
1440         BOOLEAN                 bBtHsOperation;         // BT HS mode is under progress\r
1441         BOOLEAN                 bBtDisableEdcaTurbo;    // Under some condition, don't enable the EDCA Turbo\r
1442         BOOLEAN                 bBtLimitedDig;                  // BT is busy.\r
1443 //------------CALL BY VALUE-------------//\r
1444         u1Byte                  RSSI_A;\r
1445         u1Byte                  RSSI_B;\r
1446         u8Byte                  RSSI_TRSW;      \r
1447         u8Byte                  RSSI_TRSW_H;\r
1448         u8Byte                  RSSI_TRSW_L;    \r
1449         u8Byte                  RSSI_TRSW_iso;\r
1450 \r
1451         u1Byte                  RxRate;\r
1452         BOOLEAN                 StopDIG;\r
1453         BOOLEAN                 bNoisyState;\r
1454         u1Byte                  TxRate;\r
1455         u1Byte                  LinkedInterval;\r
1456         u1Byte                  preChannel;\r
1457         u4Byte                  TxagcOffsetValueA;\r
1458         BOOLEAN                 IsTxagcOffsetPositiveA;\r
1459         u4Byte                  TxagcOffsetValueB;\r
1460         BOOLEAN                 IsTxagcOffsetPositiveB;\r
1461         u8Byte                  lastTxOkCnt;\r
1462         u8Byte                  lastRxOkCnt;\r
1463         u4Byte                  BbSwingOffsetA;\r
1464         BOOLEAN                 IsBbSwingOffsetPositiveA;\r
1465         u4Byte                  BbSwingOffsetB;\r
1466         BOOLEAN                 IsBbSwingOffsetPositiveB;\r
1467         s1Byte                  TH_L2H_ini;\r
1468         s1Byte                  TH_EDCCA_HL_diff;\r
1469         s1Byte                  IGI_Base;\r
1470         u1Byte                  IGI_target;\r
1471         BOOLEAN                 ForceEDCCA;\r
1472         u1Byte                  AdapEn_RSSI;\r
1473         s1Byte                  Force_TH_H;\r
1474         s1Byte                  Force_TH_L;\r
1475         u1Byte                  IGI_LowerBound;\r
1476         u1Byte                  antdiv_rssi;\r
1477         u1Byte                  AntType;\r
1478         u1Byte                  pre_AntType;\r
1479         u1Byte                  antdiv_period;\r
1480         u1Byte                  antdiv_select;  \r
1481         //2 Define STA info.\r
1482         // _ODM_STA_INFO\r
1483         // 2012/01/12 MH For MP, we need to reduce one array pointer for default port.??\r
1484         PSTA_INFO_T             pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];\r
1485 \r
1486 #if (RATE_ADAPTIVE_SUPPORT == 1)\r
1487         u2Byte                  CurrminRptTime;\r
1488         ODM_RA_INFO_T   RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; //See HalMacID support\r
1489 #endif\r
1490         //\r
1491         // 2012/02/14 MH Add to share 88E ra with other SW team.\r
1492         // We need to colelct all support abilit to a proper area.\r
1493         //\r
1494         BOOLEAN                         RaSupport88E;\r
1495 \r
1496         // Define ...........\r
1497 \r
1498         // Latest packet phy info (ODM write)\r
1499         ODM_PHY_DBG_INFO_T       PhyDbgInfo;\r
1500         //PHY_INFO_88E          PhyInfo;\r
1501 \r
1502         // Latest packet phy info (ODM write)\r
1503         ODM_MAC_INFO            *pMacInfo;\r
1504         //MAC_INFO_88E          MacInfo;\r
1505 \r
1506         // Different Team independt structure??\r
1507 \r
1508         //\r
1509         //TX_RTP_CMN            TX_retrpo;\r
1510         //TX_RTP_88E            TX_retrpo;\r
1511         //TX_RTP_8195           TX_retrpo;\r
1512 \r
1513         //\r
1514         //ODM Structure\r
1515         //\r
1516         FAT_T           DM_FatTable;\r
1517         DIG_T           DM_DigTable;\r
1518         PS_T            DM_PSTable;\r
1519         Pri_CCA_T       DM_PriCCA;\r
1520         RXHP_T          DM_RXHP_Table;\r
1521         RA_T            DM_RA_Table;  \r
1522         FALSE_ALARM_STATISTICS  FalseAlmCnt;\r
1523         FALSE_ALARM_STATISTICS  FlaseAlmCntBuddyAdapter;\r
1524         //#ifdef CONFIG_ANTENNA_DIVERSITY\r
1525         SWAT_T          DM_SWAT_Table;\r
1526         BOOLEAN         RSSI_test;\r
1527         //#endif \r
1528         \r
1529 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
1530         //Path Div Struct\r
1531         PATHDIV_PARA    pathIQK;\r
1532 #endif  \r
1533 \r
1534         EDCA_T          DM_EDCA_Table;\r
1535         u4Byte          WMMEDCA_BE;\r
1536         PATHDIV_T       DM_PathDiv;\r
1537         // Copy from SD4 structure\r
1538         //\r
1539         // ==================================================\r
1540         //\r
1541 \r
1542         //common\r
1543         //u1Byte                DM_Type;        \r
1544         //u1Byte    PSD_Report_RXHP[80];   // Add By Gary\r
1545         //u1Byte    PSD_func_flag;               // Add By Gary\r
1546         //for DIG\r
1547         //u1Byte                bDMInitialGainEnable;\r
1548         //u1Byte                binitialized; // for dm_initial_gain_Multi_STA use.\r
1549         //for Antenna diversity\r
1550         //u8    AntDivCfg;// 0:OFF , 1:ON, 2:by efuse\r
1551         //PSTA_INFO_T RSSI_target;\r
1552 \r
1553         BOOLEAN                 *pbDriverStopped;\r
1554         BOOLEAN                 *pbDriverIsGoingToPnpSetPowerSleep;\r
1555         BOOLEAN                 *pinit_adpt_in_progress;\r
1556 \r
1557         //PSD\r
1558         BOOLEAN                 bUserAssignLevel;\r
1559         RT_TIMER                PSDTimer;\r
1560         u1Byte                  RSSI_BT;                        //come from BT\r
1561         BOOLEAN                 bPSDinProcess;\r
1562         BOOLEAN                 bPSDactive;\r
1563         BOOLEAN                 bDMInitialGainEnable;\r
1564 \r
1565         //MPT DIG\r
1566         RT_TIMER                MPT_DIGTimer;\r
1567         \r
1568         //for rate adaptive, in fact,  88c/92c fw will handle this\r
1569         u1Byte                  bUseRAMask;\r
1570 \r
1571         ODM_RATE_ADAPTIVE       RateAdaptive;\r
1572 \r
1573         ANT_DETECTED_INFO       AntDetectedInfo; // Antenna detected information for RSSI tool\r
1574 \r
1575         ODM_RF_CAL_T    RFCalibrateInfo;\r
1576         \r
1577         //\r
1578         // TX power tracking\r
1579         //\r
1580         u1Byte                  BbSwingIdxOfdm[MAX_RF_PATH];\r
1581         u1Byte                  BbSwingIdxOfdmCurrent;\r
1582         u1Byte                  BbSwingIdxOfdmBase[MAX_RF_PATH];\r
1583         BOOLEAN                 BbSwingFlagOfdm;\r
1584         u1Byte                  BbSwingIdxCck;\r
1585         u1Byte                  BbSwingIdxCckCurrent;\r
1586         u1Byte                  BbSwingIdxCckBase;\r
1587         u1Byte                  DefaultOfdmIndex;\r
1588         u1Byte                  DefaultCckIndex;        \r
1589         BOOLEAN                 BbSwingFlagCck;\r
1590         \r
1591         s1Byte                  Absolute_OFDMSwingIdx[MAX_RF_PATH];   \r
1592         s1Byte                  Remnant_OFDMSwingIdx[MAX_RF_PATH];   \r
1593         s1Byte                  Remnant_CCKSwingIdx;\r
1594         s1Byte                  Modify_TxAGC_Value;       //Remnat compensate value at TxAGC \r
1595         BOOLEAN                 Modify_TxAGC_Flag_PathA;\r
1596         BOOLEAN                 Modify_TxAGC_Flag_PathB;\r
1597         BOOLEAN                 Modify_TxAGC_Flag_PathA_CCK;\r
1598 \r
1599         //\r
1600         // Dynamic ATC switch\r
1601         //\r
1602         BOOLEAN                 bATCStatus;\r
1603         BOOLEAN                 largeCFOHit;\r
1604         BOOLEAN                 bIsfreeze;\r
1605         int                             CFO_tail[2];\r
1606         int                             CFO_ave_pre;\r
1607         int                             CrystalCap;\r
1608         u1Byte                  CFOThreshold;\r
1609         u4Byte                  packetCount;\r
1610         u4Byte                  packetCount_pre;\r
1611         \r
1612         //\r
1613         // ODM system resource.\r
1614         //\r
1615 \r
1616         // ODM relative time.\r
1617         RT_TIMER                                PathDivSwitchTimer;\r
1618         //2011.09.27 add for Path Diversity\r
1619         RT_TIMER                                CCKPathDiversityTimer;\r
1620         RT_TIMER        FastAntTrainingTimer;\r
1621         \r
1622         // ODM relative workitem.\r
1623 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1624         #if USE_WORKITEM\r
1625         RT_WORK_ITEM                    PathDivSwitchWorkitem;\r
1626         RT_WORK_ITEM                    CCKPathDiversityWorkitem;\r
1627         RT_WORK_ITEM                    FastAntTrainingWorkitem;\r
1628         RT_WORK_ITEM                    MPT_DIGWorkitem;\r
1629         RT_WORK_ITEM                    RaRptWorkitem;\r
1630         #endif\r
1631 #endif\r
1632 \r
1633 #if(DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
1634         \r
1635 #if (RT_PLATFORM != PLATFORM_LINUX)\r
1636 } DM_ODM_T, *PDM_ODM_T;         // DM_Dynamic_Mechanism_Structure\r
1637 #else\r
1638 };\r
1639 #endif  \r
1640 \r
1641 #else// for AP,ADSL,CE Team\r
1642 } DM_ODM_T, *PDM_ODM_T;         // DM_Dynamic_Mechanism_Structure\r
1643 #endif\r
1644 \r
1645 \r
1646 \r
1647 #if 1 //92c-series\r
1648 #define ODM_RF_PATH_MAX 2\r
1649 #else //jaguar - series\r
1650 #define ODM_RF_PATH_MAX 4\r
1651 #endif\r
1652 \r
1653 typedef enum _ODM_RF_RADIO_PATH {\r
1654     ODM_RF_PATH_A = 0,   //Radio Path A\r
1655     ODM_RF_PATH_B = 1,   //Radio Path B\r
1656     ODM_RF_PATH_C = 2,   //Radio Path C\r
1657     ODM_RF_PATH_D = 3,   //Radio Path D\r
1658     ODM_RF_PATH_AB,\r
1659     ODM_RF_PATH_AC,\r
1660     ODM_RF_PATH_AD,\r
1661     ODM_RF_PATH_BC,\r
1662     ODM_RF_PATH_BD,\r
1663     ODM_RF_PATH_CD,\r
1664     ODM_RF_PATH_ABC,\r
1665     ODM_RF_PATH_ACD,\r
1666     ODM_RF_PATH_BCD,\r
1667     ODM_RF_PATH_ABCD,\r
1668   //  ODM_RF_PATH_MAX,    //Max RF number 90 support\r
1669 } ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E;\r
1670 \r
1671  typedef enum _ODM_RF_CONTENT{\r
1672         odm_radioa_txt = 0x1000,\r
1673         odm_radiob_txt = 0x1001,\r
1674         odm_radioc_txt = 0x1002,\r
1675         odm_radiod_txt = 0x1003\r
1676 } ODM_RF_CONTENT;\r
1677 \r
1678 typedef enum _ODM_BB_Config_Type{\r
1679     CONFIG_BB_PHY_REG,   \r
1680     CONFIG_BB_AGC_TAB,   \r
1681     CONFIG_BB_AGC_TAB_2G,\r
1682     CONFIG_BB_AGC_TAB_5G, \r
1683     CONFIG_BB_PHY_REG_PG,  \r
1684     CONFIG_BB_PHY_REG_MP,\r
1685     CONFIG_BB_AGC_TAB_DIFF,\r
1686 } ODM_BB_Config_Type, *PODM_BB_Config_Type;\r
1687 \r
1688 typedef enum _ODM_RF_Config_Type{ \r
1689         CONFIG_RF_RADIO,\r
1690     CONFIG_RF_TXPWR_LMT,\r
1691 } ODM_RF_Config_Type, *PODM_RF_Config_Type;\r
1692 \r
1693 typedef enum _ODM_FW_Config_Type{\r
1694     CONFIG_FW_NIC,\r
1695     CONFIG_FW_NIC_2,\r
1696     CONFIG_FW_AP,\r
1697     CONFIG_FW_MP,\r
1698     CONFIG_FW_WoWLAN,\r
1699     CONFIG_FW_WoWLAN_2,\r
1700     CONFIG_FW_AP_WoWLAN,\r
1701     CONFIG_FW_BT,\r
1702 } ODM_FW_Config_Type;\r
1703 \r
1704 // Status code\r
1705 #if (DM_ODM_SUPPORT_TYPE != ODM_WIN)\r
1706 typedef enum _RT_STATUS{\r
1707         RT_STATUS_SUCCESS,\r
1708         RT_STATUS_FAILURE,\r
1709         RT_STATUS_PENDING,\r
1710         RT_STATUS_RESOURCE,\r
1711         RT_STATUS_INVALID_CONTEXT,\r
1712         RT_STATUS_INVALID_PARAMETER,\r
1713         RT_STATUS_NOT_SUPPORT,\r
1714         RT_STATUS_OS_API_FAILED,\r
1715 }RT_STATUS,*PRT_STATUS;\r
1716 #endif // end of RT_STATUS definition\r
1717 \r
1718 #ifdef REMOVE_PACK\r
1719 #pragma pack()\r
1720 #endif\r
1721 \r
1722 //#include "odm_function.h"\r
1723 \r
1724 //3===========================================================\r
1725 //3 DIG\r
1726 //3===========================================================\r
1727 \r
1728 typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition\r
1729 {\r
1730         DIG_TYPE_THRESH_HIGH    = 0,\r
1731         DIG_TYPE_THRESH_LOW     = 1,\r
1732         DIG_TYPE_BACKOFF                = 2,\r
1733         DIG_TYPE_RX_GAIN_MIN    = 3,\r
1734         DIG_TYPE_RX_GAIN_MAX    = 4,\r
1735         DIG_TYPE_ENABLE                 = 5,\r
1736         DIG_TYPE_DISABLE                = 6,    \r
1737         DIG_OP_TYPE_MAX\r
1738 }DM_DIG_OP_E;\r
1739 /*\r
1740 typedef enum tag_CCK_Packet_Detection_Threshold_Type_Definition\r
1741 {\r
1742         CCK_PD_STAGE_LowRssi = 0,\r
1743         CCK_PD_STAGE_HighRssi = 1,\r
1744         CCK_PD_STAGE_MAX = 3,\r
1745 }DM_CCK_PDTH_E;\r
1746 \r
1747 typedef enum tag_DIG_EXT_PORT_ALGO_Definition\r
1748 {\r
1749         DIG_EXT_PORT_STAGE_0 = 0,\r
1750         DIG_EXT_PORT_STAGE_1 = 1,\r
1751         DIG_EXT_PORT_STAGE_2 = 2,\r
1752         DIG_EXT_PORT_STAGE_3 = 3,\r
1753         DIG_EXT_PORT_STAGE_MAX = 4,\r
1754 }DM_DIG_EXT_PORT_ALG_E;\r
1755 \r
1756 typedef enum tag_DIG_Connect_Definition\r
1757 {\r
1758         DIG_STA_DISCONNECT = 0, \r
1759         DIG_STA_CONNECT = 1,\r
1760         DIG_STA_BEFORE_CONNECT = 2,\r
1761         DIG_MultiSTA_DISCONNECT = 3,\r
1762         DIG_MultiSTA_CONNECT = 4,\r
1763         DIG_CONNECT_MAX\r
1764 }DM_DIG_CONNECT_E;\r
1765 \r
1766 \r
1767 #define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;}\r
1768 \r
1769 #define DM_MultiSTA_InitGainChangeNotify_CONNECT(_ADAPTER)      \\r
1770         DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_CONNECT)\r
1771 \r
1772 #define DM_MultiSTA_InitGainChangeNotify_DISCONNECT(_ADAPTER)   \\r
1773         DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_DISCONNECT)\r
1774 */\r
1775 #define         DM_DIG_THRESH_HIGH                      40\r
1776 #define         DM_DIG_THRESH_LOW                       35\r
1777 \r
1778 #define         DM_FALSEALARM_THRESH_LOW        400\r
1779 #define         DM_FALSEALARM_THRESH_HIGH       1000\r
1780 \r
1781 #define         DM_DIG_MAX_NIC                          0x3e\r
1782 #define         DM_DIG_MIN_NIC                          0x1e //0x22//0x1c\r
1783 \r
1784 #define         DM_DIG_MAX_AP                                   0x32\r
1785 #define         DM_DIG_MIN_AP                                   0x20\r
1786 \r
1787 #define         DM_DIG_MAX_NIC_HP                       0x46\r
1788 #define         DM_DIG_MIN_NIC_HP                       0x2e\r
1789 \r
1790 #define         DM_DIG_MAX_AP_HP                                0x42\r
1791 #define         DM_DIG_MIN_AP_HP                                0x30\r
1792 \r
1793 //vivi 92c&92d has different definition, 20110504\r
1794 //this is for 92c\r
1795 #ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV\r
1796 #define         DM_DIG_FA_TH0                           0x80//0x20\r
1797 #else\r
1798 #define         DM_DIG_FA_TH0                           0x200//0x20\r
1799 #endif\r
1800 #define         DM_DIG_FA_TH1                           0x300//0x100\r
1801 #define         DM_DIG_FA_TH2                           0x400//0x200\r
1802 //this is for 92d\r
1803 #define         DM_DIG_FA_TH0_92D                       0x100\r
1804 #define         DM_DIG_FA_TH1_92D                       0x400\r
1805 #define         DM_DIG_FA_TH2_92D                       0x600\r
1806 \r
1807 #define         DM_DIG_BACKOFF_MAX                      12\r
1808 #define         DM_DIG_BACKOFF_MIN                      -4\r
1809 #define         DM_DIG_BACKOFF_DEFAULT          10\r
1810 \r
1811 //3===========================================================\r
1812 //3 AGC RX High Power Mode\r
1813 //3===========================================================\r
1814 #define          LNA_Low_Gain_1                      0x64\r
1815 #define          LNA_Low_Gain_2                      0x5A\r
1816 #define          LNA_Low_Gain_3                      0x58\r
1817 \r
1818 #define          FA_RXHP_TH1                           5000\r
1819 #define          FA_RXHP_TH2                           1500\r
1820 #define          FA_RXHP_TH3                             800\r
1821 #define          FA_RXHP_TH4                             600\r
1822 #define          FA_RXHP_TH5                             500\r
1823 \r
1824 //3===========================================================\r
1825 //3 EDCA\r
1826 //3===========================================================\r
1827 \r
1828 //3===========================================================\r
1829 //3 Dynamic Tx Power\r
1830 //3===========================================================\r
1831 //Dynamic Tx Power Control Threshold\r
1832 #define         TX_POWER_NEAR_FIELD_THRESH_LVL2 74\r
1833 #define         TX_POWER_NEAR_FIELD_THRESH_LVL1 67\r
1834 #define         TX_POWER_NEAR_FIELD_THRESH_AP           0x3F\r
1835 \r
1836 #define         TxHighPwrLevel_Normal           0       \r
1837 #define         TxHighPwrLevel_Level1           1\r
1838 #define         TxHighPwrLevel_Level2           2\r
1839 #define         TxHighPwrLevel_BT1                      3\r
1840 #define         TxHighPwrLevel_BT2                      4\r
1841 #define         TxHighPwrLevel_15                       5\r
1842 #define         TxHighPwrLevel_35                       6\r
1843 #define         TxHighPwrLevel_50                       7\r
1844 #define         TxHighPwrLevel_70                       8\r
1845 #define         TxHighPwrLevel_100                      9\r
1846 \r
1847 //3===========================================================\r
1848 //3 Tx Power Tracking\r
1849 //3===========================================================\r
1850 #if 0 //mask this, since these have been defined in typdef.h, vivi\r
1851 #define OFDM_TABLE_SIZE         43\r
1852 #define CCK_TABLE_SIZE          33\r
1853 #endif  \r
1854 \r
1855 \r
1856 //3===========================================================\r
1857 //3 Rate Adaptive\r
1858 //3===========================================================\r
1859 #define         DM_RATR_STA_INIT                        0\r
1860 #define         DM_RATR_STA_HIGH                        1\r
1861 #define                 DM_RATR_STA_MIDDLE              2\r
1862 #define                 DM_RATR_STA_LOW                 3\r
1863 \r
1864 //3===========================================================\r
1865 //3 BB Power Save\r
1866 //3===========================================================\r
1867 \r
1868 \r
1869 //3===========================================================\r
1870 //3 Dynamic ATC switch\r
1871 //3===========================================================\r
1872 #define         ATC_Status_Off                          0x0                     // enable\r
1873 #define         ATC_Status_On                           0x1                     // disable\r
1874 #define         CFO_Threshold_Xtal                      10                      // kHz\r
1875 #define         CFO_Threshold_ATC                       80                      // kHz\r
1876 \r
1877 typedef enum tag_1R_CCA_Type_Definition\r
1878 {\r
1879         CCA_1R =0,\r
1880         CCA_2R = 1,\r
1881         CCA_MAX = 2,\r
1882 }DM_1R_CCA_E;\r
1883 \r
1884 typedef enum tag_RF_Type_Definition\r
1885 {\r
1886         RF_Save =0,\r
1887         RF_Normal = 1,\r
1888         RF_MAX = 2,\r
1889 }DM_RF_E;\r
1890 \r
1891 //3===========================================================\r
1892 //3 Antenna Diversity\r
1893 //3===========================================================\r
1894 typedef enum tag_SW_Antenna_Switch_Definition\r
1895 {\r
1896         Antenna_A = 1,\r
1897         Antenna_B = 2,  \r
1898         Antenna_MAX = 3,\r
1899 }DM_SWAS_E;\r
1900 \r
1901 \r
1902 // Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28.\r
1903 #define MAX_ANTENNA_DETECTION_CNT       10 \r
1904 \r
1905 //\r
1906 // Extern Global Variables.\r
1907 //\r
1908 extern  u4Byte OFDMSwingTable[OFDM_TABLE_SIZE];\r
1909 extern  u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];\r
1910 extern  u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];\r
1911 \r
1912 extern  u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE];\r
1913 extern  u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8];\r
1914 extern  u1Byte CCKSwingTable_Ch14_New [CCK_TABLE_SIZE][8];\r
1915 \r
1916 extern  u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE];\r
1917 \r
1918 // <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table.\r
1919 static u1Byte DeltaSwingTableIdx_2GA_P_8188E[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4,  4,  4,  4,  4,  4,  5,  5,  7,  7,  8,  8,  8,  9,  9,  9,  9,  9};\r
1920 static u1Byte DeltaSwingTableIdx_2GA_N_8188E[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5,  6,  6,  7,  7,  7,  7,  8,  8,  9,  9, 10, 10, 10, 11, 11, 11, 11}; \r
1921 \r
1922 //\r
1923 // check Sta pointer valid or not\r
1924 //\r
1925 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
1926 #define IS_STA_VALID(pSta)              (pSta && pSta->expire_to)\r
1927 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)\r
1928 #define IS_STA_VALID(pSta)              (pSta && pSta->bUsed)\r
1929 #else\r
1930 #define IS_STA_VALID(pSta)              (pSta)\r
1931 #endif\r
1932 // 20100514 Joseph: Add definition for antenna switching test after link.\r
1933 // This indicates two different the steps. \r
1934 // In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air.\r
1935 // In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK\r
1936 // with original RSSI to determine if it is necessary to switch antenna.\r
1937 #define SWAW_STEP_PEAK          0\r
1938 #define SWAW_STEP_DETERMINE     1\r
1939 \r
1940 VOID ODM_Write_DIG(IN   PDM_ODM_T       pDM_Odm,        IN      u1Byte  CurrentIGI);\r
1941 VOID ODM_Write_CCK_CCA_Thres(IN PDM_ODM_T       pDM_Odm, IN     u1Byte  CurCCK_CCAThres);\r
1942 \r
1943 VOID\r
1944 ODM_SetAntenna(\r
1945         IN      PDM_ODM_T       pDM_Odm,\r
1946         IN      u1Byte          Antenna);\r
1947 \r
1948 \r
1949 #define dm_RF_Saving    ODM_RF_Saving\r
1950 void ODM_RF_Saving(     IN      PDM_ODM_T       pDM_Odm,\r
1951                                                         IN      u1Byte          bForceInNormal );\r
1952 \r
1953 #define SwAntDivRestAfterLink   ODM_SwAntDivRestAfterLink\r
1954 VOID ODM_SwAntDivRestAfterLink( IN      PDM_ODM_T       pDM_Odm);\r
1955 \r
1956 #define dm_CheckTXPowerTracking         ODM_TXPowerTrackingCheck\r
1957 VOID    \r
1958 ODM_TXPowerTrackingCheck(\r
1959         IN              PDM_ODM_T               pDM_Odm\r
1960         );\r
1961                                                 \r
1962 BOOLEAN \r
1963 ODM_RAStateCheck(\r
1964         IN              PDM_ODM_T               pDM_Odm,\r
1965         IN              s4Byte                  RSSI,\r
1966         IN              BOOLEAN                 bForceUpdate,\r
1967         OUT             pu1Byte                 pRATRState\r
1968         );\r
1969 \r
1970 #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_AP|ODM_ADSL))\r
1971 //============================================================\r
1972 // function prototype\r
1973 //============================================================\r
1974 //#define DM_ChangeDynamicInitGainThresh                ODM_ChangeDynamicInitGainThresh\r
1975 //void  ODM_ChangeDynamicInitGainThresh(IN      PADAPTER        pAdapter,\r
1976 //                                                                                      IN      INT32           DM_Type,\r
1977 //                                                                                      IN      INT32           DM_Value);\r
1978 VOID\r
1979 ODM_ChangeDynamicInitGainThresh(\r
1980         IN      PDM_ODM_T       pDM_Odm,\r
1981         IN      u4Byte  DM_Type,\r
1982         IN      u4Byte DM_Value\r
1983         );\r
1984 \r
1985 BOOLEAN\r
1986 ODM_CheckPowerStatus(\r
1987         IN      PADAPTER                Adapter\r
1988         );\r
1989 \r
1990 \r
1991 #if (DM_ODM_SUPPORT_TYPE != ODM_ADSL) \r
1992 VOID\r
1993 ODM_RateAdaptiveStateApInit(\r
1994         IN      PADAPTER        Adapter ,\r
1995         IN      PRT_WLAN_STA  pEntry\r
1996         );\r
1997 #endif\r
1998 #define AP_InitRateAdaptiveState        ODM_RateAdaptiveStateApInit\r
1999 \r
2000 \r
2001 #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
2002 #ifdef WIFI_WMM\r
2003 VOID\r
2004 ODM_IotEdcaSwitch(\r
2005         IN      PDM_ODM_T       pDM_Odm,\r
2006         IN      unsigned char           enable\r
2007         );\r
2008 #endif\r
2009 \r
2010 BOOLEAN\r
2011 ODM_ChooseIotMainSTA(\r
2012         IN      PDM_ODM_T               pDM_Odm,\r
2013         IN      PSTA_INFO_T             pstat\r
2014         );\r
2015 #endif\r
2016 \r
2017 #if(DM_ODM_SUPPORT_TYPE==ODM_AP)\r
2018 #ifdef HW_ANT_SWITCH\r
2019 u1Byte\r
2020 ODM_Diversity_AntennaSelect(\r
2021         IN      PDM_ODM_T       pDM_Odm,\r
2022         IN      u1Byte  *data\r
2023 );\r
2024 #endif\r
2025 #endif\r
2026 \r
2027 #define SwAntDivResetBeforeLink         ODM_SwAntDivResetBeforeLink\r
2028 VOID ODM_SwAntDivResetBeforeLink(IN     PDM_ODM_T       pDM_Odm);\r
2029 \r
2030 #define SwAntDivCheckBeforeLink ODM_SwAntDivCheckBeforeLink\r
2031 \r
2032 BOOLEAN \r
2033 ODM_SwAntDivCheckBeforeLink(\r
2034         IN              PDM_ODM_T               pDM_Odm\r
2035         );\r
2036 \r
2037 \r
2038 #endif\r
2039 \r
2040 #define dm_SWAW_RSSI_Check      ODM_SwAntDivChkPerPktRssi\r
2041 VOID ODM_SwAntDivChkPerPktRssi( \r
2042         IN PDM_ODM_T            pDM_Odm,\r
2043         IN u1Byte                       StationID,\r
2044         IN PODM_PHY_INFO_T pPhyInfo\r
2045         );\r
2046 \r
2047 #if((DM_ODM_SUPPORT_TYPE==ODM_WIN)||(DM_ODM_SUPPORT_TYPE==ODM_CE))\r
2048 \r
2049 u4Byte ConvertTo_dB(u4Byte Value);\r
2050 \r
2051 u4Byte\r
2052 GetPSDData(\r
2053         PDM_ODM_T       pDM_Odm,\r
2054         unsigned int    point,\r
2055         u1Byte initial_gain_psd);\r
2056 \r
2057 #endif\r
2058 \r
2059 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
2060 \r
2061 VOID\r
2062 odm_DIGbyRSSI_LPS(\r
2063         IN              PDM_ODM_T               pDM_Odm\r
2064         );\r
2065 \r
2066 u4Byte ODM_Get_Rate_Bitmap(\r
2067         IN      PDM_ODM_T       pDM_Odm,\r
2068         IN      u4Byte          macid,\r
2069         IN      u4Byte          ra_mask,        \r
2070         IN      u1Byte          rssi_level);\r
2071 \r
2072 #endif\r
2073         \r
2074 \r
2075 #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN))\r
2076 #define dm_PSDMonitorCallback   odm_PSDMonitorCallback\r
2077 VOID    odm_PSDMonitorCallback(PRT_TIMER                pTimer);\r
2078 \r
2079 VOID\r
2080 odm_PSDMonitorWorkItemCallback(\r
2081     IN PVOID            pContext\r
2082     );\r
2083 \r
2084 VOID\r
2085 ODM_MPT_DIG(\r
2086         IN      PDM_ODM_T       pDM_Odm\r
2087 );\r
2088 \r
2089 VOID\r
2090 PatchDCTone(\r
2091         IN      PDM_ODM_T       pDM_Odm,\r
2092         pu4Byte         PSD_report,\r
2093         u1Byte          initial_gain_psd\r
2094 );\r
2095 VOID\r
2096 ODM_PSDMonitor(\r
2097         IN      PDM_ODM_T       pDM_Odm\r
2098         );\r
2099 VOID    odm_PSD_Monitor(PDM_ODM_T       pDM_Odm);\r
2100 VOID    odm_PSDMonitorInit(PDM_ODM_T    pDM_Odm);\r
2101 \r
2102 VOID\r
2103 ODM_PSDDbgControl(\r
2104         IN      PADAPTER        Adapter,\r
2105         IN      u4Byte          mode,\r
2106         IN      u4Byte          btRssi\r
2107         );\r
2108 \r
2109 #endif  // DM_ODM_SUPPORT_TYPE\r
2110 \r
2111 \r
2112 #if (BEAMFORMING_SUPPORT == 1)\r
2113 BEAMFORMING_CAP\r
2114 Beamforming_GetEntryBeamCapByMacId(\r
2115  IN PMGNT_INFO pMgntInfo,\r
2116  IN u1Byte  MacId\r
2117  );\r
2118 #endif\r
2119 \r
2120 \r
2121 \r
2122 VOID ODM_DMInit( IN     PDM_ODM_T       pDM_Odm);\r
2123 \r
2124 VOID\r
2125 ODM_DMWatchdog(\r
2126         IN              PDM_ODM_T                       pDM_Odm                 // For common use in the future\r
2127         );\r
2128 \r
2129 VOID\r
2130 ODM_CmnInfoInit(\r
2131         IN              PDM_ODM_T               pDM_Odm,\r
2132         IN              ODM_CMNINFO_E   CmnInfo,\r
2133         IN              u4Byte                  Value   \r
2134         );\r
2135 \r
2136 VOID\r
2137 ODM_CmnInfoHook(\r
2138         IN              PDM_ODM_T               pDM_Odm,\r
2139         IN              ODM_CMNINFO_E   CmnInfo,\r
2140         IN              PVOID                   pValue  \r
2141         );\r
2142 \r
2143 VOID\r
2144 ODM_CmnInfoPtrArrayHook(\r
2145         IN              PDM_ODM_T               pDM_Odm,\r
2146         IN              ODM_CMNINFO_E   CmnInfo,\r
2147         IN              u2Byte                  Index,\r
2148         IN              PVOID                   pValue  \r
2149         );\r
2150 \r
2151 VOID\r
2152 ODM_CmnInfoUpdate(\r
2153         IN              PDM_ODM_T               pDM_Odm,\r
2154         IN              u4Byte                  CmnInfo,\r
2155         IN              u8Byte                  Value   \r
2156         );\r
2157 \r
2158 VOID \r
2159 ODM_InitAllTimers(\r
2160     IN PDM_ODM_T        pDM_Odm \r
2161     );\r
2162 \r
2163 VOID \r
2164 ODM_CancelAllTimers(\r
2165     IN PDM_ODM_T    pDM_Odm \r
2166     );\r
2167 \r
2168 VOID\r
2169 ODM_ReleaseAllTimers(\r
2170     IN PDM_ODM_T        pDM_Odm \r
2171     );\r
2172 \r
2173 VOID\r
2174 ODM_ResetIQKResult(\r
2175     IN PDM_ODM_T pDM_Odm \r
2176     );\r
2177 \r
2178 \r
2179 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
2180 VOID ODM_InitAllWorkItems(IN PDM_ODM_T  pDM_Odm );\r
2181 VOID ODM_FreeAllWorkItems(IN PDM_ODM_T  pDM_Odm );\r
2182 \r
2183 VOID odm_PathDivChkAntSwitch(PDM_ODM_T pDM_Odm);\r
2184 VOID ODM_PathDivRestAfterLink(\r
2185         IN      PDM_ODM_T               pDM_Odm\r
2186         );\r
2187 \r
2188 \r
2189 //===========================================//\r
2190 // Neil Chen----2011--06--15--\r
2191 \r
2192 //3 Path Diversity\r
2193 //===========================================================\r
2194 \r
2195 #define TP_MODE                0\r
2196 #define RSSI_MODE                      1\r
2197 #define TRAFFIC_LOW            0\r
2198 #define TRAFFIC_HIGH           1\r
2199 \r
2200 //#define   PATHDIV_ENABLE       1\r
2201 \r
2202 //VOID odm_PathDivChkAntSwitch(PADAPTER Adapter,u1Byte  Step);\r
2203 VOID ODM_PathDivRestAfterLink(\r
2204         IN      PDM_ODM_T       pDM_Odm\r
2205         );\r
2206 \r
2207 #define dm_PathDiv_RSSI_Check   ODM_PathDivChkPerPktRssi\r
2208 VOID ODM_PathDivChkPerPktRssi(PADAPTER          Adapter,\r
2209                                                                                 BOOLEAN                 bIsDefPort,\r
2210                                                                                 BOOLEAN                 bMatchBSSID,\r
2211                                                                                 PRT_WLAN_STA    pEntry,\r
2212                                                                                 PRT_RFD                 pRfd    );\r
2213 \r
2214 u8Byte\r
2215 PlatformDivision64(\r
2216         IN u8Byte       x,\r
2217         IN u8Byte       y\r
2218 );\r
2219 \r
2220 \r
2221 // 20100514 Joseph: Add definition for antenna switching test after link.\r
2222 // This indicates two different the steps. \r
2223 // In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air.\r
2224 // In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK\r
2225 // with original RSSI to determine if it is necessary to switch antenna.\r
2226 #define SWAW_STEP_PEAK          0\r
2227 #define SWAW_STEP_DETERMINE     1\r
2228 \r
2229 //====================================================\r
2230 //3 PathDiV End\r
2231 //====================================================\r
2232 \r
2233 #define PathDivCheckBeforeLink8192C     ODM_PathDiversityBeforeLink92C\r
2234 BOOLEAN \r
2235 ODM_PathDiversityBeforeLink92C(\r
2236         //IN    PADAPTER        Adapter\r
2237         IN              PDM_ODM_T               pDM_Odm\r
2238         );\r
2239 \r
2240 #define DM_ChangeDynamicInitGainThresh          ODM_ChangeDynamicInitGainThresh\r
2241 //void  ODM_ChangeDynamicInitGainThresh(IN      PADAPTER        pAdapter,\r
2242 //                                                                                      IN      INT32           DM_Type,\r
2243 //                                                                                      IN      INT32           DM_Value);\r
2244 //\r
2245 \r
2246 \r
2247 VOID\r
2248 ODM_CCKPathDiversityChkPerPktRssi(\r
2249         PADAPTER                Adapter,\r
2250         BOOLEAN                 bIsDefPort,\r
2251         BOOLEAN                 bMatchBSSID,\r
2252         PRT_WLAN_STA    pEntry,\r
2253         PRT_RFD                 pRfd,\r
2254         pu1Byte                 pDesc\r
2255         );\r
2256 \r
2257 \r
2258 typedef enum tag_DIG_Connect_Definition\r
2259 {\r
2260         DIG_STA_DISCONNECT = 0, \r
2261         DIG_STA_CONNECT = 1,\r
2262         DIG_STA_BEFORE_CONNECT = 2,\r
2263         DIG_MultiSTA_DISCONNECT = 3,\r
2264         DIG_MultiSTA_CONNECT = 4,\r
2265         DIG_CONNECT_MAX\r
2266 }DM_DIG_CONNECT_E;\r
2267 \r
2268 \r
2269 VOID\r
2270 ODM_FillTXPathInTXDESC(\r
2271                 IN      PADAPTER        Adapter,\r
2272                 IN      PRT_TCB         pTcb,\r
2273                 IN      pu1Byte         pDesc\r
2274 );\r
2275 \r
2276 \r
2277 #define dm_SWAW_RSSI_Check      ODM_SwAntDivChkPerPktRssi\r
2278 \r
2279 //\r
2280 // 2012/01/12 MH Check afapter status. Temp fix BSOD.\r
2281 //\r
2282 #define HAL_ADAPTER_STS_CHK(pDM_Odm)\\r
2283         if (pDM_Odm->Adapter == NULL)\\r
2284         {\\r
2285                 return;\\r
2286         }\\r
2287 \r
2288 \r
2289 //\r
2290 // For new definition in MP temporarily fro power tracking,\r
2291 //\r
2292 #define odm_TXPowerTrackingDirectCall(_Adapter) \\r
2293         IS_HARDWARE_TYPE_8192D(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_92D(_Adapter) : \\r
2294         IS_HARDWARE_TYPE_8192C(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_92C(_Adapter) : \\r
2295         IS_HARDWARE_TYPE_8723A(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_8723A(_Adapter) :\\r
2296         ODM_TXPowerTrackingCallback_ThermalMeter(_Adapter)\r
2297 \r
2298 VOID\r
2299 ODM_SetTxAntByTxInfo_88C_92D(\r
2300         IN              PDM_ODM_T               pDM_Odm,\r
2301         IN              pu1Byte                 pDesc,\r
2302         IN              u1Byte                  macId   \r
2303         );\r
2304 \r
2305 #endif  // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
2306 VOID\r
2307 ODM_AntselStatistics_88C(\r
2308         IN              PDM_ODM_T               pDM_Odm,\r
2309         IN              u1Byte                  MacId,\r
2310         IN              u4Byte                  PWDBAll,\r
2311         IN              BOOLEAN                 isCCKrate\r
2312 );\r
2313 \r
2314 #if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE))\r
2315 \r
2316 VOID\r
2317 ODM_SingleDualAntennaDefaultSetting(\r
2318         IN              PDM_ODM_T               pDM_Odm\r
2319         );\r
2320 \r
2321 BOOLEAN\r
2322 ODM_SingleDualAntennaDetection(\r
2323         IN              PDM_ODM_T               pDM_Odm,\r
2324         IN              u1Byte                  mode\r
2325         );\r
2326 \r
2327 VOID\r
2328 ODM_DynamicATCSwitch(\r
2329         IN              PDM_ODM_T               pDM_Odm\r
2330 );\r
2331 \r
2332 \r
2333 #endif  // #if((DM_ODM_SUPPORT_TYPE==ODM_WIN)||(DM_ODM_SUPPORT_TYPE==ODM_CE))\r
2334 VOID\r
2335 ODM_UpdateNoisyState(\r
2336         IN      PDM_ODM_T       pDM_Odm,\r
2337         IN      BOOLEAN         bNoisyStateFromC2H\r
2338 );\r
2339 \r
2340 u4Byte\r
2341 Set_RA_DM_Ratrbitmap_by_Noisy(\r
2342         IN      PDM_ODM_T       pDM_Odm,\r
2343         IN      WIRELESS_MODE   WirelessMode,\r
2344         IN      u4Byte                  ratr_bitmap,\r
2345         IN      u1Byte                  rssi_level\r
2346 );\r
2347 \r
2348 VOID\r
2349 ODM_UpdateInitRate(\r
2350         IN      PDM_ODM_T       pDM_Odm,\r
2351         IN      u1Byte          Rate\r
2352         );\r
2353 \r
2354 VOID\r
2355 ODM_DynamicARFBSelect(\r
2356         IN              PDM_ODM_T               pDM_Odm,\r
2357         IN              u1Byte                  rate,\r
2358         IN              BOOLEAN                 Collision_State \r
2359         );\r
2360 \r
2361 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
2362 void odm_dtc(PDM_ODM_T pDM_Odm);\r
2363 #endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */\r
2364 \r
2365 #endif\r
2366 \r