drivers/net/wireless/rockchip_wlan/rtl8189es/hal/OUTSRC/odm.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20
  21 //============================================================
  22 // include files
  23 //============================================================
  24
  25 #include "odm_precomp.h"
  26
  27
  28 const u2Byte dB_Invert_Table[8][12] = {
  29         {       1,              1,              1,              2,              2,              2,              2,              3,              3,              3,              4,              4},
  30         {       4,              5,              6,              6,              7,              8,              9,              10,             11,             13,             14,             16},
  31         {       18,             20,             22,             25,             28,             32,             35,             40,             45,             50,             56,             63},
  32         {       71,             79,             89,             100,    112,    126,    141,    158,    178,    200,    224,    251},
  33         {       282,    316,    355,    398,    447,    501,    562,    631,    708,    794,    891,    1000},
  34         {       1122,   1259,   1413,   1585,   1778,   1995,   2239,   2512,   2818,   3162,   3548,   3981},
  35         {       4467,   5012,   5623,   6310,   7079,   7943,   8913,   10000,  11220,  12589,  14125,  15849},
  36         {       17783,  19953,  22387,  25119,  28184,  31623,  35481,  39811,  44668,  50119,  56234,  65535}};
  37
  38
  39 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
  40 static u4Byte edca_setting_UL[HT_IOT_PEER_MAX] =
  41 // UNKNOWN              REALTEK_90      REALTEK_92SE    BROADCOM                RALINK          ATHEROS         CISCO           MERU        MARVELL     92U_AP          SELF_AP(DownLink/Tx)
  42 { 0x5e4322,             0xa44f,                 0x5e4322,               0x5ea32b,               0x5ea422,       0x5ea322,       0x3ea430,       0x5ea42b, 0x5ea44f,     0x5e4322,       0x5e4322};
  43
  44
  45 static u4Byte edca_setting_DL[HT_IOT_PEER_MAX] =
  46 // UNKNOWN              REALTEK_90      REALTEK_92SE    BROADCOM                RALINK          ATHEROS         CISCO           MERU,       MARVELL     92U_AP          SELF_AP(UpLink/Rx)
  47 { 0xa44f,               0x5ea44f,       0x5e4322,               0x5ea42b,               0xa44f,                 0xa630,                 0x5ea630,       0x5ea42b, 0xa44f,               0xa42b,         0xa42b};
  48
  49 static u4Byte edca_setting_DL_GMode[HT_IOT_PEER_MAX] =
  50 // UNKNOWN              REALTEK_90      REALTEK_92SE    BROADCOM                RALINK          ATHEROS         CISCO           MERU,       MARVELL     92U_AP          SELF_AP
  51 { 0x4322,               0xa44f,                 0x5e4322,               0xa42b,                         0x5e4322,       0x4322,                 0xa42b,         0x5ea42b, 0xa44f,               0x5e4322,       0x5ea42b};
  52
  53
  54 //============================================================
  55 // EDCA Paramter for AP/ADSL   by Mingzhi 2011-11-22
  56 //============================================================
  57 #elif (DM_ODM_SUPPORT_TYPE &ODM_ADSL)
  58 enum qos_prio { BK, BE, VI, VO, VI_AG, VO_AG };
  59
  60 static const struct ParaRecord rtl_ap_EDCA[] =
  61 {
  62 //ACM,AIFSN, ECWmin, ECWmax, TXOplimit
  63      {0,     7,      4,      10,     0},            //BK
  64      {0,     3,      4,      6,      0},             //BE
  65      {0,     1,      3,      4,      188},         //VI
  66      {0,     1,      2,      3,      102},         //VO
  67      {0,     1,      3,      4,      94},          //VI_AG
  68      {0,     1,      2,      3,      47},          //VO_AG
  69 };
  70
  71 static const struct ParaRecord rtl_sta_EDCA[] =
  72 {
  73 //ACM,AIFSN, ECWmin, ECWmax, TXOplimit
  74      {0,     7,      4,      10,     0},
  75      {0,     3,      4,      10,     0},
  76      {0,     2,      3,      4,      188},
  77      {0,     2,      2,      3,      102},
  78      {0,     2,      3,      4,      94},
  79      {0,     2,      2,      3,      47},
  80 };
  81 #endif
  82
  83 //============================================================
  84 // Global var
  85 //============================================================
  86
  87 u4Byte  OFDMSwingTable[OFDM_TABLE_SIZE] = {
  88         0x7f8001fe,     // 0, +6.0dB
  89         0x788001e2,     // 1, +5.5dB
  90         0x71c001c7,     // 2, +5.0dB
  91         0x6b8001ae,     // 3, +4.5dB
  92         0x65400195,     // 4, +4.0dB
  93         0x5fc0017f,     // 5, +3.5dB
  94         0x5a400169,     // 6, +3.0dB
  95         0x55400155,     // 7, +2.5dB
  96         0x50800142,     // 8, +2.0dB
  97         0x4c000130,     // 9, +1.5dB
  98         0x47c0011f,     // 10, +1.0dB
  99         0x43c0010f,     // 11, +0.5dB
 100         0x40000100,     // 12, +0dB
 101         0x3c8000f2,     // 13, -0.5dB
 102         0x390000e4,     // 14, -1.0dB
 103         0x35c000d7,     // 15, -1.5dB
 104         0x32c000cb,     // 16, -2.0dB
 105         0x300000c0,     // 17, -2.5dB
 106         0x2d4000b5,     // 18, -3.0dB
 107         0x2ac000ab,     // 19, -3.5dB
 108         0x288000a2,     // 20, -4.0dB
 109         0x26000098,     // 21, -4.5dB
 110         0x24000090,     // 22, -5.0dB
 111         0x22000088,     // 23, -5.5dB
 112         0x20000080,     // 24, -6.0dB
 113         0x1e400079,     // 25, -6.5dB
 114         0x1c800072,     // 26, -7.0dB
 115         0x1b00006c,     // 27. -7.5dB
 116         0x19800066,     // 28, -8.0dB
 117         0x18000060,     // 29, -8.5dB
 118         0x16c0005b,     // 30, -9.0dB
 119         0x15800056,     // 31, -9.5dB
 120         0x14400051,     // 32, -10.0dB
 121         0x1300004c,     // 33, -10.5dB
 122         0x12000048,     // 34, -11.0dB
 123         0x11000044,     // 35, -11.5dB
 124         0x10000040,     // 36, -12.0dB
 125 };
 126
 127 u1Byte  CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = {
 128         {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},       // 0, +0dB
 129         {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},       // 1, -0.5dB
 130         {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},       // 2, -1.0dB
 131         {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},       // 3, -1.5dB
 132         {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},       // 4, -2.0dB
 133         {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},       // 5, -2.5dB
 134         {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},       // 6, -3.0dB
 135         {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},       // 7, -3.5dB
 136         {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},       // 8, -4.0dB
 137         {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},       // 9, -4.5dB
 138         {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},       // 10, -5.0dB
 139         {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},       // 11, -5.5dB
 140         {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},       // 12, -6.0dB <== default
 141         {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},       // 13, -6.5dB
 142         {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},       // 14, -7.0dB
 143         {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},       // 15, -7.5dB
 144         {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},       // 16, -8.0dB
 145         {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},       // 17, -8.5dB
 146         {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},       // 18, -9.0dB
 147         {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},       // 19, -9.5dB
 148         {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},       // 20, -10.0dB
 149         {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},       // 21, -10.5dB
 150         {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},       // 22, -11.0dB
 151         {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},       // 23, -11.5dB
 152         {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},       // 24, -12.0dB
 153         {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},       // 25, -12.5dB
 154         {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},       // 26, -13.0dB
 155         {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},       // 27, -13.5dB
 156         {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},       // 28, -14.0dB
 157         {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},       // 29, -14.5dB
 158         {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},       // 30, -15.0dB
 159         {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},       // 31, -15.5dB
 160         {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}        // 32, -16.0dB
 161 };
 162
 163
 164 u1Byte  CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = {
 165         {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},       // 0, +0dB
 166         {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},       // 1, -0.5dB
 167         {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},       // 2, -1.0dB
 168         {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},       // 3, -1.5dB
 169         {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},       // 4, -2.0dB
 170         {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},       // 5, -2.5dB
 171         {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},       // 6, -3.0dB
 172         {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},       // 7, -3.5dB
 173         {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},       // 8, -4.0dB
 174         {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},       // 9, -4.5dB
 175         {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},       // 10, -5.0dB
 176         {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},       // 11, -5.5dB
 177         {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},       // 12, -6.0dB  <== default
 178         {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},       // 13, -6.5dB
 179         {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},       // 14, -7.0dB
 180         {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},       // 15, -7.5dB
 181         {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},       // 16, -8.0dB
 182         {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},       // 17, -8.5dB
 183         {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},       // 18, -9.0dB
 184         {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},       // 19, -9.5dB
 185         {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},       // 20, -10.0dB
 186         {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},       // 21, -10.5dB
 187         {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},       // 22, -11.0dB
 188         {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},       // 23, -11.5dB
 189         {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},       // 24, -12.0dB
 190         {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},       // 25, -12.5dB
 191         {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},       // 26, -13.0dB
 192         {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},       // 27, -13.5dB
 193         {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},       // 28, -14.0dB
 194         {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},       // 29, -14.5dB
 195         {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},       // 30, -15.0dB
 196         {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},       // 31, -15.5dB
 197         {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}        // 32, -16.0dB
 198 };
 199
 200
 201 u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE] = {
 202         0x0b40002d, // 0,  -15.0dB
 203         0x0c000030, // 1,  -14.5dB
 204         0x0cc00033, // 2,  -14.0dB
 205         0x0d800036, // 3,  -13.5dB
 206         0x0e400039, // 4,  -13.0dB
 207         0x0f00003c, // 5,  -12.5dB
 208         0x10000040, // 6,  -12.0dB
 209         0x11000044, // 7,  -11.5dB
 210         0x12000048, // 8,  -11.0dB
 211         0x1300004c, // 9,  -10.5dB
 212         0x14400051, // 10, -10.0dB
 213         0x15800056, // 11, -9.5dB
 214         0x16c0005b, // 12, -9.0dB
 215         0x18000060, // 13, -8.5dB
 216         0x19800066, // 14, -8.0dB
 217         0x1b00006c, // 15, -7.5dB
 218         0x1c800072, // 16, -7.0dB
 219         0x1e400079, // 17, -6.5dB
 220         0x20000080, // 18, -6.0dB
 221         0x22000088, // 19, -5.5dB
 222         0x24000090, // 20, -5.0dB
 223         0x26000098, // 21, -4.5dB
 224         0x288000a2, // 22, -4.0dB
 225         0x2ac000ab, // 23, -3.5dB
 226         0x2d4000b5, // 24, -3.0dB
 227         0x300000c0, // 25, -2.5dB
 228         0x32c000cb, // 26, -2.0dB
 229         0x35c000d7, // 27, -1.5dB
 230         0x390000e4, // 28, -1.0dB
 231         0x3c8000f2, // 29, -0.5dB
 232         0x40000100, // 30, +0dB
 233         0x43c0010f, // 31, +0.5dB
 234         0x47c0011f, // 32, +1.0dB
 235         0x4c000130, // 33, +1.5dB
 236         0x50800142, // 34, +2.0dB
 237         0x55400155, // 35, +2.5dB
 238         0x5a400169, // 36, +3.0dB
 239         0x5fc0017f, // 37, +3.5dB
 240         0x65400195, // 38, +4.0dB
 241         0x6b8001ae, // 39, +4.5dB
 242         0x71c001c7, // 40, +5.0dB
 243         0x788001e2, // 41, +5.5dB
 244         0x7f8001fe  // 42, +6.0dB
 245 };
 246
 247
 248 u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8] = {
 249         {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01},       //  0, -16.0dB
 250         {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},       //  1, -15.5dB
 251         {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},       //  2, -15.0dB
 252         {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},       //  3, -14.5dB
 253         {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},       //  4, -14.0dB
 254         {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},       //  5, -13.5dB
 255         {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},       //  6, -13.0dB
 256         {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},       //  7, -12.5dB
 257         {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},       //  8, -12.0dB
 258         {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},       //  9, -11.5dB
 259         {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},       // 10, -11.0dB
 260         {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},       // 11, -10.5dB
 261         {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},       // 12, -10.0dB
 262         {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},       // 13, -9.5dB
 263         {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},       // 14, -9.0dB
 264         {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},       // 15, -8.5dB
 265         {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},       // 16, -8.0dB
 266         {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},       // 17, -7.5dB
 267         {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},       // 18, -7.0dB
 268         {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},       // 19, -6.5dB
 269     {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},   // 20, -6.0dB
 270         {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},       // 21, -5.5dB
 271         {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},       // 22, -5.0dB
 272         {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},       // 23, -4.5dB
 273         {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},       // 24, -4.0dB
 274         {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},       // 25, -3.5dB
 275         {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},       // 26, -3.0dB
 276         {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},       // 27, -2.5dB
 277         {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},       // 28, -2.0dB
 278         {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},       // 29, -1.5dB
 279         {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},       // 30, -1.0dB
 280         {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},       // 31, -0.5dB
 281         {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}        // 32, +0dB
 282 };
 283
 284
 285 u1Byte CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8]= {
 286         {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00},       //  0, -16.0dB
 287         {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},       //  1, -15.5dB
 288         {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},       //  2, -15.0dB
 289         {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},       //  3, -14.5dB
 290         {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},       //  4, -14.0dB
 291         {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},       //  5, -13.5dB
 292         {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},       //  6, -13.0dB
 293         {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},       //  7, -12.5dB
 294         {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},       //  8, -12.0dB
 295         {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},       //  9, -11.5dB
 296         {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},       // 10, -11.0dB
 297         {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},       // 11, -10.5dB
 298         {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},       // 12, -10.0dB
 299         {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},       // 13, -9.5dB
 300         {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},       // 14, -9.0dB
 301         {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},       // 15, -8.5dB
 302         {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},       // 16, -8.0dB
 303         {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},       // 17, -7.5dB
 304         {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},       // 18, -7.0dB
 305         {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},       // 19, -6.5dB
 306         {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},       // 20, -6.0dB
 307         {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},       // 21, -5.5dB
 308         {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},       // 22, -5.0dB
 309         {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},       // 23, -4.5dB
 310         {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},       // 24, -4.0dB
 311         {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},       // 25, -3.5dB
 312         {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},       // 26, -3.0dB
 313         {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},       // 27, -2.5dB
 314         {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},       // 28, -2.0dB
 315         {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},       // 29, -1.5dB
 316         {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},       // 30, -1.0dB
 317         {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},       // 31, -0.5dB
 318         {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}        // 32, +0dB
 319 };
 320
 321 u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE] =
 322 {
 323         0x081, // 0,  -12.0dB
 324         0x088, // 1,  -11.5dB
 325         0x090, // 2,  -11.0dB
 326         0x099, // 3,  -10.5dB
 327         0x0A2, // 4,  -10.0dB
 328         0x0AC, // 5,  -9.5dB
 329         0x0B6, // 6,  -9.0dB
 330         0x0C0, // 7,  -8.5dB
 331         0x0CC, // 8,  -8.0dB
 332         0x0D8, // 9,  -7.5dB
 333         0x0E5, // 10, -7.0dB
 334         0x0F2, // 11, -6.5dB
 335         0x101, // 12, -6.0dB
 336         0x110, // 13, -5.5dB
 337         0x120, // 14, -5.0dB
 338         0x131, // 15, -4.5dB
 339         0x143, // 16, -4.0dB
 340         0x156, // 17, -3.5dB
 341         0x16A, // 18, -3.0dB
 342         0x180, // 19, -2.5dB
 343         0x197, // 20, -2.0dB
 344         0x1AF, // 21, -1.5dB
 345         0x1C8, // 22, -1.0dB
 346         0x1E3, // 23, -0.5dB
 347         0x200, // 24, +0  dB
 348         0x21E, // 25, +0.5dB
 349         0x23E, // 26, +1.0dB
 350         0x261, // 27, +1.5dB
 351         0x285, // 28, +2.0dB
 352         0x2AB, // 29, +2.5dB
 353         0x2D3, // 30, +3.0dB
 354         0x2FE, // 31, +3.5dB
 355         0x32B, // 32, +4.0dB
 356         0x35C, // 33, +4.5dB
 357         0x38E, // 34, +5.0dB
 358         0x3C4, // 35, +5.5dB
 359         0x3FE  // 36, +6.0dB
 360 };
 361
 362 #ifdef AP_BUILD_WORKAROUND
 363
 364 unsigned int TxPwrTrk_OFDM_SwingTbl[TxPwrTrk_OFDM_SwingTbl_Len] = {
 365         /*  +6.0dB */ 0x7f8001fe,
 366         /*  +5.5dB */ 0x788001e2,
 367         /*  +5.0dB */ 0x71c001c7,
 368         /*  +4.5dB */ 0x6b8001ae,
 369         /*  +4.0dB */ 0x65400195,
 370         /*  +3.5dB */ 0x5fc0017f,
 371         /*  +3.0dB */ 0x5a400169,
 372         /*  +2.5dB */ 0x55400155,
 373         /*  +2.0dB */ 0x50800142,
 374         /*  +1.5dB */ 0x4c000130,
 375         /*  +1.0dB */ 0x47c0011f,
 376         /*  +0.5dB */ 0x43c0010f,
 377         /*   0.0dB */ 0x40000100,
 378         /*  -0.5dB */ 0x3c8000f2,
 379         /*  -1.0dB */ 0x390000e4,
 380         /*  -1.5dB */ 0x35c000d7,
 381         /*  -2.0dB */ 0x32c000cb,
 382         /*  -2.5dB */ 0x300000c0,
 383         /*  -3.0dB */ 0x2d4000b5,
 384         /*  -3.5dB */ 0x2ac000ab,
 385         /*  -4.0dB */ 0x288000a2,
 386         /*  -4.5dB */ 0x26000098,
 387         /*  -5.0dB */ 0x24000090,
 388         /*  -5.5dB */ 0x22000088,
 389         /*  -6.0dB */ 0x20000080,
 390         /*  -6.5dB */ 0x1a00006c,
 391         /*  -7.0dB */ 0x1c800072,
 392         /*  -7.5dB */ 0x18000060,
 393         /*  -8.0dB */ 0x19800066,
 394         /*  -8.5dB */ 0x15800056,
 395         /*  -9.0dB */ 0x26c0005b,
 396         /*  -9.5dB */ 0x14400051,
 397         /* -10.0dB */ 0x24400051,
 398         /* -10.5dB */ 0x1300004c,
 399         /* -11.0dB */ 0x12000048,
 400         /* -11.5dB */ 0x11000044,
 401         /* -12.0dB */ 0x10000040
 402 };
 403 #endif
 404
 405 //============================================================
 406 // Local Function predefine.
 407 //============================================================
 408
 409 //START------------COMMON INFO RELATED---------------//
 410 VOID
 411 odm_CommonInfoSelfInit(
 412         IN              PDM_ODM_T               pDM_Odm
 413         );
 414
 415 VOID
 416 odm_CommonInfoSelfUpdate(
 417         IN              PDM_ODM_T               pDM_Odm
 418         );
 419
 420 VOID
 421 odm_CmnInfoInit_Debug(
 422         IN              PDM_ODM_T               pDM_Odm
 423         );
 424
 425 VOID
 426 odm_CmnInfoHook_Debug(
 427         IN              PDM_ODM_T               pDM_Odm
 428         );
 429
 430 VOID
 431 odm_CmnInfoUpdate_Debug(
 432         IN              PDM_ODM_T               pDM_Odm
 433         );
 434 VOID
 435 odm_BasicDbgMessage
 436 (
 437         IN              PDM_ODM_T               pDM_Odm
 438         );
 439
 440 //END------------COMMON INFO RELATED---------------//
 441
 442 //START---------------DIG---------------------------//
 443 VOID
 444 odm_FalseAlarmCounterStatistics(
 445         IN              PDM_ODM_T               pDM_Odm
 446         );
 447
 448 VOID
 449 odm_DIGInit(
 450         IN              PDM_ODM_T               pDM_Odm
 451         );
 452
 453 VOID
 454 odm_DIG(
 455         IN              PDM_ODM_T               pDM_Odm
 456         );
 457
 458 BOOLEAN
 459 odm_DigAbort(
 460         IN              PDM_ODM_T               pDM_Odm
 461         );
 462
 463 VOID
 464 odm_CCKPacketDetectionThresh(
 465         IN              PDM_ODM_T               pDM_Odm
 466         );
 467
 468 VOID
 469 odm_AdaptivityInit(
 470         IN              PDM_ODM_T               pDM_Odm
 471 );
 472
 473 VOID
 474 odm_Adaptivity(
 475         IN              PDM_ODM_T               pDM_Odm,
 476         IN              u1Byte                  IGI
 477 );
 478 //END---------------DIG---------------------------//
 479
 480 //START-------BB POWER SAVE-----------------------//
 481 VOID
 482 odm_DynamicBBPowerSavingInit(
 483         IN              PDM_ODM_T               pDM_Odm
 484         );
 485
 486 VOID
 487 odm_DynamicBBPowerSaving(
 488         IN              PDM_ODM_T               pDM_Odm
 489         );
 490
 491 VOID
 492 odm_1R_CCA(
 493         IN              PDM_ODM_T               pDM_Odm
 494         );
 495 //END---------BB POWER SAVE-----------------------//
 496
 497 //START-----------------PSD-----------------------//
 498 #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN))
 499 //============================================================
 500 // Function predefine.
 501 //============================================================
 502 VOID    odm_PathDiversityInit_92C(      IN      PADAPTER        Adapter);
 503 VOID    odm_2TPathDiversityInit_92C(    IN      PADAPTER        Adapter);
 504 VOID    odm_1TPathDiversityInit_92C(    IN      PADAPTER        Adapter);
 505 BOOLEAN odm_IsConnected_92C(IN  PADAPTER        Adapter);
 506 VOID    odm_PathDiversityAfterLink_92C( IN      PADAPTER        Adapter);
 507
 508 VOID
 509 odm_CCKTXPathDiversityCallback(
 510         PRT_TIMER               pTimer
 511         );
 512
 513 VOID
 514 odm_CCKTXPathDiversityWorkItemCallback(
 515     IN PVOID            pContext
 516     );
 517
 518 VOID
 519 odm_PathDivChkAntSwitchCallback(
 520         PRT_TIMER               pTimer
 521         );
 522
 523 VOID
 524 odm_PathDivChkAntSwitchWorkitemCallback(
 525     IN PVOID            pContext
 526     );
 527
 528 VOID    odm_SetRespPath_92C(            IN      PADAPTER        Adapter,        IN      u1Byte  DefaultRespPath);
 529 VOID    odm_OFDMTXPathDiversity_92C(    IN      PADAPTER        Adapter);
 530 VOID    odm_CCKTXPathDiversity_92C(     IN      PADAPTER        Adapter);
 531 VOID    odm_ResetPathDiversity_92C(             IN      PADAPTER        Adapter);
 532
 533 //Start-------------------- RX High Power------------------------//
 534 VOID    odm_RXHPInit(   IN              PDM_ODM_T               pDM_Odm);
 535 VOID    odm_RXHP(       IN              PDM_ODM_T               pDM_Odm);
 536 VOID    odm_Write_RXHP( IN      PDM_ODM_T       pDM_Odm);
 537
 538 VOID    odm_PSD_RXHP(           IN      PDM_ODM_T       pDM_Odm);
 539 VOID    odm_PSD_RXHPCallback(   PRT_TIMER               pTimer);
 540 VOID    odm_PSD_RXHPWorkitemCallback(   IN PVOID            pContext);
 541 //End--------------------- RX High Power -----------------------//
 542
 543 VOID    odm_PathDivInit_92D(    IN      PDM_ODM_T       pDM_Odm);
 544
 545 VOID
 546 odm_SetRespPath_92C(
 547         IN      PADAPTER        Adapter,
 548         IN      u1Byte  DefaultRespPath
 549         );
 550
 551 #endif
 552 //END-------------------PSD-----------------------//
 553
 554 VOID
 555 odm_RefreshRateAdaptiveMaskMP(
 556         IN              PDM_ODM_T               pDM_Odm
 557         );
 558
 559 VOID
 560 odm_RefreshRateAdaptiveMaskCE(
 561         IN              PDM_ODM_T               pDM_Odm
 562         );
 563
 564 VOID
 565 odm_RefreshRateAdaptiveMaskAPADSL(
 566         IN              PDM_ODM_T               pDM_Odm
 567         );
 568
 569 VOID
 570 ODM_DynamicATCSwitch_init(
 571         IN              PDM_ODM_T               pDM_Odm
 572         );
 573
 574 VOID
 575 ODM_DynamicATCSwitch(
 576         IN              PDM_ODM_T               pDM_Odm
 577         );
 578
 579 VOID
 580 odm_Write_CrystalCap(
 581         IN              PDM_ODM_T               pDM_Odm,
 582         IN              u1Byte                  CrystalCap
 583 );
 584
 585 VOID
 586 odm_DynamicTxPowerInit(
 587         IN              PDM_ODM_T               pDM_Odm
 588         );
 589
 590 VOID
 591 odm_DynamicTxPowerRestorePowerIndex(
 592         IN      PDM_ODM_T       pDM_Odm
 593         );
 594
 595 VOID
 596 odm_DynamicTxPowerNIC(
 597         IN      PDM_ODM_T       pDM_Odm
 598         );
 599
 600 #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
 601 VOID
 602 odm_DynamicTxPowerSavePowerIndex(
 603         IN              PDM_ODM_T               pDM_Odm
 604         );
 605
 606 VOID
 607 odm_DynamicTxPowerWritePowerIndex(
 608         IN      PDM_ODM_T       pDM_Odm,
 609         IN      u1Byte          Value);
 610
 611 VOID
 612 odm_DynamicTxPower_92C(
 613         IN      PDM_ODM_T       pDM_Odm
 614         );
 615
 616 VOID
 617 odm_DynamicTxPower_92D(
 618         IN      PDM_ODM_T       pDM_Odm
 619         );
 620
 621 VOID
 622 odm_MPT_DIGCallback(
 623         PRT_TIMER               pTimer
 624 );
 625
 626 VOID
 627 odm_MPT_DIGWorkItemCallback(
 628     IN PVOID            pContext
 629     );
 630 #endif
 631
 632
 633 VOID
 634 odm_RSSIMonitorInit(
 635         IN      PDM_ODM_T       pDM_Odm
 636         );
 637
 638 VOID
 639 odm_RSSIMonitorCheckMP(
 640         IN      PDM_ODM_T       pDM_Odm
 641         );
 642
 643 VOID
 644 odm_RSSIMonitorCheckCE(
 645         IN              PDM_ODM_T               pDM_Odm
 646         );
 647 VOID
 648 odm_RSSIMonitorCheckAP(
 649         IN              PDM_ODM_T               pDM_Odm
 650         );
 651
 652
 653
 654 VOID
 655 odm_RSSIMonitorCheck(
 656         IN              PDM_ODM_T               pDM_Odm
 657         );
 658 VOID
 659 odm_DynamicTxPower(
 660         IN              PDM_ODM_T               pDM_Odm
 661         );
 662
 663 VOID
 664 odm_DynamicTxPowerAP(
 665         IN              PDM_ODM_T               pDM_Odm
 666         );
 667
 668
 669 VOID
 670 odm_SwAntDivInit(
 671         IN              PDM_ODM_T               pDM_Odm
 672         );
 673
 674 VOID
 675 odm_SwAntDivInit_NIC(
 676         IN              PDM_ODM_T               pDM_Odm
 677         );
 678
 679 VOID
 680 odm_SwAntDetectInit(
 681         IN              PDM_ODM_T               pDM_Odm
 682         );
 683
 684 VOID
 685 odm_SwAntDivChkAntSwitch(
 686         IN              PDM_ODM_T               pDM_Odm,
 687         IN              u1Byte                  Step
 688         );
 689
 690 VOID
 691 odm_SwAntDivChkAntSwitchNIC(
 692         IN              PDM_ODM_T               pDM_Odm,
 693         IN              u1Byte          Step
 694         );
 695
 696
 697 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 698 VOID
 699 odm_SwAntDivChkAntSwitchCallback(
 700         PRT_TIMER               pTimer
 701 );
 702 VOID
 703 odm_SwAntDivChkAntSwitchWorkitemCallback(
 704     IN PVOID            pContext
 705     );
 706 VOID
 707 ODM_UpdateInitRateWorkItemCallback(
 708     IN PVOID            pContext
 709     );
 710 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
 711 VOID odm_SwAntDivChkAntSwitchCallback(void *FunctionContext);
 712 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
 713 VOID odm_SwAntDivChkAntSwitchCallback(void *FunctionContext);
 714 #endif
 715
 716
 717
 718 VOID
 719 odm_GlobalAdapterCheck(
 720         IN              VOID
 721         );
 722
 723 VOID
 724 odm_RefreshBasicRateMask(
 725         IN              PDM_ODM_T               pDM_Odm
 726         );
 727
 728 VOID
 729 odm_RefreshRateAdaptiveMask(
 730         IN              PDM_ODM_T               pDM_Odm
 731         );
 732
 733 VOID
 734 ODM_TXPowerTrackingCheck(
 735         IN              PDM_ODM_T               pDM_Odm
 736         );
 737
 738 VOID
 739 odm_TXPowerTrackingCheckAP(
 740         IN              PDM_ODM_T               pDM_Odm
 741         );
 742
 743
 744
 745
 746
 747
 748
 749 VOID
 750 odm_RateAdaptiveMaskInit(
 751         IN      PDM_ODM_T       pDM_Odm
 752         );
 753
 754 VOID
 755 odm_TXPowerTrackingThermalMeterInit(
 756         IN      PDM_ODM_T       pDM_Odm
 757         );
 758
 759
 760 VOID
 761 odm_IQCalibrate(
 762                 IN      PDM_ODM_T       pDM_Odm
 763                 );
 764
 765 VOID
 766 odm_TXPowerTrackingInit(
 767         IN      PDM_ODM_T       pDM_Odm
 768         );
 769
 770 VOID
 771 odm_TXPowerTrackingCheckMP(
 772         IN      PDM_ODM_T       pDM_Odm
 773         );
 774
 775
 776 VOID
 777 odm_TXPowerTrackingCheckCE(
 778         IN      PDM_ODM_T       pDM_Odm
 779         );
 780
 781 #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN))
 782
 783 VOID
 784 ODM_RateAdaptiveStateApInit(
 785         IN      PADAPTER        Adapter ,
 786         IN      PRT_WLAN_STA  pEntry
 787         );
 788
 789 VOID
 790 odm_TXPowerTrackingCallbackThermalMeter92C(
 791             IN PADAPTER Adapter
 792             );
 793
 794 VOID
 795 odm_TXPowerTrackingCallbackRXGainThermalMeter92D(
 796         IN PADAPTER     Adapter
 797         );
 798
 799 VOID
 800 odm_TXPowerTrackingCallbackThermalMeter92D(
 801             IN PADAPTER Adapter
 802             );
 803
 804 VOID
 805 odm_TXPowerTrackingDirectCall92C(
 806             IN  PADAPTER                Adapter
 807             );
 808
 809 VOID
 810 odm_TXPowerTrackingThermalMeterCheck(
 811         IN      PADAPTER                Adapter
 812         );
 813
 814 #endif
 815
 816 VOID
 817 odm_EdcaTurboCheck(
 818         IN              PDM_ODM_T               pDM_Odm
 819         );
 820 VOID
 821 ODM_EdcaTurboInit(
 822         IN      PDM_ODM_T               pDM_Odm
 823 );
 824
 825 #if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
 826 VOID
 827 odm_EdcaTurboCheckMP(
 828         IN              PDM_ODM_T               pDM_Odm
 829         );
 830
 831 //check if edca turbo is disabled
 832 BOOLEAN
 833 odm_IsEdcaTurboDisable(
 834         IN      PDM_ODM_T       pDM_Odm
 835 );
 836 //choose edca paramter for special IOT case
 837 VOID
 838 ODM_EdcaParaSelByIot(
 839         IN      PDM_ODM_T       pDM_Odm,
 840         OUT     u4Byte          *EDCA_BE_UL,
 841         OUT u4Byte              *EDCA_BE_DL
 842         );
 843 //check if it is UL or DL
 844 VOID
 845 odm_EdcaChooseTrafficIdx(
 846         IN      PDM_ODM_T               pDM_Odm,
 847         IN      u8Byte                          cur_tx_bytes,
 848         IN      u8Byte                          cur_rx_bytes,
 849         IN      BOOLEAN                 bBiasOnRx,
 850         OUT BOOLEAN             *pbIsCurRDLState
 851         );
 852
 853 #elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
 854 VOID
 855 odm_EdcaTurboCheckCE(
 856         IN              PDM_ODM_T               pDM_Odm
 857         );
 858 #else
 859 VOID
 860 odm_IotEngine(
 861         IN      PDM_ODM_T       pDM_Odm
 862         );
 863
 864 VOID
 865 odm_EdcaParaInit(
 866         IN      PDM_ODM_T       pDM_Odm
 867         );
 868 #endif
 869
 870
 871
 872 #define         RxDefaultAnt1           0x65a9
 873 #define RxDefaultAnt2           0x569a
 874
 875 VOID
 876 odm_InitHybridAntDiv(
 877         IN PDM_ODM_T    pDM_Odm
 878         );
 879
 880 BOOLEAN
 881 odm_StaDefAntSel(
 882         IN PDM_ODM_T    pDM_Odm,
 883         IN u4Byte               OFDM_Ant1_Cnt,
 884         IN u4Byte               OFDM_Ant2_Cnt,
 885         IN u4Byte               CCK_Ant1_Cnt,
 886         IN u4Byte               CCK_Ant2_Cnt,
 887         OUT u1Byte              *pDefAnt
 888         );
 889
 890 VOID
 891 odm_SetRxIdleAnt(
 892         IN      PDM_ODM_T       pDM_Odm,
 893         IN      u1Byte  Ant,
 894         IN   BOOLEAN   bDualPath
 895 );
 896
 897
 898
 899 VOID
 900 odm_HwAntDiv(
 901         IN      PDM_ODM_T       pDM_Odm
 902 );
 903
 904 VOID    odm_PathDiversityInit(IN        PDM_ODM_T       pDM_Odm);
 905 VOID    odm_PathDiversity(      IN      PDM_ODM_T       pDM_Odm);
 906
 907
 908
 909 //============================================================
 910 //3 Export Interface
 911 //============================================================
 912
 913 //
 914 // 2011/09/21 MH Add to describe different team necessary resource allocate??
 915 //
 916 VOID
 917 ODM_DMInit(
 918         IN              PDM_ODM_T               pDM_Odm
 919         )
 920 {
 921
 922         //2012.05.03 Luke: For all IC series
 923         odm_CommonInfoSelfInit(pDM_Odm);
 924         odm_CmnInfoInit_Debug(pDM_Odm);
 925         odm_DIGInit(pDM_Odm);
 926         odm_AdaptivityInit(pDM_Odm);
 927         odm_RateAdaptiveMaskInit(pDM_Odm);
 928         odm_RSSIMonitorInit(pDM_Odm);
 929
 930 #if (RTL8192E_SUPPORT == 1)
 931         if(pDM_Odm->SupportICType==ODM_RTL8192E)
 932         {
 933                 odm_PrimaryCCA_Check_Init(pDM_Odm);
 934         }
 935 #endif
 936
 937 //#if (MP_DRIVER != 1)
 938         if ( *(pDM_Odm->mp_mode) != 1)
 939             odm_PathDiversityInit(pDM_Odm);
 940 //#endif
 941         ODM_EdcaTurboInit(pDM_Odm);
 942
 943         if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
 944         {
 945                 odm_TXPowerTrackingInit(pDM_Odm);
 946 //#if (MP_DRIVER != 1)
 947                 if ( *(pDM_Odm->mp_mode) != 1)
 948                         ODM_AntDivInit(pDM_Odm);
 949 //#endif
 950         }
 951         else if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
 952         {
 953                 odm_DynamicBBPowerSavingInit(pDM_Odm);
 954                 odm_DynamicTxPowerInit(pDM_Odm);
 955                 odm_TXPowerTrackingInit(pDM_Odm);
 956                 //ODM_EdcaTurboInit(pDM_Odm);
 957 //#if (MP_DRIVER != 1)
 958                 if ( *(pDM_Odm->mp_mode) != 1) {
 959                 if(pDM_Odm->SupportICType==ODM_RTL8723A)
 960                         odm_SwAntDivInit(pDM_Odm);
 961                 else if(pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8192D))
 962                 {
 963                         if(pDM_Odm->AntDivType == HW_ANTDIV)
 964                         odm_InitHybridAntDiv(pDM_Odm);
 965                         else
 966                         odm_SwAntDivInit(pDM_Odm);
 967                 }
 968                 else
 969                         ODM_AntDivInit(pDM_Odm);
 970
 971                 if(pDM_Odm->SupportICType == ODM_RTL8723B)
 972                         odm_SwAntDetectInit(pDM_Odm);
 973                 }
 974 //#endif
 975
 976 //2010.05.30 LukeLee: For CE platform, files in IC subfolders may not be included to be compiled,
 977 // so compile flags must be left here to prevent from compile errors
 978 #if (RTL8188E_SUPPORT == 1)
 979                 if(pDM_Odm->SupportICType==ODM_RTL8188E)
 980                 {
 981                         odm_PrimaryCCA_Init(pDM_Odm);    // Gary
 982                         ODM_RAInfo_Init_all(pDM_Odm);
 983                 }
 984 #endif
 985
 986 //2010.05.30 LukeLee: Following are not incorporated into ODM structure yet.
 987 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 988                 if(pDM_Odm->SupportICType&ODM_RTL8723A)
 989                         odm_PSDMonitorInit(pDM_Odm);
 990
 991                 if(!(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8188E)))
 992                 {
 993                         odm_RXHPInit(pDM_Odm);
 994                 }
 995                 if(pDM_Odm->SupportICType==ODM_RTL8192D)
 996                 {
 997                         odm_PathDivInit_92D(pDM_Odm); //92D Path Div Init   //Neil Chen
 998                 }
 999 #endif
1000         }
1001
1002         ODM_DynamicATCSwitch_init(pDM_Odm);
1003         ODM_ClearTxPowerTrackingState(pDM_Odm);
1004
1005 }
1006
1007 //
1008 // 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM.
1009 // You can not add any dummy function here, be care, you can only use DM structure
1010 // to perform any new ODM_DM.
1011 //
1012 VOID
1013 ODM_DMWatchdog(
1014         IN              PDM_ODM_T               pDM_Odm
1015         )
1016 {
1017         if((pDM_Odm->SupportICType == ODM_RTL8821) && (pDM_Odm->SupportInterface == ODM_ITRF_USB))
1018         {
1019                 if(pDM_Odm->RSSI_Min > 25)
1020                         ODM_Write1Byte(pDM_Odm, 0x4CF, 0x02);
1021                 else if(pDM_Odm->RSSI_Min < 20)
1022                         ODM_Write1Byte(pDM_Odm, 0x4CF, 0x00);
1023         }
1024
1025
1026         odm_CommonInfoSelfUpdate(pDM_Odm);
1027         odm_BasicDbgMessage(pDM_Odm);
1028         odm_FalseAlarmCounterStatistics(pDM_Odm);
1029         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): RSSI=0x%x\n",pDM_Odm->RSSI_Min));
1030
1031         odm_RSSIMonitorCheck(pDM_Odm);
1032
1033 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1034 //#ifdef CONFIG_PLATFORM_SPRD
1035         //For CE Platform(SPRD or Tablet)
1036         //8723A or 8189ES platform
1037         //NeilChen--2012--08--24--
1038         //Fix Leave LPS issue
1039         if(     (adapter_to_pwrctl(pDM_Odm->Adapter)->pwr_mode != PS_MODE_ACTIVE) // in LPS mode
1040                 //&&(
1041                 //      (pDM_Odm->SupportICType & (ODM_RTL8723A ) )||
1042                 //      (pDM_Odm->SupportICType & (ODM_RTL8188E) &&((pDM_Odm->SupportInterface  == ODM_ITRF_SDIO)) )
1043                 //)
1044         )
1045         {
1046                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("----Step1: odm_DIG is in LPS mode\n"));
1047                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("---Step2: 8723AS is in LPS mode\n"));
1048                         odm_DIGbyRSSI_LPS(pDM_Odm);
1049         }
1050         else
1051 //#endif
1052 #endif
1053         {
1054                 odm_DIG(pDM_Odm);
1055         }
1056
1057         {
1058                 pDIG_T  pDM_DigTable = &pDM_Odm->DM_DigTable;
1059                 odm_Adaptivity(pDM_Odm, pDM_DigTable->CurIGValue);
1060         }
1061         odm_CCKPacketDetectionThresh(pDM_Odm);
1062
1063         if(*(pDM_Odm->pbPowerSaving)==TRUE)
1064                 return;
1065
1066
1067         odm_RefreshRateAdaptiveMask(pDM_Odm);
1068         odm_RefreshBasicRateMask(pDM_Odm);
1069         odm_DynamicBBPowerSaving(pDM_Odm);
1070         odm_EdcaTurboCheck(pDM_Odm);
1071         odm_PathDiversity(pDM_Odm);
1072         ODM_DynamicATCSwitch(pDM_Odm);
1073         odm_DynamicTxPower(pDM_Odm);
1074
1075 #if (RTL8192E_SUPPORT == 1)
1076         if(pDM_Odm->SupportICType==ODM_RTL8192E)
1077                 odm_DynamicPrimaryCCA_Check(pDM_Odm);
1078 #endif
1079          //if(pDM_Odm->SupportICType == ODM_RTL8192E)
1080          //        return;
1081
1082
1083 //#if (MP_DRIVER != 1)
1084 if ( *(pDM_Odm->mp_mode) != 1) {
1085         if(pDM_Odm->SupportICType==ODM_RTL8723A)
1086         {
1087                 odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_PEAK);
1088         }
1089         else if(pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8192D))
1090         {
1091                 if(pDM_Odm->AntDivType == HW_ANTDIV)
1092                         odm_HwAntDiv(pDM_Odm);
1093                 else
1094                         odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_PEAK);
1095         }
1096         else
1097                 ODM_AntDiv(pDM_Odm);
1098 }
1099 //#endif
1100
1101         if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
1102         {
1103                 ODM_TXPowerTrackingCheck(pDM_Odm);
1104
1105                 odm_IQCalibrate(pDM_Odm);
1106         }
1107         else if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
1108         {
1109                 ODM_TXPowerTrackingCheck(pDM_Odm);
1110
1111                 //odm_EdcaTurboCheck(pDM_Odm);
1112
1113                 #if( DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1114                 if(!(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8188E)))
1115                         odm_RXHP(pDM_Odm);
1116                 #endif
1117
1118         //2010.05.30 LukeLee: For CE platform, files in IC subfolders may not be included to be compiled,
1119         // so compile flags must be left here to prevent from compile errors
1120 #if (RTL8192D_SUPPORT == 1)
1121                 if(pDM_Odm->SupportICType==ODM_RTL8192D)
1122                         ODM_DynamicEarlyMode(pDM_Odm);
1123 #endif
1124                 odm_DynamicBBPowerSaving(pDM_Odm);
1125 #if (RTL8188E_SUPPORT == 1)
1126                 if(pDM_Odm->SupportICType==ODM_RTL8188E)
1127                         odm_DynamicPrimaryCCA(pDM_Odm);
1128 #endif
1129
1130         }
1131         pDM_Odm->PhyDbgInfo.NumQryBeaconPkt = 0;
1132
1133 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1134         odm_dtc(pDM_Odm);
1135 #endif
1136 }
1137
1138
1139 //
1140 // Init /.. Fixed HW value. Only init time.
1141 //
1142 VOID
1143 ODM_CmnInfoInit(
1144         IN              PDM_ODM_T               pDM_Odm,
1145         IN              ODM_CMNINFO_E   CmnInfo,
1146         IN              u4Byte                  Value
1147         )
1148 {
1149         //
1150         // This section is used for init value
1151         //
1152         switch  (CmnInfo)
1153         {
1154                 //
1155                 // Fixed ODM value.
1156                 //
1157                 case    ODM_CMNINFO_ABILITY:
1158                         pDM_Odm->SupportAbility = (u4Byte)Value;
1159                         break;
1160
1161                 case    ODM_CMNINFO_RF_TYPE:
1162                         pDM_Odm->RFType = (u1Byte)Value;
1163                         break;
1164
1165                 case    ODM_CMNINFO_PLATFORM:
1166                         pDM_Odm->SupportPlatform = (u1Byte)Value;
1167                         break;
1168
1169                 case    ODM_CMNINFO_INTERFACE:
1170                         pDM_Odm->SupportInterface = (u1Byte)Value;
1171                         break;
1172
1173                 case    ODM_CMNINFO_MP_TEST_CHIP:
1174                         pDM_Odm->bIsMPChip= (u1Byte)Value;
1175                         break;
1176
1177                 case    ODM_CMNINFO_IC_TYPE:
1178                         pDM_Odm->SupportICType = Value;
1179                         break;
1180
1181                 case    ODM_CMNINFO_CUT_VER:
1182                         pDM_Odm->CutVersion = (u1Byte)Value;
1183                         break;
1184
1185                 case    ODM_CMNINFO_FAB_VER:
1186                         pDM_Odm->FabVersion = (u1Byte)Value;
1187                         break;
1188
1189                 case    ODM_CMNINFO_RFE_TYPE:
1190                         pDM_Odm->RFEType = (u1Byte)Value;
1191                         break;
1192
1193                 case    ODM_CMNINFO_RF_ANTENNA_TYPE:
1194                         pDM_Odm->AntDivType= (u1Byte)Value;
1195                         break;
1196
1197                 case    ODM_CMNINFO_BOARD_TYPE:
1198                         pDM_Odm->BoardType = (u1Byte)Value;
1199                         break;
1200
1201                 case    ODM_CMNINFO_PACKAGE_TYPE:
1202                         pDM_Odm->PackageType = (u1Byte)Value;
1203                         break;
1204
1205                 case    ODM_CMNINFO_EXT_LNA:
1206                         pDM_Odm->ExtLNA = (u1Byte)Value;
1207                         break;
1208
1209                 case    ODM_CMNINFO_5G_EXT_LNA:
1210                         pDM_Odm->ExtLNA5G = (u1Byte)Value;
1211                         break;
1212
1213                 case    ODM_CMNINFO_EXT_PA:
1214                         pDM_Odm->ExtPA = (u1Byte)Value;
1215                         break;
1216
1217                 case    ODM_CMNINFO_5G_EXT_PA:
1218                         pDM_Odm->ExtPA5G = (u1Byte)Value;
1219                         break;
1220
1221                 case    ODM_CMNINFO_GPA:
1222                         pDM_Odm->TypeGPA= (ODM_TYPE_GPA_E)Value;
1223                         break;
1224                 case    ODM_CMNINFO_APA:
1225                         pDM_Odm->TypeAPA= (ODM_TYPE_APA_E)Value;
1226                         break;
1227                 case    ODM_CMNINFO_GLNA:
1228                         pDM_Odm->TypeGLNA= (ODM_TYPE_GLNA_E)Value;
1229                         break;
1230                 case    ODM_CMNINFO_ALNA:
1231                         pDM_Odm->TypeALNA= (ODM_TYPE_ALNA_E)Value;
1232                         break;
1233
1234                 case    ODM_CMNINFO_EXT_TRSW:
1235                         pDM_Odm->ExtTRSW = (u1Byte)Value;
1236                         break;
1237                 case    ODM_CMNINFO_PATCH_ID:
1238                         pDM_Odm->PatchID = (u1Byte)Value;
1239                         break;
1240                 case    ODM_CMNINFO_BINHCT_TEST:
1241                         pDM_Odm->bInHctTest = (BOOLEAN)Value;
1242                         break;
1243                 case    ODM_CMNINFO_BWIFI_TEST:
1244                         pDM_Odm->bWIFITest = (BOOLEAN)Value;
1245                         break;
1246
1247                 case    ODM_CMNINFO_SMART_CONCURRENT:
1248                         pDM_Odm->bDualMacSmartConcurrent = (BOOLEAN )Value;
1249                         break;
1250
1251                 //To remove the compiler warning, must add an empty default statement to handle the other values.
1252                 default:
1253                         //do nothing
1254                         break;
1255
1256         }
1257
1258 }
1259
1260
1261 VOID
1262 ODM_CmnInfoHook(
1263         IN              PDM_ODM_T               pDM_Odm,
1264         IN              ODM_CMNINFO_E   CmnInfo,
1265         IN              PVOID                   pValue
1266         )
1267 {
1268         //
1269         // Hook call by reference pointer.
1270         //
1271         switch  (CmnInfo)
1272         {
1273                 //
1274                 // Dynamic call by reference pointer.
1275                 //
1276                 case    ODM_CMNINFO_MAC_PHY_MODE:
1277                         pDM_Odm->pMacPhyMode = (u1Byte *)pValue;
1278                         break;
1279
1280                 case    ODM_CMNINFO_TX_UNI:
1281                         pDM_Odm->pNumTxBytesUnicast = (u8Byte *)pValue;
1282                         break;
1283
1284                 case    ODM_CMNINFO_RX_UNI:
1285                         pDM_Odm->pNumRxBytesUnicast = (u8Byte *)pValue;
1286                         break;
1287
1288                 case    ODM_CMNINFO_WM_MODE:
1289                         pDM_Odm->pWirelessMode = (u1Byte *)pValue;
1290                         break;
1291
1292                 case    ODM_CMNINFO_BAND:
1293                         pDM_Odm->pBandType = (u1Byte *)pValue;
1294                         break;
1295
1296                 case    ODM_CMNINFO_SEC_CHNL_OFFSET:
1297                         pDM_Odm->pSecChOffset = (u1Byte *)pValue;
1298                         break;
1299
1300                 case    ODM_CMNINFO_SEC_MODE:
1301                         pDM_Odm->pSecurity = (u1Byte *)pValue;
1302                         break;
1303
1304                 case    ODM_CMNINFO_BW:
1305                         pDM_Odm->pBandWidth = (u1Byte *)pValue;
1306                         break;
1307
1308                 case    ODM_CMNINFO_CHNL:
1309                         pDM_Odm->pChannel = (u1Byte *)pValue;
1310                         break;
1311
1312                 case    ODM_CMNINFO_DMSP_GET_VALUE:
1313                         pDM_Odm->pbGetValueFromOtherMac = (BOOLEAN *)pValue;
1314                         break;
1315
1316                 case    ODM_CMNINFO_BUDDY_ADAPTOR:
1317                         pDM_Odm->pBuddyAdapter = (PADAPTER *)pValue;
1318                         break;
1319
1320                 case    ODM_CMNINFO_DMSP_IS_MASTER:
1321                         pDM_Odm->pbMasterOfDMSP = (BOOLEAN *)pValue;
1322                         break;
1323
1324                 case    ODM_CMNINFO_SCAN:
1325                         pDM_Odm->pbScanInProcess = (BOOLEAN *)pValue;
1326                         break;
1327
1328                 case    ODM_CMNINFO_POWER_SAVING:
1329                         pDM_Odm->pbPowerSaving = (BOOLEAN *)pValue;
1330                         break;
1331
1332                 case    ODM_CMNINFO_ONE_PATH_CCA:
1333                         pDM_Odm->pOnePathCCA = (u1Byte *)pValue;
1334                         break;
1335
1336                 case    ODM_CMNINFO_DRV_STOP:
1337                         pDM_Odm->pbDriverStopped =  (BOOLEAN *)pValue;
1338                         break;
1339
1340                 case    ODM_CMNINFO_PNP_IN:
1341                         pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep =  (BOOLEAN *)pValue;
1342                         break;
1343
1344                 case    ODM_CMNINFO_INIT_ON:
1345                         pDM_Odm->pinit_adpt_in_progress =  (BOOLEAN *)pValue;
1346                         break;
1347
1348                 case    ODM_CMNINFO_ANT_TEST:
1349                         pDM_Odm->pAntennaTest =  (u1Byte *)pValue;
1350                         break;
1351
1352                 case    ODM_CMNINFO_NET_CLOSED:
1353                         pDM_Odm->pbNet_closed = (BOOLEAN *)pValue;
1354                         break;
1355
1356                 case    ODM_CMNINFO_FORCED_RATE:
1357                         pDM_Odm->pForcedDataRate = (pu2Byte)pValue;
1358                         break;
1359
1360                 case  ODM_CMNINFO_FORCED_IGI_LB:
1361                         pDM_Odm->pu1ForcedIgiLb = (u1Byte *)pValue;
1362                         break;
1363
1364                 case    ODM_CMNINFO_MP_MODE:
1365                         pDM_Odm->mp_mode = (u1Byte *)pValue;
1366                         break;
1367
1368                 //case  ODM_CMNINFO_RTSTA_AID:
1369                 //      pDM_Odm->pAidMap =  (u1Byte *)pValue;
1370                 //      break;
1371
1372                 //case  ODM_CMNINFO_BT_COEXIST:
1373                 //      pDM_Odm->BTCoexist = (BOOLEAN *)pValue;
1374
1375                 //case  ODM_CMNINFO_STA_STATUS:
1376                         //pDM_Odm->pODM_StaInfo[] = (PSTA_INFO_T)pValue;
1377                         //break;
1378
1379                 //case  ODM_CMNINFO_PHY_STATUS:
1380                 //      pDM_Odm->pPhyInfo = (ODM_PHY_INFO *)pValue;
1381                 //      break;
1382
1383                 //case  ODM_CMNINFO_MAC_STATUS:
1384                 //      pDM_Odm->pMacInfo = (ODM_MAC_INFO *)pValue;
1385                 //      break;
1386                 //To remove the compiler warning, must add an empty default statement to handle the other values.
1387                 default:
1388                         //do nothing
1389                         break;
1390
1391         }
1392
1393 }
1394
1395
1396 VOID
1397 ODM_CmnInfoPtrArrayHook(
1398         IN              PDM_ODM_T               pDM_Odm,
1399         IN              ODM_CMNINFO_E   CmnInfo,
1400         IN              u2Byte                  Index,
1401         IN              PVOID                   pValue
1402         )
1403 {
1404         //
1405         // Hook call by reference pointer.
1406         //
1407         switch  (CmnInfo)
1408         {
1409                 //
1410                 // Dynamic call by reference pointer.
1411                 //
1412                 case    ODM_CMNINFO_STA_STATUS:
1413                         pDM_Odm->pODM_StaInfo[Index] = (PSTA_INFO_T)pValue;
1414                         break;
1415                 //To remove the compiler warning, must add an empty default statement to handle the other values.
1416                 default:
1417                         //do nothing
1418                         break;
1419         }
1420
1421 }
1422
1423
1424 //
1425 // Update Band/CHannel/.. The values are dynamic but non-per-packet.
1426 //
1427 VOID
1428 ODM_CmnInfoUpdate(
1429         IN              PDM_ODM_T               pDM_Odm,
1430         IN              u4Byte                  CmnInfo,
1431         IN              u8Byte                  Value
1432         )
1433 {
1434         //
1435         // This init variable may be changed in run time.
1436         //
1437         switch  (CmnInfo)
1438         {
1439                 case ODM_CMNINFO_LINK_IN_PROGRESS:
1440                         pDM_Odm->bLinkInProcess = (BOOLEAN)Value;
1441                         break;
1442
1443                 case    ODM_CMNINFO_ABILITY:
1444                         pDM_Odm->SupportAbility = (u4Byte)Value;
1445                         break;
1446
1447                 case    ODM_CMNINFO_RF_TYPE:
1448                         pDM_Odm->RFType = (u1Byte)Value;
1449                         break;
1450
1451                 case    ODM_CMNINFO_WIFI_DIRECT:
1452                         pDM_Odm->bWIFI_Direct = (BOOLEAN)Value;
1453                         break;
1454
1455                 case    ODM_CMNINFO_WIFI_DISPLAY:
1456                         pDM_Odm->bWIFI_Display = (BOOLEAN)Value;
1457                         break;
1458
1459                 case    ODM_CMNINFO_LINK:
1460                         pDM_Odm->bLinked = (BOOLEAN)Value;
1461                         break;
1462
1463                 case    ODM_CMNINFO_STATION_STATE:
1464                         pDM_Odm->bsta_state = (BOOLEAN)Value;
1465                         break;
1466
1467                 case    ODM_CMNINFO_RSSI_MIN:
1468                         pDM_Odm->RSSI_Min= (u1Byte)Value;
1469                         break;
1470
1471                 case    ODM_CMNINFO_DBG_COMP:
1472                         pDM_Odm->DebugComponents = Value;
1473                         break;
1474
1475                 case    ODM_CMNINFO_DBG_LEVEL:
1476                         pDM_Odm->DebugLevel = (u4Byte)Value;
1477                         break;
1478                 case    ODM_CMNINFO_RA_THRESHOLD_HIGH:
1479                         pDM_Odm->RateAdaptive.HighRSSIThresh = (u1Byte)Value;
1480                         break;
1481
1482                 case    ODM_CMNINFO_RA_THRESHOLD_LOW:
1483                         pDM_Odm->RateAdaptive.LowRSSIThresh = (u1Byte)Value;
1484                         break;
1485                 // The following is for BT HS mode and BT coexist mechanism.
1486                 case ODM_CMNINFO_BT_DISABLED:
1487                         pDM_Odm->bBtDisabled = (BOOLEAN)Value;
1488                         break;
1489
1490                 case ODM_CMNINFO_BT_HS_CONNECT_PROCESS:
1491                         pDM_Odm->bBtConnectProcess = (BOOLEAN)Value;
1492                         break;
1493
1494                 case ODM_CMNINFO_BT_HS_RSSI:
1495                         pDM_Odm->btHsRssi = (u1Byte)Value;
1496                         break;
1497
1498                 case    ODM_CMNINFO_BT_OPERATION:
1499                         pDM_Odm->bBtHsOperation = (BOOLEAN)Value;
1500                         break;
1501
1502                 case    ODM_CMNINFO_BT_LIMITED_DIG:
1503                         pDM_Odm->bBtLimitedDig = (BOOLEAN)Value;
1504                         break;
1505
1506                 case    ODM_CMNINFO_BT_DISABLE_EDCA:
1507                         pDM_Odm->bBtDisableEdcaTurbo = (BOOLEAN)Value;
1508                         break;
1509
1510 /*
1511                 case    ODM_CMNINFO_OP_MODE:
1512                         pDM_Odm->OPMode = (u1Byte)Value;
1513                         break;
1514
1515                 case    ODM_CMNINFO_WM_MODE:
1516                         pDM_Odm->WirelessMode = (u1Byte)Value;
1517                         break;
1518
1519                 case    ODM_CMNINFO_BAND:
1520                         pDM_Odm->BandType = (u1Byte)Value;
1521                         break;
1522
1523                 case    ODM_CMNINFO_SEC_CHNL_OFFSET:
1524                         pDM_Odm->SecChOffset = (u1Byte)Value;
1525                         break;
1526
1527                 case    ODM_CMNINFO_SEC_MODE:
1528                         pDM_Odm->Security = (u1Byte)Value;
1529                         break;
1530
1531                 case    ODM_CMNINFO_BW:
1532                         pDM_Odm->BandWidth = (u1Byte)Value;
1533                         break;
1534
1535                 case    ODM_CMNINFO_CHNL:
1536                         pDM_Odm->Channel = (u1Byte)Value;
1537                         break;
1538 */
1539                 default:
1540                         //do nothing
1541                         break;
1542         }
1543
1544
1545 }
1546
1547 VOID
1548 odm_CommonInfoSelfInit(
1549         IN              PDM_ODM_T               pDM_Odm
1550         )
1551 {
1552         pFAT_T                  pDM_FatTable = &pDM_Odm->DM_FatTable;
1553         pDM_Odm->bCckHighPower = (BOOLEAN) ODM_GetBBReg(pDM_Odm, ODM_REG(CCK_RPT_FORMAT,pDM_Odm), ODM_BIT(CCK_RPT_FORMAT,pDM_Odm));
1554         pDM_Odm->RFPathRxEnable = (u1Byte) ODM_GetBBReg(pDM_Odm, ODM_REG(BB_RX_PATH,pDM_Odm), ODM_BIT(BB_RX_PATH,pDM_Odm));
1555 #if (DM_ODM_SUPPORT_TYPE != ODM_CE)
1556         pDM_Odm->pbNet_closed = &pDM_Odm->BOOLEAN_temp;
1557 #endif
1558
1559         ODM_InitDebugSetting(pDM_Odm);
1560
1561         if(pDM_Odm->SupportICType==ODM_RTL8723A)
1562         {
1563                 pDM_Odm->AntDivType = SW_ANTDIV;
1564         }
1565         else if(pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8192D))
1566         {
1567            #if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
1568                 pDM_Odm->AntDivType = HW_ANTDIV;
1569            #elif (defined(CONFIG_SW_ANTENNA_DIVERSITY))
1570                 pDM_Odm->AntDivType = SW_ANTDIV;
1571            #endif
1572         }
1573         pDM_Odm->TxRate = 0xFF;
1574 #if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
1575 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
1576
1577         if(pDM_Odm->SupportICType==ODM_RTL8723B)
1578         {
1579                 if((!pDM_Odm->DM_SWAT_Table.ANTA_ON || !pDM_Odm->DM_SWAT_Table.ANTB_ON))
1580                         pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);
1581         }
1582
1583 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
1584
1585         #if(defined(CONFIG_NOT_SUPPORT_ANTDIV))
1586                 pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);
1587                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Disable AntDiv function] : Not Support 2.4G & 5G Antenna Diversity\n"));
1588         #elif(defined(CONFIG_2G5G_SUPPORT_ANTDIV))
1589                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Enable AntDiv function] : 2.4G & 5G Support Antenna Diversity Simultaneously \n"));
1590                 pDM_FatTable->AntDiv_2G_5G = (ODM_ANTDIV_2G|ODM_ANTDIV_5G);
1591                 if(pDM_Odm->SupportICType & ODM_ANTDIV_SUPPORT)
1592                         pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV;
1593                 if(*pDM_Odm->pBandType == ODM_BAND_5G )
1594                 {
1595                         #if ( defined(CONFIG_5G_CGCS_RX_DIVERSITY) )
1596                                 pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV;
1597                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n"));
1598                         #elif( defined(CONFIG_5G_CG_TRX_DIVERSITY) )
1599                                 pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;
1600                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CG_TRX_HW_ANTDIV\n"));
1601                         #elif( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) )
1602                                 pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV;
1603                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CG_SMART_ANTDIV\n"));
1604                         #endif
1605                 }
1606                 else    if(*pDM_Odm->pBandType == ODM_BAND_2_4G )
1607                 {
1608                         #if ( defined(CONFIG_2G_CGCS_RX_DIVERSITY) )
1609                                 pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV;
1610                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n"));
1611                         #elif( defined(CONFIG_2G_CG_TRX_DIVERSITY) )
1612                                 pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;
1613                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CG_TRX_HW_ANTDIV\n"));
1614                         #elif( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) )
1615                                 pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV;
1616                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CG_SMART_ANTDIV\n"));
1617                         #endif
1618                 }
1619         #elif(defined(CONFIG_5G_SUPPORT_ANTDIV))
1620                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n"));
1621                 pDM_FatTable->AntDiv_2G_5G = (ODM_ANTDIV_5G);
1622                 if(*pDM_Odm->pBandType == ODM_BAND_5G )
1623                 {
1624                         if(pDM_Odm->SupportICType & ODM_ANTDIV_5G_SUPPORT_IC)
1625                                 pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV;
1626                         #if ( defined(CONFIG_5G_CGCS_RX_DIVERSITY) )
1627                                 pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV;
1628                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n"));
1629                         #elif( defined(CONFIG_5G_CG_TRX_DIVERSITY) )
1630                                 pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;
1631                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CG_TRX_HW_ANTDIV\n"));
1632                         #elif( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) )
1633                                 pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV;
1634                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CG_SMART_ANTDIV\n"));
1635                         #endif
1636                 }
1637                 else if(*pDM_Odm->pBandType == ODM_BAND_2_4G )
1638                 {
1639                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Not Support 2G AntDivType\n"));
1640                         pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);
1641                 }
1642         #elif(defined(CONFIG_2G_SUPPORT_ANTDIV))
1643                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Enable AntDiv function] : Only 2.4G Support Antenna Diversity\n"));
1644                 pDM_FatTable->AntDiv_2G_5G = (ODM_ANTDIV_2G);
1645                 if(*pDM_Odm->pBandType == ODM_BAND_2_4G )
1646                 {
1647                         if(pDM_Odm->SupportICType & ODM_ANTDIV_2G_SUPPORT_IC)
1648                                 pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV;
1649                         #if ( defined(CONFIG_2G_CGCS_RX_DIVERSITY) )
1650                                 pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV;
1651                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n"));
1652                         #elif( defined(CONFIG_2G_CG_TRX_DIVERSITY) )
1653                                 pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;
1654                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CG_TRX_HW_ANTDIV\n"));
1655                         #elif( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) )
1656                                 pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV;
1657                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CG_SMART_ANTDIV\n"));
1658                         #endif
1659                 }
1660                 else if(*pDM_Odm->pBandType == ODM_BAND_5G )
1661                 {
1662                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Not Support 5G AntDivType\n"));
1663                         pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);
1664                 }
1665         #endif
1666 #endif //#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
1667 #endif //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
1668
1669 }
1670
1671 VOID
1672 odm_CommonInfoSelfUpdate(
1673         IN              PDM_ODM_T               pDM_Odm
1674         )
1675 {
1676         u1Byte  EntryCnt=0;
1677         u1Byte  i;
1678         PSTA_INFO_T     pEntry;
1679
1680 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1681
1682         PADAPTER        Adapter =  pDM_Odm->Adapter;
1683         PMGNT_INFO      pMgntInfo = &Adapter->MgntInfo;
1684
1685         pEntry = pDM_Odm->pODM_StaInfo[0];
1686         if(pMgntInfo->mAssoc)
1687         {
1688                 pEntry->bUsed=TRUE;
1689                 for (i=0; i<6; i++)
1690                         pEntry->MacAddr[i] = pMgntInfo->Bssid[i];
1691         }
1692         else
1693         {
1694                 pEntry->bUsed=FALSE;
1695                 for (i=0; i<6; i++)
1696                         pEntry->MacAddr[i] = 0;
1697         }
1698 #endif
1699
1700
1701         if(*(pDM_Odm->pBandWidth) == ODM_BW40M)
1702         {
1703                 if(*(pDM_Odm->pSecChOffset) == 1)
1704                         pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) -2;
1705                 else if(*(pDM_Odm->pSecChOffset) == 2)
1706                         pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) +2;
1707         }
1708         else
1709                 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel);
1710
1711         for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
1712         {
1713                 pEntry = pDM_Odm->pODM_StaInfo[i];
1714                 if(IS_STA_VALID(pEntry))
1715                         EntryCnt++;
1716         }
1717         if(EntryCnt == 1)
1718                 pDM_Odm->bOneEntryOnly = TRUE;
1719         else
1720                 pDM_Odm->bOneEntryOnly = FALSE;
1721 }
1722
1723 VOID
1724 odm_CmnInfoInit_Debug(
1725         IN              PDM_ODM_T               pDM_Odm
1726         )
1727 {
1728         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoInit_Debug==>\n"));
1729         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportPlatform=%d\n",pDM_Odm->SupportPlatform) );
1730         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportAbility=0x%x\n",pDM_Odm->SupportAbility) );
1731         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportInterface=%d\n",pDM_Odm->SupportInterface) );
1732         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportICType=0x%x\n",pDM_Odm->SupportICType) );
1733         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("CutVersion=%d\n",pDM_Odm->CutVersion) );
1734         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("FabVersion=%d\n",pDM_Odm->FabVersion) );
1735         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("RFType=%d\n",pDM_Odm->RFType) );
1736         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("BoardType=%d\n",pDM_Odm->BoardType) );
1737         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtLNA=%d\n",pDM_Odm->ExtLNA) );
1738         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtPA=%d\n",pDM_Odm->ExtPA) );
1739         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtTRSW=%d\n",pDM_Odm->ExtTRSW) );
1740         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("PatchID=%d\n",pDM_Odm->PatchID) );
1741         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bInHctTest=%d\n",pDM_Odm->bInHctTest) );
1742         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFITest=%d\n",pDM_Odm->bWIFITest) );
1743         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bDualMacSmartConcurrent=%d\n",pDM_Odm->bDualMacSmartConcurrent) );
1744
1745 }
1746
1747 VOID
1748 odm_CmnInfoHook_Debug(
1749         IN              PDM_ODM_T               pDM_Odm
1750         )
1751 {
1752         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoHook_Debug==>\n"));
1753         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumTxBytesUnicast=%llu\n",*(pDM_Odm->pNumTxBytesUnicast)) );
1754         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumRxBytesUnicast=%llu\n",*(pDM_Odm->pNumRxBytesUnicast)) );
1755         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pWirelessMode=0x%x\n",*(pDM_Odm->pWirelessMode)) );
1756         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecChOffset=%d\n",*(pDM_Odm->pSecChOffset)) );
1757         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecurity=%d\n",*(pDM_Odm->pSecurity)) );
1758         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandWidth=%d\n",*(pDM_Odm->pBandWidth)) );
1759         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pChannel=%d\n",*(pDM_Odm->pChannel)) );
1760
1761         if(pDM_Odm->SupportICType==ODM_RTL8192D)
1762         {
1763                 if(pDM_Odm->pBandType)
1764                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandType=%d\n",*(pDM_Odm->pBandType)) );
1765                 if(pDM_Odm->pMacPhyMode)
1766                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pMacPhyMode=%d\n",*(pDM_Odm->pMacPhyMode)) );
1767                 if(pDM_Odm->pBuddyAdapter)
1768                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbGetValueFromOtherMac=%d\n",*(pDM_Odm->pbGetValueFromOtherMac)) );
1769                 if(pDM_Odm->pBuddyAdapter)
1770                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBuddyAdapter=%p\n",*(pDM_Odm->pBuddyAdapter)) );
1771                 if(pDM_Odm->pbMasterOfDMSP)
1772                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbMasterOfDMSP=%d\n",*(pDM_Odm->pbMasterOfDMSP)) );
1773         }
1774         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbScanInProcess=%d\n",*(pDM_Odm->pbScanInProcess)) );
1775         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbPowerSaving=%d\n",*(pDM_Odm->pbPowerSaving)) );
1776
1777         if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
1778                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pOnePathCCA=%d\n",*(pDM_Odm->pOnePathCCA)) );
1779 }
1780
1781 VOID
1782 odm_CmnInfoUpdate_Debug(
1783         IN              PDM_ODM_T               pDM_Odm
1784         )
1785 {
1786         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoUpdate_Debug==>\n"));
1787         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Direct=%d\n",pDM_Odm->bWIFI_Direct) );
1788         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Display=%d\n",pDM_Odm->bWIFI_Display) );
1789         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked=%d\n",pDM_Odm->bLinked) );
1790         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min=%d\n",pDM_Odm->RSSI_Min) );
1791 }
1792
1793 VOID
1794 odm_BasicDbgMessage
1795 (
1796         IN              PDM_ODM_T               pDM_Odm
1797         )
1798 {
1799         PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
1800         pDIG_T  pDM_DigTable = &pDM_Odm->DM_DigTable;
1801
1802         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_BasicDbgMsg==>\n"));
1803         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked = %d, RSSI_Min = %d, CurrentIGI = 0x%x \n",
1804                 pDM_Odm->bLinked, pDM_Odm->RSSI_Min, pDM_DigTable->CurIGValue) );
1805         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("Cnt_Cck_fail = %d, Cnt_Ofdm_fail = %d, Total False Alarm = %d\n",
1806                 FalseAlmCnt->Cnt_Cck_fail, FalseAlmCnt->Cnt_Ofdm_fail, FalseAlmCnt->Cnt_all));
1807         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("RxRate = 0x%x, RSSI_A = %d, RSSI_B = %d\n",
1808                 pDM_Odm->RxRate, pDM_Odm->RSSI_A, pDM_Odm->RSSI_B));
1809         //ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_C = %d, RSSI_D = %d\n", pDM_Odm->RSSI_C, pDM_Odm->RSSI_D));
1810
1811 }
1812
1813 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1814 VOID
1815 ODM_InitAllWorkItems(IN PDM_ODM_T       pDM_Odm )
1816 {
1817 #if USE_WORKITEM
1818         PADAPTER                pAdapter = pDM_Odm->Adapter;
1819
1820         ODM_InitializeWorkItem( pDM_Odm,
1821                                                         &pDM_Odm->DM_SWAT_Table.SwAntennaSwitchWorkitem_8723B,
1822                                                         (RT_WORKITEM_CALL_BACK)ODM_SW_AntDiv_WorkitemCallback,
1823                                                         (PVOID)pAdapter,
1824                                                         "AntennaSwitchWorkitem");
1825
1826         ODM_InitializeWorkItem( pDM_Odm,
1827                                                         &pDM_Odm->DM_SWAT_Table.SwAntennaSwitchWorkitem,
1828                                                         (RT_WORKITEM_CALL_BACK)odm_SwAntDivChkAntSwitchWorkitemCallback,
1829                                                         (PVOID)pAdapter,
1830                                                         "AntennaSwitchWorkitem");
1831
1832
1833         ODM_InitializeWorkItem(
1834                 pDM_Odm,
1835                 &(pDM_Odm->PathDivSwitchWorkitem),
1836                 (RT_WORKITEM_CALL_BACK)odm_PathDivChkAntSwitchWorkitemCallback,
1837                 (PVOID)pAdapter,
1838                 "SWAS_WorkItem");
1839
1840         ODM_InitializeWorkItem(
1841                 pDM_Odm,
1842                 &(pDM_Odm->CCKPathDiversityWorkitem),
1843                 (RT_WORKITEM_CALL_BACK)odm_CCKTXPathDiversityWorkItemCallback,
1844                 (PVOID)pAdapter,
1845                 "CCKTXPathDiversityWorkItem");
1846
1847         ODM_InitializeWorkItem(
1848                 pDM_Odm,
1849                 &(pDM_Odm->MPT_DIGWorkitem),
1850                 (RT_WORKITEM_CALL_BACK)odm_MPT_DIGWorkItemCallback,
1851                 (PVOID)pAdapter,
1852                 "MPT_DIGWorkitem");
1853
1854         ODM_InitializeWorkItem(
1855                 pDM_Odm,
1856                 &(pDM_Odm->RaRptWorkitem),
1857                 (RT_WORKITEM_CALL_BACK)ODM_UpdateInitRateWorkItemCallback,
1858                 (PVOID)pAdapter,
1859                 "RaRptWorkitem");
1860
1861 #if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
1862 #if (RTL8188E_SUPPORT == 1)
1863         ODM_InitializeWorkItem(
1864                 pDM_Odm,
1865                 &(pDM_Odm->FastAntTrainingWorkitem),
1866                 (RT_WORKITEM_CALL_BACK)odm_FastAntTrainingWorkItemCallback,
1867                 (PVOID)pAdapter,
1868                 "FastAntTrainingWorkitem");
1869 #endif
1870 #endif
1871         ODM_InitializeWorkItem(
1872                 pDM_Odm,
1873                 &(pDM_Odm->DM_RXHP_Table.PSDTimeWorkitem),
1874                 (RT_WORKITEM_CALL_BACK)odm_PSD_RXHPWorkitemCallback,
1875                 (PVOID)pAdapter,
1876                 "PSDRXHP_WorkItem");
1877 #endif
1878 }
1879
1880 VOID
1881 ODM_FreeAllWorkItems(IN PDM_ODM_T       pDM_Odm )
1882 {
1883 #if USE_WORKITEM
1884         ODM_FreeWorkItem(       &(pDM_Odm->DM_SWAT_Table.SwAntennaSwitchWorkitem_8723B));
1885
1886         ODM_FreeWorkItem(       &(pDM_Odm->DM_SWAT_Table.SwAntennaSwitchWorkitem));
1887
1888         ODM_FreeWorkItem(&(pDM_Odm->PathDivSwitchWorkitem));
1889
1890         ODM_FreeWorkItem(&(pDM_Odm->CCKPathDiversityWorkitem));
1891
1892         ODM_FreeWorkItem(&(pDM_Odm->FastAntTrainingWorkitem));
1893
1894         ODM_FreeWorkItem(&(pDM_Odm->MPT_DIGWorkitem));
1895
1896         ODM_FreeWorkItem(&(pDM_Odm->RaRptWorkitem));
1897
1898         ODM_FreeWorkItem((&pDM_Odm->DM_RXHP_Table.PSDTimeWorkitem));
1899 #endif
1900
1901 }
1902 #endif
1903
1904 /*
1905 VOID
1906 odm_FindMinimumRSSI(
1907         IN              PDM_ODM_T               pDM_Odm
1908         )
1909 {
1910         u4Byte  i;
1911         u1Byte  RSSI_Min = 0xFF;
1912
1913         for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
1914         {
1915 //              if(pDM_Odm->pODM_StaInfo[i] != NULL)
1916                 if(IS_STA_VALID(pDM_Odm->pODM_StaInfo[i]) )
1917                 {
1918                         if(pDM_Odm->pODM_StaInfo[i]->RSSI_Ave < RSSI_Min)
1919                         {
1920                                 RSSI_Min = pDM_Odm->pODM_StaInfo[i]->RSSI_Ave;
1921                         }
1922                 }
1923         }
1924
1925         pDM_Odm->RSSI_Min = RSSI_Min;
1926
1927 }
1928
1929 VOID
1930 odm_IsLinked(
1931         IN              PDM_ODM_T               pDM_Odm
1932         )
1933 {
1934         u4Byte i;
1935         BOOLEAN Linked = FALSE;
1936
1937         for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
1938         {
1939                         if(IS_STA_VALID(pDM_Odm->pODM_StaInfo[i]) )
1940                         {
1941                                 Linked = TRUE;
1942                                 break;
1943                         }
1944
1945         }
1946
1947         pDM_Odm->bLinked = Linked;
1948 }
1949 */
1950
1951
1952 //3============================================================
1953 //3 DIG
1954 //3============================================================
1955 /*-----------------------------------------------------------------------------
1956  * Function:    odm_DIGInit()
1957  *
1958  * Overview:    Set DIG scheme init value.
1959  *
1960  * Input:               NONE
1961  *
1962  * Output:              NONE
1963  *
1964  * Return:              NONE
1965  *
1966  * Revised History:
1967  *      When            Who             Remark
1968  *
1969  *---------------------------------------------------------------------------*/
1970 VOID
1971 ODM_ChangeDynamicInitGainThresh(
1972         IN      PDM_ODM_T       pDM_Odm,
1973         IN      u4Byte          DM_Type,
1974         IN      u4Byte          DM_Value
1975         )
1976 {
1977         pDIG_T  pDM_DigTable = &pDM_Odm->DM_DigTable;
1978
1979         if (DM_Type == DIG_TYPE_THRESH_HIGH)
1980         {
1981                 pDM_DigTable->RssiHighThresh = DM_Value;
1982         }
1983         else if (DM_Type == DIG_TYPE_THRESH_LOW)
1984         {
1985                 pDM_DigTable->RssiLowThresh = DM_Value;
1986         }
1987         else if (DM_Type == DIG_TYPE_ENABLE)
1988         {
1989                 pDM_DigTable->Dig_Enable_Flag   = TRUE;
1990         }
1991         else if (DM_Type == DIG_TYPE_DISABLE)
1992         {
1993                 pDM_DigTable->Dig_Enable_Flag = FALSE;
1994         }
1995         else if (DM_Type == DIG_TYPE_BACKOFF)
1996         {
1997                 if(DM_Value > 30)
1998                         DM_Value = 30;
1999                 pDM_DigTable->BackoffVal = (u1Byte)DM_Value;
2000         }
2001         else if(DM_Type == DIG_TYPE_RX_GAIN_MIN)
2002         {
2003                 if(DM_Value == 0)
2004                         DM_Value = 0x1;
2005                 pDM_DigTable->rx_gain_range_min = (u1Byte)DM_Value;
2006         }
2007         else if(DM_Type == DIG_TYPE_RX_GAIN_MAX)
2008         {
2009                 if(DM_Value > 0x50)
2010                         DM_Value = 0x50;
2011                 pDM_DigTable->rx_gain_range_max = (u1Byte)DM_Value;
2012         }
2013 }       /* DM_ChangeDynamicInitGainThresh */
2014
2015 int getIGIForDiff(int value_IGI)
2016 {
2017         #define ONERCCA_LOW_TH          0x30
2018         #define ONERCCA_LOW_DIFF        8
2019
2020         if (value_IGI < ONERCCA_LOW_TH) {
2021                 if ((ONERCCA_LOW_TH - value_IGI) < ONERCCA_LOW_DIFF)
2022                         return ONERCCA_LOW_TH;
2023                 else
2024                         return value_IGI + ONERCCA_LOW_DIFF;
2025         } else {
2026                 return value_IGI;
2027         }
2028 }
2029
2030
2031 VOID
2032 odm_AdaptivityInit(
2033 IN PDM_ODM_T pDM_Odm
2034 )
2035 {
2036         if(pDM_Odm->SupportICType == ODM_RTL8723B)
2037         {
2038                 pDM_Odm->TH_L2H_ini = 0xf8; // -8
2039         }
2040         if((pDM_Odm->SupportICType == ODM_RTL8192E)&&(pDM_Odm->SupportInterface == ODM_ITRF_PCIE))
2041         {
2042                 pDM_Odm->TH_L2H_ini = 0xf0; // -16
2043         }
2044         else
2045         {
2046                 pDM_Odm->TH_L2H_ini = 0xf9; // -7
2047         }
2048
2049         pDM_Odm->TH_EDCCA_HL_diff = 7;
2050         pDM_Odm->IGI_Base = 0x32;
2051         pDM_Odm->IGI_target = 0x1c;
2052         pDM_Odm->ForceEDCCA = 0;
2053         pDM_Odm->AdapEn_RSSI = 20;
2054
2055         //Reg524[11]=0 is easily to transmit packets during adaptivity test
2056
2057         //ODM_SetBBReg(pDM_Odm, 0x524, BIT11, 1);// stop counting if EDCCA is asserted
2058 }
2059
2060 // Add by Neil Chen to enable edcca to MP Platform
2061 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2062
2063 VOID
2064 odm_EnableEDCCA(
2065         IN              PDM_ODM_T               pDM_Odm
2066 )
2067 {
2068
2069         // This should be moved out of OUTSRC
2070         PADAPTER                pAdapter        = pDM_Odm->Adapter;
2071         // Enable EDCCA. The value is suggested by SD3 Wilson.
2072
2073         //
2074         // Revised for ASUS 11b/g performance issues, suggested by BB Neil, 2012.04.13.
2075         //
2076         if((pDM_Odm->SupportICType == ODM_RTL8723A)&&(IS_WIRELESS_MODE_G(pAdapter)))
2077         {
2078                 //PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold, 0x00);
2079                 ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold,0x00);
2080                 ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold+2,0xFD);
2081
2082         }
2083         else
2084         {
2085                 //PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold, 0x03);
2086                 ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold,0x03);
2087                 ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold+2,0x00);
2088         }
2089
2090         //PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold+2, 0x00);
2091 }
2092
2093 VOID
2094 odm_DisableEDCCA(
2095         IN              PDM_ODM_T               pDM_Odm
2096 )
2097 {
2098         // Disable EDCCA..
2099         ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold, 0x7f);
2100         ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold+2, 0x7f);
2101 }
2102
2103 //
2104 // Description: According to initial gain value to determine to enable or disable EDCCA.
2105 //
2106 // Suggested by SD3 Wilson. Added by tynli. 2011.11.25.
2107 //
2108 VOID
2109 odm_DynamicEDCCA(
2110         IN              PDM_ODM_T               pDM_Odm
2111 )
2112 {
2113         PADAPTER                pAdapter        = pDM_Odm->Adapter;
2114         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
2115         u1Byte  RegC50, RegC58;
2116         BOOLEAN         bFwCurrentInPSMode=FALSE;
2117
2118         pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode));
2119
2120         // Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.
2121         if(bFwCurrentInPSMode)
2122                 return;
2123
2124         RegC50 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0);
2125         RegC58 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0);
2126
2127
2128         if((RegC50 > 0x28 && RegC58 > 0x28) ||
2129                 ((pDM_Odm->SupportICType == ODM_RTL8723A && IS_WIRELESS_MODE_G(pAdapter) && RegC50>0x26)) ||
2130                 (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 > 0x28))
2131         {
2132                 if(!pHalData->bPreEdccaEnable)
2133                 {
2134                         odm_EnableEDCCA(pDM_Odm);
2135                         pHalData->bPreEdccaEnable = TRUE;
2136                 }
2137
2138         }
2139         else if((RegC50 < 0x25 && RegC58 < 0x25) || (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 < 0x25))
2140         {
2141                 if(pHalData->bPreEdccaEnable)
2142                 {
2143                         odm_DisableEDCCA(pDM_Odm);
2144                         pHalData->bPreEdccaEnable = FALSE;
2145                 }
2146         }
2147 }
2148
2149
2150 #endif    // end MP platform support
2151
2152 VOID
2153 odm_Adaptivity(
2154         IN              PDM_ODM_T               pDM_Odm,
2155         IN              u1Byte                  IGI
2156 )
2157 {
2158         s1Byte TH_L2H_dmc, TH_H2L_dmc;
2159         s1Byte Diff, IGI_target;
2160         BOOLEAN EDCCA_State = 0;
2161         BOOLEAN isInterference = 0;
2162         u4Byte  value32 = 0;
2163
2164 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2165         PADAPTER                pAdapter        = pDM_Odm->Adapter;
2166         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
2167         BOOLEAN         bFwCurrentInPSMode=FALSE;
2168         PMGNT_INFO                              pMgntInfo = &(pAdapter->MgntInfo);
2169
2170         pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode));
2171
2172         // Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.
2173         if(bFwCurrentInPSMode)
2174                 return;
2175 #endif
2176
2177         if(!(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY))
2178         {
2179                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("Go to odm_DynamicEDCCA() \n"));
2180                 // Add by Neil Chen to enable edcca to MP Platform
2181 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2182                 // Adjust EDCCA.
2183                 if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
2184                         odm_DynamicEDCCA(pDM_Odm);
2185 #endif
2186                 return;
2187         }
2188         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_Adaptivity() =====> \n"));
2189
2190         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("ForceEDCCA=%d, IGI_Base=0x%x, TH_L2H_ini = %d, TH_EDCCA_HL_diff = %d, AdapEn_RSSI = %d\n",
2191                 pDM_Odm->ForceEDCCA, pDM_Odm->IGI_Base, pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff, pDM_Odm->AdapEn_RSSI));
2192
2193         if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
2194                 ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 0); //ADC_mask enable
2195
2196         if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
2197                 ODM_SetBBReg(pDM_Odm, 0x908, bMaskDWord, 0x208);
2198                 value32 = ODM_GetBBReg(pDM_Odm, 0xdf4, bMaskDWord);
2199         }
2200
2201         if (value32 & BIT30)
2202                 isInterference = TRUE;
2203         else
2204                 isInterference = FALSE;
2205
2206         if(((!pDM_Odm->bLinked) && (!isInterference)) || (*pDM_Odm->pChannel >= 149)) // Band4 doesn't need adaptivity
2207         {
2208                 if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
2209                 {
2210                         ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte0, 0x7f);
2211                         ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte2, 0x7f);
2212                 }
2213                 else
2214                         ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, 0xFFFF, (0x7f<<8) | 0x7f);
2215                 return;
2216         }
2217
2218 #if (DM_ODM_SUPPORT_TYPE==ODM_WIN)
2219                 if(pMgntInfo->IOTPeer == HT_IOT_PEER_BROADCOM)
2220                         ODM_Write1Byte(pDM_Odm, REG_TRX_SIFS_OFDM, 0x0a);
2221                 else
2222                         ODM_Write1Byte(pDM_Odm, REG_TRX_SIFS_OFDM, 0x0e);
2223 #endif
2224         if(!pDM_Odm->ForceEDCCA)
2225         {
2226                 if(pDM_Odm->RSSI_Min > pDM_Odm->AdapEn_RSSI)
2227                         EDCCA_State = 1;
2228                 else if(pDM_Odm->RSSI_Min < (pDM_Odm->AdapEn_RSSI - 5))
2229                         EDCCA_State = 0;
2230         }
2231         else
2232                 EDCCA_State = 1;
2233         //if((pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) && (*pDM_Odm->pBandType == BAND_ON_5G))
2234                 //IGI_target = pDM_Odm->IGI_Base;
2235         //else
2236         {
2237
2238                 if(*pDM_Odm->pBandWidth == ODM_BW20M) //CHANNEL_WIDTH_20
2239                         IGI_target = pDM_Odm->IGI_Base;
2240                 else if(*pDM_Odm->pBandWidth == ODM_BW40M)
2241                         IGI_target = pDM_Odm->IGI_Base + 2;
2242                 else if(*pDM_Odm->pBandWidth == ODM_BW80M)
2243                         IGI_target = pDM_Odm->IGI_Base + 6;
2244                 else
2245                         IGI_target = pDM_Odm->IGI_Base;
2246         }
2247
2248         pDM_Odm->IGI_target = (u1Byte) IGI_target;
2249
2250         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("BandWidth=%s, IGI_target=0x%x, EDCCA_State=%d\n",
2251                 (*pDM_Odm->pBandWidth==ODM_BW80M)?"80M":((*pDM_Odm->pBandWidth==ODM_BW40M)?"40M":"20M"), IGI_target, EDCCA_State));
2252
2253         if(EDCCA_State == 1)
2254         {
2255                 Diff = IGI_target -(s1Byte)IGI;
2256                 TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;
2257                 if(TH_L2H_dmc > 10)     TH_L2H_dmc = 10;
2258                 TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
2259         }
2260         else
2261         {
2262                 TH_L2H_dmc = 0x7f;
2263                 TH_H2L_dmc = 0x7f;
2264         }
2265         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d\n",
2266                 IGI, TH_L2H_dmc, TH_H2L_dmc));
2267
2268         if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
2269         {
2270                 ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte0, (u1Byte)TH_L2H_dmc);
2271                 ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte2, (u1Byte)TH_H2L_dmc);
2272         }
2273         else
2274                 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, 0xFFFF, ((u1Byte)TH_H2L_dmc<<8) | (u1Byte)TH_L2H_dmc);
2275 }
2276
2277 VOID
2278 ODM_DynamicATCSwitch_init(
2279         IN              PDM_ODM_T               pDM_Odm
2280 )
2281 {
2282         PADAPTER                Adapter = pDM_Odm->Adapter;
2283         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2284
2285 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN )
2286
2287         pDM_Odm->CrystalCap = pHalData->CrystalCap;
2288         pDM_Odm->bATCStatus = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM1_CFOTracking, BIT11);
2289         pDM_Odm->CFOThreshold = CFO_Threshold_Xtal;
2290
2291 #endif
2292 }
2293
2294 VOID
2295 ODM_DynamicATCSwitch(
2296         IN              PDM_ODM_T               pDM_Odm
2297 )
2298 {
2299         PADAPTER                Adapter = pDM_Odm->Adapter;
2300         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2301         u1Byte                  CrystalCap,ATC_status_temp = 0;
2302         u4Byte                  packet_count;
2303         int                             CFO_kHz_A,CFO_kHz_B,CFO_ave = 0, Adjust_Xtal = 0;
2304         int                             CFO_ave_diff;
2305
2306 #if (MP_DRIVER == 1)
2307         if ( *(pDM_Odm->mp_mode) == 1)
2308                 pDM_Odm->bLinked = TRUE;
2309 #endif
2310
2311 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN )
2312
2313         if(!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_ATC))
2314                 return;
2315
2316         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("=========> ODM_DynamicATCSwitch()\n"));
2317
2318         //2 No link!
2319         //
2320         if(!pDM_Odm->bLinked)
2321         {
2322                 //3
2323                 //3 1.Enable ATC
2324                 if(pDM_Odm->bATCStatus == ATC_Status_Off)
2325                 {
2326                         if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
2327                                 ODM_SetBBReg(pDM_Odm, rOFDM1_CFOTracking, BIT11, ATC_Status_On);
2328
2329                         if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
2330                                 ODM_SetBBReg(pDM_Odm, rFc_area_Jaguar, BIT14, ATC_Status_On);
2331
2332                         pDM_Odm->bATCStatus = ATC_Status_On;
2333                 }
2334
2335                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): No link!!\n"));
2336                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): ATCStatus = %d\n", pDM_Odm->bATCStatus));
2337
2338                 //3 2.Disable CFO tracking for BT
2339                 if(!pDM_Odm->bBtDisabled)
2340                 {
2341                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): Disable CFO tracking for BT!!\n"));
2342                         return;
2343                 }
2344
2345                 //3 3.Reset Crystal Cap.
2346                 if(pDM_Odm->CrystalCap != pHalData->CrystalCap)
2347                 {
2348                         pDM_Odm->CrystalCap = pHalData->CrystalCap;
2349                         CrystalCap = pDM_Odm->CrystalCap & 0x3f;
2350                         odm_Write_CrystalCap(pDM_Odm,CrystalCap);
2351                 }
2352                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): CrystalCap = 0x%x\n", pDM_Odm->CrystalCap));
2353
2354         }
2355         else
2356         {
2357
2358         //2 Initialization
2359         //
2360                 //3 1. Calculate CFO for path-A & path-B
2361                 CFO_kHz_A =  (int)(pDM_Odm->CFO_tail[0] * 3125)  / 1280;
2362                 CFO_kHz_B =  (int)(pDM_Odm->CFO_tail[1] * 3125)  / 1280;
2363                 packet_count = pDM_Odm->packetCount;
2364
2365                 //3 2.No new packet
2366                 if(packet_count == pDM_Odm->packetCount_pre)
2367                 {
2368                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): packet counter doesn't change\n"));
2369                         return;
2370                 }
2371                 pDM_Odm->packetCount_pre = packet_count;
2372                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): packet counter = %d\n", pDM_Odm->packetCount));
2373
2374                 //3 3.Average CFO
2375                 if(pDM_Odm->RFType == ODM_1T1R)
2376                         CFO_ave = CFO_kHz_A;
2377                 else
2378                         CFO_ave = (int)(CFO_kHz_A + CFO_kHz_B) >> 1;
2379
2380                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): CFO_kHz_A = %dkHz, CFO_kHz_B = %dkHz, CFO_ave = %dkHz\n",
2381                                                 CFO_kHz_A, CFO_kHz_B, CFO_ave));
2382
2383                 //3 4.Avoid abnormal large CFO
2384                 CFO_ave_diff = (pDM_Odm->CFO_ave_pre >= CFO_ave)?(pDM_Odm->CFO_ave_pre - CFO_ave):(CFO_ave - pDM_Odm->CFO_ave_pre);
2385                 if(CFO_ave_diff > 20 && pDM_Odm->largeCFOHit == 0)
2386                 {
2387                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): first large CFO hit\n"));
2388                         pDM_Odm->largeCFOHit = 1;
2389                         return;
2390                 }
2391                 else
2392                         pDM_Odm->largeCFOHit = 0;
2393                 pDM_Odm->CFO_ave_pre = CFO_ave;
2394
2395         //2 CFO tracking by adjusting Xtal cap.
2396         //
2397                 if (pDM_Odm->bBtDisabled)
2398                 {
2399                         //3 1.Dynamic Xtal threshold
2400                         if(CFO_ave >= -pDM_Odm->CFOThreshold && CFO_ave <= pDM_Odm->CFOThreshold && pDM_Odm->bIsfreeze == 0)
2401                         {
2402                                 if (pDM_Odm->CFOThreshold == CFO_Threshold_Xtal)
2403                                 {
2404                                         pDM_Odm->CFOThreshold = CFO_Threshold_Xtal + 10;
2405                                         pDM_Odm->bIsfreeze = 1;
2406                                 }
2407                                 else
2408                                         pDM_Odm->CFOThreshold = CFO_Threshold_Xtal;
2409                         }
2410                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): Dynamic threshold = %d\n", pDM_Odm->CFOThreshold));
2411
2412                 //3      2.Calculate Xtal offset
2413                         if(CFO_ave > pDM_Odm->CFOThreshold && pDM_Odm->CrystalCap < 0x3f)
2414                                 Adjust_Xtal =  ((CFO_ave - CFO_Threshold_Xtal) >> 2) + 1;
2415                         else if(CFO_ave < (-pDM_Odm->CFOThreshold) && pDM_Odm->CrystalCap > 0)
2416                                 Adjust_Xtal =  ((CFO_ave + CFO_Threshold_Xtal) >> 2) - 1;
2417                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): Crystal cap = 0x%x, Crystal cap offset = %d\n", pDM_Odm->CrystalCap, Adjust_Xtal));
2418
2419                         //3 3.Adjudt Crystal Cap.
2420                         if(Adjust_Xtal != 0)
2421                         {
2422                                 pDM_Odm->bIsfreeze = 0;
2423                                 pDM_Odm->CrystalCap = pDM_Odm->CrystalCap + Adjust_Xtal;
2424
2425                                 if(pDM_Odm->CrystalCap > 0x3f)
2426                                         pDM_Odm->CrystalCap = 0x3f;
2427                                 else if (pDM_Odm->CrystalCap < 0)
2428                                         pDM_Odm->CrystalCap = 0;
2429
2430                                 CrystalCap = pDM_Odm->CrystalCap & 0x3f;
2431                                 odm_Write_CrystalCap(pDM_Odm,CrystalCap);
2432
2433                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): New crystal cap = 0x%x \n", pDM_Odm->CrystalCap));
2434                         }
2435                 }
2436                 else if(pDM_Odm->CrystalCap != pHalData->CrystalCap)
2437                 {
2438                         //3 Reset Xtal Cap when BT is enable
2439                         pDM_Odm->CrystalCap = pHalData->CrystalCap;
2440                         CrystalCap = pDM_Odm->CrystalCap & 0x3f;
2441                         odm_Write_CrystalCap(pDM_Odm,CrystalCap);
2442                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): Disable CFO tracking for BT!! (CrystalCap is reset)\n"));
2443                 }
2444                 else
2445                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): Disable CFO tracking for BT!! (CrystalCap is unchanged)\n"));
2446                 if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES){
2447                         //2 Dynamic ATC switch
2448                         //
2449                                 //3 1.Enable ATC when CFO is larger then 80kHz
2450                                 if(CFO_ave < CFO_Threshold_ATC && CFO_ave > -CFO_Threshold_ATC)
2451                                 {
2452                                         if(pDM_Odm->bATCStatus == ATC_Status_On)
2453                                         {
2454                                         ODM_SetBBReg(pDM_Odm, rOFDM1_CFOTracking, BIT11, ATC_Status_Off);
2455                                         pDM_Odm->bATCStatus = ATC_Status_Off;
2456                                         }
2457                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): Disable ATC!!\n"));
2458                                 }
2459                                 else
2460                                 {
2461                                         if(pDM_Odm->bATCStatus == ATC_Status_Off)
2462                                         {
2463                                                 ODM_SetBBReg(pDM_Odm, rOFDM1_CFOTracking, BIT11, ATC_Status_On);
2464                                                 pDM_Odm->bATCStatus = ATC_Status_On;
2465                                         }
2466                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): Enable ATC!!\n"));
2467                                 }
2468                 }
2469         }
2470 #endif
2471 }
2472
2473 VOID
2474 odm_Write_CrystalCap(
2475         IN              PDM_ODM_T               pDM_Odm,
2476         IN              u1Byte                  CrystalCap
2477 )
2478 {
2479         PADAPTER                Adapter = pDM_Odm->Adapter;
2480         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2481
2482         if(IS_HARDWARE_TYPE_8192D(Adapter))
2483         {
2484                 PHY_SetBBReg(Adapter, 0x24, 0xF0, CrystalCap & 0x0F);
2485                 PHY_SetBBReg(Adapter, 0x28, 0xF0000000, ((CrystalCap & 0xF0) >> 4));
2486         }
2487
2488         if(IS_HARDWARE_TYPE_8188E(Adapter))
2489         {
2490                 // write 0x24[16:11] = 0x24[22:17] = CrystalCap
2491                 PHY_SetBBReg(Adapter, REG_AFE_XTAL_CTRL, 0x7ff800, (CrystalCap | (CrystalCap << 6)));
2492         }
2493
2494         if(IS_HARDWARE_TYPE_8812(Adapter))
2495         {
2496                 // write 0x2C[30:25] = 0x2C[24:19] = CrystalCap
2497                 CrystalCap = CrystalCap & 0x3F;
2498                 PHY_SetBBReg(Adapter, REG_MAC_PHY_CTRL, 0x7FF80000, (CrystalCap | (CrystalCap << 6)));
2499         }
2500
2501         //only for B-cut
2502         if ((IS_HARDWARE_TYPE_8723A(Adapter) && pHalData->EEPROMVersion >= 0x01) ||
2503                 IS_HARDWARE_TYPE_8723B(Adapter) ||IS_HARDWARE_TYPE_8192E(Adapter) || IS_HARDWARE_TYPE_8821(Adapter))
2504         {
2505                 // 0x2C[23:18] = 0x2C[17:12] = CrystalCap
2506                 CrystalCap = CrystalCap & 0x3F;
2507                 PHY_SetBBReg(Adapter, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap | (CrystalCap << 6)));
2508         }
2509
2510         if(IS_HARDWARE_TYPE_8723AE(Adapter))
2511                 PHY_SetBBReg(Adapter, REG_LDOA15_CTRL, bMaskDWord, 0x01572505);
2512
2513 }
2514
2515
2516 VOID
2517 ODM_Write_DIG(
2518         IN      PDM_ODM_T               pDM_Odm,
2519         IN      u1Byte                  CurrentIGI
2520         )
2521 {
2522         pDIG_T  pDM_DigTable = &pDM_Odm->DM_DigTable;
2523
2524         if(pDM_Odm->StopDIG)
2525         {
2526                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("Stop Writing IGI\n"));
2527                 return;
2528         }
2529
2530         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_REG(IGI_A,pDM_Odm)=0x%x, ODM_BIT(IGI,pDM_Odm)=0x%x \n",
2531                 ODM_REG(IGI_A,pDM_Odm),ODM_BIT(IGI,pDM_Odm)));
2532
2533         if(pDM_DigTable->CurIGValue != CurrentIGI)//if(pDM_DigTable->PreIGValue != CurrentIGI)
2534         {
2535                 if(pDM_Odm->SupportPlatform & (ODM_CE|ODM_WIN))
2536                 {
2537                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
2538                         if(pDM_Odm->RFType != ODM_1T1R)
2539                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
2540                         }
2541                 else if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
2542                 {
2543                         switch(*(pDM_Odm->pOnePathCCA))
2544                         {
2545                         case ODM_CCA_2R:
2546                         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
2547                                         if(pDM_Odm->RFType != ODM_1T1R)
2548                                         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
2549                                 break;
2550                         case ODM_CCA_1R_A:
2551                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
2552                                         if(pDM_Odm->RFType != ODM_1T1R)
2553                                         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), getIGIForDiff(CurrentIGI));
2554                                 break;
2555                         case ODM_CCA_1R_B:
2556                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), getIGIForDiff(CurrentIGI));
2557                                         if(pDM_Odm->RFType != ODM_1T1R)
2558                                         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
2559                                         break;
2560                                 }
2561                 }
2562
2563                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x). \n",CurrentIGI));
2564                 //pDM_DigTable->PreIGValue = pDM_DigTable->CurIGValue;
2565                 pDM_DigTable->CurIGValue = CurrentIGI;
2566         }
2567         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_Write_DIG():CurrentIGI=0x%x \n",CurrentIGI));
2568
2569 }
2570
2571 VOID
2572 odm_DIGbyRSSI_LPS(
2573         IN              PDM_ODM_T               pDM_Odm
2574         )
2575 {
2576         //PADAPTER                                      pAdapter =pDM_Odm->Adapter;
2577         //pDIG_T                                                pDM_DigTable = &pDM_Odm->DM_DigTable;
2578         PFALSE_ALARM_STATISTICS         pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
2579
2580 #if 0           //and 2.3.5 coding rule
2581         struct mlme_priv        *pmlmepriv = &(pAdapter->mlmepriv);
2582         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
2583         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
2584 #endif
2585
2586         u1Byte  RSSI_Lower=DM_DIG_MIN_NIC;   //0x1E or 0x1C
2587         u1Byte  CurrentIGI=pDM_Odm->RSSI_Min;
2588
2589         CurrentIGI=CurrentIGI+RSSI_OFFSET_DIG;
2590
2591
2592         //ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG_LPS, ODM_DBG_LOUD, ("odm_DIG()==>\n"));
2593
2594         // Using FW PS mode to make IGI
2595
2596         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("---Neil---odm_DIG is in LPS mode\n"));
2597         //Adjust by  FA in LPS MODE
2598         if(pFalseAlmCnt->Cnt_all> DM_DIG_FA_TH2_LPS)
2599                 CurrentIGI = CurrentIGI+2;
2600         else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS)
2601                 CurrentIGI = CurrentIGI+1;
2602         else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_LPS)
2603                 CurrentIGI = CurrentIGI-1;
2604
2605
2606         //Lower bound checking
2607
2608         //RSSI Lower bound check
2609         if((pDM_Odm->RSSI_Min-10) > DM_DIG_MIN_NIC)
2610                 RSSI_Lower =(pDM_Odm->RSSI_Min-10);
2611         else
2612                 RSSI_Lower =DM_DIG_MIN_NIC;
2613
2614         //Upper and Lower Bound checking
2615          if(CurrentIGI > DM_DIG_MAX_NIC)
2616                 CurrentIGI=DM_DIG_MAX_NIC;
2617          else if(CurrentIGI < RSSI_Lower)
2618                 CurrentIGI =RSSI_Lower;
2619
2620         ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue);
2621
2622 }
2623
2624 VOID
2625 odm_DIGInit(
2626         IN              PDM_ODM_T               pDM_Odm
2627         )
2628 {
2629         pDIG_T  pDM_DigTable = &pDM_Odm->DM_DigTable;
2630
2631         //pDM_DigTable->Dig_Enable_Flag = TRUE;
2632         //pDM_DigTable->Dig_Ext_Port_Stage = DIG_EXT_PORT_STAGE_MAX;
2633         pDM_DigTable->CurIGValue = (u1Byte) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm));
2634         //pDM_DigTable->PreIGValue = 0x0;
2635         //pDM_DigTable->CurSTAConnectState = pDM_DigTable->PreSTAConnectState = DIG_STA_DISCONNECT;
2636         //pDM_DigTable->CurMultiSTAConnectState = DIG_MultiSTA_DISCONNECT;
2637         pDM_DigTable->RssiLowThresh     = DM_DIG_THRESH_LOW;
2638         pDM_DigTable->RssiHighThresh    = DM_DIG_THRESH_HIGH;
2639         pDM_DigTable->FALowThresh       = DM_FALSEALARM_THRESH_LOW;
2640         pDM_DigTable->FAHighThresh      = DM_FALSEALARM_THRESH_HIGH;
2641         if(pDM_Odm->BoardType & (ODM_BOARD_EXT_PA|ODM_BOARD_EXT_LNA))
2642         {
2643                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
2644                 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
2645         }
2646         else
2647         {
2648                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
2649                 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
2650         }
2651         pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT;
2652         pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX;
2653         pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN;
2654         pDM_DigTable->PreCCK_CCAThres = 0xFF;
2655         pDM_DigTable->CurCCK_CCAThres = 0x83;
2656         pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC;
2657         pDM_DigTable->LargeFAHit = 0;
2658         pDM_DigTable->Recover_cnt = 0;
2659         pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC;
2660         pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC;
2661         pDM_DigTable->bMediaConnect_0 = FALSE;
2662         pDM_DigTable->bMediaConnect_1 = FALSE;
2663
2664         //To Initialize pDM_Odm->bDMInitialGainEnable == FALSE to avoid DIG error
2665         pDM_Odm->bDMInitialGainEnable = TRUE;
2666
2667         //To Initi BT30 IGI
2668         pDM_DigTable->BT30_CurIGI=0x32;
2669
2670 }
2671
2672 VOID
2673 odm_DigForBtHsMode(
2674         IN              PDM_ODM_T               pDM_Odm
2675         )
2676 {
2677 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2678         pDIG_T                                  pDM_DigTable=&pDM_Odm->DM_DigTable;
2679         u1Byte                                  digForBtHs=0;
2680         u1Byte                                  digUpBound=0x5a;
2681
2682         if(pDM_Odm->bBtConnectProcess)
2683         {
2684                 if(pDM_Odm->SupportICType&(ODM_RTL8723A))
2685                         digForBtHs = 0x28;
2686                 else
2687                         digForBtHs = 0x22;
2688         }
2689         else
2690         {
2691                 //
2692                 // Decide DIG value by BT HS RSSI.
2693                 //
2694                 digForBtHs = pDM_Odm->btHsRssi+4;
2695
2696                 //DIG Bound
2697                 if(pDM_Odm->SupportICType&(ODM_RTL8723A))
2698                         digUpBound = 0x3e;
2699
2700                 if(digForBtHs > digUpBound)
2701                         digForBtHs = digUpBound;
2702                 if(digForBtHs < 0x1c)
2703                         digForBtHs = 0x1c;
2704
2705                 // update Current IGI
2706                 pDM_DigTable->BT30_CurIGI = digForBtHs;
2707         }
2708         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DigForBtHsMode() : set DigValue=0x%x\n", digForBtHs));
2709 #endif
2710 }
2711
2712 VOID
2713 odm_DIG(
2714         IN              PDM_ODM_T               pDM_Odm
2715         )
2716 {
2717         pDIG_T                                          pDM_DigTable = &pDM_Odm->DM_DigTable;
2718         PFALSE_ALARM_STATISTICS         pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
2719         pRXHP_T                                         pRX_HP_Table  = &pDM_Odm->DM_RXHP_Table;
2720         u1Byte                                          DIG_Dynamic_MIN;
2721         u1Byte                                          DIG_MaxOfMin;
2722         BOOLEAN                                         FirstConnect, FirstDisConnect;
2723         u1Byte                                          dm_dig_max, dm_dig_min, offset;
2724         u1Byte                                          CurrentIGI = pDM_DigTable->CurIGValue;
2725         u1Byte                                          Adap_IGI_Upper = pDM_Odm->IGI_target + 30 + (u1Byte) pDM_Odm->TH_L2H_ini -(u1Byte) pDM_Odm->TH_EDCCA_HL_diff;
2726
2727 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2728 // This should be moved out of OUTSRC
2729         PADAPTER                pAdapter        = pDM_Odm->Adapter;
2730 #if OS_WIN_FROM_WIN7(OS_VERSION)
2731         if(IsAPModeExist( pAdapter) && pAdapter->bInHctTest)
2732         {
2733                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: Is AP mode or In HCT Test \n"));
2734                 return;
2735         }
2736 #endif
2737 /*
2738         if (pDM_Odm->SupportICType==ODM_RTL8723B)
2739                 return;
2740 */
2741
2742         if(pDM_Odm->bBtHsOperation)
2743         {
2744                 odm_DigForBtHsMode(pDM_Odm);
2745         }
2746
2747         if(!(pDM_Odm->SupportICType &(ODM_RTL8723A|ODM_RTL8188E)))
2748         {
2749                 if(pRX_HP_Table->RXHP_flag == 1)
2750                 {
2751                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In RXHP Operation \n"));
2752                         return;
2753                 }
2754         }
2755 #endif
2756 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2757 #ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
2758         if((pDM_Odm->bLinked) && (pDM_Odm->Adapter->registrypriv.force_igi !=0))
2759         {
2760                 printk("pDM_Odm->RSSI_Min=%d \n",pDM_Odm->RSSI_Min);
2761                 ODM_Write_DIG(pDM_Odm,pDM_Odm->Adapter->registrypriv.force_igi);
2762                 return;
2763         }
2764 #endif
2765 #endif
2766 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
2767         prtl8192cd_priv priv                    = pDM_Odm->priv;
2768         if (!((priv->up_time > 5) && (priv->up_time % 2)) )
2769         {
2770                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: Not In DIG Operation Period \n"));
2771                 return;
2772         }
2773 #endif
2774
2775         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG()==>\n"));
2776         //if(!(pDM_Odm->SupportAbility & (ODM_BB_DIG|ODM_BB_FA_CNT)))
2777         if((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) ||(!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT)))
2778         {
2779 #if 0
2780                 if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
2781                 {
2782                         if ((pDM_Odm->SupportICType == ODM_RTL8192C) && (pDM_Odm->ExtLNA == 1))
2783                                 CurrentIGI = 0x30; //pDM_DigTable->CurIGValue  = 0x30;
2784                         else
2785                                 CurrentIGI = 0x20; //pDM_DigTable->CurIGValue  = 0x20;
2786                         ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue);
2787                 }
2788 #endif
2789                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n"));
2790                 return;
2791         }
2792
2793         if(*(pDM_Odm->pbScanInProcess))
2794         {
2795                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In Scan Progress \n"));
2796                 return;
2797         }
2798
2799         //add by Neil Chen to avoid PSD is processing
2800         if(pDM_Odm->SupportICType==ODM_RTL8723A)
2801         {
2802                 if(pDM_Odm->bDMInitialGainEnable == FALSE)
2803                 {
2804                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: PSD is Processing \n"));
2805                         return;
2806                 }
2807         }
2808
2809         if(pDM_Odm->SupportICType == ODM_RTL8192D)
2810         {
2811                 if(*(pDM_Odm->pMacPhyMode) == ODM_DMSP)
2812                 {
2813                         if(*(pDM_Odm->pbMasterOfDMSP))
2814                         {
2815                                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
2816                                 FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE);
2817                                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE);
2818                         }
2819                         else
2820                         {
2821                                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1;
2822                                 FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == FALSE);
2823                                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == TRUE);
2824                         }
2825                 }
2826                 else
2827                 {
2828                         if(*(pDM_Odm->pBandType) == ODM_BAND_5G)
2829                         {
2830                                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
2831                                 FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE);
2832                                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE);
2833                         }
2834                         else
2835                         {
2836                                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1;
2837                                 FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == FALSE);
2838                                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == TRUE);
2839                         }
2840                 }
2841         }
2842         else
2843         {
2844                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
2845                 FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE);
2846                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE);
2847         }
2848
2849         //1 Boundary Decision
2850         if(pDM_Odm->SupportICType & (ODM_RTL8192C) &&(pDM_Odm->BoardType & (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_PA)))
2851         {
2852                 if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
2853                 {
2854
2855                         dm_dig_max = DM_DIG_MAX_AP_HP;
2856                         dm_dig_min = DM_DIG_MIN_AP_HP;
2857                 }
2858                 else
2859                 {
2860                         dm_dig_max = DM_DIG_MAX_NIC_HP;
2861                         dm_dig_min = DM_DIG_MIN_NIC_HP;
2862                 }
2863                 DIG_MaxOfMin = DM_DIG_MAX_AP_HP;
2864         }
2865         else
2866         {
2867                 if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
2868                 {
2869 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
2870 #ifdef DFS
2871                         if (!priv->pmib->dot11DFSEntry.disable_DFS &&
2872                                 (OPMODE & WIFI_AP_STATE) &&
2873                                 (((pDM_Odm->ControlChannel >= 52) &&
2874                                 (pDM_Odm->ControlChannel <= 64)) ||
2875                                 ((pDM_Odm->ControlChannel >= 100) &&
2876                                 (pDM_Odm->ControlChannel <= 140))))
2877                                 dm_dig_max = 0x24;
2878                         else
2879 #endif
2880                         if (priv->pmib->dot11RFEntry.tx2path) {
2881                                 if (*(pDM_Odm->pWirelessMode) == ODM_WM_B)//(priv->pmib->dot11BssType.net_work_type == WIRELESS_11B)
2882                                         dm_dig_max = 0x2A;
2883                                 else
2884                                         dm_dig_max = 0x32;
2885                         }
2886                         else
2887 #endif
2888                         dm_dig_max = DM_DIG_MAX_AP;
2889                         dm_dig_min = DM_DIG_MIN_AP;
2890                         DIG_MaxOfMin = dm_dig_max;
2891                 }
2892                 else
2893                 {
2894                         if((pDM_Odm->SupportICType >= ODM_RTL8188E) && (pDM_Odm->SupportPlatform & (ODM_WIN|ODM_CE)))
2895                                 dm_dig_max = 0x5A;
2896                         else
2897                                 dm_dig_max = DM_DIG_MAX_NIC;
2898
2899                         if(pDM_Odm->SupportICType != ODM_RTL8821)
2900                                 dm_dig_min = DM_DIG_MIN_NIC;
2901                         else
2902                                 dm_dig_min = 0x1C;
2903
2904                         DIG_MaxOfMin = DM_DIG_MAX_AP;
2905                 }
2906         }
2907
2908         if(0 < *pDM_Odm->pu1ForcedIgiLb)
2909         {
2910                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): force IGI lb to: %u\n", *pDM_Odm->pu1ForcedIgiLb));
2911                 dm_dig_min = *pDM_Odm->pu1ForcedIgiLb;
2912                 dm_dig_max = (dm_dig_min <= dm_dig_max) ? (dm_dig_max) : (dm_dig_min + 1);
2913         }
2914
2915         if(pDM_Odm->bLinked)
2916         {
2917                 if(pDM_Odm->SupportICType&(ODM_RTL8723A/*|ODM_RTL8821*/))
2918                 {
2919                         //2 Upper Bound
2920                         if(( pDM_Odm->RSSI_Min + 10) > DM_DIG_MAX_NIC )
2921                                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
2922                         else if(( pDM_Odm->RSSI_Min + 10) < DM_DIG_MIN_NIC )
2923                                 pDM_DigTable->rx_gain_range_max = DM_DIG_MIN_NIC;
2924                         else
2925                                 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 10;
2926
2927                         //BT is Concurrent
2928
2929                         if(pDM_Odm->bBtLimitedDig)
2930                         {
2931                                 if(pDM_Odm->RSSI_Min>10)
2932                                 {
2933                                         if((pDM_Odm->RSSI_Min - 10) > DM_DIG_MAX_NIC)
2934                                                 DIG_Dynamic_MIN = DM_DIG_MAX_NIC;
2935                                         else if((pDM_Odm->RSSI_Min - 10) < DM_DIG_MIN_NIC)
2936                                                 DIG_Dynamic_MIN = DM_DIG_MIN_NIC;
2937                                         else
2938                                                 DIG_Dynamic_MIN = pDM_Odm->RSSI_Min - 10;
2939                                 }
2940                                 else
2941                                         DIG_Dynamic_MIN=DM_DIG_MIN_NIC;
2942                         }
2943                         else
2944                         {
2945                                 if((pDM_Odm->RSSI_Min + 20) > dm_dig_max )
2946                                         pDM_DigTable->rx_gain_range_max = dm_dig_max;
2947                                 else if((pDM_Odm->RSSI_Min + 20) < dm_dig_min )
2948                                         pDM_DigTable->rx_gain_range_max = dm_dig_min;
2949                                 else
2950                                         pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20;
2951
2952                         }
2953                 }
2954                 else
2955                 {
2956                         if((pDM_Odm->SupportICType & (ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8812|ODM_RTL8821)) && (pDM_Odm->bBtLimitedDig==1)){
2957                                 //2 Modify DIG upper bound for 92E, 8723B, 8821 & 8812 BT
2958                                 if((pDM_Odm->RSSI_Min + 10) > dm_dig_max )
2959                                         pDM_DigTable->rx_gain_range_max = dm_dig_max;
2960                                 else if((pDM_Odm->RSSI_Min + 10) < dm_dig_min )
2961                                         pDM_DigTable->rx_gain_range_max = dm_dig_min;
2962                                 else
2963                                         pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 10;
2964                         }
2965                         else{
2966
2967                         //2 Modify DIG upper bound
2968                         //2013.03.19 Luke: Modified upper bound for Netgear rental house test
2969                         if(pDM_Odm->SupportICType != ODM_RTL8821 && pDM_Odm->SupportICType != ODM_RTL8192E)
2970                                 offset = 20;
2971                         else
2972                                 offset = 10;
2973
2974                         if((pDM_Odm->RSSI_Min + offset) > dm_dig_max )
2975                                 pDM_DigTable->rx_gain_range_max = dm_dig_max;
2976                                 else if((pDM_Odm->RSSI_Min + offset) < dm_dig_min )
2977                                         pDM_DigTable->rx_gain_range_max = dm_dig_min;
2978                         else
2979                                 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + offset;
2980
2981                         }
2982
2983                         //2 Modify DIG lower bound
2984                 /*
2985                         if((pFalseAlmCnt->Cnt_all > 500)&&(DIG_Dynamic_MIN < 0x25))
2986                                 DIG_Dynamic_MIN++;
2987                         else if(((pFalseAlmCnt->Cnt_all < 500)||(pDM_Odm->RSSI_Min < 8))&&(DIG_Dynamic_MIN > dm_dig_min))
2988                                 DIG_Dynamic_MIN--;
2989                 */
2990                         if(pDM_Odm->bOneEntryOnly)
2991                         {
2992                                 if(pDM_Odm->SupportICType != ODM_RTL8723B)
2993                                         offset = 0;
2994                                 else
2995                                         offset = 12;
2996
2997                                 if(pDM_Odm->RSSI_Min - offset < dm_dig_min)
2998                                         DIG_Dynamic_MIN = dm_dig_min;
2999                                 else if (pDM_Odm->RSSI_Min - offset > DIG_MaxOfMin)
3000                                         DIG_Dynamic_MIN = DIG_MaxOfMin;
3001                                 else
3002                                         DIG_Dynamic_MIN = pDM_Odm->RSSI_Min - offset;
3003
3004                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : bOneEntryOnly=TRUE,  DIG_Dynamic_MIN=0x%x\n",DIG_Dynamic_MIN));
3005                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : pDM_Odm->RSSI_Min=%d",pDM_Odm->RSSI_Min));
3006                         }
3007                         //1 Lower Bound for 88E AntDiv
3008 #if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
3009                         else if( (pDM_Odm->SupportICType & ODM_ANTDIV_SUPPORT) &&(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) )
3010                         //else if((pDM_Odm->SupportICType == ODM_RTL8188E)&&(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))
3011                         {
3012                                 if((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)||(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) ||pDM_Odm->AntDivType == S0S1_SW_ANTDIV)
3013                                 {
3014                                         DIG_Dynamic_MIN = (u1Byte) pDM_DigTable->AntDiv_RSSI_max;
3015                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_DIG(): pDM_DigTable->AntDiv_RSSI_max=%d \n",pDM_DigTable->AntDiv_RSSI_max));
3016                                 }
3017                         }
3018 #endif
3019                         else
3020                         {
3021                                 DIG_Dynamic_MIN=dm_dig_min;
3022                         }
3023                 }
3024         }
3025         else
3026         {
3027                 pDM_DigTable->rx_gain_range_max = dm_dig_max;
3028                 DIG_Dynamic_MIN = dm_dig_min;
3029                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : No Link\n"));
3030         }
3031
3032         //1 Modify DIG lower bound, deal with abnorally large false alarm
3033         if(pFalseAlmCnt->Cnt_all > 10000)
3034         {
3035                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("dm_DIG(): Abnornally false alarm case. \n"));
3036
3037                 if(pDM_DigTable->LargeFAHit != 3)
3038                         pDM_DigTable->LargeFAHit++;
3039                 if(pDM_DigTable->ForbiddenIGI < CurrentIGI)//if(pDM_DigTable->ForbiddenIGI < pDM_DigTable->CurIGValue)
3040                 {
3041                         pDM_DigTable->ForbiddenIGI = (u1Byte)CurrentIGI;//pDM_DigTable->ForbiddenIGI = pDM_DigTable->CurIGValue;
3042                         pDM_DigTable->LargeFAHit = 1;
3043                 }
3044
3045                 if(pDM_DigTable->LargeFAHit >= 3)
3046                 {
3047                         if((pDM_DigTable->ForbiddenIGI+1) >pDM_DigTable->rx_gain_range_max)
3048                                 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max;
3049                         else
3050                                 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
3051                         pDM_DigTable->Recover_cnt = 3600; //3600=2hr
3052                 }
3053
3054         }
3055         else
3056         {
3057                 //Recovery mechanism for IGI lower bound
3058                 if(pDM_DigTable->Recover_cnt != 0)
3059                         pDM_DigTable->Recover_cnt --;
3060                 else
3061                 {
3062                         if(pDM_DigTable->LargeFAHit < 3)
3063                         {
3064                                 if((pDM_DigTable->ForbiddenIGI -1) < DIG_Dynamic_MIN) //DM_DIG_MIN)
3065                                 {
3066                                         pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; //DM_DIG_MIN;
3067                                         pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; //DM_DIG_MIN;
3068                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n"));
3069                                 }
3070                                 else
3071                                 {
3072                                         pDM_DigTable->ForbiddenIGI --;
3073                                         pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
3074                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Approach Lower Bound\n"));
3075                                 }
3076                         }
3077                         else
3078                         {
3079                                 pDM_DigTable->LargeFAHit = 0;
3080                         }
3081                 }
3082         }
3083         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): pDM_DigTable->LargeFAHit=%d\n",pDM_DigTable->LargeFAHit));
3084
3085         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3086         if(IS_STA_VALID(pDM_Odm->pODM_StaInfo[0])) //STA mode is linked to AP
3087                 pDM_Odm->bsta_state = _TRUE;
3088         #endif
3089
3090         if((pDM_Odm->SupportPlatform&(ODM_WIN|ODM_CE))&&(pDM_Odm->PhyDbgInfo.NumQryBeaconPkt < 2) && (pDM_Odm->bsta_state) )
3091         {
3092                         pDM_DigTable->rx_gain_range_min = dm_dig_min;
3093         }
3094
3095         if(pDM_DigTable->rx_gain_range_min > pDM_DigTable->rx_gain_range_max)
3096                 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max;
3097
3098         //1 Adjust initial gain by false alarm
3099         if(pDM_Odm->bLinked)
3100         {
3101                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG AfterLink\n"));
3102                 if(FirstConnect)
3103                 {
3104                         if(pDM_Odm->RSSI_Min <= DIG_MaxOfMin)
3105                                 CurrentIGI = pDM_Odm->RSSI_Min;
3106                         else
3107                                 CurrentIGI = DIG_MaxOfMin;
3108                         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n"));
3109
3110                         ODM_ConfigBBWithHeaderFile(pDM_Odm, CONFIG_BB_AGC_TAB_DIFF);
3111                 }
3112                 else
3113                 {
3114                         if(pDM_Odm->SupportICType == ODM_RTL8192D)
3115                         {
3116                                 if(pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_92D)
3117                                         CurrentIGI = CurrentIGI + 4;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2;
3118                                 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_92D)
3119                                         CurrentIGI = CurrentIGI + 2; //pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1;
3120                                 else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_92D)
3121                                         CurrentIGI = CurrentIGI - 2;//pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1;
3122                         }
3123                         else
3124                         {
3125                                 //FA for Combo IC--NeilChen--2012--09--28
3126                                 if(pDM_Odm->SupportICType == ODM_RTL8723A)
3127                                 {
3128                                         //WLAN and BT ConCurrent
3129                                         if(pDM_Odm->bBtLimitedDig)
3130                                         {
3131                                                 if(pFalseAlmCnt->Cnt_all > 0x300)
3132                                                         CurrentIGI = CurrentIGI + 4;
3133                                                 else if (pFalseAlmCnt->Cnt_all > 0x250)
3134                                                         CurrentIGI = CurrentIGI + 2;
3135                                                 else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0)
3136                                                         CurrentIGI = CurrentIGI -2;
3137                                         }
3138                                         else //Not Concurrent
3139                                         {
3140                                                 if(pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2)
3141                                                         CurrentIGI = CurrentIGI + 4;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2;
3142                                                 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1)
3143                                                         CurrentIGI = CurrentIGI + 2;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1;
3144                                                 else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0)
3145                                                         CurrentIGI = CurrentIGI - 2;//pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1;
3146                                         }
3147                                 }
3148                                 else
3149                                 {
3150                                         if(pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2)
3151                                                 CurrentIGI = CurrentIGI + 4;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2;
3152                                         else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1)
3153                                                 CurrentIGI = CurrentIGI + 2;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1;
3154                                         else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0)
3155                                                 CurrentIGI = CurrentIGI - 2;//pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1;
3156
3157                                         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3158                                         if(IS_STA_VALID(pDM_Odm->pODM_StaInfo[0])) //STA mode is linked to AP
3159                                                 pDM_Odm->bsta_state = _TRUE;
3160                                         #endif
3161
3162                                         if((pDM_Odm->SupportPlatform&(ODM_WIN|ODM_CE))&&(pDM_Odm->PhyDbgInfo.NumQryBeaconPkt < 2)
3163                                                 &&(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH1) && (pDM_Odm->bsta_state))
3164                                         {
3165                                                 CurrentIGI = pDM_DigTable->rx_gain_range_min;
3166                                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Beacon is less than 10 and FA is less than 768, IGI GOES TO 0x1E!!!!!!!!!!!!\n"));
3167                                         }
3168                                         /*{
3169                                                 u2Byte value16;
3170                                                 value16 = (u2Byte) ODM_GetBBReg(pDM_Odm, 0x664, bMaskLWord);
3171                                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): NumQryBeaconPkt = %d, OFDM_OK_Cnt = %d\n",
3172                                                         pDM_Odm->PhyDbgInfo.NumQryBeaconPkt, value16));
3173                                         }*/
3174                                 }
3175                         }
3176                 }
3177         }
3178         else
3179         {
3180                 //CurrentIGI = pDM_DigTable->rx_gain_range_min;//pDM_DigTable->CurIGValue = pDM_DigTable->rx_gain_range_min
3181                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG BeforeLink\n"));
3182                 if(FirstDisConnect)
3183                 {
3184                                 CurrentIGI = pDM_DigTable->rx_gain_range_min;
3185                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First DisConnect \n"));
3186                 }
3187                 else
3188                 {
3189                         //2012.03.30 LukeLee: enable DIG before link but with very high thresholds
3190                      if(pFalseAlmCnt->Cnt_all > 10000)
3191                                 CurrentIGI = CurrentIGI + 4;
3192                         else if (pFalseAlmCnt->Cnt_all > 8000)
3193                                 CurrentIGI = CurrentIGI + 2;
3194                         else if(pFalseAlmCnt->Cnt_all < 500)
3195                                 CurrentIGI = CurrentIGI - 2;
3196                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): England DIG \n"));
3197                 }
3198         }
3199         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG End Adjust IGI\n"));
3200         //1 Check initial gain by upper/lower bound
3201
3202         if(CurrentIGI > pDM_DigTable->rx_gain_range_max)
3203                 CurrentIGI = pDM_DigTable->rx_gain_range_max;
3204         if(CurrentIGI < pDM_DigTable->rx_gain_range_min)
3205                 CurrentIGI = pDM_DigTable->rx_gain_range_min;
3206
3207         if(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY)
3208         {
3209                 if(CurrentIGI > Adap_IGI_Upper)
3210                         CurrentIGI = Adap_IGI_Upper;
3211
3212                 if(pDM_Odm->IGI_LowerBound != 0)
3213                 {
3214                         if(CurrentIGI < pDM_Odm->IGI_LowerBound)
3215                                 CurrentIGI = pDM_Odm->IGI_LowerBound;
3216                 }
3217                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): pDM_Odm->IGI_LowerBound = %d\n", pDM_Odm->IGI_LowerBound));
3218         }
3219
3220         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): rx_gain_range_max=0x%x, rx_gain_range_min=0x%x\n",
3221                 pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min));
3222         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TotalFA=%d\n", pFalseAlmCnt->Cnt_all));
3223         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue=0x%x\n", CurrentIGI));
3224
3225         //2 High power RSSI threshold
3226 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
3227 {
3228         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pDM_Odm->Adapter);
3229         //PMGNT_INFO                    pMgntInfo       = &(pAdapter->MgntInfo);
3230         // for LC issue to dymanic modify DIG lower bound----------LC Mocca Issue
3231         u8Byte                  curTxOkCnt=0, curRxOkCnt=0;
3232         static u8Byte           lastTxOkCnt=0, lastRxOkCnt=0;
3233
3234         //u8Byte                        OKCntAll=0;
3235         //static u8Byte         TXByteCnt_A=0, TXByteCnt_B=0, RXByteCnt_A=0, RXByteCnt_B=0;
3236         //u8Byte                        CurByteCnt=0, PreByteCnt=0;
3237
3238         curTxOkCnt = pAdapter->TxStats.NumTxBytesUnicast - lastTxOkCnt;
3239         curRxOkCnt =pAdapter->RxStats.NumRxBytesUnicast - lastRxOkCnt;
3240         lastTxOkCnt = pAdapter->TxStats.NumTxBytesUnicast;
3241         lastRxOkCnt = pAdapter->RxStats.NumRxBytesUnicast;
3242         //----------------------------------------------------------end for LC Mocca issue
3243         if((pDM_Odm->SupportICType == ODM_RTL8723A)&& (pHalData->UndecoratedSmoothedPWDB > DM_DIG_HIGH_PWR_THRESHOLD))
3244         {
3245                 // High power IGI lower bound
3246                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): UndecoratedSmoothedPWDB(%#x)\n", pHalData->UndecoratedSmoothedPWDB));
3247                 if(CurrentIGI < DM_DIG_HIGH_PWR_IGI_LOWER_BOUND)
3248                 {
3249                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue(%#x)\n", pDM_DigTable->CurIGValue));
3250                         //pDM_DigTable->CurIGValue = DM_DIG_HIGH_PWR_IGI_LOWER_BOUND;
3251                         CurrentIGI=DM_DIG_HIGH_PWR_IGI_LOWER_BOUND;
3252                 }
3253         }
3254         if((pDM_Odm->SupportICType & ODM_RTL8723A) &&
3255                         IS_WIRELESS_MODE_G(pAdapter))
3256                 {
3257                         if(pHalData->UndecoratedSmoothedPWDB > 0x28)
3258                         {
3259                                 if(CurrentIGI < DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND)
3260                                 {
3261                                         //pDM_DigTable->CurIGValue = DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND;
3262                                         CurrentIGI = DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND;
3263                                 }
3264                         }
3265                 }
3266 #if 0
3267         if((pDM_Odm->SupportICType & ODM_RTL8723A)&&(pMgntInfo->CustomerID = RT_CID_LENOVO_CHINA))
3268         {
3269                 OKCntAll = (curTxOkCnt+curRxOkCnt);
3270                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue(%#x)\n", CurrentIGI));
3271                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): UndecoratedSmoothedPWDB(%#x)\n", pHalData->UndecoratedSmoothedPWDB));
3272                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): OKCntAll(%#x)\n", OKCntAll));
3273                 //8723AS_VAU
3274                 if(pDM_Odm->SupportInterface==ODM_ITRF_USB)
3275                 {
3276                         if(pHalData->UndecoratedSmoothedPWDB < 12)
3277                         {
3278                                 if(CurrentIGI > DM_DIG_MIN_NIC)
3279                                 {
3280                                         if(OKCntAll >= 1500000)                  // >=6Mbps
3281                                                 CurrentIGI=0x1B;
3282                                         else if(OKCntAll >= 1000000)     //4Mbps
3283                                                 CurrentIGI=0x1A;
3284                                         else if(OKCntAll >= 500000)              //2Mbps
3285                                                 CurrentIGI=0x19;
3286                                         else if(OKCntAll >= 250000)             //1Mbps
3287                                                 CurrentIGI=0x18;
3288                                         else
3289                                         {
3290                                                 CurrentIGI=0x17;                //SCAN mode
3291                                         }
3292                                 }
3293                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Modify---->CurIGValue(%#x)\n", CurrentIGI));
3294                         }
3295                 }
3296         }
3297 #endif
3298 }
3299 #endif
3300
3301 #if (RTL8192D_SUPPORT==1)
3302         if(pDM_Odm->SupportICType == ODM_RTL8192D)
3303         {
3304                 //sherry  delete DualMacSmartConncurrent 20110517
3305                 if(*(pDM_Odm->pMacPhyMode) == ODM_DMSP)
3306                 {
3307                         ODM_Write_DIG_DMSP(pDM_Odm, (u1Byte)CurrentIGI);//ODM_Write_DIG_DMSP(pDM_Odm, pDM_DigTable->CurIGValue);
3308                         if(*(pDM_Odm->pbMasterOfDMSP))
3309                         {
3310                                 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
3311                                 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
3312                         }
3313                         else
3314                         {
3315                                 pDM_DigTable->bMediaConnect_1 = pDM_Odm->bLinked;
3316                                 pDM_DigTable->DIG_Dynamic_MIN_1 = DIG_Dynamic_MIN;
3317                         }
3318                 }
3319                 else
3320                 {
3321                         ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue);
3322                         if(*(pDM_Odm->pBandType) == ODM_BAND_5G)
3323                         {
3324                                 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
3325                                 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
3326                         }
3327                         else
3328                         {
3329                                 pDM_DigTable->bMediaConnect_1 = pDM_Odm->bLinked;
3330                                 pDM_DigTable->DIG_Dynamic_MIN_1 = DIG_Dynamic_MIN;
3331                         }
3332                 }
3333         }
3334         else
3335 #endif
3336         {
3337                 if(pDM_Odm->bBtHsOperation)
3338                 {
3339                         if(pDM_Odm->bLinked)
3340                         {
3341                                 if(pDM_DigTable->BT30_CurIGI > (CurrentIGI))
3342                                 {
3343                                         ODM_Write_DIG(pDM_Odm, CurrentIGI);
3344
3345                                 }
3346                                 else
3347                                 {
3348                                         ODM_Write_DIG(pDM_Odm, pDM_DigTable->BT30_CurIGI);
3349                                 }
3350                                 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
3351                                 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
3352                         }
3353                         else
3354                         {
3355                                 if(pDM_Odm->bLinkInProcess)
3356                                 {
3357                                         ODM_Write_DIG(pDM_Odm, 0x1c);
3358                                 }
3359                                 else if(pDM_Odm->bBtConnectProcess)
3360                                 {
3361                                         ODM_Write_DIG(pDM_Odm, 0x28);
3362                                 }
3363                                 else
3364                                 {
3365                                         ODM_Write_DIG(pDM_Odm, pDM_DigTable->BT30_CurIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue);
3366                                 }
3367                         }
3368                 }
3369                 else            // BT is not using
3370                 {
3371                         ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue);
3372                         pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
3373                         pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
3374                 }
3375         }
3376 }
3377
3378
3379 BOOLEAN
3380 odm_DigAbort(
3381         IN              PDM_ODM_T               pDM_Odm
3382         )
3383 {
3384 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3385 // This should be moved out of OUTSRC
3386         PADAPTER                pAdapter        = pDM_Odm->Adapter;
3387         pRXHP_T                 pRX_HP_Table  = &pDM_Odm->DM_RXHP_Table;
3388
3389 #if OS_WIN_FROM_WIN7(OS_VERSION)
3390         if(IsAPModeExist( pAdapter) && pAdapter->bInHctTest)
3391         {
3392                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: Is AP mode or In HCT Test \n"));
3393                 return  TRUE;
3394         }
3395 #endif
3396
3397         if(pRX_HP_Table->RXHP_flag == 1)
3398         {
3399                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In RXHP Operation \n"));
3400                 return  TRUE;
3401         }
3402
3403         return  FALSE;
3404 #else   // For Other team any special case for DIG?
3405         return  FALSE;
3406 #endif
3407
3408
3409 }
3410
3411 //3============================================================
3412 //3 FASLE ALARM CHECK
3413 //3============================================================
3414
3415 VOID
3416 odm_FalseAlarmCounterStatistics(
3417         IN              PDM_ODM_T               pDM_Odm
3418         )
3419 {
3420         u4Byte ret_value;
3421         PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
3422
3423 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
3424         prtl8192cd_priv priv            = pDM_Odm->priv;
3425         if( (priv->auto_channel != 0) && (priv->auto_channel != 2) )
3426                 return;
3427 #endif
3428
3429 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3430         if((pDM_Odm->SupportICType == ODM_RTL8192D) &&
3431                 (*(pDM_Odm->pMacPhyMode)==ODM_DMSP)&&    ////modify by Guo.Mingzhi 2011-12-29
3432                 (!(*(pDM_Odm->pbMasterOfDMSP))))
3433         {
3434                 odm_FalseAlarmCounterStatistics_ForSlaveOfDMSP(pDM_Odm);
3435                 return;
3436         }
3437 #endif
3438
3439         if(!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))
3440                 return;
3441
3442         if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
3443         {
3444
3445         //hold ofdm counter
3446                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); //hold page C counter
3447                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); //hold page D counter
3448
3449                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord);
3450                 FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff);
3451                 FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16);
3452                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord);
3453                 FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff);
3454                 FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16);
3455                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord);
3456                 FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff);
3457                 FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16);
3458                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord);
3459                 FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff);
3460
3461                 FalseAlmCnt->Cnt_Ofdm_fail =    FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal +
3462                                                                         FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail +
3463                                                                         FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail;
3464
3465 #if (RTL8188E_SUPPORT==1)
3466                 if((pDM_Odm->SupportICType == ODM_RTL8188E)||(pDM_Odm->SupportICType == ODM_RTL8192E))
3467                 {
3468                                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_SC_CNT_11N, bMaskDWord);
3469                         FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff);
3470                         FalseAlmCnt->Cnt_BW_USC = ((ret_value&0xffff0000)>>16);
3471                 }
3472 #endif
3473
3474 #if (RTL8192D_SUPPORT==1)
3475                 if(pDM_Odm->SupportICType == ODM_RTL8192D)
3476                 {
3477                         odm_GetCCKFalseAlarm_92D(pDM_Odm);
3478                 }
3479                 else
3480 #endif
3481                 {
3482                         //hold cck counter
3483                                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT12, 1);
3484                                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT14, 1);
3485
3486                                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_LSB_11N, bMaskByte0);
3487                         FalseAlmCnt->Cnt_Cck_fail = ret_value;
3488                                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_MSB_11N, bMaskByte3);
3489                         FalseAlmCnt->Cnt_Cck_fail +=  (ret_value& 0xff)<<8;
3490
3491                                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord);
3492                         FalseAlmCnt->Cnt_CCK_CCA = ((ret_value&0xFF)<<8) |((ret_value&0xFF00)>>8);
3493                 }
3494
3495                 FalseAlmCnt->Cnt_all = (        FalseAlmCnt->Cnt_Fast_Fsync +
3496                                                         FalseAlmCnt->Cnt_SB_Search_fail +
3497                                                         FalseAlmCnt->Cnt_Parity_Fail +
3498                                                         FalseAlmCnt->Cnt_Rate_Illegal +
3499                                                         FalseAlmCnt->Cnt_Crc8_fail +
3500                                                         FalseAlmCnt->Cnt_Mcs_fail +
3501                                                         FalseAlmCnt->Cnt_Cck_fail);
3502
3503                 FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA;
3504
3505 #if (RTL8192C_SUPPORT==1)
3506                 if(pDM_Odm->SupportICType == ODM_RTL8192C)
3507                         odm_ResetFACounter_92C(pDM_Odm);
3508 #endif
3509
3510 #if (RTL8192D_SUPPORT==1)
3511                 if(pDM_Odm->SupportICType == ODM_RTL8192D)
3512                         odm_ResetFACounter_92D(pDM_Odm);
3513 #endif
3514
3515                 if(pDM_Odm->SupportICType >=ODM_RTL8723A)
3516                 {
3517                         //reset false alarm counter registers
3518                                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 1);
3519                                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 0);
3520                                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 1);
3521                                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 0);
3522                         //update ofdm counter
3523                                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 0); //update page C counter
3524                                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 0); //update page D counter
3525
3526                         //reset CCK CCA counter
3527                                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 0);
3528                                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 2);
3529                         //reset CCK FA counter
3530                                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 0);
3531                                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 2);
3532                 }
3533
3534                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Enter odm_FalseAlarmCounterStatistics\n"));
3535                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Fast_Fsync=%d, Cnt_SB_Search_fail=%d\n",
3536                         FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail));
3537                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Parity_Fail=%d, Cnt_Rate_Illegal=%d\n",
3538                         FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal));
3539                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n",
3540                         FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail));
3541         }
3542         else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
3543         {
3544                 u4Byte CCKenable;
3545                 //read OFDM FA counter
3546                 FalseAlmCnt->Cnt_Ofdm_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_11AC, bMaskLWord);
3547                 FalseAlmCnt->Cnt_Cck_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_11AC, bMaskLWord);
3548
3549                 CCKenable =  ODM_GetBBReg(pDM_Odm, ODM_REG_BB_RX_PATH_11AC, BIT28);
3550                 if(CCKenable)//if(*pDM_Odm->pBandType == ODM_BAND_2_4G)
3551                         FalseAlmCnt->Cnt_all = FalseAlmCnt->Cnt_Ofdm_fail + FalseAlmCnt->Cnt_Cck_fail;
3552                 else
3553                         FalseAlmCnt->Cnt_all = FalseAlmCnt->Cnt_Ofdm_fail;
3554
3555                 // reset OFDM FA coutner
3556                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 1);
3557                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 0);
3558                 // reset CCK FA counter
3559                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 0);
3560                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 1);
3561         }
3562         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail=%d\n",       FalseAlmCnt->Cnt_Cck_fail));
3563         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail=%d\n",      FalseAlmCnt->Cnt_Ofdm_fail));
3564         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm=%d\n",  FalseAlmCnt->Cnt_all));
3565 }
3566
3567 //3============================================================
3568 //3 CCK Packet Detect Threshold
3569 //3============================================================
3570
3571 VOID
3572 odm_CCKPacketDetectionThresh(
3573         IN              PDM_ODM_T               pDM_Odm
3574         )
3575 {
3576
3577         u1Byte  CurCCK_CCAThres;
3578         PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
3579
3580 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3581 //modify by Guo.Mingzhi 2011-12-29
3582         if (pDM_Odm->bDualMacSmartConcurrent == TRUE)
3583 //      if (pDM_Odm->bDualMacSmartConcurrent == FALSE)
3584                 return;
3585
3586         if(pDM_Odm->bBtHsOperation)
3587         {
3588                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_CCKPacketDetectionThresh() write 0xcd for BT HS mode!!\n"));
3589                 ODM_Write_CCK_CCA_Thres(pDM_Odm, 0xcd);
3590                 return;
3591         }
3592
3593 #endif
3594
3595         if(!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD|ODM_BB_FA_CNT)))
3596                 return;
3597
3598         if(pDM_Odm->ExtLNA)
3599                 return;
3600
3601         if(pDM_Odm->bLinked)
3602         {
3603                 if(pDM_Odm->RSSI_Min > 25)
3604                         CurCCK_CCAThres = 0xcd;
3605                 else if((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10))
3606                         CurCCK_CCAThres = 0x83;
3607                 else
3608                 {
3609                         if(FalseAlmCnt->Cnt_Cck_fail > 1000)
3610                                 CurCCK_CCAThres = 0x83;
3611                         else
3612                                 CurCCK_CCAThres = 0x40;
3613                 }
3614         }
3615         else
3616         {
3617                 if(FalseAlmCnt->Cnt_Cck_fail > 1000)
3618                         CurCCK_CCAThres = 0x83;
3619                 else
3620                         CurCCK_CCAThres = 0x40;
3621         }
3622
3623 #if (RTL8192D_SUPPORT==1)
3624         if((pDM_Odm->SupportICType == ODM_RTL8192D)&&(*pDM_Odm->pBandType == ODM_BAND_2_4G))
3625                 ODM_Write_CCK_CCA_Thres_92D(pDM_Odm, CurCCK_CCAThres);
3626         else
3627 #endif
3628                 ODM_Write_CCK_CCA_Thres(pDM_Odm, CurCCK_CCAThres);
3629 }
3630
3631 VOID
3632 ODM_Write_CCK_CCA_Thres(
3633         IN      PDM_ODM_T               pDM_Odm,
3634         IN      u1Byte                  CurCCK_CCAThres
3635         )
3636 {
3637         pDIG_T  pDM_DigTable = &pDM_Odm->DM_DigTable;
3638
3639         if(pDM_DigTable->CurCCK_CCAThres!=CurCCK_CCAThres)              //modify by Guo.Mingzhi 2012-01-03
3640         {
3641                 ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA,pDM_Odm), CurCCK_CCAThres);
3642         }
3643         pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres;
3644         pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres;
3645
3646 }
3647
3648 //3============================================================
3649 //3 BB Power Save
3650 //3============================================================
3651 VOID
3652 odm_DynamicBBPowerSavingInit(
3653         IN              PDM_ODM_T               pDM_Odm
3654         )
3655 {
3656         pPS_T   pDM_PSTable = &pDM_Odm->DM_PSTable;
3657
3658         pDM_PSTable->PreCCAState = CCA_MAX;
3659         pDM_PSTable->CurCCAState = CCA_MAX;
3660         pDM_PSTable->PreRFState = RF_MAX;
3661         pDM_PSTable->CurRFState = RF_MAX;
3662         pDM_PSTable->Rssi_val_min = 0;
3663         pDM_PSTable->initialize = 0;
3664 }
3665
3666
3667 VOID
3668 odm_DynamicBBPowerSaving(
3669         IN              PDM_ODM_T               pDM_Odm
3670         )
3671 {
3672 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
3673
3674         if (pDM_Odm->SupportICType != ODM_RTL8723A)
3675                 return;
3676         if(!(pDM_Odm->SupportAbility & ODM_BB_PWR_SAVE))
3677                 return;
3678         if(!(pDM_Odm->SupportPlatform & (ODM_WIN|ODM_CE)))
3679                 return;
3680
3681         //1 2.Power Saving for 92C
3682         if((pDM_Odm->SupportICType == ODM_RTL8192C) &&(pDM_Odm->RFType == ODM_2T2R))
3683         {
3684                 odm_1R_CCA(pDM_Odm);
3685         }
3686
3687         // 20100628 Joseph: Turn off BB power save for 88CE because it makesthroughput unstable.
3688         // 20100831 Joseph: Turn ON BB power save again after modifying AGC delay from 900ns ot 600ns.
3689         //1 3.Power Saving for 88C
3690         else
3691         {
3692                 ODM_RF_Saving(pDM_Odm, FALSE);
3693         }
3694 #endif  // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3695
3696 }
3697
3698 VOID
3699 odm_1R_CCA(
3700         IN      PDM_ODM_T       pDM_Odm
3701         )
3702 {
3703         pPS_T   pDM_PSTable = &pDM_Odm->DM_PSTable;
3704
3705         if(pDM_Odm->RSSI_Min!= 0xFF)
3706         {
3707
3708                 if(pDM_PSTable->PreCCAState == CCA_2R)
3709                 {
3710                         if(pDM_Odm->RSSI_Min >= 35)
3711                                 pDM_PSTable->CurCCAState = CCA_1R;
3712                         else
3713                                 pDM_PSTable->CurCCAState = CCA_2R;
3714
3715                 }
3716                 else{
3717                         if(pDM_Odm->RSSI_Min <= 30)
3718                                 pDM_PSTable->CurCCAState = CCA_2R;
3719                         else
3720                                 pDM_PSTable->CurCCAState = CCA_1R;
3721                 }
3722         }
3723         else{
3724                 pDM_PSTable->CurCCAState=CCA_MAX;
3725         }
3726
3727         if(pDM_PSTable->PreCCAState != pDM_PSTable->CurCCAState)
3728         {
3729                 if(pDM_PSTable->CurCCAState == CCA_1R)
3730                 {
3731                         if(  pDM_Odm->RFType ==ODM_2T2R )
3732                         {
3733                                 ODM_SetBBReg(pDM_Odm, 0xc04  , bMaskByte0, 0x13);
3734                                 //PHY_SetBBReg(pAdapter, 0xe70, bMaskByte3, 0x20);
3735                         }
3736                         else
3737                         {
3738                                 ODM_SetBBReg(pDM_Odm, 0xc04  , bMaskByte0, 0x23);
3739                                 //PHY_SetBBReg(pAdapter, 0xe70, 0x7fc00000, 0x10c); // Set RegE70[30:22] = 9b'100001100
3740                         }
3741                 }
3742                 else
3743                 {
3744                         ODM_SetBBReg(pDM_Odm, 0xc04  , bMaskByte0, 0x33);
3745                         //PHY_SetBBReg(pAdapter,0xe70, bMaskByte3, 0x63);
3746                 }
3747                 pDM_PSTable->PreCCAState = pDM_PSTable->CurCCAState;
3748         }
3749         //ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, ("CCAStage = %s\n",(pDM_PSTable->CurCCAState==0)?"1RCCA":"2RCCA"));
3750 }
3751
3752 void
3753 ODM_RF_Saving(
3754         IN      PDM_ODM_T       pDM_Odm,
3755         IN      u1Byte          bForceInNormal
3756         )
3757 {
3758 #if (DM_ODM_SUPPORT_TYPE != ODM_AP)
3759         pPS_T   pDM_PSTable = &pDM_Odm->DM_PSTable;
3760         u1Byte  Rssi_Up_bound = 30 ;
3761         u1Byte  Rssi_Low_bound = 25;
3762         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
3763         if(pDM_Odm->PatchID == 40 ) //RT_CID_819x_FUNAI_TV
3764         {
3765                 Rssi_Up_bound = 50 ;
3766                 Rssi_Low_bound = 45;
3767         }
3768         #endif
3769         if(pDM_PSTable->initialize == 0){
3770
3771                 pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14;
3772                 pDM_PSTable->RegC70 = (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord)&BIT3)>>3;
3773                 pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24;
3774                 pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12;
3775                 //Reg818 = PHY_QueryBBReg(pAdapter, 0x818, bMaskDWord);
3776                 pDM_PSTable->initialize = 1;
3777         }
3778
3779         if(!bForceInNormal)
3780         {
3781                 if(pDM_Odm->RSSI_Min != 0xFF)
3782                 {
3783                         if(pDM_PSTable->PreRFState == RF_Normal)
3784                         {
3785                                 if(pDM_Odm->RSSI_Min >= Rssi_Up_bound)
3786                                         pDM_PSTable->CurRFState = RF_Save;
3787                                 else
3788                                         pDM_PSTable->CurRFState = RF_Normal;
3789                         }
3790                         else{
3791                                 if(pDM_Odm->RSSI_Min <= Rssi_Low_bound)
3792                                         pDM_PSTable->CurRFState = RF_Normal;
3793                                 else
3794                                         pDM_PSTable->CurRFState = RF_Save;
3795                         }
3796                 }
3797                 else
3798                         pDM_PSTable->CurRFState=RF_MAX;
3799         }
3800         else
3801         {
3802                 pDM_PSTable->CurRFState = RF_Normal;
3803         }
3804
3805         if(pDM_PSTable->PreRFState != pDM_PSTable->CurRFState)
3806         {
3807                 if(pDM_PSTable->CurRFState == RF_Save)
3808                 {
3809                         // <tynli_note> 8723 RSSI report will be wrong. Set 0x874[5]=1 when enter BB power saving mode.
3810                         // Suggested by SD3 Yu-Nan. 2011.01.20.
3811                         if(pDM_Odm->SupportICType == ODM_RTL8723A)
3812                         {
3813                                 ODM_SetBBReg(pDM_Odm, 0x874  , BIT5, 0x1); //Reg874[5]=1b'1
3814                         }
3815                         ODM_SetBBReg(pDM_Odm, 0x874  , 0x1C0000, 0x2); //Reg874[20:18]=3'b010
3816                         ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, 0); //RegC70[3]=1'b0
3817                         ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); //Reg85C[31:24]=0x63
3818                         ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); //Reg874[15:14]=2'b10
3819                         ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); //RegA75[7:4]=0x3
3820                         ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); //Reg818[28]=1'b0
3821                         ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x1); //Reg818[28]=1'b1
3822                         //ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, (" RF_Save"));
3823                 }
3824                 else
3825                 {
3826                         ODM_SetBBReg(pDM_Odm, 0x874  , 0x1CC000, pDM_PSTable->Reg874);
3827                         ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, pDM_PSTable->RegC70);
3828                         ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);
3829                         ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->RegA74);
3830                         ODM_SetBBReg(pDM_Odm,0x818, BIT28, 0x0);
3831
3832                         if(pDM_Odm->SupportICType == ODM_RTL8723A)
3833                         {
3834                                 ODM_SetBBReg(pDM_Odm,0x874  , BIT5, 0x0); //Reg874[5]=1b'0
3835                         }
3836                         //ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, (" RF_Normal"));
3837                 }
3838                 pDM_PSTable->PreRFState =pDM_PSTable->CurRFState;
3839         }
3840 #endif
3841 }
3842
3843
3844 //3============================================================
3845 //3 RATR MASK
3846 //3============================================================
3847 //3============================================================
3848 //3 Rate Adaptive
3849 //3============================================================
3850
3851 VOID
3852 odm_RateAdaptiveMaskInit(
3853         IN      PDM_ODM_T       pDM_Odm
3854         )
3855 {
3856         PODM_RATE_ADAPTIVE      pOdmRA = &pDM_Odm->RateAdaptive;
3857
3858 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3859         PMGNT_INFO              pMgntInfo = &pDM_Odm->Adapter->MgntInfo;
3860         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pDM_Odm->Adapter);
3861
3862         pMgntInfo->Ratr_State = DM_RATR_STA_INIT;
3863
3864         if (pMgntInfo->DM_Type == DM_Type_ByDriver)
3865                 pHalData->bUseRAMask = TRUE;
3866         else
3867                 pHalData->bUseRAMask = FALSE;
3868
3869 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
3870         pOdmRA->Type = DM_Type_ByDriver;
3871         if (pOdmRA->Type == DM_Type_ByDriver)
3872                 pDM_Odm->bUseRAMask = _TRUE;
3873         else
3874                 pDM_Odm->bUseRAMask = _FALSE;
3875 #endif
3876
3877         pOdmRA->RATRState = DM_RATR_STA_INIT;
3878         pOdmRA->LdpcThres = 35;
3879         pOdmRA->bUseLdpc = FALSE;
3880         pOdmRA->HighRSSIThresh = 50;
3881         pOdmRA->LowRSSIThresh = 20;
3882 }
3883
3884 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
3885 VOID
3886 ODM_RateAdaptiveStateApInit(
3887         IN      PADAPTER                Adapter ,
3888         IN      PRT_WLAN_STA    pEntry
3889         )
3890 {
3891         pEntry->Ratr_State = DM_RATR_STA_INIT;
3892 }
3893 #endif
3894
3895 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
3896 u4Byte ODM_Get_Rate_Bitmap(
3897         IN      PDM_ODM_T       pDM_Odm,
3898         IN      u4Byte          macid,
3899         IN      u4Byte          ra_mask,
3900         IN      u1Byte          rssi_level)
3901 {
3902         PSTA_INFO_T     pEntry;
3903         u4Byte  rate_bitmap = 0;
3904         u1Byte  WirelessMode;
3905         //u1Byte        WirelessMode =*(pDM_Odm->pWirelessMode);
3906
3907
3908         pEntry = pDM_Odm->pODM_StaInfo[macid];
3909         if(!IS_STA_VALID(pEntry))
3910                 return ra_mask;
3911
3912         WirelessMode = pEntry->wireless_mode;
3913
3914         switch(WirelessMode)
3915         {
3916                 case ODM_WM_B:
3917                         if(ra_mask & 0x0000000c)                //11M or 5.5M enable
3918                                 rate_bitmap = 0x0000000d;
3919                         else
3920                                 rate_bitmap = 0x0000000f;
3921                         break;
3922
3923                 case (ODM_WM_G):
3924                 case (ODM_WM_A):
3925                         if(rssi_level == DM_RATR_STA_HIGH)
3926                                 rate_bitmap = 0x00000f00;
3927                         else
3928                                 rate_bitmap = 0x00000ff0;
3929                         break;
3930
3931                 case (ODM_WM_B|ODM_WM_G):
3932                         if(rssi_level == DM_RATR_STA_HIGH)
3933                                 rate_bitmap = 0x00000f00;
3934                         else if(rssi_level == DM_RATR_STA_MIDDLE)
3935                                 rate_bitmap = 0x00000ff0;
3936                         else
3937                                 rate_bitmap = 0x00000ff5;
3938                         break;
3939
3940                 case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G)    :
3941                 case (ODM_WM_B|ODM_WM_N24G)     :
3942                 case (ODM_WM_G|ODM_WM_N24G)     :
3943                 case (ODM_WM_A|ODM_WM_N5G)      :
3944                         {
3945                                 if (    pDM_Odm->RFType == ODM_1T2R ||pDM_Odm->RFType == ODM_1T1R)
3946                                 {
3947                                         if(rssi_level == DM_RATR_STA_HIGH)
3948                                         {
3949                                                 rate_bitmap = 0x000f0000;
3950                                         }
3951                                         else if(rssi_level == DM_RATR_STA_MIDDLE)
3952                                         {
3953                                                 rate_bitmap = 0x000ff000;
3954                                         }
3955                                         else{
3956                                                 if (*(pDM_Odm->pBandWidth) == ODM_BW40M)
3957                                                         rate_bitmap = 0x000ff015;
3958                                                 else
3959                                                         rate_bitmap = 0x000ff005;
3960                                         }
3961                                 }
3962                                 else
3963                                 {
3964                                         if(rssi_level == DM_RATR_STA_HIGH)
3965                                         {
3966                                                 rate_bitmap = 0x0f8f0000;
3967                                         }
3968                                         else if(rssi_level == DM_RATR_STA_MIDDLE)
3969                                         {
3970                                                 rate_bitmap = 0x0f8ff000;
3971                                         }
3972                                         else
3973                                         {
3974                                                 if (*(pDM_Odm->pBandWidth) == ODM_BW40M)
3975                                                         rate_bitmap = 0x0f8ff015;
3976                                                 else
3977                                                         rate_bitmap = 0x0f8ff005;
3978                                         }
3979                                 }
3980                         }
3981                         break;
3982
3983                 case (ODM_WM_AC|ODM_WM_G):
3984                         if(rssi_level == 1)
3985                                 rate_bitmap = 0xfc3f0000;
3986                         else if(rssi_level == 2)
3987                                 rate_bitmap = 0xfffff000;
3988                         else
3989                                 rate_bitmap = 0xffffffff;
3990                         break;
3991
3992                 case (ODM_WM_AC|ODM_WM_A):
3993
3994                         if (pDM_Odm->RFType == RF_1T1R)
3995                         {
3996                                 if(rssi_level == 1)                             // add by Gary for ac-series
3997                                         rate_bitmap = 0x003f8000;
3998                                 else if (rssi_level == 2)
3999                                         rate_bitmap = 0x003ff000;
4000                                 else
4001                                         rate_bitmap = 0x003ff010;
4002                         }
4003                         else
4004                         {
4005                                 if(rssi_level == 1)                             // add by Gary for ac-series
4006                                         rate_bitmap = 0xfe3f8000;       // VHT 2SS MCS3~9
4007                                 else if (rssi_level == 2)
4008                                         rate_bitmap = 0xfffff000;       // VHT 2SS MCS0~9
4009                                 else
4010                                         rate_bitmap = 0xfffff010;       // All
4011                         }
4012                         break;
4013
4014                 default:
4015                         if(pDM_Odm->RFType == RF_1T2R)
4016                                 rate_bitmap = 0x000fffff;
4017                         else
4018                                 rate_bitmap = 0x0fffffff;
4019                         break;
4020
4021         }
4022
4023         //printk("%s ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n",__FUNCTION__,rssi_level,WirelessMode,rate_bitmap);
4024         ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n",rssi_level,WirelessMode,rate_bitmap));
4025
4026         return (ra_mask&rate_bitmap);
4027
4028 }
4029 #endif
4030
4031
4032 VOID
4033 odm_RefreshBasicRateMask(
4034         IN              PDM_ODM_T               pDM_Odm
4035         )
4036 {
4037 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
4038         PADAPTER                Adapter  =  pDM_Odm->Adapter;
4039         static u1Byte           Stage = 0;
4040         u1Byte                  CurStage = 0;
4041         OCTET_STRING    osRateSet;
4042         PMGNT_INFO              pMgntInfo = GetDefaultMgntInfo(Adapter);
4043         u1Byte                  RateSet[5] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M, MGN_6M};
4044
4045         if(pDM_Odm->SupportICType != ODM_RTL8812 && pDM_Odm->SupportICType != ODM_RTL8821 )
4046                 return;
4047
4048         if(pDM_Odm->bLinked == FALSE)   // unlink Default port information
4049                 CurStage = 0;
4050         else if(pDM_Odm->RSSI_Min < 40) // link RSSI  < 40%
4051                 CurStage = 1;
4052         else if(pDM_Odm->RSSI_Min > 45) // link RSSI > 45%
4053                 CurStage = 3;
4054         else
4055                 CurStage = 2;                                   // link  25% <= RSSI <= 30%
4056
4057         if(CurStage != Stage)
4058         {
4059                 if(CurStage == 1)
4060                 {
4061                         FillOctetString(osRateSet, RateSet, 5);
4062                         FilterSupportRate(pMgntInfo->mBrates, &osRateSet, FALSE);
4063                         Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_BASIC_RATE, (pu1Byte)&osRateSet);
4064                 }
4065                 else if(CurStage == 3 && (Stage == 1 || Stage == 2))
4066                 {
4067                         Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_BASIC_RATE, (pu1Byte)(&pMgntInfo->mBrates) );
4068                 }
4069         }
4070
4071         Stage = CurStage;
4072 #endif
4073 }
4074
4075 /*-----------------------------------------------------------------------------
4076  * Function:    odm_RefreshRateAdaptiveMask()
4077  *
4078  * Overview:    Update rate table mask according to rssi
4079  *
4080  * Input:               NONE
4081  *
4082  * Output:              NONE
4083  *
4084  * Return:              NONE
4085  *
4086  * Revised History:
4087  *      When            Who             Remark
4088  *      05/27/2009      hpfan   Create Version 0.
4089  *
4090  *---------------------------------------------------------------------------*/
4091 VOID
4092 odm_RefreshRateAdaptiveMask(
4093         IN              PDM_ODM_T               pDM_Odm
4094         )
4095 {
4096
4097         ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("odm_RefreshRateAdaptiveMask()---------->\n"));
4098         if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK))
4099         {
4100                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("odm_RefreshRateAdaptiveMask(): Return cos not supported\n"));
4101                 return;
4102         }
4103         //
4104         // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
4105         // at the same time. In the stage2/3, we need to prive universal interface and merge all
4106         // HW dynamic mechanism.
4107         //
4108         switch  (pDM_Odm->SupportPlatform)
4109         {
4110                 case    ODM_WIN:
4111                         odm_RefreshRateAdaptiveMaskMP(pDM_Odm);
4112                         break;
4113
4114                 case    ODM_CE:
4115                         odm_RefreshRateAdaptiveMaskCE(pDM_Odm);
4116                         break;
4117
4118                 case    ODM_AP:
4119                 case    ODM_ADSL:
4120                         odm_RefreshRateAdaptiveMaskAPADSL(pDM_Odm);
4121                         break;
4122         }
4123
4124 }
4125
4126 VOID
4127 odm_RefreshRateAdaptiveMaskMP(
4128         IN              PDM_ODM_T               pDM_Odm
4129         )
4130 {
4131 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
4132         PADAPTER                                pAdapter         =  pDM_Odm->Adapter;
4133         PADAPTER                                pTargetAdapter = NULL;
4134         HAL_DATA_TYPE                   *pHalData = GET_HAL_DATA(pAdapter);
4135         PMGNT_INFO                              pMgntInfo = GetDefaultMgntInfo(pAdapter);
4136         PODM_RATE_ADAPTIVE              pRA = &pDM_Odm->RateAdaptive;
4137
4138         if(pAdapter->bDriverStopped)
4139         {
4140                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n"));
4141                 return;
4142         }
4143
4144         if(!pHalData->bUseRAMask)
4145         {
4146                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n"));
4147                 return;
4148         }
4149
4150         // if default port is connected, update RA table for default port (infrastructure mode only)
4151         if(pMgntInfo->mAssoc && (!ACTING_AS_AP(pAdapter)))
4152         {
4153
4154                 if(pHalData->UndecoratedSmoothedPWDB < pRA->LdpcThres)
4155                 {
4156                         pRA->bUseLdpc = TRUE;
4157                         pRA->bLowerRtsRate = TRUE;
4158                         if((pDM_Odm->SupportICType == ODM_RTL8821) && (pDM_Odm->CutVersion == ODM_CUT_A))
4159                                 MgntSet_TX_LDPC(pAdapter,0,TRUE);
4160                         //DbgPrint("RSSI=%d, bUseLdpc = TRUE\n", pHalData->UndecoratedSmoothedPWDB);
4161                 }
4162                 else if(pHalData->UndecoratedSmoothedPWDB > (pRA->LdpcThres-5))
4163                 {
4164                         pRA->bUseLdpc = FALSE;
4165                         pRA->bLowerRtsRate = FALSE;
4166                         if((pDM_Odm->SupportICType == ODM_RTL8821) && (pDM_Odm->CutVersion == ODM_CUT_A))
4167                                 MgntSet_TX_LDPC(pAdapter,0,FALSE);
4168                         //DbgPrint("RSSI=%d, bUseLdpc = FALSE\n", pHalData->UndecoratedSmoothedPWDB);
4169                 }
4170
4171                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_RefreshRateAdaptiveMask(): Infrasture Mode\n"));
4172                 if( ODM_RAStateCheck(pDM_Odm, pHalData->UndecoratedSmoothedPWDB, pMgntInfo->bSetTXPowerTrainingByOid, &pMgntInfo->Ratr_State) )
4173                 {
4174                         ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr : "), pMgntInfo->Bssid);
4175                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pHalData->UndecoratedSmoothedPWDB, pMgntInfo->Ratr_State));
4176                         pAdapter->HalFunc.UpdateHalRAMaskHandler(pAdapter, pMgntInfo->mMacId, NULL, pMgntInfo->Ratr_State);
4177                 }
4178         }
4179
4180         //
4181         // The following part configure AP/VWifi/IBSS rate adaptive mask.
4182         //
4183
4184         if(pMgntInfo->mIbss)    // Target: AP/IBSS peer.
4185                 pTargetAdapter = GetDefaultAdapter(pAdapter);
4186         else
4187                 pTargetAdapter = GetFirstAPAdapter(pAdapter);
4188
4189         // if extension port (softap) is started, updaet RA table for more than one clients associate
4190         if(pTargetAdapter != NULL)
4191         {
4192                 int     i;
4193                 PRT_WLAN_STA    pEntry;
4194
4195                 for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
4196                 {
4197                         pEntry = AsocEntry_EnumStation(pTargetAdapter, i);
4198                         if(NULL != pEntry)
4199                         {
4200                                 if(pEntry->bAssociated)
4201                                 {
4202                                         if(ODM_RAStateCheck(pDM_Odm, pEntry->rssi_stat.UndecoratedSmoothedPWDB, pMgntInfo->bSetTXPowerTrainingByOid, &pEntry->Ratr_State) )
4203                                         {
4204                                                 ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), pEntry->MacAddr);
4205                                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntry->Ratr_State));
4206                                                 pAdapter->HalFunc.UpdateHalRAMaskHandler(pTargetAdapter, pEntry->AssociatedMacId, pEntry, pEntry->Ratr_State);
4207                                         }
4208                                 }
4209                         }
4210                 }
4211         }
4212
4213         if(pMgntInfo->bSetTXPowerTrainingByOid)
4214                 pMgntInfo->bSetTXPowerTrainingByOid = FALSE;
4215 #endif  // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
4216 }
4217
4218
4219 VOID
4220 odm_RefreshRateAdaptiveMaskCE(
4221         IN              PDM_ODM_T               pDM_Odm
4222         )
4223 {
4224 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
4225         u1Byte  i;
4226         PADAPTER        pAdapter         =  pDM_Odm->Adapter;
4227         PODM_RATE_ADAPTIVE              pRA = &pDM_Odm->RateAdaptive;
4228
4229         if(pAdapter->bDriverStopped)
4230         {
4231                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n"));
4232                 return;
4233         }
4234
4235         if(!pDM_Odm->bUseRAMask)
4236         {
4237                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n"));
4238                 return;
4239         }
4240
4241         //printk("==> %s \n",__FUNCTION__);
4242
4243         for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++){
4244                 PSTA_INFO_T pstat = pDM_Odm->pODM_StaInfo[i];
4245                 if(IS_STA_VALID(pstat) ) {
4246                         if(IS_MCAST( pstat->hwaddr))  //if(psta->mac_id ==1)
4247                                  continue;
4248                         if(IS_MCAST( pstat->hwaddr))
4249                                 continue;
4250
4251                         #if((RTL8812A_SUPPORT==1)||(RTL8821A_SUPPORT==1))
4252                         if((pDM_Odm->SupportICType == ODM_RTL8812)||(pDM_Odm->SupportICType == ODM_RTL8821))
4253                         {
4254                                 if(pstat->rssi_stat.UndecoratedSmoothedPWDB < pRA->LdpcThres)
4255                                 {
4256                                         pRA->bUseLdpc = TRUE;
4257                                         pRA->bLowerRtsRate = TRUE;
4258                                         if((pDM_Odm->SupportICType == ODM_RTL8821) && (pDM_Odm->CutVersion == ODM_CUT_A))
4259                                                 Set_RA_LDPC_8812(pstat, TRUE);
4260                                         //DbgPrint("RSSI=%d, bUseLdpc = TRUE\n", pHalData->UndecoratedSmoothedPWDB);
4261                                 }
4262                                 else if(pstat->rssi_stat.UndecoratedSmoothedPWDB > (pRA->LdpcThres-5))
4263                                 {
4264                                         pRA->bUseLdpc = FALSE;
4265                                         pRA->bLowerRtsRate = FALSE;
4266                                         if((pDM_Odm->SupportICType == ODM_RTL8821) && (pDM_Odm->CutVersion == ODM_CUT_A))
4267                                                 Set_RA_LDPC_8812(pstat, FALSE);
4268                                         //DbgPrint("RSSI=%d, bUseLdpc = FALSE\n", pHalData->UndecoratedSmoothedPWDB);
4269                                 }
4270                         }
4271                         #endif
4272
4273                         if( TRUE == ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, FALSE , &pstat->rssi_level) )
4274                         {
4275                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level));
4276                                 //printk("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level);
4277                                 rtw_hal_update_ra_mask(pstat, pstat->rssi_level);
4278                         }
4279
4280                 }
4281         }
4282
4283 #endif
4284 }
4285
4286 VOID
4287 odm_RefreshRateAdaptiveMaskAPADSL(
4288         IN              PDM_ODM_T               pDM_Odm
4289         )
4290 {
4291 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
4292         struct rtl8192cd_priv *priv = pDM_Odm->priv;
4293         struct stat_info        *pstat;
4294
4295         if (!priv->pmib->dot11StationConfigEntry.autoRate)
4296                 return;
4297
4298         if (list_empty(&priv->asoc_list))
4299                 return;
4300
4301         list_for_each_entry(pstat, &priv->asoc_list, asoc_list) {
4302                 if(ODM_RAStateCheck(pDM_Odm, (s4Byte)pstat->rssi, FALSE, &pstat->rssi_level) ) {
4303                         ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), pstat->hwaddr);
4304                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi, pstat->rssi_level));
4305
4306 #ifdef CONFIG_RTL_88E_SUPPORT
4307                         if (GET_CHIP_VER(priv)==VERSION_8188E) {
4308 #ifdef TXREPORT
4309                                 add_RATid(priv, pstat);
4310 #endif
4311                         } else
4312 #endif
4313                         {
4314 #if defined(CONFIG_RTL_92D_SUPPORT) || defined(CONFIG_RTL_92C_SUPPORT)
4315                         add_update_RATid(priv, pstat);
4316 #endif
4317                         }
4318                 }
4319         }
4320 #endif
4321 }
4322
4323 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
4324 VOID
4325 ODM_DynamicARFBSelect(
4326         IN              PDM_ODM_T               pDM_Odm,
4327         IN              u1Byte                  rate,
4328         IN              BOOLEAN                 Collision_State
4329 )
4330 {
4331
4332         if(pDM_Odm->SupportICType != ODM_RTL8192E)
4333                 return;
4334
4335         if (rate >= DESC_RATEMCS8  && rate <= DESC_RATEMCS12){
4336                 if (Collision_State == 1){
4337                         if(rate == DESC_RATEMCS12){
4338
4339                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0);
4340                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x07060501);
4341                         }
4342                         else if(rate == DESC_RATEMCS11){
4343
4344                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0);
4345                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x07070605);
4346                         }
4347                         else if(rate == DESC_RATEMCS10){
4348
4349                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0);
4350                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x08080706);
4351                         }
4352                         else if(rate == DESC_RATEMCS9){
4353
4354                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0);
4355                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x08080707);
4356                         }
4357                         else{
4358
4359                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0);
4360                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x09090808);
4361                         }
4362                 }
4363                 else{   // Collision_State == 0
4364                         if(rate == DESC_RATEMCS12){
4365
4366                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x05010000);
4367                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x09080706);
4368                         }
4369                         else if(rate == DESC_RATEMCS11){
4370
4371                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x06050000);
4372                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x09080807);
4373                         }
4374                         else if(rate == DESC_RATEMCS10){
4375
4376                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x07060000);
4377                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x0a090908);
4378                         }
4379                         else if(rate == DESC_RATEMCS9){
4380
4381                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x07070000);
4382                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x0a090808);
4383                         }
4384                         else{
4385
4386                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x08080000);
4387                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x0b0a0909);
4388                         }
4389                 }
4390         }
4391         else{  // MCS13~MCS15,  1SS, G-mode
4392                 if (Collision_State == 1){
4393                         if(rate == DESC_RATEMCS15){
4394
4395                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x00000000);
4396                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x05040302);
4397                         }
4398                         else if(rate == DESC_RATEMCS14){
4399
4400                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x00000000);
4401                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x06050302);
4402                         }
4403                         else if(rate == DESC_RATEMCS13){
4404
4405                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x00000000);
4406                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x07060502);
4407                         }
4408                         else{
4409
4410                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x00000000);
4411                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x06050402);
4412                         }
4413                 }
4414                 else{   // Collision_State == 0
4415                         if(rate == DESC_RATEMCS15){
4416
4417                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x03020000);
4418                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x07060504);
4419                         }
4420                         else if(rate == DESC_RATEMCS14){
4421
4422                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x03020000);
4423                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x08070605);
4424                         }
4425                         else if(rate == DESC_RATEMCS13){
4426
4427                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x05020000);
4428                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x09080706);
4429                         }
4430                         else{
4431
4432                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x04020000);
4433                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x08070605);
4434                         }
4435
4436
4437                 }
4438
4439         }
4440
4441 }
4442
4443 #endif
4444
4445 // Return Value: BOOLEAN
4446 // - TRUE: RATRState is changed.
4447 BOOLEAN
4448 ODM_RAStateCheck(
4449         IN              PDM_ODM_T               pDM_Odm,
4450         IN              s4Byte                  RSSI,
4451         IN              BOOLEAN                 bForceUpdate,
4452         OUT             pu1Byte                 pRATRState
4453         )
4454 {
4455         PODM_RATE_ADAPTIVE pRA = &pDM_Odm->RateAdaptive;
4456         const u1Byte GoUpGap = 5;
4457         u1Byte HighRSSIThreshForRA = pRA->HighRSSIThresh;
4458         u1Byte LowRSSIThreshForRA = pRA->LowRSSIThresh;
4459         u1Byte RATRState;
4460
4461         // Threshold Adjustment:
4462         // when RSSI state trends to go up one or two levels, make sure RSSI is high enough.
4463         // Here GoUpGap is added to solve the boundary's level alternation issue.
4464         switch (*pRATRState)
4465         {
4466                 case DM_RATR_STA_INIT:
4467                 case DM_RATR_STA_HIGH:
4468                         break;
4469
4470                 case DM_RATR_STA_MIDDLE:
4471                         HighRSSIThreshForRA += GoUpGap;
4472                         break;
4473
4474                 case DM_RATR_STA_LOW:
4475                         HighRSSIThreshForRA += GoUpGap;
4476                         LowRSSIThreshForRA += GoUpGap;
4477                         break;
4478
4479                 default:
4480                         ODM_RT_ASSERT(pDM_Odm, FALSE, ("wrong rssi level setting %d !", *pRATRState) );
4481                         break;
4482         }
4483
4484         // Decide RATRState by RSSI.
4485         if(RSSI > HighRSSIThreshForRA)
4486                 RATRState = DM_RATR_STA_HIGH;
4487         else if(RSSI > LowRSSIThreshForRA)
4488                 RATRState = DM_RATR_STA_MIDDLE;
4489         else
4490                 RATRState = DM_RATR_STA_LOW;
4491         //printk("==>%s,RATRState:0x%02x ,RSSI:%d \n",__FUNCTION__,RATRState,RSSI);
4492
4493         if( *pRATRState!=RATRState || bForceUpdate)
4494         {
4495                 ODM_RT_TRACE( pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI Level %d -> %d\n", *pRATRState, RATRState) );
4496                 *pRATRState = RATRState;
4497                 return TRUE;
4498         }
4499
4500         return FALSE;
4501 }
4502
4503
4504 //============================================================
4505
4506 //3============================================================
4507 //3 Dynamic Tx Power
4508 //3============================================================
4509
4510 VOID
4511 odm_DynamicTxPowerInit(
4512         IN              PDM_ODM_T               pDM_Odm
4513         )
4514 {
4515 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
4516         PADAPTER        Adapter = pDM_Odm->Adapter;
4517         PMGNT_INFO                      pMgntInfo = &Adapter->MgntInfo;
4518         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
4519
4520         #if DEV_BUS_TYPE==RT_USB_INTERFACE
4521         if(RT_GetInterfaceSelection(Adapter) == INTF_SEL1_USB_High_Power)
4522         {
4523                 odm_DynamicTxPowerSavePowerIndex(pDM_Odm);
4524                 pMgntInfo->bDynamicTxPowerEnable = TRUE;
4525         }
4526         else
4527         #else
4528         //so 92c pci do not need dynamic tx power? vivi check it later
4529         if(IS_HARDWARE_TYPE_8192D(Adapter))
4530                 pMgntInfo->bDynamicTxPowerEnable = TRUE;
4531         else
4532                 pMgntInfo->bDynamicTxPowerEnable = FALSE;
4533         #endif
4534
4535
4536         pHalData->LastDTPLvl = TxHighPwrLevel_Normal;
4537         pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
4538 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
4539         PADAPTER        Adapter = pDM_Odm->Adapter;
4540         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
4541         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
4542         pdmpriv->bDynamicTxPowerEnable = _FALSE;
4543
4544         #if (RTL8192C_SUPPORT==1)
4545         #ifdef CONFIG_USB_HCI
4546
4547         #ifdef CONFIG_INTEL_PROXIM
4548         if((pHalData->BoardType == BOARD_USB_High_PA)||(Adapter->proximity.proxim_support==_TRUE))
4549         #else
4550         if(pHalData->BoardType == BOARD_USB_High_PA)
4551         #endif
4552
4553         {
4554                 //odm_SavePowerIndex(Adapter);
4555                 odm_DynamicTxPowerSavePowerIndex(pDM_Odm);
4556                 pdmpriv->bDynamicTxPowerEnable = _TRUE;
4557         }
4558         else
4559         #else
4560                 pdmpriv->bDynamicTxPowerEnable = _FALSE;
4561         #endif
4562         #endif
4563
4564         pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal;
4565         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
4566
4567 #endif
4568
4569 }
4570
4571 VOID
4572 odm_DynamicTxPowerSavePowerIndex(
4573         IN              PDM_ODM_T               pDM_Odm
4574         )
4575 {
4576         u1Byte          index;
4577         u4Byte          Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
4578
4579 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
4580         PADAPTER        Adapter = pDM_Odm->Adapter;
4581         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
4582         for(index = 0; index< 6; index++)
4583                 pHalData->PowerIndex_backup[index] = PlatformEFIORead1Byte(Adapter, Power_Index_REG[index]);
4584 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
4585         PADAPTER        Adapter = pDM_Odm->Adapter;
4586         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
4587         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
4588         for(index = 0; index< 6; index++)
4589                 pdmpriv->PowerIndex_backup[index] = rtw_read8(Adapter, Power_Index_REG[index]);
4590 #endif
4591 }
4592
4593 VOID
4594 odm_DynamicTxPowerRestorePowerIndex(
4595         IN              PDM_ODM_T               pDM_Odm
4596         )
4597 {
4598         u1Byte                  index;
4599         PADAPTER                Adapter = pDM_Odm->Adapter;
4600
4601 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
4602         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
4603         u4Byte                  Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
4604 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
4605         for(index = 0; index< 6; index++)
4606                 PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], pHalData->PowerIndex_backup[index]);
4607 #elif(DM_ODM_SUPPORT_TYPE == ODM_CE)
4608         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
4609         for(index = 0; index< 6; index++)
4610                 rtw_write8(Adapter, Power_Index_REG[index], pdmpriv->PowerIndex_backup[index]);
4611 #endif
4612 #endif
4613 }
4614
4615 VOID
4616 odm_DynamicTxPowerWritePowerIndex(
4617         IN      PDM_ODM_T       pDM_Odm,
4618         IN      u1Byte          Value)
4619 {
4620
4621         u1Byte                  index;
4622         u4Byte                  Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
4623
4624         for(index = 0; index< 6; index++)
4625                 //PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], Value);
4626                 ODM_Write1Byte(pDM_Odm, Power_Index_REG[index], Value);
4627
4628 }
4629
4630
4631 VOID
4632 odm_DynamicTxPower(
4633         IN              PDM_ODM_T               pDM_Odm
4634         )
4635 {
4636         //
4637         // For AP/ADSL use prtl8192cd_priv
4638         // For CE/NIC use PADAPTER
4639         //
4640         //PADAPTER              pAdapter = pDM_Odm->Adapter;
4641 //      prtl8192cd_priv priv            = pDM_Odm->priv;
4642
4643         if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR))
4644                 return;
4645
4646         //
4647         // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
4648         // at the same time. In the stage2/3, we need to prive universal interface and merge all
4649         // HW dynamic mechanism.
4650         //
4651         switch  (pDM_Odm->SupportPlatform)
4652         {
4653                 case    ODM_WIN:
4654                 case    ODM_CE:
4655                         odm_DynamicTxPowerNIC(pDM_Odm);
4656                         break;
4657                 case    ODM_AP:
4658                         odm_DynamicTxPowerAP(pDM_Odm);
4659                         break;
4660
4661                 case    ODM_ADSL:
4662                         //odm_DIGAP(pDM_Odm);
4663                         break;
4664         }
4665
4666
4667 }
4668
4669
4670 VOID
4671 odm_DynamicTxPowerNIC(
4672         IN              PDM_ODM_T               pDM_Odm
4673         )
4674 {
4675         if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR))
4676                 return;
4677
4678 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
4679
4680         if(pDM_Odm->SupportICType == ODM_RTL8192C)
4681         {
4682                 odm_DynamicTxPower_92C(pDM_Odm);
4683         }
4684         else if(pDM_Odm->SupportICType == ODM_RTL8192D)
4685         {
4686                 odm_DynamicTxPower_92D(pDM_Odm);
4687         }
4688         else if (pDM_Odm->SupportICType == ODM_RTL8821)
4689         {
4690 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
4691                 PADAPTER                Adapter  =  pDM_Odm->Adapter;
4692                 PMGNT_INFO              pMgntInfo = GetDefaultMgntInfo(Adapter);
4693
4694                 if (pMgntInfo->RegRspPwr == 1)
4695                 {
4696                         if(pDM_Odm->RSSI_Min > 60)
4697                         {
4698                                 ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11AC, BIT20|BIT19|BIT18, 1); // Resp TXAGC offset = -3dB
4699
4700                         }
4701                         else if(pDM_Odm->RSSI_Min < 55)
4702                         {
4703                                 ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11AC, BIT20|BIT19|BIT18, 0); // Resp TXAGC offset = 0dB
4704                         }
4705                 }
4706 #endif
4707         }
4708 #endif
4709 }
4710
4711 VOID
4712 odm_DynamicTxPowerAP(
4713         IN              PDM_ODM_T               pDM_Odm
4714
4715         )
4716 {
4717 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
4718         prtl8192cd_priv priv            = pDM_Odm->priv;
4719         s4Byte i;
4720
4721         if(!priv->pshare->rf_ft_var.tx_pwr_ctrl)
4722                 return;
4723
4724 #ifdef HIGH_POWER_EXT_PA
4725         if(pDM_Odm->ExtPA)
4726                 tx_power_control(priv);
4727 #endif
4728
4729         /*
4730          *      Check if station is near by to use lower tx power
4731          */
4732
4733         if ((priv->up_time % 3) == 0 )  {
4734                 for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++){
4735                         PSTA_INFO_T pstat = pDM_Odm->pODM_StaInfo[i];
4736                         if(IS_STA_VALID(pstat) ) {
4737                                 if ((pstat->hp_level == 0) && (pstat->rssi > TX_POWER_NEAR_FIELD_THRESH_AP+4))
4738                                         pstat->hp_level = 1;
4739                                 else if ((pstat->hp_level == 1) && (pstat->rssi < TX_POWER_NEAR_FIELD_THRESH_AP))
4740                                         pstat->hp_level = 0;
4741                         }
4742                 }
4743         }
4744
4745 #endif
4746 }
4747
4748
4749 VOID
4750 odm_DynamicTxPower_92C(
4751         IN      PDM_ODM_T       pDM_Odm
4752         )
4753 {
4754 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
4755         PADAPTER Adapter = pDM_Odm->Adapter;
4756         PMGNT_INFO                      pMgntInfo = &Adapter->MgntInfo;
4757         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
4758         s4Byte                          UndecoratedSmoothedPWDB;
4759
4760         // 2012/01/12 MH According to Luke's suggestion, only high power will support the feature.
4761         if (pDM_Odm->ExtPA == FALSE)
4762                 return;
4763
4764         // STA not connected and AP not connected
4765         if((!pMgntInfo->bMediaConnect) &&
4766                 (pHalData->EntryMinUndecoratedSmoothedPWDB == 0))
4767         {
4768                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("Not connected to any \n"));
4769                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
4770
4771                 //the LastDTPlvl should reset when disconnect,
4772                 //otherwise the tx power level wouldn't change when disconnect and connect again.
4773                 // Maddest 20091220.
4774                  pHalData->LastDTPLvl=TxHighPwrLevel_Normal;
4775                 return;
4776         }
4777
4778 #if (INTEL_PROXIMITY_SUPPORT == 1)
4779         // Intel set fixed tx power
4780         if(pMgntInfo->IntelProximityModeInfo.PowerOutput > 0)
4781         {
4782                 switch(pMgntInfo->IntelProximityModeInfo.PowerOutput){
4783                         case 1:
4784                                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_100;
4785                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_100\n"));
4786                                 break;
4787                         case 2:
4788                                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_70;
4789                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_70\n"));
4790                                 break;
4791                         case 3:
4792                                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_50;
4793                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_50\n"));
4794                                 break;
4795                         case 4:
4796                                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_35;
4797                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_35\n"));
4798                                 break;
4799                         case 5:
4800                                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_15;
4801                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_15\n"));
4802                                 break;
4803                         default:
4804                                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_100;
4805                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_100\n"));
4806                                 break;
4807                 }
4808         }
4809         else
4810 #endif
4811         {
4812                 if(     (pMgntInfo->bDynamicTxPowerEnable != TRUE) ||
4813                         (pHalData->DMFlag & HAL_DM_HIPWR_DISABLE) ||
4814                         pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)
4815                 {
4816                         pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
4817                 }
4818                 else
4819                 {
4820                         if(pMgntInfo->bMediaConnect)    // Default port
4821                         {
4822                                 if(ACTING_AS_AP(Adapter) || ACTING_AS_IBSS(Adapter))
4823                                 {
4824                                         UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB;
4825                                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
4826                                 }
4827                                 else
4828                                 {
4829                                         UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB;
4830                                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
4831                                 }
4832                         }
4833                         else // associated entry pwdb
4834                         {
4835                                 UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB;
4836                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
4837                         }
4838
4839                         if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2)
4840                         {
4841                                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
4842                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n"));
4843                         }
4844                         else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) &&
4845                                 (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) )
4846                         {
4847                                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
4848                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
4849                         }
4850                         else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5))
4851                         {
4852                                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
4853                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n"));
4854                         }
4855                 }
4856         }
4857         if( pHalData->DynamicTxHighPowerLvl != pHalData->LastDTPLvl )
4858         {
4859                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("PHY_SetTxPowerLevel8192C() Channel = %d \n" , pHalData->CurrentChannel));
4860                 PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
4861                 if(     (pHalData->DynamicTxHighPowerLvl == TxHighPwrLevel_Normal) &&
4862                         (pHalData->LastDTPLvl == TxHighPwrLevel_Level1 || pHalData->LastDTPLvl == TxHighPwrLevel_Level2)) //TxHighPwrLevel_Normal
4863                         odm_DynamicTxPowerRestorePowerIndex(pDM_Odm);
4864                 else if(pHalData->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
4865                         odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x14);
4866                 else if(pHalData->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
4867                         odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x10);
4868         }
4869         pHalData->LastDTPLvl = pHalData->DynamicTxHighPowerLvl;
4870
4871
4872 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
4873
4874         #if (RTL8192C_SUPPORT==1)
4875         PADAPTER Adapter = pDM_Odm->Adapter;
4876         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
4877         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
4878         struct mlme_priv        *pmlmepriv = &(Adapter->mlmepriv);
4879         struct mlme_ext_priv    *pmlmeext = &Adapter->mlmeextpriv;
4880         int     UndecoratedSmoothedPWDB;
4881
4882         if(!pdmpriv->bDynamicTxPowerEnable)
4883                 return;
4884
4885 #ifdef CONFIG_INTEL_PROXIM
4886         if(Adapter->proximity.proxim_on== _TRUE){
4887                 struct proximity_priv *prox_priv=Adapter->proximity.proximity_priv;
4888                 // Intel set fixed tx power
4889                 printk("\n %s  Adapter->proximity.proxim_on=%d prox_priv->proxim_modeinfo->power_output=%d \n",__FUNCTION__,Adapter->proximity.proxim_on,prox_priv->proxim_modeinfo->power_output);
4890                 if(prox_priv!=NULL){
4891                         if(prox_priv->proxim_modeinfo->power_output> 0)
4892                         {
4893                                 switch(prox_priv->proxim_modeinfo->power_output)
4894                                 {
4895                                         case 1:
4896                                                 pdmpriv->DynamicTxHighPowerLvl  = TxHighPwrLevel_100;
4897                                                 printk("TxHighPwrLevel_100\n");
4898                                                 break;
4899                                         case 2:
4900                                                 pdmpriv->DynamicTxHighPowerLvl  = TxHighPwrLevel_70;
4901                                                 printk("TxHighPwrLevel_70\n");
4902                                                 break;
4903                                         case 3:
4904                                                 pdmpriv->DynamicTxHighPowerLvl  = TxHighPwrLevel_50;
4905                                                 printk("TxHighPwrLevel_50\n");
4906                                                 break;
4907                                         case 4:
4908                                                 pdmpriv->DynamicTxHighPowerLvl  = TxHighPwrLevel_35;
4909                                                 printk("TxHighPwrLevel_35\n");
4910                                                 break;
4911                                         case 5:
4912                                                 pdmpriv->DynamicTxHighPowerLvl  = TxHighPwrLevel_15;
4913                                                 printk("TxHighPwrLevel_15\n");
4914                                                 break;
4915                                         default:
4916                                                 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_100;
4917                                                 printk("TxHighPwrLevel_100\n");
4918                                                 break;
4919                                 }
4920                         }
4921                 }
4922         }
4923         else
4924 #endif
4925         {
4926                 // STA not connected and AP not connected
4927                 if((check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) &&
4928                         (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
4929                 {
4930                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("Not connected to any \n"));
4931                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
4932
4933                         //the LastDTPlvl should reset when disconnect,
4934                         //otherwise the tx power level wouldn't change when disconnect and connect again.
4935                         // Maddest 20091220.
4936                         pdmpriv->LastDTPLvl=TxHighPwrLevel_Normal;
4937                         return;
4938                 }
4939
4940                 if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)       // Default port
4941                 {
4942                 #if 0
4943                         //todo: AP Mode
4944                         if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
4945                                (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
4946                         {
4947                                 UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
4948                                 //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
4949                         }
4950                         else
4951                         {
4952                                 UndecoratedSmoothedPWDB = pdmpriv->UndecoratedSmoothedPWDB;
4953                                 //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
4954                         }
4955                 #else
4956                 UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
4957                 #endif
4958                 }
4959                 else // associated entry pwdb
4960                 {
4961                         UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
4962                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
4963                 }
4964
4965                 if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2)
4966                 {
4967                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
4968                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n"));
4969                 }
4970                 else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) &&
4971                         (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) )
4972                 {
4973                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
4974                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
4975                 }
4976                 else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5))
4977                 {
4978                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
4979                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n"));
4980                 }
4981         }
4982         if( (pdmpriv->DynamicTxHighPowerLvl != pdmpriv->LastDTPLvl) )
4983         {
4984                 PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
4985                 if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Normal) // HP1 -> Normal  or HP2 -> Normal
4986                         odm_DynamicTxPowerRestorePowerIndex(pDM_Odm);
4987                 else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
4988                         odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x14);
4989                 else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
4990                         odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x10);
4991         }
4992         pdmpriv->LastDTPLvl = pdmpriv->DynamicTxHighPowerLvl;
4993         #endif
4994 #endif  // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
4995
4996 }
4997
4998
4999 VOID
5000 odm_DynamicTxPower_92D(
5001         IN      PDM_ODM_T       pDM_Odm
5002         )
5003 {
5004 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
5005         PADAPTER Adapter = pDM_Odm->Adapter;
5006         PMGNT_INFO                      pMgntInfo = &Adapter->MgntInfo;
5007         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
5008         s4Byte                          UndecoratedSmoothedPWDB;
5009
5010         PADAPTER        BuddyAdapter = Adapter->BuddyAdapter;
5011         BOOLEAN         bGetValueFromBuddyAdapter = dm_DualMacGetParameterFromBuddyAdapter(Adapter);
5012         u1Byte          HighPowerLvlBackForMac0 = TxHighPwrLevel_Level1;
5013
5014         // 2012/01/12 MH According to Luke's suggestion, only high power will support the feature.
5015         if (pDM_Odm->ExtPA == FALSE)
5016                 return;
5017
5018         // If dynamic high power is disabled.
5019         if( (pMgntInfo->bDynamicTxPowerEnable != TRUE) ||
5020                 (pHalData->DMFlag & HAL_DM_HIPWR_DISABLE) ||
5021                 pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)
5022         {
5023                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
5024                 return;
5025         }
5026
5027         // STA not connected and AP not connected
5028         if((!pMgntInfo->bMediaConnect) &&
5029                 (pHalData->EntryMinUndecoratedSmoothedPWDB == 0))
5030         {
5031                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("Not connected to any \n"));
5032                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
5033
5034                 //the LastDTPlvl should reset when disconnect,
5035                 //otherwise the tx power level wouldn't change when disconnect and connect again.
5036                 // Maddest 20091220.
5037                  pHalData->LastDTPLvl=TxHighPwrLevel_Normal;
5038                 return;
5039         }
5040
5041         if(pMgntInfo->bMediaConnect)    // Default port
5042         {
5043                 if(ACTING_AS_AP(Adapter) || pMgntInfo->mIbss)
5044                 {
5045                         UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB;
5046                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
5047                 }
5048                 else
5049                 {
5050                         UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB;
5051                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
5052                 }
5053         }
5054         else // associated entry pwdb
5055         {
5056                 UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB;
5057                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
5058         }
5059
5060         if(IS_HARDWARE_TYPE_8192D(Adapter) && GET_HAL_DATA(Adapter)->CurrentBandType == 1){
5061                 if(UndecoratedSmoothedPWDB >= 0x33)
5062                 {
5063                         pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
5064                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level2 (TxPwr=0x0)\n"));
5065                 }
5066                 else if((UndecoratedSmoothedPWDB <0x33) &&
5067                         (UndecoratedSmoothedPWDB >= 0x2b) )
5068                 {
5069                         pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
5070                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
5071                 }
5072                 else if(UndecoratedSmoothedPWDB < 0x2b)
5073                 {
5074                         pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
5075                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Normal\n"));
5076                 }
5077
5078         }
5079         else
5080
5081         {
5082                 if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2)
5083                 {
5084                         pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
5085                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n"));
5086                 }
5087                 else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) &&
5088                         (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) )
5089                 {
5090                         pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
5091                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
5092                 }
5093                 else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5))
5094                 {
5095                         pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
5096                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n"));
5097                 }
5098
5099         }
5100
5101 //sherry  delete flag 20110517
5102         if(bGetValueFromBuddyAdapter)
5103         {
5104                 ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 1 \n"));
5105                 if(Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP)
5106                 {
5107                         ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() change value \n"));
5108                         HighPowerLvlBackForMac0 = pHalData->DynamicTxHighPowerLvl;
5109                         pHalData->DynamicTxHighPowerLvl = Adapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP;
5110                         PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
5111                         pHalData->DynamicTxHighPowerLvl = HighPowerLvlBackForMac0;
5112                         Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = FALSE;
5113                 }
5114         }
5115
5116         if( (pHalData->DynamicTxHighPowerLvl != pHalData->LastDTPLvl) )
5117         {
5118                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("PHY_SetTxPowerLevel8192S() Channel = %d \n" , pHalData->CurrentChannel));
5119                         if(Adapter->DualMacSmartConcurrent == TRUE)
5120                         {
5121                                 if(BuddyAdapter == NULL)
5122                                 {
5123                                         ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter == NULL case \n"));
5124                                         if(!Adapter->bSlaveOfDMSP)
5125                                         {
5126                                                 PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
5127                                         }
5128                                 }
5129                                 else
5130                                 {
5131                                         if(pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY)
5132                                         {
5133                                                 ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMSP \n"));
5134                                                 if(Adapter->bSlaveOfDMSP)
5135                                                 {
5136                                                         ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() bslave case  \n"));
5137                                                         BuddyAdapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = TRUE;
5138                                                         BuddyAdapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP = pHalData->DynamicTxHighPowerLvl;
5139                                                 }
5140                                                 else
5141                                                 {
5142                                                         ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() master case  \n"));
5143                                                         if(!bGetValueFromBuddyAdapter)
5144                                                         {
5145                                                                 ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 0 \n"));
5146                                                                 PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
5147                                                         }
5148                                                 }
5149                                         }
5150                                         else
5151                                         {
5152                                                 ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMDP\n"));
5153                                                 PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
5154                                         }
5155                                 }
5156                         }
5157                         else
5158                         {
5159                                 PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
5160                         }
5161
5162                 }
5163         pHalData->LastDTPLvl = pHalData->DynamicTxHighPowerLvl;
5164 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
5165 #if (RTL8192D_SUPPORT==1)
5166         PADAPTER Adapter = pDM_Odm->Adapter;
5167         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
5168         struct mlme_priv        *pmlmepriv = &(Adapter->mlmepriv);
5169
5170         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
5171         DM_ODM_T                *podmpriv = &pHalData->odmpriv;
5172         int     UndecoratedSmoothedPWDB;
5173         #if (RTL8192D_EASY_SMART_CONCURRENT == 1)
5174         PADAPTER        BuddyAdapter = Adapter->BuddyAdapter;
5175         BOOLEAN         bGetValueFromBuddyAdapter = DualMacGetParameterFromBuddyAdapter(Adapter);
5176         u8              HighPowerLvlBackForMac0 = TxHighPwrLevel_Level1;
5177         #endif
5178
5179         // If dynamic high power is disabled.
5180         if( (pdmpriv->bDynamicTxPowerEnable != _TRUE) ||
5181                 (!(podmpriv->SupportAbility& ODM_BB_DYNAMIC_TXPWR)) )
5182         {
5183                 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
5184                 return;
5185         }
5186
5187         // STA not connected and AP not connected
5188         if((check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) &&
5189                 (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
5190         {
5191                 //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("Not connected to any \n"));
5192                 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
5193                 //the LastDTPlvl should reset when disconnect,
5194                 //otherwise the tx power level wouldn't change when disconnect and connect again.
5195                 // Maddest 20091220.
5196                 pdmpriv->LastDTPLvl=TxHighPwrLevel_Normal;
5197                 return;
5198         }
5199
5200         if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)       // Default port
5201         {
5202         #if 0
5203                 //todo: AP Mode
5204                 if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
5205                (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
5206                 {
5207                         UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
5208                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
5209                 }
5210                 else
5211                 {
5212                         UndecoratedSmoothedPWDB = pdmpriv->UndecoratedSmoothedPWDB;
5213                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
5214                 }
5215         #else
5216         UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
5217         #endif
5218         }
5219         else // associated entry pwdb
5220         {
5221                 UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
5222                 //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
5223         }
5224 #if TX_POWER_FOR_5G_BAND == 1
5225         if(pHalData->CurrentBandType92D == BAND_ON_5G){
5226                 if(UndecoratedSmoothedPWDB >= 0x33)
5227                 {
5228                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
5229                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level2 (TxPwr=0x0)\n"));
5230                 }
5231                 else if((UndecoratedSmoothedPWDB <0x33) &&
5232                         (UndecoratedSmoothedPWDB >= 0x2b) )
5233                 {
5234                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
5235                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
5236                 }
5237                 else if(UndecoratedSmoothedPWDB < 0x2b)
5238                 {
5239                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
5240                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Normal\n"));
5241                 }
5242         }
5243         else
5244 #endif
5245         {
5246                 if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2)
5247                 {
5248                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
5249                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n"));
5250                 }
5251                 else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) &&
5252                         (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) )
5253                 {
5254                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
5255                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
5256                 }
5257                 else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5))
5258                 {
5259                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
5260                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n"));
5261                 }
5262         }
5263 #if (RTL8192D_EASY_SMART_CONCURRENT == 1)
5264         if(bGetValueFromBuddyAdapter)
5265         {
5266                 //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 1 \n"));
5267                 if(Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP)
5268                 {
5269                         //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() change value \n"));
5270                         HighPowerLvlBackForMac0 = pHalData->DynamicTxHighPowerLvl;
5271                         pHalData->DynamicTxHighPowerLvl = Adapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP;
5272                         PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
5273                         pHalData->DynamicTxHighPowerLvl = HighPowerLvlBackForMac0;
5274                         Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = _FALSE;
5275                 }
5276         }
5277 #endif
5278
5279         if( (pdmpriv->DynamicTxHighPowerLvl != pdmpriv->LastDTPLvl) )
5280         {
5281                 //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("PHY_SetTxPowerLevel8192S() Channel = %d \n" , pHalData->CurrentChannel));
5282 #if (RTL8192D_EASY_SMART_CONCURRENT == 1)
5283                 if(BuddyAdapter == NULL)
5284                 {
5285                         //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter == NULL case \n"));
5286                         if(!Adapter->bSlaveOfDMSP)
5287                         {
5288                                 PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
5289                         }
5290                 }
5291                 else
5292                 {
5293                         if(pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY)
5294                         {
5295                                 //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMSP \n"));
5296                                 if(Adapter->bSlaveOfDMSP)
5297                                 {
5298                                         //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() bslave case  \n"));
5299                                         BuddyAdapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = _TRUE;
5300                                         BuddyAdapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP = pHalData->DynamicTxHighPowerLvl;
5301                                 }
5302                                 else
5303                                 {
5304                                         //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() master case  \n"));
5305                                         if(!bGetValueFromBuddyAdapter)
5306                                         {
5307                                                 //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 0 \n"));
5308                                                 PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
5309                                         }
5310                                 }
5311                         }
5312                         else
5313                         {
5314                                 //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMDP\n"));
5315                                 PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
5316                         }
5317                 }
5318 #else
5319                 PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
5320 #endif
5321         }
5322         pdmpriv->LastDTPLvl = pdmpriv->DynamicTxHighPowerLvl;
5323 #endif
5324 #endif  // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
5325
5326 }
5327
5328
5329 //3============================================================
5330 //3 RSSI Monitor
5331 //3============================================================
5332
5333 VOID
5334 odm_RSSIDumpToRegister(
5335         IN      PDM_ODM_T       pDM_Odm
5336         )
5337 {
5338 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
5339         PADAPTER                Adapter = pDM_Odm->Adapter;
5340
5341         if(pDM_Odm->SupportICType == ODM_RTL8812)
5342         {
5343                 PlatformEFIOWrite1Byte(Adapter, rA_RSSIDump_Jaguar, Adapter->RxStats.RxRSSIPercentage[0]);
5344                 PlatformEFIOWrite1Byte(Adapter, rB_RSSIDump_Jaguar, Adapter->RxStats.RxRSSIPercentage[1]);
5345
5346                 // Rx EVM
5347                 PlatformEFIOWrite1Byte(Adapter, rS1_RXevmDump_Jaguar, Adapter->RxStats.RxEVMdbm[0]);
5348                 PlatformEFIOWrite1Byte(Adapter, rS2_RXevmDump_Jaguar, Adapter->RxStats.RxEVMdbm[1]);
5349
5350                 // Rx SNR
5351                 PlatformEFIOWrite1Byte(Adapter, rA_RXsnrDump_Jaguar, (u1Byte)(Adapter->RxStats.RxSNRdB[0]));
5352                 PlatformEFIOWrite1Byte(Adapter, rB_RXsnrDump_Jaguar, (u1Byte)(Adapter->RxStats.RxSNRdB[1]));
5353
5354                 // Rx Cfo_Short
5355                 PlatformEFIOWrite2Byte(Adapter, rA_CfoShortDump_Jaguar, Adapter->RxStats.RxCfoShort[0]);
5356                 PlatformEFIOWrite2Byte(Adapter, rB_CfoShortDump_Jaguar, Adapter->RxStats.RxCfoShort[1]);
5357
5358                 // Rx Cfo_Tail
5359                 PlatformEFIOWrite2Byte(Adapter, rA_CfoLongDump_Jaguar, Adapter->RxStats.RxCfoTail[0]);
5360                 PlatformEFIOWrite2Byte(Adapter, rB_CfoLongDump_Jaguar, Adapter->RxStats.RxCfoTail[1]);
5361         }
5362         else if(pDM_Odm->SupportICType == ODM_RTL8192E)
5363         {
5364                 PlatformEFIOWrite1Byte(Adapter, rA_RSSIDump_92E, Adapter->RxStats.RxRSSIPercentage[0]);
5365                 PlatformEFIOWrite1Byte(Adapter, rB_RSSIDump_92E, Adapter->RxStats.RxRSSIPercentage[1]);
5366                 // Rx EVM
5367                 PlatformEFIOWrite1Byte(Adapter, rS1_RXevmDump_92E, Adapter->RxStats.RxEVMdbm[0]);
5368                 PlatformEFIOWrite1Byte(Adapter, rS2_RXevmDump_92E, Adapter->RxStats.RxEVMdbm[1]);
5369                 // Rx SNR
5370                 PlatformEFIOWrite1Byte(Adapter, rA_RXsnrDump_92E, (u1Byte)(Adapter->RxStats.RxSNRdB[0]));
5371                 PlatformEFIOWrite1Byte(Adapter, rB_RXsnrDump_92E, (u1Byte)(Adapter->RxStats.RxSNRdB[1]));
5372                 // Rx Cfo_Short
5373                 PlatformEFIOWrite2Byte(Adapter, rA_CfoShortDump_92E, Adapter->RxStats.RxCfoShort[0]);
5374                 PlatformEFIOWrite2Byte(Adapter, rB_CfoShortDump_92E, Adapter->RxStats.RxCfoShort[1]);
5375                 // Rx Cfo_Tail
5376                 PlatformEFIOWrite2Byte(Adapter, rA_CfoLongDump_92E, Adapter->RxStats.RxCfoTail[0]);
5377                 PlatformEFIOWrite2Byte(Adapter, rB_CfoLongDump_92E, Adapter->RxStats.RxCfoTail[1]);
5378          }
5379 #endif
5380 }
5381
5382
5383 VOID
5384 odm_RSSIMonitorInit(
5385         IN      PDM_ODM_T       pDM_Odm
5386         )
5387 {
5388         pRA_T           pRA_Table = &pDM_Odm->DM_RA_Table;
5389
5390         pRA_Table->firstconnect = FALSE;
5391
5392 }
5393
5394 VOID
5395 odm_RSSIMonitorCheck(
5396         IN              PDM_ODM_T               pDM_Odm
5397         )
5398 {
5399         //
5400         // For AP/ADSL use prtl8192cd_priv
5401         // For CE/NIC use PADAPTER
5402         //
5403
5404         if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR))
5405                 return;
5406
5407         //
5408         // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
5409         // at the same time. In the stage2/3, we need to prive universal interface and merge all
5410         // HW dynamic mechanism.
5411         //
5412         switch  (pDM_Odm->SupportPlatform)
5413         {
5414                 case    ODM_WIN:
5415                         odm_RSSIMonitorCheckMP(pDM_Odm);
5416                         break;
5417
5418                 case    ODM_CE:
5419                         odm_RSSIMonitorCheckCE(pDM_Odm);
5420                         break;
5421
5422                 case    ODM_AP:
5423                         odm_RSSIMonitorCheckAP(pDM_Odm);
5424                         break;
5425
5426                 case    ODM_ADSL:
5427                         //odm_DIGAP(pDM_Odm);
5428                         break;
5429         }
5430
5431 }       // odm_RSSIMonitorCheck
5432
5433
5434 VOID
5435 odm_RSSIMonitorCheckMP(
5436         IN      PDM_ODM_T       pDM_Odm
5437         )
5438 {
5439 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
5440         PADAPTER                Adapter = pDM_Odm->Adapter;
5441         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
5442         PRT_WLAN_STA    pEntry;
5443         u1Byte                  i;
5444         s4Byte                  tmpEntryMaxPWDB=0, tmpEntryMinPWDB=0xff;
5445         u1Byte                  H2C_Parameter[4] ={0};
5446         PMGNT_INFO              pMgntInfo = &Adapter->MgntInfo;
5447         u8Byte                  curTxOkCnt = 0, curRxOkCnt = 0;
5448         u1Byte                  STBC_TX = 0;
5449         BOOLEAN                 FirstConnect;
5450         pRA_T                   pRA_Table = &pDM_Odm->DM_RA_Table;
5451 #if (BEAMFORMING_SUPPORT == 1)
5452         BEAMFORMING_CAP Beamform_cap = BEAMFORMING_CAP_NONE;
5453         u1Byte                  TxBF_EN = 0;
5454 #endif
5455
5456         RT_DISP(FDM, DM_PWDB, ("pHalData->UndecoratedSmoothedPWDB = 0x%x( %d)\n",
5457                 pHalData->UndecoratedSmoothedPWDB,
5458                 pHalData->UndecoratedSmoothedPWDB));
5459
5460         curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - pMgntInfo->lastTxOkCnt;
5461         curRxOkCnt = Adapter->RxStats.NumRxBytesUnicast - pMgntInfo->lastRxOkCnt;
5462         pMgntInfo->lastTxOkCnt = curTxOkCnt;
5463         pMgntInfo->lastRxOkCnt = curRxOkCnt;
5464
5465         RT_DISP(FDM, DM_PWDB, ("Tx = %d Rx = %d\n", curTxOkCnt, curRxOkCnt));
5466
5467        FirstConnect = (pHalData->bLinked) && (pRA_Table->firstconnect == FALSE);
5468         pRA_Table->firstconnect = pHalData->bLinked;
5469        H2C_Parameter[3] |= FirstConnect << 5;
5470
5471         if(pDM_Odm->SupportICType == ODM_RTL8188E && (pMgntInfo->CustomerID==RT_CID_819x_HP))
5472         {
5473                 if(curRxOkCnt >(curTxOkCnt*6))
5474                         PlatformEFIOWrite4Byte(Adapter, REG_ARFR0, 0x8f015);
5475                 else
5476                         PlatformEFIOWrite4Byte(Adapter, REG_ARFR0, 0xff015);
5477         }
5478
5479         if(pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8821)
5480         {
5481                 if(curRxOkCnt >(curTxOkCnt*6))
5482                         H2C_Parameter[3]=0x01;
5483                 else
5484                         H2C_Parameter[3]=0x00;
5485         }
5486
5487         for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
5488         {
5489                 if(IsAPModeExist(Adapter)  && GetFirstExtAdapter(Adapter) != NULL)
5490                 {
5491                         pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i);
5492                 }
5493                 else
5494                 {
5495                         pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i);
5496                 }
5497
5498                 if(pEntry != NULL)
5499                 {
5500                         if(pEntry->bAssociated)
5501                         {
5502
5503                                 RT_DISP_ADDR(FDM, DM_PWDB, ("pEntry->MacAddr ="), pEntry->MacAddr);
5504                                 RT_DISP(FDM, DM_PWDB, ("pEntry->rssi = 0x%x(%d)\n",
5505                                         pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntry->rssi_stat.UndecoratedSmoothedPWDB));
5506
5507                                 if(pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8812)
5508                                 {
5509
5510 #if (BEAMFORMING_SUPPORT == 1)
5511                                         Beamform_cap = Beamforming_GetEntryBeamCapByMacId(pMgntInfo, pEntry->AssociatedMacId);
5512                                         if(Beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT |BEAMFORMER_CAP_VHT_SU))
5513                                                 TxBF_EN = 1;
5514                                         else
5515                                                 TxBF_EN = 0;
5516
5517                                         H2C_Parameter[3] |= TxBF_EN << 6;
5518
5519                                         if(TxBF_EN)
5520                                                 STBC_TX = 0;
5521                                         else
5522 #endif
5523                                         {
5524                                                 if(IS_WIRELESS_MODE_AC(Adapter))
5525                                                         STBC_TX = TEST_FLAG(pEntry->VHTInfo.STBC, STBC_VHT_ENABLE_TX);
5526                                                 else
5527                                                         STBC_TX = TEST_FLAG(pEntry->HTInfo.STBC, STBC_HT_ENABLE_TX);
5528                                         }
5529
5530                                         H2C_Parameter[3] |= STBC_TX << 1;
5531                                 }
5532
5533                                 if(pEntry->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB)
5534                                         tmpEntryMinPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB;
5535                                 if(pEntry->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
5536                                         tmpEntryMaxPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB;
5537
5538                                 H2C_Parameter[2] = (u1Byte)(pEntry->rssi_stat.UndecoratedSmoothedPWDB & 0xFF);
5539                                 H2C_Parameter[1] = 0x20;   // fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1
5540                                 H2C_Parameter[0] = (pEntry->AssociatedMacId);
5541                                 if(pDM_Odm->SupportICType == ODM_RTL8812)
5542                                         ODM_FillH2CCmd(Adapter, ODM_H2C_RSSI_REPORT, 4, H2C_Parameter);
5543                                 else if(pDM_Odm->SupportICType == ODM_RTL8192E)
5544                                         ODM_FillH2CCmd(Adapter, ODM_H2C_RSSI_REPORT, 4, H2C_Parameter);
5545                                 else
5546                                         ODM_FillH2CCmd(Adapter, ODM_H2C_RSSI_REPORT, 3, H2C_Parameter);
5547                         }
5548                 }
5549                 else
5550                 {
5551                         break;
5552                 }
5553         }
5554
5555         if(tmpEntryMaxPWDB != 0)        // If associated entry is found
5556         {
5557                 pHalData->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB;
5558                 RT_DISP(FDM, DM_PWDB, ("EntryMaxPWDB = 0x%x(%d)\n",     tmpEntryMaxPWDB, tmpEntryMaxPWDB));
5559         }
5560         else
5561         {
5562                 pHalData->EntryMaxUndecoratedSmoothedPWDB = 0;
5563         }
5564
5565         if(tmpEntryMinPWDB != 0xff) // If associated entry is found
5566         {
5567                 pHalData->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB;
5568                 RT_DISP(FDM, DM_PWDB, ("EntryMinPWDB = 0x%x(%d)\n", tmpEntryMinPWDB, tmpEntryMinPWDB));
5569
5570         }
5571         else
5572         {
5573                 pHalData->EntryMinUndecoratedSmoothedPWDB = 0;
5574         }
5575
5576         // Indicate Rx signal strength to FW.
5577         if(pHalData->bUseRAMask)
5578         {
5579                 if(pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8812)
5580                 {
5581                         PRT_HIGH_THROUGHPUT             pHTInfo = GET_HT_INFO(pMgntInfo);
5582                         PRT_VERY_HIGH_THROUGHPUT        pVHTInfo = GET_VHT_INFO(pMgntInfo);
5583
5584 #if (BEAMFORMING_SUPPORT == 1)
5585
5586                         Beamform_cap = Beamforming_GetEntryBeamCapByMacId(pMgntInfo, pMgntInfo->mMacId);
5587
5588                         if(Beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT |BEAMFORMER_CAP_VHT_SU))
5589                                 TxBF_EN = 1;
5590                         else
5591                                 TxBF_EN = 0;
5592
5593                         H2C_Parameter[3] |= TxBF_EN << 6;
5594
5595                         if(TxBF_EN)
5596                                 STBC_TX = 0;
5597                         else
5598 #endif
5599                         {
5600                                 if(IS_WIRELESS_MODE_AC(Adapter))
5601                                         STBC_TX = TEST_FLAG(pVHTInfo->VhtCurStbc, STBC_VHT_ENABLE_TX);
5602                                 else
5603                                         STBC_TX = TEST_FLAG(pHTInfo->HtCurStbc, STBC_HT_ENABLE_TX);
5604                         }
5605
5606                         H2C_Parameter[3] |= STBC_TX << 1;
5607                 }
5608
5609                 H2C_Parameter[2] = (u1Byte)(pHalData->UndecoratedSmoothedPWDB & 0xFF);
5610                 H2C_Parameter[1] = 0x20;        // fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1
5611                 H2C_Parameter[0] = 0;           // fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1
5612                 if(pDM_Odm->SupportICType == ODM_RTL8812)
5613                         ODM_FillH2CCmd(Adapter, ODM_H2C_RSSI_REPORT, 4, H2C_Parameter);
5614                 else  if(pDM_Odm->SupportICType == ODM_RTL8192E)
5615                         ODM_FillH2CCmd(Adapter, ODM_H2C_RSSI_REPORT, 4, H2C_Parameter);
5616                 else
5617                         ODM_FillH2CCmd(Adapter, ODM_H2C_RSSI_REPORT, 3, H2C_Parameter);
5618         }
5619         else
5620         {
5621                 PlatformEFIOWrite1Byte(Adapter, 0x4fe, (u1Byte)pHalData->UndecoratedSmoothedPWDB);
5622         }
5623
5624         if((pDM_Odm->SupportICType == ODM_RTL8812)||(pDM_Odm->SupportICType == ODM_RTL8192E))
5625                 odm_RSSIDumpToRegister(pDM_Odm);
5626
5627         odm_FindMinimumRSSI(Adapter);
5628         ODM_CmnInfoUpdate(&pHalData->DM_OutSrc ,ODM_CMNINFO_LINK, (u8Byte)pHalData->bLinked);
5629         ODM_CmnInfoUpdate(&pHalData->DM_OutSrc ,ODM_CMNINFO_RSSI_MIN, (u8Byte)pHalData->MinUndecoratedPWDBForDM);
5630 #endif  // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
5631 }
5632
5633 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
5634 //
5635 //sherry move from DUSC to here 20110517
5636 //
5637 static VOID
5638 FindMinimumRSSI_Dmsp(
5639         IN      PADAPTER        pAdapter
5640 )
5641 {
5642 #if 0
5643         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
5644         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
5645         s32     Rssi_val_min_back_for_mac0;
5646         BOOLEAN         bGetValueFromBuddyAdapter = dm_DualMacGetParameterFromBuddyAdapter(pAdapter);
5647         BOOLEAN         bRestoreRssi = _FALSE;
5648         PADAPTER        BuddyAdapter = pAdapter->BuddyAdapter;
5649
5650         if(pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY)
5651         {
5652                 if(BuddyAdapter!= NULL)
5653                 {
5654                         if(pHalData->bSlaveOfDMSP)
5655                         {
5656                                 //ODM_RT_TRACE(pDM_Odm,COMP_EASY_CONCURRENT,DBG_LOUD,("bSlavecase of dmsp\n"));
5657                                 BuddyAdapter->DualMacDMSPControl.RssiValMinForAnotherMacOfDMSP = pdmpriv->MinUndecoratedPWDBForDM;
5658                         }
5659                         else
5660                         {
5661                                 if(bGetValueFromBuddyAdapter)
5662                                 {
5663                                         //ODM_RT_TRACE(pDM_Odm,COMP_EASY_CONCURRENT,DBG_LOUD,("get new RSSI\n"));
5664                                         bRestoreRssi = _TRUE;
5665                                         Rssi_val_min_back_for_mac0 = pdmpriv->MinUndecoratedPWDBForDM;
5666                                         pdmpriv->MinUndecoratedPWDBForDM = pAdapter->DualMacDMSPControl.RssiValMinForAnotherMacOfDMSP;
5667                                 }
5668                         }
5669                 }
5670
5671         }
5672
5673         if(bRestoreRssi)
5674         {
5675                 bRestoreRssi = _FALSE;
5676                 pdmpriv->MinUndecoratedPWDBForDM = Rssi_val_min_back_for_mac0;
5677         }
5678 #endif
5679 }
5680
5681 static void
5682 FindMinimumRSSI(
5683 IN      PADAPTER        pAdapter
5684         )
5685 {
5686         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
5687         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
5688         PDM_ODM_T               pDM_Odm = &(pHalData->odmpriv);
5689
5690         //1 1.Determine the minimum RSSI
5691
5692         if((pDM_Odm->bLinked != _TRUE) &&
5693                 (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
5694         {
5695                 pdmpriv->MinUndecoratedPWDBForDM = 0;
5696                 //ODM_RT_TRACE(pDM_Odm,COMP_BB_POWERSAVING, DBG_LOUD, ("Not connected to any \n"));
5697         }
5698         else
5699         {
5700                 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
5701         }
5702
5703         //DBG_8192C("%s=>MinUndecoratedPWDBForDM(%d)\n",__FUNCTION__,pdmpriv->MinUndecoratedPWDBForDM);
5704         //ODM_RT_TRACE(pDM_Odm,COMP_DIG, DBG_LOUD, ("MinUndecoratedPWDBForDM =%d\n",pHalData->MinUndecoratedPWDBForDM));
5705 }
5706 #endif
5707
5708 VOID
5709 odm_RSSIMonitorCheckCE(
5710         IN              PDM_ODM_T               pDM_Odm
5711         )
5712 {
5713 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
5714         PADAPTER        Adapter = pDM_Odm->Adapter;
5715         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
5716         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
5717         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(Adapter);
5718         int     i;
5719         int     tmpEntryMaxPWDB=0, tmpEntryMinPWDB=0xff;
5720         u8      sta_cnt=0;
5721         u32     UL_DL_STATE = 0, STBC_TX = 0, TxBF_EN = 0;
5722         u32     PWDB_rssi[NUM_STA]={0};//[0~15]:MACID, [16~31]:PWDB_rssi
5723         BOOLEAN                 FirstConnect = FALSE;
5724         pRA_T                   pRA_Table = &pDM_Odm->DM_RA_Table;
5725
5726         if(pDM_Odm->bLinked != _TRUE)
5727                 return;
5728
5729         #if((RTL8812A_SUPPORT==1)||(RTL8821A_SUPPORT==1))
5730         if((pDM_Odm->SupportICType == ODM_RTL8812)||(pDM_Odm->SupportICType == ODM_RTL8821))
5731         {
5732                 u64     curTxOkCnt = pdvobjpriv->traffic_stat.cur_tx_bytes;
5733                 u64     curRxOkCnt = pdvobjpriv->traffic_stat.cur_rx_bytes;
5734
5735                 if(curRxOkCnt >(curTxOkCnt*6))
5736                         UL_DL_STATE = 1;
5737                 else
5738                         UL_DL_STATE = 0;
5739         }
5740         #endif
5741
5742        FirstConnect = (pDM_Odm->bLinked) && (pRA_Table->firstconnect == FALSE);
5743         pRA_Table->firstconnect = pDM_Odm->bLinked;
5744
5745         //if(check_fwstate(&Adapter->mlmepriv, WIFI_AP_STATE|WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == _TRUE)
5746         {
5747                 #if 1
5748                 struct sta_info *psta;
5749
5750                 for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++) {
5751                         if (IS_STA_VALID(psta = pDM_Odm->pODM_StaInfo[i]))
5752                         {
5753                                         if(IS_MCAST( psta->hwaddr))  //if(psta->mac_id ==1)
5754                                                  continue;
5755
5756                                         if(psta->rssi_stat.UndecoratedSmoothedPWDB == (-1))
5757                                                  continue;
5758
5759                                         if(psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB)
5760                                                 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
5761
5762                                         if(psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
5763                                                 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
5764
5765                                         #if 0
5766                                         DBG_871X("%s mac_id:%u, mac:"MAC_FMT", rssi:%d\n", __func__,
5767                                                 psta->mac_id, MAC_ARG(psta->hwaddr), psta->rssi_stat.UndecoratedSmoothedPWDB);
5768                                         #endif
5769
5770                                         if(psta->rssi_stat.UndecoratedSmoothedPWDB != (-1)) {
5771
5772 #ifdef CONFIG_80211N_HT
5773                                                 if(pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8812)
5774                                                 {
5775 #ifdef CONFIG_BEAMFORMING
5776                                                         BEAMFORMING_CAP Beamform_cap = beamforming_get_entry_beam_cap_by_mac_id(&Adapter->mlmepriv, psta->mac_id);
5777
5778                                                         if(Beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT |BEAMFORMER_CAP_VHT_SU))
5779                                                                 TxBF_EN = 1;
5780                                                         else
5781                                                                 TxBF_EN = 0;
5782
5783                                                         if (TxBF_EN) {
5784                                                                 STBC_TX = 0;
5785                                                         }
5786                                                         else
5787 #endif
5788                                                         {
5789 #ifdef CONFIG_80211AC_VHT
5790                                                                 if(IsSupportedVHT(psta->wireless_mode))
5791                                                                         STBC_TX = TEST_FLAG(psta->vhtpriv.stbc_cap, STBC_VHT_ENABLE_TX);
5792                                                                 else
5793 #endif
5794                                                                         STBC_TX = TEST_FLAG(psta->htpriv.stbc_cap, STBC_HT_ENABLE_TX);
5795                                                         }
5796                                                 }
5797 #endif
5798
5799                                                 if(pDM_Odm->SupportICType == ODM_RTL8192D)
5800                                                         PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16) | ((Adapter->stapriv.asoc_sta_count+1) << 8));
5801                                                 else if ((pDM_Odm->SupportICType == ODM_RTL8192E)||(pDM_Odm->SupportICType == ODM_RTL8812)||(pDM_Odm->SupportICType == ODM_RTL8821))
5802                                                         PWDB_rssi[sta_cnt++] = (((u8)(psta->mac_id&0xFF)) | ((psta->rssi_stat.UndecoratedSmoothedPWDB&0x7F)<<16) |(STBC_TX << 25) | (FirstConnect << 29) | (TxBF_EN << 30));
5803                                                 else
5804                                                         PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16) );
5805                                         }
5806                         }
5807                 }
5808                 #else
5809                 _irqL irqL;
5810                 _list   *plist, *phead;
5811                 struct sta_info *psta;
5812                 struct sta_priv *pstapriv = &Adapter->stapriv;
5813                 u8 bcast_addr[ETH_ALEN]= {0xff,0xff,0xff,0xff,0xff,0xff};
5814
5815                 _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
5816
5817                 for(i=0; i< NUM_STA; i++)
5818                 {
5819                         phead = &(pstapriv->sta_hash[i]);
5820                         plist = get_next(phead);
5821
5822                         while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
5823                         {
5824                                 psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
5825
5826                                 plist = get_next(plist);
5827
5828                                 if(_rtw_memcmp(psta->hwaddr, bcast_addr, ETH_ALEN) ||
5829                                         _rtw_memcmp(psta->hwaddr, myid(&Adapter->eeprompriv), ETH_ALEN))
5830                                         continue;
5831
5832                                 if(psta->state & WIFI_ASOC_STATE)
5833                                 {
5834
5835                                         if(psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB)
5836                                                 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
5837
5838                                         if(psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
5839                                                 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
5840
5841                                         if(psta->rssi_stat.UndecoratedSmoothedPWDB != (-1)){
5842                                                 //printk("%s==> mac_id(%d),rssi(%d)\n",__FUNCTION__,psta->mac_id,psta->rssi_stat.UndecoratedSmoothedPWDB);
5843                                                 #if(RTL8192D_SUPPORT==1)
5844                                                 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16) | ((Adapter->stapriv.asoc_sta_count+1) << 8));
5845                                                 #else
5846                                                 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16) );
5847                                                 #endif
5848                                         }
5849                                 }
5850
5851                         }
5852
5853                 }
5854
5855                 _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
5856                 #endif
5857
5858                 //printk("%s==> sta_cnt(%d)\n",__FUNCTION__,sta_cnt);
5859
5860                 for(i=0; i< sta_cnt; i++)
5861                 {
5862                         if(PWDB_rssi[i] != (0)){
5863                                 if(pHalData->fw_ractrl == _TRUE)// Report every sta's RSSI to FW
5864                                 {
5865                                         #if(RTL8192D_SUPPORT==1)
5866                                         if(pDM_Odm->SupportICType == ODM_RTL8192D){
5867                                                 FillH2CCmd92D(Adapter, H2C_RSSI_REPORT, 3, (u8 *)(&PWDB_rssi[i]));
5868                                         }
5869                                         #endif
5870
5871                                         #if((RTL8192C_SUPPORT==1)||(RTL8723A_SUPPORT==1))
5872                                         if((pDM_Odm->SupportICType == ODM_RTL8192C)||(pDM_Odm->SupportICType == ODM_RTL8723A)){
5873                                                 rtl8192c_set_rssi_cmd(Adapter, (u8*)&PWDB_rssi[i]);
5874                                         }
5875                                         #endif
5876
5877                                         #if((RTL8812A_SUPPORT==1)||(RTL8821A_SUPPORT==1))
5878                                         if((pDM_Odm->SupportICType == ODM_RTL8812)||(pDM_Odm->SupportICType == ODM_RTL8821)){
5879                                                 PWDB_rssi[i] |= (UL_DL_STATE << 24);
5880                                                 rtl8812_set_rssi_cmd(Adapter, (u8 *)(&PWDB_rssi[i]));
5881                                         }
5882                                         #endif
5883                                         #if(RTL8192E_SUPPORT==1)
5884                                         if(pDM_Odm->SupportICType == ODM_RTL8192E){
5885                                                 rtl8192e_set_rssi_cmd(Adapter, (u8 *)(&PWDB_rssi[i]));
5886                                         }
5887                                         #endif
5888                                         #if(RTL8723B_SUPPORT==1)
5889                                         if(pDM_Odm->SupportICType == ODM_RTL8723B){
5890                                                 rtl8723b_set_rssi_cmd(Adapter, (u8 *)(&PWDB_rssi[i]));
5891                                         }
5892                                         #endif
5893                                 }
5894                                 else{
5895                                         #if((RTL8188E_SUPPORT==1)&&(RATE_ADAPTIVE_SUPPORT == 1))
5896                                         if(pDM_Odm->SupportICType == ODM_RTL8188E){
5897                                                 ODM_RA_SetRSSI_8188E(
5898                                                 &(pHalData->odmpriv), (PWDB_rssi[i]&0xFF), (u8)((PWDB_rssi[i]>>16) & 0xFF));
5899                                         }
5900                                         #endif
5901                                 }
5902                         }
5903                 }
5904         }
5905
5906
5907
5908         if(tmpEntryMaxPWDB != 0)        // If associated entry is found
5909         {
5910                 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB;
5911         }
5912         else
5913         {
5914                 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0;
5915         }
5916
5917         if(tmpEntryMinPWDB != 0xff) // If associated entry is found
5918         {
5919                 pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB;
5920         }
5921         else
5922         {
5923                 pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0;
5924         }
5925
5926         FindMinimumRSSI(Adapter);//get pdmpriv->MinUndecoratedPWDBForDM
5927
5928         #if(RTL8192D_SUPPORT==1)
5929         FindMinimumRSSI_Dmsp(Adapter);
5930         #endif
5931         pDM_Odm->RSSI_Min = pdmpriv->MinUndecoratedPWDBForDM;
5932         //ODM_CmnInfoUpdate(&pHalData->odmpriv ,ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM);
5933 #endif//if (DM_ODM_SUPPORT_TYPE == ODM_CE)
5934 }
5935 VOID
5936 odm_RSSIMonitorCheckAP(
5937         IN              PDM_ODM_T               pDM_Odm
5938         )
5939 {
5940 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
5941 #ifdef CONFIG_RTL_92C_SUPPORT || defined(CONFIG_RTL_92D_SUPPORT)
5942
5943         u4Byte i;
5944         PSTA_INFO_T pstat;
5945
5946         for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
5947         {
5948                 pstat = pDM_Odm->pODM_StaInfo[i];
5949                 if(IS_STA_VALID(pstat) )
5950                 {
5951 #ifdef STA_EXT
5952                         if (REMAP_AID(pstat) < (FW_NUM_STAT - 1))
5953 #endif
5954                                 add_update_rssi(pDM_Odm->priv, pstat);
5955
5956                 }
5957         }
5958 #endif
5959 #endif
5960
5961 }
5962
5963
5964
5965 VOID
5966 ODM_InitAllTimers(
5967         IN PDM_ODM_T    pDM_Odm
5968         )
5969 {
5970 #if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
5971 #if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)
5972         ODM_InitializeTimer(pDM_Odm,&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer_8723B,
5973         (RT_TIMER_CALL_BACK)ODM_SW_AntDiv_Callback, NULL, "SwAntennaSwitchTimer_8723B");
5974 #endif
5975 #endif
5976
5977 #if(defined(CONFIG_SW_ANTENNA_DIVERSITY))
5978         ODM_InitializeTimer(pDM_Odm,&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer,
5979                 (RT_TIMER_CALL_BACK)odm_SwAntDivChkAntSwitchCallback, NULL, "SwAntennaSwitchTimer");
5980 #endif
5981
5982 #if (!(DM_ODM_SUPPORT_TYPE == ODM_CE))
5983 #if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
5984 #if (RTL8188E_SUPPORT == 1)
5985         ODM_InitializeTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer,
5986                 (RT_TIMER_CALL_BACK)odm_FastAntTrainingCallback, NULL, "FastAntTrainingTimer");
5987 #endif
5988 #endif
5989 #endif
5990
5991 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
5992         ODM_InitializeTimer(pDM_Odm, &pDM_Odm->PSDTimer,
5993                 (RT_TIMER_CALL_BACK)dm_PSDMonitorCallback, NULL, "PSDTimer");
5994         //
5995         //Path Diversity
5996         //Neil Chen--2011--06--16--  / 2012/02/23 MH Revise Arch.
5997         //
5998         ODM_InitializeTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer,
5999                 (RT_TIMER_CALL_BACK)odm_PathDivChkAntSwitchCallback, NULL, "PathDivTimer");
6000
6001         ODM_InitializeTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer,
6002                 (RT_TIMER_CALL_BACK)odm_CCKTXPathDiversityCallback, NULL, "CCKPathDiversityTimer");
6003
6004         ODM_InitializeTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer,
6005                 (RT_TIMER_CALL_BACK)odm_MPT_DIGCallback, NULL, "MPT_DIGTimer");
6006
6007         ODM_InitializeTimer(pDM_Odm, &pDM_Odm->DM_RXHP_Table.PSDTimer,
6008                 (RT_TIMER_CALL_BACK)odm_PSD_RXHPCallback, NULL, "PSDRXHPTimer");
6009 #endif
6010 }
6011
6012 VOID
6013 ODM_CancelAllTimers(
6014         IN PDM_ODM_T    pDM_Odm
6015         )
6016 {
6017 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
6018         //
6019         // 2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in
6020         // win7 platform.
6021         //
6022         HAL_ADAPTER_STS_CHK(pDM_Odm)
6023 #endif
6024 #if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
6025 #if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)
6026         ODM_CancelTimer(pDM_Odm,&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer_8723B);
6027 #endif
6028 #endif
6029
6030 #if(defined(CONFIG_SW_ANTENNA_DIVERSITY))
6031         ODM_CancelTimer(pDM_Odm,&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer);
6032 #endif
6033
6034 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
6035
6036 #if (RTL8188E_SUPPORT == 1)
6037         ODM_CancelTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer);
6038 #endif
6039         ODM_CancelTimer(pDM_Odm, &pDM_Odm->PSDTimer);
6040         //
6041         //Path Diversity
6042         //Neil Chen--2011--06--16--  / 2012/02/23 MH Revise Arch.
6043         //
6044         ODM_CancelTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer);
6045
6046         ODM_CancelTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer);
6047
6048         ODM_CancelTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer);
6049
6050         ODM_CancelTimer(pDM_Odm, &pDM_Odm->DM_RXHP_Table.PSDTimer);
6051 #endif
6052 }
6053
6054
6055 VOID
6056 ODM_ReleaseAllTimers(
6057         IN PDM_ODM_T    pDM_Odm
6058         )
6059 {
6060 #if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
6061 #if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)
6062         ODM_ReleaseTimer(pDM_Odm,&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer_8723B);
6063 #endif
6064 #endif
6065
6066 #if(defined(CONFIG_SW_ANTENNA_DIVERSITY))
6067         ODM_ReleaseTimer(pDM_Odm,&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer);
6068 #endif
6069
6070 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
6071
6072 #if (RTL8188E_SUPPORT == 1)
6073         ODM_ReleaseTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer);
6074 #endif
6075
6076         ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->PSDTimer);
6077         //
6078         //Path Diversity
6079         //Neil Chen--2011--06--16--  / 2012/02/23 MH Revise Arch.
6080         //
6081         ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer);
6082
6083         ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer);
6084
6085         ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer);
6086
6087         ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->DM_RXHP_Table.PSDTimer);
6088 #endif
6089 }
6090
6091
6092 //3============================================================
6093 //3 Tx Power Tracking
6094 //3============================================================
6095
6096 VOID
6097 odm_IQCalibrate(
6098                 IN      PDM_ODM_T       pDM_Odm
6099                 )
6100 {
6101         PADAPTER        Adapter = pDM_Odm->Adapter;
6102
6103         if(!IS_HARDWARE_TYPE_JAGUAR(Adapter))
6104                 return;
6105         else if(IS_HARDWARE_TYPE_8812AU(Adapter))
6106                 return;
6107 #if (RTL8821A_SUPPORT == 1)
6108         if(pDM_Odm->bLinked)
6109         {
6110                 if((*pDM_Odm->pChannel != pDM_Odm->preChannel) && (!*pDM_Odm->pbScanInProcess))
6111                 {
6112                         pDM_Odm->preChannel = *pDM_Odm->pChannel;
6113                         pDM_Odm->LinkedInterval = 0;
6114                 }
6115
6116                 if(pDM_Odm->LinkedInterval < 3)
6117                         pDM_Odm->LinkedInterval++;
6118
6119                 if(pDM_Odm->LinkedInterval == 2)
6120                 {
6121                         // Mark out IQK flow to prevent tx stuck. by Maddest 20130306
6122                         // Open it verified by James 20130715
6123                         PHY_IQCalibrate_8821A(Adapter, FALSE);
6124                 }
6125         }
6126         else
6127                 pDM_Odm->LinkedInterval = 0;
6128 #endif
6129 }
6130
6131
6132 VOID
6133 odm_TXPowerTrackingInit(
6134         IN      PDM_ODM_T       pDM_Odm
6135         )
6136 {
6137         odm_TXPowerTrackingThermalMeterInit(pDM_Odm);
6138 }
6139
6140 u1Byte
6141 getSwingIndex(
6142         IN      PDM_ODM_T       pDM_Odm
6143         )
6144 {
6145         PADAPTER                Adapter = pDM_Odm->Adapter;
6146         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
6147         u1Byte                  i = 0;
6148         u4Byte                  bbSwing;
6149         u4Byte                  swingTableSize;
6150         pu4Byte                         pSwingTable;
6151
6152         if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723B ||
6153                 pDM_Odm->SupportICType == ODM_RTL8192E)
6154         {
6155                 bbSwing = PHY_QueryBBReg(Adapter, rOFDM0_XATxIQImbalance, 0xFFC00000);
6156
6157                 pSwingTable = OFDMSwingTable_New;
6158                 swingTableSize = OFDM_TABLE_SIZE;
6159         } else {
6160 #if ((RTL8812A_SUPPORT==1)||(RTL8821A_SUPPORT==1))
6161                 if (pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8821)
6162                 {
6163                         bbSwing = PHY_GetTxBBSwing_8812A(Adapter, pHalData->CurrentBandType, ODM_RF_PATH_A);
6164                         pSwingTable = TxScalingTable_Jaguar;
6165                         swingTableSize = TXSCALE_TABLE_SIZE;
6166                 }
6167                 else
6168 #endif
6169                 {
6170                         bbSwing = 0;
6171                         pSwingTable = OFDMSwingTable;
6172                         swingTableSize = OFDM_TABLE_SIZE;
6173                 }
6174         }
6175
6176         for (i = 0; i < swingTableSize; ++i) {
6177                 u4Byte tableValue = pSwingTable[i];
6178
6179                 if (tableValue >= 0x100000 )
6180                         tableValue >>= 22;
6181                 if (bbSwing == tableValue)
6182                         break;
6183         }
6184         return i;
6185 }
6186
6187 VOID
6188 odm_TXPowerTrackingThermalMeterInit(
6189         IN      PDM_ODM_T       pDM_Odm
6190         )
6191 {
6192         u1Byte defaultSwingIndex = getSwingIndex(pDM_Odm);
6193         u1Byte                  p = 0;
6194 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
6195         PADAPTER                Adapter = pDM_Odm->Adapter;
6196         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
6197
6198         #if     MP_DRIVER != 1                                  //for mp driver, turn off txpwrtracking as default
6199         pHalData->TxPowerTrackControl = TRUE;
6200         #endif
6201 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
6202         PADAPTER                        Adapter = pDM_Odm->Adapter;
6203         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
6204
6205
6206         if (pDM_Odm->SupportICType >= ODM_RTL8188E)
6207         {
6208                 pDM_Odm->RFCalibrateInfo.bTXPowerTracking = _TRUE;
6209                 pDM_Odm->RFCalibrateInfo.TXPowercount = 0;
6210                 pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = _FALSE;
6211                 //#if   (MP_DRIVER != 1)                //for mp driver, turn off txpwrtracking as default
6212                 if ( *(pDM_Odm->mp_mode) != 1)
6213                         pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE;
6214                 //#endif//#if   (MP_DRIVER != 1)
6215                 MSG_8192C("pDM_Odm TxPowerTrackControl = %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl);
6216         }
6217         else
6218         {
6219                 struct dm_priv  *pdmpriv = &pHalData->dmpriv;
6220
6221                 pdmpriv->bTXPowerTracking = _TRUE;
6222                 pdmpriv->TXPowercount = 0;
6223                 pdmpriv->bTXPowerTrackingInit = _FALSE;
6224                 //#if   (MP_DRIVER != 1)                //for mp driver, turn off txpwrtracking as default
6225
6226                 if (*(pDM_Odm->mp_mode) != 1)
6227                         pdmpriv->TxPowerTrackControl = _TRUE;
6228                 //#endif//#if   (MP_DRIVER != 1)
6229
6230                 //MSG_8192C("pdmpriv->TxPowerTrackControl = %d\n", pdmpriv->TxPowerTrackControl);
6231         }
6232
6233 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
6234         #ifdef RTL8188E_SUPPORT
6235         {
6236                 pDM_Odm->RFCalibrateInfo.bTXPowerTracking = _TRUE;
6237                 pDM_Odm->RFCalibrateInfo.TXPowercount = 0;
6238                 pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = _FALSE;
6239                 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE;
6240         }
6241         #endif
6242 #endif
6243
6244         pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = TRUE;
6245         pDM_Odm->RFCalibrateInfo.ThermalValue = pHalData->EEPROMThermalMeter;
6246         pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = pHalData->EEPROMThermalMeter;
6247         pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = pHalData->EEPROMThermalMeter;
6248
6249         // The index of "0 dB" in SwingTable.
6250         if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723B ||
6251                 pDM_Odm->SupportICType == ODM_RTL8192E)
6252         {
6253                 pDM_Odm->DefaultOfdmIndex = (defaultSwingIndex >= OFDM_TABLE_SIZE) ? 30 : defaultSwingIndex;
6254                 pDM_Odm->DefaultCckIndex = 20;
6255         }
6256         else
6257         {
6258                 pDM_Odm->DefaultOfdmIndex = (defaultSwingIndex >= TXSCALE_TABLE_SIZE) ? 24 : defaultSwingIndex;
6259                 pDM_Odm->DefaultCckIndex = 24;
6260         }
6261
6262         pDM_Odm->BbSwingIdxCckBase = pDM_Odm->DefaultCckIndex;
6263         pDM_Odm->RFCalibrateInfo.CCK_index = pDM_Odm->DefaultCckIndex;
6264
6265         for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p)
6266         {
6267                 pDM_Odm->BbSwingIdxOfdmBase[p] = pDM_Odm->DefaultOfdmIndex;
6268                 pDM_Odm->RFCalibrateInfo.OFDM_index[p] = pDM_Odm->DefaultOfdmIndex;
6269                 pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] = 0;
6270                 pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[p] = 0;
6271                 pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = 0;
6272         }
6273
6274 }
6275
6276
6277 VOID
6278 ODM_TXPowerTrackingCheck(
6279         IN              PDM_ODM_T               pDM_Odm
6280         )
6281 {
6282         //
6283         // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
6284         // at the same time. In the stage2/3, we need to prive universal interface and merge all
6285         // HW dynamic mechanism.
6286         //
6287         switch  (pDM_Odm->SupportPlatform)
6288         {
6289                 case    ODM_WIN:
6290                         odm_TXPowerTrackingCheckMP(pDM_Odm);
6291                         break;
6292
6293                 case    ODM_CE:
6294                         odm_TXPowerTrackingCheckCE(pDM_Odm);
6295                         break;
6296
6297                 case    ODM_AP:
6298                         odm_TXPowerTrackingCheckAP(pDM_Odm);
6299                         break;
6300
6301                 case    ODM_ADSL:
6302                         //odm_DIGAP(pDM_Odm);
6303                         break;
6304         }
6305
6306 }
6307
6308 VOID
6309 odm_TXPowerTrackingCheckCE(
6310         IN              PDM_ODM_T               pDM_Odm
6311         )
6312 {
6313 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
6314         PADAPTER        Adapter = pDM_Odm->Adapter;
6315         #if( (RTL8192C_SUPPORT==1) ||  (RTL8723A_SUPPORT==1) )
6316         if(IS_HARDWARE_TYPE_8192C(Adapter)){
6317                 rtl8192c_odm_CheckTXPowerTracking(Adapter);
6318                 return;
6319         }
6320         #endif
6321
6322         #if (RTL8192D_SUPPORT==1)
6323         if(IS_HARDWARE_TYPE_8192D(Adapter)){
6324                 #if (RTL8192D_EASY_SMART_CONCURRENT == 1)
6325                 if(!Adapter->bSlaveOfDMSP)
6326                 #endif
6327                         rtl8192d_odm_CheckTXPowerTracking(Adapter);
6328                 return;
6329         }
6330         #endif
6331
6332         #if(((RTL8188E_SUPPORT==1) ||  (RTL8812A_SUPPORT==1) ||  (RTL8821A_SUPPORT==1) ||  (RTL8192E_SUPPORT==1)  ||  (RTL8723B_SUPPORT==1)  ))
6333         if(!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK))
6334         {
6335                 return;
6336         }
6337
6338         if(!pDM_Odm->RFCalibrateInfo.TM_Trigger)                //at least delay 1 sec
6339         {
6340                 //pHalData->TxPowerCheckCnt++;  //cosa add for debug
6341                 if(IS_HARDWARE_TYPE_8188E(Adapter) || IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8192E(Adapter)||IS_HARDWARE_TYPE_8723B(Adapter))
6342                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_T_METER_NEW, (BIT17 | BIT16), 0x03);
6343                 else
6344                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_T_METER_OLD, bRFRegOffsetMask, 0x60);
6345
6346                 //DBG_871X("Trigger Thermal Meter!!\n");
6347
6348                 pDM_Odm->RFCalibrateInfo.TM_Trigger = 1;
6349                 return;
6350         }
6351         else
6352         {
6353                 //DBG_871X("Schedule TxPowerTracking direct call!!\n");
6354                 ODM_TXPowerTrackingCallback_ThermalMeter(Adapter);
6355                 pDM_Odm->RFCalibrateInfo.TM_Trigger = 0;
6356         }
6357         #endif
6358 #endif
6359 }
6360
6361 VOID
6362 odm_TXPowerTrackingCheckMP(
6363         IN              PDM_ODM_T               pDM_Odm
6364         )
6365 {
6366 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
6367         PADAPTER        Adapter = pDM_Odm->Adapter;
6368
6369         if (ODM_CheckPowerStatus(Adapter) == FALSE)
6370         {
6371                 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("===>ODM_CheckPowerStatus() return FALSE\n"));
6372                 return;
6373         }
6374
6375         if(IS_HARDWARE_TYPE_8723A(Adapter))
6376                 return;
6377
6378         if(!Adapter->bSlaveOfDMSP || Adapter->DualMacSmartConcurrent == FALSE)
6379                 odm_TXPowerTrackingThermalMeterCheck(Adapter);
6380         else {
6381                 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("!Adapter->bSlaveOfDMSP || Adapter->DualMacSmartConcurrent == FALSE\n"));
6382         }
6383 #endif
6384
6385 }
6386
6387
6388 VOID
6389 odm_TXPowerTrackingCheckAP(
6390         IN              PDM_ODM_T               pDM_Odm
6391         )
6392 {
6393 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
6394         prtl8192cd_priv priv            = pDM_Odm->priv;
6395
6396         if ( (priv->pmib->dot11RFEntry.ther) && ((priv->up_time % priv->pshare->rf_ft_var.tpt_period) == 0)){
6397 #ifdef CONFIG_RTL_92D_SUPPORT
6398                 if (GET_CHIP_VER(priv)==VERSION_8192D){
6399                         tx_power_tracking_92D(priv);
6400                 } else
6401 #endif
6402                 {
6403 #ifdef CONFIG_RTL_92C_SUPPORT
6404                         tx_power_tracking(priv);
6405 #endif
6406                 }
6407         }
6408 #endif
6409
6410 }
6411
6412
6413
6414 //antenna mapping info
6415 // 1: right-side antenna
6416 // 2/0: left-side antenna
6417 //PDM_SWAT_Table->CCK_Ant1_Cnt /OFDM_Ant1_Cnt:  for right-side antenna:   Ant:1    RxDefaultAnt1
6418 //PDM_SWAT_Table->CCK_Ant2_Cnt /OFDM_Ant2_Cnt:  for left-side antenna:     Ant:0    RxDefaultAnt2
6419 // We select left antenna as default antenna in initial process, modify it as needed
6420 //
6421
6422 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
6423
6424 VOID
6425 odm_TXPowerTrackingThermalMeterCheck(
6426         IN      PADAPTER                Adapter
6427         )
6428 {
6429 #ifndef AP_BUILD_WORKAROUND
6430         static u1Byte                   TM_Trigger = 0;
6431
6432         if(!(GET_HAL_DATA(Adapter)->DM_OutSrc.SupportAbility & ODM_RF_TX_PWR_TRACK))
6433         {
6434                 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
6435                         ("===>odm_TXPowerTrackingThermalMeterCheck(),pMgntInfo->bTXPowerTracking is FALSE, return!!\n"));
6436                 return;
6437         }
6438
6439         if(!TM_Trigger)         //at least delay 1 sec
6440         {
6441                 if(IS_HARDWARE_TYPE_8192D(Adapter))
6442                         PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER_92D, BIT17 | BIT16, 0x03);
6443                 else if(IS_HARDWARE_TYPE_8188E(Adapter) || IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8192E(Adapter) ||
6444                             IS_HARDWARE_TYPE_8723B(Adapter))
6445                         PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03);
6446                 else
6447                         PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60);
6448
6449                 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Trigger Thermal Meter!!\n"));
6450
6451                 TM_Trigger = 1;
6452                 return;
6453         }
6454         else
6455         {
6456                 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Schedule TxPowerTracking direct call!!\n"));
6457                 odm_TXPowerTrackingDirectCall(Adapter); //Using direct call is instead, added by Roger, 2009.06.18.
6458                 TM_Trigger = 0;
6459         }
6460 #endif
6461 }
6462
6463 // Only for 8723A SW ANT DIV INIT--2012--07--17
6464 VOID
6465 odm_SwAntDivInit_NIC_8723A(
6466         IN      PDM_ODM_T               pDM_Odm)
6467 {
6468         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
6469         PADAPTER                Adapter = pDM_Odm->Adapter;
6470
6471         u1Byte                  btAntNum=BT_GetPgAntNum(Adapter);
6472
6473         if(IS_HARDWARE_TYPE_8723A(Adapter))
6474         {
6475                 pDM_SWAT_Table->ANTA_ON =TRUE;
6476
6477                 // Set default antenna B status by PG
6478                 if(btAntNum == 2)
6479                         pDM_SWAT_Table->ANTB_ON = TRUE;
6480                 else if(btAntNum == 1)
6481                         pDM_SWAT_Table->ANTB_ON = FALSE;
6482                 else
6483                         pDM_SWAT_Table->ANTB_ON = TRUE;
6484         }
6485
6486 }
6487
6488 #endif //end #ifMP
6489
6490
6491
6492 //3============================================================
6493 //3 SW Antenna Diversity
6494 //3============================================================
6495 #if(defined(CONFIG_SW_ANTENNA_DIVERSITY))
6496 VOID
6497 odm_SwAntDivInit(
6498         IN              PDM_ODM_T               pDM_Odm
6499         )
6500 {
6501 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
6502         odm_SwAntDivInit_NIC(pDM_Odm);
6503 #elif(DM_ODM_SUPPORT_TYPE == ODM_AP)
6504         dm_SW_AntennaSwitchInit(pDM_Odm->priv);
6505 #endif
6506 }
6507
6508 VOID
6509 odm_SwAntDivInit_NIC(
6510         IN              PDM_ODM_T               pDM_Odm
6511         )
6512 {
6513         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
6514
6515
6516 // Init SW ANT DIV mechanism for 8723AE/AU/AS
6517 // Neil Chen--2012--07--17---
6518 // CE/AP/ADSL no using SW ANT DIV for 8723A Series IC
6519 //#if (DM_ODM_SUPPORT_TYPE==ODM_WIN)
6520 #if (RTL8723A_SUPPORT==1)
6521         if(pDM_Odm->SupportICType == ODM_RTL8723A)
6522         {
6523                 odm_SwAntDivInit_NIC_8723A(pDM_Odm);
6524         }
6525 #endif
6526         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS:Init SW Antenna Switch\n"));
6527         pDM_SWAT_Table->RSSI_sum_A = 0;
6528         pDM_SWAT_Table->RSSI_cnt_A = 0;
6529         pDM_SWAT_Table->RSSI_sum_B = 0;
6530         pDM_SWAT_Table->RSSI_cnt_B = 0;
6531         pDM_SWAT_Table->CurAntenna = MAIN_ANT;
6532         pDM_SWAT_Table->PreAntenna = MAIN_ANT;
6533         pDM_SWAT_Table->try_flag = 0xff;
6534         pDM_SWAT_Table->PreRSSI = 0;
6535         pDM_SWAT_Table->SWAS_NoLink_State = 0;
6536         pDM_SWAT_Table->bTriggerAntennaSwitch = 0;
6537         pDM_SWAT_Table->SelectAntennaMap=0xAA;
6538         pDM_SWAT_Table->lastTxOkCnt = 0;
6539         pDM_SWAT_Table->lastRxOkCnt = 0;
6540         pDM_SWAT_Table->TXByteCnt_A = 0;
6541         pDM_SWAT_Table->TXByteCnt_B = 0;
6542         pDM_SWAT_Table->RXByteCnt_A = 0;
6543         pDM_SWAT_Table->RXByteCnt_B = 0;
6544         pDM_SWAT_Table->TrafficLoad = TRAFFIC_LOW;
6545         pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ODM_Read4Byte(pDM_Odm, 0x860);
6546
6547 }
6548
6549 //
6550 // 20100514 Joseph:
6551 // Add new function to reset the state of antenna diversity before link.
6552 //
6553 VOID
6554 ODM_SwAntDivResetBeforeLink(
6555         IN              PDM_ODM_T               pDM_Odm
6556         )
6557 {
6558
6559         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
6560
6561         pDM_SWAT_Table->SWAS_NoLink_State = 0;
6562
6563 }
6564
6565 //
6566 // 20100514 Luke/Joseph:
6567 // Add new function to reset antenna diversity state after link.
6568 //
6569 VOID
6570 ODM_SwAntDivRestAfterLink(
6571         IN              PDM_ODM_T               pDM_Odm
6572         )
6573 {
6574         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
6575         pFAT_T          pDM_FatTable = &pDM_Odm->DM_FatTable;
6576         u4Byte             i;
6577
6578         if(pDM_Odm->SupportICType == ODM_RTL8723A)
6579         {
6580             pDM_SWAT_Table->RSSI_cnt_A = 0;
6581             pDM_SWAT_Table->RSSI_cnt_B = 0;
6582             pDM_Odm->RSSI_test = FALSE;
6583             pDM_SWAT_Table->try_flag = 0xff;
6584             pDM_SWAT_Table->RSSI_Trying = 0;
6585             pDM_SWAT_Table->SelectAntennaMap=0xAA;
6586
6587         }
6588         else if(pDM_Odm->SupportICType & (ODM_RTL8723B|ODM_RTL8821))
6589         {
6590                 pDM_Odm->RSSI_test = FALSE;
6591                 pDM_SWAT_Table->try_flag = 0xff;
6592                 pDM_SWAT_Table->RSSI_Trying = 0;
6593                 pDM_SWAT_Table->Double_chk_flag= 0;
6594
6595                 pDM_FatTable->RxIdleAnt=MAIN_ANT;
6596
6597                 for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
6598                 {
6599                         pDM_FatTable->MainAnt_Sum[i] = 0;
6600                         pDM_FatTable->AuxAnt_Sum[i] = 0;
6601                         pDM_FatTable->MainAnt_Cnt[i] = 0;
6602                         pDM_FatTable->AuxAnt_Cnt[i] = 0;
6603                 }
6604
6605         }
6606 }
6607
6608 void
6609 odm_SwAntDetectInit(
6610         IN              PDM_ODM_T               pDM_Odm
6611         )
6612 {
6613         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
6614 #if (RTL8723B_SUPPORT == 1)
6615         pDM_SWAT_Table->SWAS_NoLink_BK_Reg92c = ODM_Read4Byte(pDM_Odm, rDPDT_control);
6616 #endif
6617         pDM_SWAT_Table->PreAntenna = MAIN_ANT;
6618         pDM_SWAT_Table->CurAntenna = MAIN_ANT;
6619         pDM_SWAT_Table->SWAS_NoLink_State = 0;
6620 }
6621
6622 VOID
6623 ODM_SwAntDivChkPerPktRssi(
6624         IN PDM_ODM_T    pDM_Odm,
6625         IN u1Byte               StationID,
6626         IN PODM_PHY_INFO_T pPhyInfo
6627         )
6628 {
6629         SWAT_T          *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
6630
6631         if(!(pDM_Odm->SupportAbility & (ODM_BB_ANT_DIV)))
6632                 return;
6633
6634 // temporary Fix 8723A MP SW ANT DIV Bug --NeilChen--2012--07--11
6635 #if (DM_ODM_SUPPORT_TYPE==ODM_WIN)
6636         if(pDM_Odm->SupportICType == ODM_RTL8723A)
6637         {
6638                 //if(StationID == pDM_SWAT_Table->RSSI_target)
6639                 //{
6640                 //1 RSSI for SW Antenna Switch
6641                 if(pDM_SWAT_Table->CurAntenna == MAIN_ANT)
6642                 {
6643                         pDM_SWAT_Table->RSSI_sum_A += pPhyInfo->RxPWDBAll;
6644                         pDM_SWAT_Table->RSSI_cnt_A++;
6645                 }
6646                 else
6647                 {
6648                         pDM_SWAT_Table->RSSI_sum_B += pPhyInfo->RxPWDBAll;
6649                         pDM_SWAT_Table->RSSI_cnt_B++;
6650
6651                 }
6652                 //}
6653         }
6654         else
6655         {
6656                 if(StationID == pDM_SWAT_Table->RSSI_target)
6657                 {
6658                         //1 RSSI for SW Antenna Switch
6659                         if(pDM_SWAT_Table->CurAntenna == MAIN_ANT)
6660                         {
6661                                 pDM_SWAT_Table->RSSI_sum_A += pPhyInfo->RxPWDBAll;
6662                                 pDM_SWAT_Table->RSSI_cnt_A++;
6663                         }
6664                         else
6665                         {
6666                                 pDM_SWAT_Table->RSSI_sum_B += pPhyInfo->RxPWDBAll;
6667                                 pDM_SWAT_Table->RSSI_cnt_B++;
6668
6669                         }
6670                 }
6671         }
6672 #else
6673         if(StationID == pDM_SWAT_Table->RSSI_target)
6674         {
6675                 //1 RSSI for SW Antenna Switch
6676                 if(pDM_SWAT_Table->CurAntenna == MAIN_ANT)
6677                 {
6678                         pDM_SWAT_Table->RSSI_sum_A += pPhyInfo->RxPWDBAll;
6679                         pDM_SWAT_Table->RSSI_cnt_A++;
6680                 }
6681                 else
6682                 {
6683                         pDM_SWAT_Table->RSSI_sum_B += pPhyInfo->RxPWDBAll;
6684                         pDM_SWAT_Table->RSSI_cnt_B++;
6685
6686                 }
6687         }
6688 #endif
6689 }
6690
6691 //
6692 VOID
6693 odm_SwAntDivChkAntSwitch(
6694         IN              PDM_ODM_T               pDM_Odm,
6695         IN              u1Byte                  Step
6696         )
6697 {
6698         //
6699         // For AP/ADSL use prtl8192cd_priv
6700         // For CE/NIC use PADAPTER
6701         //
6702         prtl8192cd_priv priv            = pDM_Odm->priv;
6703
6704         //
6705         // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
6706         // at the same time. In the stage2/3, we need to prive universal interface and merge all
6707         // HW dynamic mechanism.
6708         //
6709         switch  (pDM_Odm->SupportPlatform)
6710         {
6711                 case    ODM_WIN:
6712                         odm_SwAntDivChkAntSwitchNIC(pDM_Odm, Step);
6713                         break;
6714                 case    ODM_CE:
6715                         odm_SwAntDivChkAntSwitchNIC(pDM_Odm, Step);
6716                         break;
6717
6718                 case    ODM_AP:
6719                 case    ODM_ADSL:
6720 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP |ODM_ADSL))
6721                         if (priv->pshare->rf_ft_var.antSw_enable && (priv->up_time % 4==1))
6722                                 dm_SW_AntennaSwitch(priv, SWAW_STEP_PEAK);
6723 #endif
6724                         break;
6725         }
6726
6727 }
6728
6729 //
6730 // 20100514 Luke/Joseph:
6731 // Add new function for antenna diversity after link.
6732 // This is the main function of antenna diversity after link.
6733 // This function is called in HalDmWatchDog() and ODM_SwAntDivChkAntSwitchCallback().
6734 // HalDmWatchDog() calls this function with SWAW_STEP_PEAK to initialize the antenna test.
6735 // In SWAW_STEP_PEAK, another antenna and a 500ms timer will be set for testing.
6736 // After 500ms, ODM_SwAntDivChkAntSwitchCallback() calls this function to compare the signal just
6737 // listened on the air with the RSSI of original antenna.
6738 // It chooses the antenna with better RSSI.
6739 // There is also a aged policy for error trying. Each error trying will cost more 5 seconds waiting
6740 // penalty to get next try.
6741
6742
6743 VOID
6744 ODM_SetAntenna(
6745         IN      PDM_ODM_T       pDM_Odm,
6746         IN      u1Byte          Antenna)
6747 {
6748         ODM_SetBBReg(pDM_Odm, 0x860, BIT8|BIT9, Antenna);
6749 }
6750
6751 VOID
6752 odm_SwAntDivChkAntSwitchNIC(
6753         IN              PDM_ODM_T               pDM_Odm,
6754         IN              u1Byte          Step
6755         )
6756 {
6757 #if ((RTL8192C_SUPPORT==1)||(RTL8723A_SUPPORT==1))
6758         //PMGNT_INFO            pMgntInfo = &(Adapter->MgntInfo);
6759         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
6760
6761 #if (DM_ODM_SUPPORT_TYPE==ODM_WIN)
6762         PADAPTER                Adapter=pDM_Odm->Adapter;
6763 #endif
6764
6765         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
6766         s4Byte                  curRSSI=100, RSSI_A, RSSI_B;
6767         u1Byte                  nextAntenna=AUX_ANT;
6768         //static u8Byte         lastTxOkCnt=0, lastRxOkCnt=0;
6769         u8Byte                  curTxOkCnt=0, curRxOkCnt=0;
6770         //static u8Byte         TXByteCnt_A=0, TXByteCnt_B=0, RXByteCnt_A=0, RXByteCnt_B=0;
6771         u8Byte                  CurByteCnt=0, PreByteCnt=0;
6772         //static u1Byte         TrafficLoad = TRAFFIC_LOW;
6773         u1Byte                  Score_A=0, Score_B=0;       //A: Main; B: AUX
6774         u1Byte                  i;
6775
6776         if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))
6777                 return;
6778
6779         if (pDM_Odm->SupportICType & (ODM_RTL8192D|ODM_RTL8188E))
6780                 return;
6781
6782         if((pDM_Odm->SupportICType == ODM_RTL8192C) &&(pDM_Odm->RFType == ODM_2T2R))
6783                 return;
6784
6785         if(pDM_Odm->SupportPlatform & ODM_WIN)
6786         {
6787                 if(*(pDM_Odm->pAntennaTest))
6788                         return;
6789         }
6790
6791         if((pDM_SWAT_Table->ANTA_ON == FALSE) ||(pDM_SWAT_Table->ANTB_ON == FALSE))
6792         {
6793                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
6794                                 ("odm_SwAntDivChkAntSwitch(): No AntDiv Mechanism, Antenna A or B is off\n"));
6795                 return;
6796         }
6797
6798         // Radio off: Status reset to default and return.
6799         if(*(pDM_Odm->pbPowerSaving)==TRUE) //pHalData->eRFPowerState==eRfOff
6800         {
6801                 ODM_SwAntDivRestAfterLink(pDM_Odm);
6802                 return;
6803         }
6804
6805
6806         // Handling step mismatch condition.
6807         // Peak step is not finished at last time. Recover the variable and check again.
6808         if(     Step != pDM_SWAT_Table->try_flag        )
6809         {
6810                 ODM_SwAntDivRestAfterLink(pDM_Odm);
6811         }
6812
6813 #if  (DM_ODM_SUPPORT_TYPE &( ODM_WIN| ODM_CE ))
6814
6815         if(pDM_SWAT_Table->try_flag == 0xff)
6816         {
6817                 pDM_SWAT_Table->RSSI_target = 0xff;
6818
6819                 #if(DM_ODM_SUPPORT_TYPE & ODM_CE)
6820                 {
6821                         u1Byte                  index = 0;
6822                         PSTA_INFO_T             pEntry = NULL;
6823
6824
6825                         for(index=0; index<ODM_ASSOCIATE_ENTRY_NUM; index++)
6826                         {
6827                                 pEntry =  pDM_Odm->pODM_StaInfo[index];
6828                                 if(IS_STA_VALID(pEntry) ) {
6829                                         break;
6830                                 }
6831                         }
6832                         if(pEntry == NULL)
6833                         {
6834                                 ODM_SwAntDivRestAfterLink(pDM_Odm);
6835                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): No Link.\n"));
6836                                 return;
6837                         }
6838                         else
6839                         {
6840                                 pDM_SWAT_Table->RSSI_target = index;
6841                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): RSSI_target is PEER STA\n"));
6842                         }
6843                 }
6844                 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
6845                 {
6846                         PADAPTER        pAdapter         =  pDM_Odm->Adapter;
6847                         PMGNT_INFO      pMgntInfo=&pAdapter->MgntInfo;
6848
6849                         // Select RSSI checking target
6850                         if(pMgntInfo->mAssoc && !ACTING_AS_AP(pAdapter))
6851                         {
6852                                 // Target: Infrastructure mode AP.
6853                                 //pDM_SWAT_Table->RSSI_target = NULL;
6854                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("odm_SwAntDivChkAntSwitch(): RSSI_target is DEF AP!\n"));
6855                         }
6856                         else
6857                         {
6858                                 u1Byte                  index = 0;
6859                                 PSTA_INFO_T             pEntry = NULL;
6860                                 PADAPTER                pTargetAdapter = NULL;
6861
6862                                 if(pMgntInfo->mIbss )
6863                                 {
6864                                         // Target: AP/IBSS peer.
6865                                         pTargetAdapter = pAdapter;
6866                                 }
6867                                 else
6868                                 {
6869                                         pTargetAdapter = GetFirstAPAdapter(pAdapter);
6870                                 }
6871
6872                                 if(pTargetAdapter != NULL)
6873                                 {
6874                                         for(index=0; index<ODM_ASSOCIATE_ENTRY_NUM; index++)
6875                                         {
6876
6877                                                 pEntry = AsocEntry_EnumStation(pTargetAdapter, index);
6878                                                 if(pEntry != NULL)
6879                                                 {
6880                                                         if(pEntry->bAssociated)
6881                                                                 break;
6882                                                 }
6883
6884                                         }
6885
6886                                 }
6887
6888                                 if(pEntry == NULL)
6889                                 {
6890                                         ODM_SwAntDivRestAfterLink(pDM_Odm);
6891                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): No Link.\n"));
6892                                         return;
6893                                 }
6894                                 else
6895                                 {
6896                                         //pDM_SWAT_Table->RSSI_target = pEntry;
6897                                         pDM_SWAT_Table->RSSI_target = index;
6898                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): RSSI_target is PEER STA\n"));
6899                                 }
6900                         }//end if(pMgntInfo->mAssoc && !ACTING_AS_AP(Adapter))
6901
6902                 }
6903                 #endif
6904
6905                 pDM_SWAT_Table->RSSI_cnt_A = 0;
6906                 pDM_SWAT_Table->RSSI_cnt_B = 0;
6907                 pDM_SWAT_Table->try_flag = 0;
6908                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("odm_SwAntDivChkAntSwitch(): Set try_flag to 0 prepare for peak!\n"));
6909                 return;
6910         }
6911         else
6912         {
6913
6914 // To Fix 8723A SW ANT DIV Bug issue
6915 #if (DM_ODM_SUPPORT_TYPE==ODM_WIN)
6916                 if (pDM_Odm->SupportICType & ODM_RTL8723A)
6917                 {
6918                         curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - pDM_SWAT_Table->lastTxOkCnt;
6919                         curRxOkCnt =Adapter->RxStats.NumRxBytesUnicast - pDM_SWAT_Table->lastRxOkCnt;
6920                         pDM_SWAT_Table->lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast;
6921                         pDM_SWAT_Table->lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast;
6922                 }
6923 #else
6924                 curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - pDM_SWAT_Table->lastTxOkCnt;
6925                 curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - pDM_SWAT_Table->lastRxOkCnt;
6926                 pDM_SWAT_Table->lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast);
6927                 pDM_SWAT_Table->lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast);
6928 #endif
6929                 if(pDM_SWAT_Table->try_flag == 1)
6930                 {
6931                         if(pDM_SWAT_Table->CurAntenna == MAIN_ANT)
6932                         {
6933                                 pDM_SWAT_Table->TXByteCnt_A += curTxOkCnt;
6934                                 pDM_SWAT_Table->RXByteCnt_A += curRxOkCnt;
6935                         }
6936                         else
6937                         {
6938                                 pDM_SWAT_Table->TXByteCnt_B += curTxOkCnt;
6939                                 pDM_SWAT_Table->RXByteCnt_B += curRxOkCnt;
6940                         }
6941
6942                         nextAntenna = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? AUX_ANT : MAIN_ANT;
6943                         pDM_SWAT_Table->RSSI_Trying--;
6944                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("RSSI_Trying = %d\n",pDM_SWAT_Table->RSSI_Trying));
6945                         if(pDM_SWAT_Table->RSSI_Trying == 0)
6946                         {
6947                                 CurByteCnt = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? (pDM_SWAT_Table->TXByteCnt_A+pDM_SWAT_Table->RXByteCnt_A) : (pDM_SWAT_Table->TXByteCnt_B+pDM_SWAT_Table->RXByteCnt_B);
6948                                 PreByteCnt = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? (pDM_SWAT_Table->TXByteCnt_B+pDM_SWAT_Table->RXByteCnt_B) : (pDM_SWAT_Table->TXByteCnt_A+pDM_SWAT_Table->RXByteCnt_A);
6949
6950                                 if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH)
6951                                         //CurByteCnt = PlatformDivision64(CurByteCnt, 9);
6952                                         PreByteCnt = PreByteCnt*9;
6953                                 else if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_LOW)
6954                                         //CurByteCnt = PlatformDivision64(CurByteCnt, 2);
6955                                         PreByteCnt = PreByteCnt*2;
6956
6957                                 if(pDM_SWAT_Table->RSSI_cnt_A > 0)
6958                                         RSSI_A = pDM_SWAT_Table->RSSI_sum_A/pDM_SWAT_Table->RSSI_cnt_A;
6959                                 else
6960                                         RSSI_A = 0;
6961                                 if(pDM_SWAT_Table->RSSI_cnt_B > 0)
6962                                         RSSI_B = pDM_SWAT_Table->RSSI_sum_B/pDM_SWAT_Table->RSSI_cnt_B;
6963                                 else
6964                                         RSSI_B = 0;
6965                                 curRSSI = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? RSSI_A : RSSI_B;
6966                                 pDM_SWAT_Table->PreRSSI =  (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? RSSI_B : RSSI_A;
6967                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Luke:PreRSSI = %d, CurRSSI = %d\n",pDM_SWAT_Table->PreRSSI, curRSSI));
6968                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: preAntenna= %s, curAntenna= %s \n",
6969                                 (pDM_SWAT_Table->PreAntenna == MAIN_ANT?"MAIN":"AUX"), (pDM_SWAT_Table->CurAntenna == MAIN_ANT?"MAIN":"AUX")));
6970                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Luke:RSSI_A= %d, RSSI_cnt_A = %d, RSSI_B= %d, RSSI_cnt_B = %d\n",
6971                                         RSSI_A, pDM_SWAT_Table->RSSI_cnt_A, RSSI_B, pDM_SWAT_Table->RSSI_cnt_B));
6972                         }
6973
6974                 }
6975                 else
6976                 {
6977
6978                         if(pDM_SWAT_Table->RSSI_cnt_A > 0)
6979                                 RSSI_A = pDM_SWAT_Table->RSSI_sum_A/pDM_SWAT_Table->RSSI_cnt_A;
6980                         else
6981                                 RSSI_A = 0;
6982                         if(pDM_SWAT_Table->RSSI_cnt_B > 0)
6983                                 RSSI_B = pDM_SWAT_Table->RSSI_sum_B/pDM_SWAT_Table->RSSI_cnt_B;
6984                         else
6985                                 RSSI_B = 0;
6986                         curRSSI = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? RSSI_A : RSSI_B;
6987                         pDM_SWAT_Table->PreRSSI =  (pDM_SWAT_Table->PreAntenna == MAIN_ANT)? RSSI_A : RSSI_B;
6988                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ekul:PreRSSI = %d, CurRSSI = %d\n", pDM_SWAT_Table->PreRSSI, curRSSI));
6989                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: preAntenna= %s, curAntenna= %s \n",
6990                         (pDM_SWAT_Table->PreAntenna == MAIN_ANT?"MAIN":"AUX"), (pDM_SWAT_Table->CurAntenna == MAIN_ANT?"MAIN":"AUX")));
6991
6992                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ekul:RSSI_A= %d, RSSI_cnt_A = %d, RSSI_B= %d, RSSI_cnt_B = %d\n",
6993                                 RSSI_A, pDM_SWAT_Table->RSSI_cnt_A, RSSI_B, pDM_SWAT_Table->RSSI_cnt_B));
6994                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Ekul:curTxOkCnt = %d\n", curTxOkCnt));
6995                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Ekul:curRxOkCnt = %d\n", curRxOkCnt));
6996                 }
6997
6998                 //1 Trying State
6999                 if((pDM_SWAT_Table->try_flag == 1)&&(pDM_SWAT_Table->RSSI_Trying == 0))
7000                 {
7001
7002                         if(pDM_SWAT_Table->TestMode == TP_MODE)
7003                         {
7004                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: TestMode = TP_MODE"));
7005                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TRY:CurByteCnt = %lld,", CurByteCnt));
7006                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TRY:PreByteCnt = %lld\n",PreByteCnt));
7007                                 if(CurByteCnt < PreByteCnt)
7008                                 {
7009                                         if(pDM_SWAT_Table->CurAntenna == MAIN_ANT)
7010                                                 pDM_SWAT_Table->SelectAntennaMap=pDM_SWAT_Table->SelectAntennaMap<<1;
7011                                         else
7012                                                 pDM_SWAT_Table->SelectAntennaMap=(pDM_SWAT_Table->SelectAntennaMap<<1)+1;
7013                                 }
7014                                 else
7015                                 {
7016                                         if(pDM_SWAT_Table->CurAntenna == MAIN_ANT)
7017                                                 pDM_SWAT_Table->SelectAntennaMap=(pDM_SWAT_Table->SelectAntennaMap<<1)+1;
7018                                         else
7019                                                 pDM_SWAT_Table->SelectAntennaMap=pDM_SWAT_Table->SelectAntennaMap<<1;
7020                                 }
7021                                 for (i= 0; i<8; i++)
7022                                 {
7023                                         if(((pDM_SWAT_Table->SelectAntennaMap>>i)&BIT0) == 1)
7024                                                 Score_A++;
7025                                         else
7026                                                 Score_B++;
7027                                 }
7028                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SelectAntennaMap=%x\n ",pDM_SWAT_Table->SelectAntennaMap));
7029                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Score_A=%d, Score_B=%d\n", Score_A, Score_B));
7030
7031                                 if(pDM_SWAT_Table->CurAntenna == MAIN_ANT)
7032                                 {
7033                                         nextAntenna = (Score_A > Score_B)?MAIN_ANT:AUX_ANT;
7034                                 }
7035                                 else
7036                                 {
7037                                         nextAntenna = (Score_B > Score_A)?AUX_ANT:MAIN_ANT;
7038                                 }
7039                                 //RT_TRACE(COMP_SWAS, DBG_LOUD, ("nextAntenna=%s\n",(nextAntenna==Antenna_A)?"A":"B"));
7040                                 //RT_TRACE(COMP_SWAS, DBG_LOUD, ("preAntenna= %s, curAntenna= %s \n",
7041                                 //(DM_SWAT_Table.PreAntenna == Antenna_A?"A":"B"), (DM_SWAT_Table.CurAntenna == Antenna_A?"A":"B")));
7042
7043                                 if(nextAntenna != pDM_SWAT_Table->CurAntenna)
7044                                 {
7045                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: Switch back to another antenna"));
7046                                 }
7047                                 else
7048                                 {
7049                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: current anntena is good\n"));
7050                                 }
7051                         }
7052
7053                         if(pDM_SWAT_Table->TestMode == RSSI_MODE)
7054                         {
7055                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: TestMode = RSSI_MODE"));
7056                                 pDM_SWAT_Table->SelectAntennaMap=0xAA;
7057                                 if(curRSSI < pDM_SWAT_Table->PreRSSI) //Current antenna is worse than previous antenna
7058                                 {
7059                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: Switch back to another antenna"));
7060                                         nextAntenna = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? AUX_ANT : MAIN_ANT;
7061                                 }
7062                                 else // current anntena is good
7063                                 {
7064                                         nextAntenna =pDM_SWAT_Table->CurAntenna;
7065                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: current anntena is good\n"));
7066                                 }
7067                         }
7068                         pDM_SWAT_Table->try_flag = 0;
7069                         pDM_Odm->RSSI_test = FALSE;
7070                         pDM_SWAT_Table->RSSI_sum_A = 0;
7071                         pDM_SWAT_Table->RSSI_cnt_A = 0;
7072                         pDM_SWAT_Table->RSSI_sum_B = 0;
7073                         pDM_SWAT_Table->RSSI_cnt_B = 0;
7074                         pDM_SWAT_Table->TXByteCnt_A = 0;
7075                         pDM_SWAT_Table->TXByteCnt_B = 0;
7076                         pDM_SWAT_Table->RXByteCnt_A = 0;
7077                         pDM_SWAT_Table->RXByteCnt_B = 0;
7078
7079                 }
7080
7081                 //1 Normal State
7082                 else if(pDM_SWAT_Table->try_flag == 0)
7083                 {
7084                         if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH)
7085                         {
7086                                 if ((curTxOkCnt+curRxOkCnt) > 3750000)//if(PlatformDivision64(curTxOkCnt+curRxOkCnt, 2) > 1875000)
7087                                         pDM_SWAT_Table->TrafficLoad = TRAFFIC_HIGH;
7088                                 else
7089                                         pDM_SWAT_Table->TrafficLoad = TRAFFIC_LOW;
7090                         }
7091                         else if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_LOW)
7092                                 {
7093                                 if ((curTxOkCnt+curRxOkCnt) > 3750000) //if(PlatformDivision64(curTxOkCnt+curRxOkCnt, 2) > 1875000)
7094                                         pDM_SWAT_Table->TrafficLoad = TRAFFIC_HIGH;
7095                                 else
7096                                         pDM_SWAT_Table->TrafficLoad = TRAFFIC_LOW;
7097                         }
7098                         if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH)
7099                                 pDM_SWAT_Table->bTriggerAntennaSwitch = 0;
7100                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Normal:TrafficLoad = %llu\n", curTxOkCnt+curRxOkCnt));
7101
7102                         //Prepare To Try Antenna
7103                                         nextAntenna = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? AUX_ANT : MAIN_ANT;
7104                                         pDM_SWAT_Table->try_flag = 1;
7105                                         pDM_Odm->RSSI_test = TRUE;
7106                         if((curRxOkCnt+curTxOkCnt) > 1000)
7107                         {
7108                                 pDM_SWAT_Table->RSSI_Trying = 4;
7109                                 pDM_SWAT_Table->TestMode = TP_MODE;
7110                                 }
7111                                 else
7112                                 {
7113                                 pDM_SWAT_Table->RSSI_Trying = 2;
7114                                 pDM_SWAT_Table->TestMode = RSSI_MODE;
7115
7116                         }
7117                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: Normal State -> Begin Trying!\n"));
7118
7119
7120                         pDM_SWAT_Table->RSSI_sum_A = 0;
7121                         pDM_SWAT_Table->RSSI_cnt_A = 0;
7122                         pDM_SWAT_Table->RSSI_sum_B = 0;
7123                         pDM_SWAT_Table->RSSI_cnt_B = 0;
7124                 }
7125         }
7126
7127         //1 4.Change TRX antenna
7128         if(nextAntenna != pDM_SWAT_Table->CurAntenna)
7129         {
7130                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: Change TX Antenna!\n "));
7131                 //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, nextAntenna);
7132                 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
7133                 ODM_SetAntenna(pDM_Odm,nextAntenna);
7134                 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
7135                 {
7136                         BOOLEAN bEnqueue;
7137                         bEnqueue = (pDM_Odm->SupportInterface ==  ODM_ITRF_PCIE)?FALSE :TRUE;
7138                         rtw_antenna_select_cmd(pDM_Odm->Adapter, nextAntenna, bEnqueue);
7139                 }
7140                 #endif
7141
7142         }
7143
7144         //1 5.Reset Statistics
7145         pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna;
7146         pDM_SWAT_Table->CurAntenna = nextAntenna;
7147         pDM_SWAT_Table->PreRSSI = curRSSI;
7148
7149         //1 6.Set next timer
7150         {
7151                 //PADAPTER              pAdapter = pDM_Odm->Adapter;
7152                 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
7153
7154
7155         if(pDM_SWAT_Table->RSSI_Trying == 0)
7156                 return;
7157
7158         if(pDM_SWAT_Table->RSSI_Trying%2 == 0)
7159         {
7160                 if(pDM_SWAT_Table->TestMode == TP_MODE)
7161                 {
7162                         if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH)
7163                         {
7164                                 ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 10 ); //ms
7165
7166                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_SW_AntennaSwitch(): Test another antenna for 10 ms\n"));
7167                         }
7168                         else if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_LOW)
7169                         {
7170                                 ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 50 ); //ms
7171                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_SW_AntennaSwitch(): Test another antenna for 50 ms\n"));
7172                         }
7173                 }
7174                 else
7175                 {
7176                         ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 500 ); //ms
7177                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_SW_AntennaSwitch(): Test another antenna for 500 ms\n"));
7178                 }
7179         }
7180         else
7181         {
7182                 if(pDM_SWAT_Table->TestMode == TP_MODE)
7183                 {
7184                         if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH)
7185                                 ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 90 ); //ms
7186                         else if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_LOW)
7187                                 ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 100 ); //ms
7188                 }
7189                 else
7190                         ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 500 ); //ms
7191         }
7192         }
7193 #endif  // #if (DM_ODM_SUPPORT_TYPE  & (ODM_WIN|ODM_CE))
7194 #endif  // #if (RTL8192C_SUPPORT==1)
7195 }
7196
7197
7198 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
7199
7200 u1Byte
7201 odm_SwAntDivSelectScanChnl(
7202         IN      PADAPTER        Adapter
7203         )
7204 {
7205 #if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM)
7206         PHAL_DATA_TYPE          pHalData = GET_HAL_DATA(Adapter);
7207         PMGNT_INFO                      pMgntInfo = &(Adapter->MgntInfo);
7208         PDM_ODM_T                       pDM_Odm = &pHalData->DM_OutSrc;
7209         u1Byte                          i, j, ScanChannel = 0, ChannelNum = 0;
7210         PRT_CHANNEL_LIST        pChannelList = GET_RT_CHANNEL_LIST(pMgntInfo);
7211         u1Byte                          EachChannelSTAs[MAX_SCAN_CHANNEL_NUM] = {0};
7212
7213         if(pMgntInfo->tmpNumBssDesc == 0)
7214                 return 0;
7215
7216         for(i = 0; i < pMgntInfo->tmpNumBssDesc; i++)
7217         {
7218                 ChannelNum = pMgntInfo->tmpbssDesc[i].ChannelNumber;
7219                 for(j = 0; j < pChannelList->ChannelLen; j++)
7220                 {
7221                         if(pChannelList->ChnlListEntry[j].ChannelNum == ChannelNum)
7222                         {
7223                                 EachChannelSTAs[j]++;
7224                                 break;
7225                         }
7226                 }
7227         }
7228
7229         for(i = 0; i < MAX_SCAN_CHANNEL_NUM; i++)
7230                 {
7231                 if(EachChannelSTAs[i] > EachChannelSTAs[ScanChannel])
7232                         ScanChannel = i;
7233                 }
7234
7235         if(EachChannelSTAs[ScanChannel] == 0)
7236         {
7237                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("odm_SwAntDivSelectScanChnl(): Scan List is empty.\n"));
7238                 return 0;
7239         }
7240
7241         ScanChannel = pChannelList->ChnlListEntry[ScanChannel].ChannelNum;
7242
7243
7244
7245         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD,
7246                 ("odm_SwAntDivSelectScanChnl(): Channel %d is select as scan channel.\n", ScanChannel));
7247
7248         return ScanChannel;
7249 #else
7250         return  0;
7251 #endif
7252 }
7253
7254
7255 VOID
7256 odm_SwAntDivConstructScanChnl(
7257         IN      PADAPTER        Adapter,
7258         IN      u1Byte          ScanChnl
7259         )
7260 {
7261
7262         PMGNT_INFO                      pMgntInfo = &Adapter->MgntInfo;
7263
7264         if(ScanChnl == 0)
7265         {
7266                 u1Byte                          i;
7267                 PRT_CHANNEL_LIST        pChannelList = GET_RT_CHANNEL_LIST(pMgntInfo);
7268
7269                 // 20100519 Joseph: Original antenna scanned nothing.
7270                 // Test antenna shall scan all channel with half period in this condition.
7271                 RtActChannelList(Adapter, RT_CHNL_LIST_ACTION_CONSTRUCT_SCAN_LIST, NULL, NULL);
7272                 for(i = 0; i < pChannelList->ChannelLen; i++)
7273                         pChannelList->ChnlListEntry[i].ScanPeriod /= 2;
7274         }
7275         else
7276         {
7277                 // The using of this CustomizedScanRequest is a trick to rescan the two channels
7278                 //      under the NORMAL scanning process. It will not affect MGNT_INFO.CustomizedScanRequest.
7279                 CUSTOMIZED_SCAN_REQUEST CustomScanReq;
7280
7281                 CustomScanReq.bEnabled = TRUE;
7282                 CustomScanReq.Channels[0] = ScanChnl;
7283                 CustomScanReq.Channels[1] = pMgntInfo->dot11CurrentChannelNumber;
7284                 CustomScanReq.nChannels = 2;
7285                 CustomScanReq.ScanType = SCAN_ACTIVE;
7286                 CustomScanReq.Duration = DEFAULT_PASSIVE_SCAN_PERIOD;
7287
7288                 RtActChannelList(Adapter, RT_CHNL_LIST_ACTION_CONSTRUCT_SCAN_LIST, &CustomScanReq, NULL);
7289         }
7290
7291 }
7292 #endif //#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
7293
7294 //
7295 // 20100514 Luke/Joseph:
7296 // Callback function for 500ms antenna test trying.
7297 //
7298 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
7299 VOID
7300 odm_SwAntDivChkAntSwitchCallback(
7301         PRT_TIMER               pTimer
7302 )
7303 {
7304         PADAPTER                Adapter = (PADAPTER)pTimer->Adapter;
7305         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
7306         pSWAT_T         pDM_SWAT_Table = &pHalData->DM_OutSrc.DM_SWAT_Table;
7307
7308         #if DEV_BUS_TYPE==RT_PCI_INTERFACE
7309         #if USE_WORKITEM
7310         ODM_ScheduleWorkItem(&pDM_SWAT_Table->SwAntennaSwitchWorkitem);
7311         #else
7312         odm_SwAntDivChkAntSwitch(&pHalData->DM_OutSrc, SWAW_STEP_DETERMINE);
7313         #endif
7314         #else
7315         ODM_ScheduleWorkItem(&pDM_SWAT_Table->SwAntennaSwitchWorkitem);
7316         #endif
7317
7318 }
7319 VOID
7320 odm_SwAntDivChkAntSwitchWorkitemCallback(
7321     IN PVOID            pContext
7322     )
7323 {
7324
7325         PADAPTER                pAdapter = (PADAPTER)pContext;
7326         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
7327
7328         odm_SwAntDivChkAntSwitch(&pHalData->DM_OutSrc, SWAW_STEP_DETERMINE);
7329
7330 }
7331 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
7332 VOID odm_SwAntDivChkAntSwitchCallback(void *FunctionContext)
7333 {
7334         PDM_ODM_T       pDM_Odm= (PDM_ODM_T)FunctionContext;
7335         PADAPTER        padapter = pDM_Odm->Adapter;
7336         if(padapter->net_closed == _TRUE)
7337             return;
7338         odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_DETERMINE);
7339 }
7340 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
7341 VOID odm_SwAntDivChkAntSwitchCallback(void *FunctionContext)
7342 {
7343         PDM_ODM_T       pDM_Odm= (PDM_ODM_T)FunctionContext;
7344         odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_DETERMINE);
7345 }
7346 #endif
7347
7348 #else //#if(defined(CONFIG_SW_ANTENNA_DIVERSITY))
7349
7350 VOID odm_SwAntDivInit(  IN              PDM_ODM_T               pDM_Odm ) {}
7351 VOID ODM_SwAntDivChkPerPktRssi(
7352         IN PDM_ODM_T    pDM_Odm,
7353         IN u1Byte               StationID,
7354         IN PODM_PHY_INFO_T pPhyInfo
7355         ) {}
7356 VOID odm_SwAntDivChkAntSwitch(
7357         IN              PDM_ODM_T               pDM_Odm,
7358         IN              u1Byte                  Step
7359         ) {}
7360 VOID ODM_SwAntDivResetBeforeLink(       IN              PDM_ODM_T               pDM_Odm ){}
7361 VOID ODM_SwAntDivRestAfterLink( IN              PDM_ODM_T               pDM_Odm ){}
7362 VOID odm_SwAntDetectInit(       IN              PDM_ODM_T               pDM_Odm){}
7363 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
7364 VOID odm_SwAntDivChkAntSwitchCallback(  PRT_TIMER               pTimer){}
7365 VOID odm_SwAntDivChkAntSwitchWorkitemCallback(    IN PVOID            pContext    ){}
7366 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
7367 VOID odm_SwAntDivChkAntSwitchCallback(void *FunctionContext){}
7368 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
7369 VOID odm_SwAntDivChkAntSwitchCallback(void *FunctionContext){}
7370 #endif
7371
7372 #endif //#if(defined(CONFIG_SW_ANTENNA_DIVERSITY))
7373
7374
7375
7376 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
7377 BOOLEAN
7378 ODM_SwAntDivCheckBeforeLink(
7379         IN              PDM_ODM_T               pDM_Odm
7380         )
7381 {
7382
7383 #if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM)
7384
7385         PADAPTER                Adapter = pDM_Odm->Adapter;
7386         HAL_DATA_TYPE*  pHalData = GET_HAL_DATA(Adapter);
7387         PMGNT_INFO              pMgntInfo = &Adapter->MgntInfo;
7388         pSWAT_T                 pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
7389         pFAT_T  pDM_FatTable = &pDM_Odm->DM_FatTable;
7390         s1Byte                  Score = 0;
7391         PRT_WLAN_BSS    pTmpBssDesc, pTestBssDesc;
7392         s4Byte                  power_diff = 0, power_target = 10;
7393         u1Byte                  index, counter = 0;
7394         static u1Byte           ScanChannel;
7395         u8Byte                  tStamp_diff = 0;
7396
7397
7398         if (pDM_Odm->Adapter == NULL)  //For BSOD when plug/unplug fast.  //By YJ,120413
7399         {       // The ODM structure is not initialized.
7400                 return FALSE;
7401         }
7402
7403         // Retrieve antenna detection registry info, added by Roger, 2012.11.27.
7404         if(!IS_ANT_DETECT_SUPPORT_RSSI(Adapter))
7405                         return FALSE;
7406
7407         // Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF.
7408         PlatformAcquireSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
7409         if(pHalData->eRFPowerState!=eRfOn || pMgntInfo->RFChangeInProgress || pMgntInfo->bMediaConnect)
7410         {
7411                 PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
7412
7413                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
7414                                 ("ODM_SwAntDivCheckBeforeLink(): RFChangeInProgress(%x), eRFPowerState(%x)\n",
7415                                 pMgntInfo->RFChangeInProgress, pHalData->eRFPowerState));
7416
7417                 pDM_SWAT_Table->SWAS_NoLink_State = 0;
7418
7419                 return FALSE;
7420         }
7421         else
7422         {
7423                 PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
7424         }
7425         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("pDM_SWAT_Table->SWAS_NoLink_State = %d\n", pDM_SWAT_Table->SWAS_NoLink_State));
7426         //1 Run AntDiv mechanism "Before Link" part.
7427         if(pDM_SWAT_Table->SWAS_NoLink_State == 0)
7428         {
7429                 //1 Prepare to do Scan again to check current antenna state.
7430
7431                 // Set check state to next step.
7432                 pDM_SWAT_Table->SWAS_NoLink_State = 1;
7433
7434                 // Copy Current Scan list.
7435                 pMgntInfo->tmpNumBssDesc = pMgntInfo->NumBssDesc;
7436                 PlatformMoveMemory((PVOID)Adapter->MgntInfo.tmpbssDesc, (PVOID)pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC);
7437
7438                 // Go back to scan function again.
7439                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Scan one more time\n"));
7440                 pMgntInfo->ScanStep=0;
7441                 pMgntInfo->bScanAntDetect = TRUE;
7442                 ScanChannel = odm_SwAntDivSelectScanChnl(Adapter);
7443
7444
7445                 if(pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8821))
7446                 {
7447                         if(pDM_FatTable->RxIdleAnt == MAIN_ANT)
7448                                 ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);
7449                         else
7450                                 ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);
7451                         if(ScanChannel == 0)
7452                         {
7453                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
7454                                         ("ODM_SwAntDivCheckBeforeLink(): No AP List Avaiable, Using Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"AUX_ANT":"MAIN_ANT"));
7455
7456                                 if(IS_5G_WIRELESS_MODE(pMgntInfo->dot11CurrentWirelessMode))
7457                                 {
7458                                         pDM_SWAT_Table->Ant5G = pDM_FatTable->RxIdleAnt;
7459                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant5G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
7460                                 }
7461                                 else
7462                                 {
7463                                         pDM_SWAT_Table->Ant2G = pDM_FatTable->RxIdleAnt;
7464                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant2G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
7465                                 }
7466                                 return FALSE;
7467                         }
7468
7469                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
7470                                 ("ODM_SwAntDivCheckBeforeLink: Change to %s for testing.\n", ((pDM_FatTable->RxIdleAnt == MAIN_ANT)?"MAIN_ANT":"AUX_ANT")));
7471                 }
7472                 else if(pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8723B))
7473                 {
7474                         // Switch Antenna to another one.
7475                         pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna;
7476                         pDM_SWAT_Table->CurAntenna = (pDM_SWAT_Table->CurAntenna==MAIN_ANT)?AUX_ANT:MAIN_ANT;
7477
7478                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
7479                                 ("ODM_SwAntDivCheckBeforeLink: Change to Ant(%s) for testing.\n", (pDM_SWAT_Table->CurAntenna==MAIN_ANT)?"MAIN":"AUX"));
7480                         //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, DM_SWAT_Table.CurAntenna);
7481                         if(pDM_Odm->SupportICType == ODM_RTL8192C)
7482                         {
7483                                 pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 & 0xfffffcff) | (pDM_SWAT_Table->CurAntenna<<8));
7484                                 ODM_SetBBReg(pDM_Odm,  rFPGA0_XA_RFInterfaceOE, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg860);
7485                         }
7486                         else if(pDM_Odm->SupportICType == ODM_RTL8723B)
7487                         {
7488                                 pDM_SWAT_Table->SWAS_NoLink_BK_Reg92c = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg92c & 0xfffffffc) | (pDM_SWAT_Table->CurAntenna));
7489                                 ODM_SetBBReg(pDM_Odm,  rfe_ctrl_anta_src, 0xff, 0x77);
7490                                 ODM_SetBBReg(pDM_Odm,  rDPDT_control, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg92c);
7491                         }
7492                 }
7493
7494                 odm_SwAntDivConstructScanChnl(Adapter, ScanChannel);
7495                 PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5);
7496
7497                 return TRUE;
7498         }
7499         else
7500         {
7501                 //1 ScanComple() is called after antenna swiched.
7502                 //1 Check scan result and determine which antenna is going
7503                 //1 to be used.
7504
7505                 for(index = 0; index < pMgntInfo->tmpNumBssDesc; index++)
7506                 {
7507                         pTmpBssDesc = &(pMgntInfo->tmpbssDesc[index]); // Antenna 1
7508                         pTestBssDesc = &(pMgntInfo->bssDesc[index]); // Antenna 2
7509
7510                         if(PlatformCompareMemory(pTestBssDesc->bdBssIdBuf, pTmpBssDesc->bdBssIdBuf, 6)!=0)
7511                         {
7512                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): ERROR!! This shall not happen.\n"));
7513                                 continue;
7514                         }
7515
7516                         if(pDM_Odm->SupportICType != ODM_RTL8723B)
7517                         {
7518                                 if(pTmpBssDesc->ChannelNumber == ScanChannel)
7519                                 {
7520                         if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower)
7521                         {
7522                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Compare scan entry: Score++\n"));
7523                                                 RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen);
7524                                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
7525
7526                                 Score++;
7527                                 PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS));
7528                         }
7529                         else if(pTmpBssDesc->RecvSignalPower < pTestBssDesc->RecvSignalPower)
7530                         {
7531                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Compare scan entry: Score--\n"));
7532                                                 RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen);
7533                                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
7534                                 Score--;
7535                         }
7536                                         else
7537                                         {
7538                                                 if(pTestBssDesc->bdTstamp - pTmpBssDesc->bdTstamp < 5000)
7539                                                 {
7540                                                         RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen);
7541                                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
7542                                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("The 2nd Antenna didn't get this AP\n\n"));
7543                                                 }
7544                                         }
7545                                 }
7546                         }
7547                         else
7548                         {
7549                                 if(pTmpBssDesc->ChannelNumber == ScanChannel)
7550                                 {
7551                                         if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower)
7552                                         {
7553                                                 counter++;
7554                                                 power_diff = power_diff + (pTmpBssDesc->RecvSignalPower - pTestBssDesc->RecvSignalPower);
7555                                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
7556                                                 ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf);
7557                                                 ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf);
7558                                                 PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS));
7559                                         }
7560                                         else if(pTestBssDesc->RecvSignalPower > pTmpBssDesc->RecvSignalPower)
7561                                         {
7562                                                 counter++;
7563                                                 power_diff = power_diff + (pTestBssDesc->RecvSignalPower - pTmpBssDesc->RecvSignalPower);
7564                                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
7565                                                 ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf);
7566                                                 ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf)
7567                                         }
7568                                         else if(pTestBssDesc->bdTstamp > pTmpBssDesc->bdTstamp)
7569                                         {
7570                                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("time_diff: %lld\n", (pTestBssDesc->bdTstamp-pTmpBssDesc->bdTstamp)/1000));
7571                                                 if(pTestBssDesc->bdTstamp - pTmpBssDesc->bdTstamp > 5000)
7572                                                 {
7573                                                         counter++;
7574                                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
7575                                                         ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf);
7576                                                         ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf)
7577                                                 }
7578                                         }
7579                                 }
7580                         }
7581                 }
7582
7583                 if(pDM_Odm->SupportICType == ODM_RTL8723B)
7584                 {
7585                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter: %d power_diff: %d\n", counter, power_diff));
7586
7587                         if(counter != 0)
7588                                 power_diff = power_diff / counter;
7589
7590                         if(power_diff <= power_target && counter != 0)
7591                                 Score++;
7592                 }
7593
7594                 if(pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8821))
7595                 {
7596                         if(pMgntInfo->NumBssDesc!=0 && Score<0)
7597                         {
7598                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
7599                                                         ("ODM_SwAntDivCheckBeforeLink(): Using Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
7600                         }
7601                         else
7602                         {
7603                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
7604                                                 ("ODM_SwAntDivCheckBeforeLink(): Remain Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"AUX_ANT":"MAIN_ANT"));
7605
7606                                 if(pDM_FatTable->RxIdleAnt == MAIN_ANT)
7607                                         ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);
7608                                 else
7609                                         ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);
7610                         }
7611
7612                         if(IS_5G_WIRELESS_MODE(pMgntInfo->dot11CurrentWirelessMode))
7613                         {
7614                                 pDM_SWAT_Table->Ant5G = pDM_FatTable->RxIdleAnt;
7615                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant5G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
7616                         }
7617                         else
7618                         {
7619                                 pDM_SWAT_Table->Ant2G = pDM_FatTable->RxIdleAnt;
7620                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant2G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
7621                         }
7622                 }
7623                 else if(pDM_Odm->SupportICType == ODM_RTL8723B)
7624                 {
7625                         pDM_SWAT_Table->CurAntenna = pDM_SWAT_Table->PreAntenna;
7626                         pDM_SWAT_Table->SWAS_NoLink_BK_Reg92c = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg92c & 0xfffffffc) | (pDM_SWAT_Table->CurAntenna));
7627                         ODM_SetBBReg(pDM_Odm,  rfe_ctrl_anta_src, 0xff, 0x77);
7628                         ODM_SetBBReg(pDM_Odm,  rDPDT_control,bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg92c);
7629
7630                         if(counter != 0)
7631                         {
7632                                 if(pMgntInfo->NumBssDesc != 0 && Score > 0)
7633                                 {
7634                                         if(pDM_Odm->DM_SWAT_Table.ANTB_ON == FALSE)
7635                                         {
7636                                                 pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE;
7637                                                 pDM_Odm->DM_SWAT_Table.ANTB_ON = TRUE;
7638                                         }
7639                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SwAntDivCheckBeforeLink(): Dual antenna\n"));
7640                                 }
7641                                 else
7642                                 {
7643                                         if(pDM_Odm->DM_SWAT_Table.ANTB_ON == TRUE)
7644                                         {
7645                                                 pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE;
7646                                                 pDM_Odm->DM_SWAT_Table.ANTB_ON = FALSE;
7647                                                 BT_SetBtCoexAntNum(Adapter, BT_COEX_ANT_TYPE_DETECTED, 1);
7648                                         }
7649                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n"));
7650                                 }
7651                         }
7652                         else
7653                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SwAntDivCheckBeforeLink(): Igone result\n"));
7654                 }
7655                 else if(pDM_Odm->SupportICType == ODM_RTL8192C)
7656                 {
7657                         if(pMgntInfo->NumBssDesc!=0 && Score<=0)
7658                         {
7659                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
7660                                         ("ODM_SwAntDivCheckBeforeLink(): Using Ant(%s)\n", (pDM_SWAT_Table->CurAntenna==MAIN_ANT)?"MAIN":"AUX"));
7661
7662                                 pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna;
7663                         }
7664                         else
7665                         {
7666                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
7667                                         ("ODM_SwAntDivCheckBeforeLink(): Remain Ant(%s)\n", (pDM_SWAT_Table->CurAntenna==MAIN_ANT)?"AUX":"MAIN"));
7668
7669                                 pDM_SWAT_Table->CurAntenna = pDM_SWAT_Table->PreAntenna;
7670
7671                                 //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, DM_SWAT_Table.CurAntenna);
7672                                 pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 & 0xfffffcff) | (pDM_SWAT_Table->CurAntenna<<8));
7673                                 PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg860);
7674                         }
7675                 }
7676
7677                 // Check state reset to default and wait for next time.
7678                 pDM_SWAT_Table->SWAS_NoLink_State = 0;
7679                 pMgntInfo->bScanAntDetect = FALSE;
7680
7681                 return FALSE;
7682         }
7683
7684 #else
7685                 return  FALSE;
7686 #endif
7687
7688 return FALSE;
7689 }
7690
7691 #endif //#if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
7692
7693
7694 //3============================================================
7695 //3 SW Antenna Diversity
7696 //3============================================================
7697
7698 #if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
7699 VOID
7700 odm_InitHybridAntDiv_88C_92D(
7701         IN PDM_ODM_T    pDM_Odm
7702         )
7703 {
7704
7705 #if((DM_ODM_SUPPORT_TYPE==ODM_AP)||(DM_ODM_SUPPORT_TYPE==ODM_ADSL))
7706         struct rtl8192cd_priv *priv=pDM_Odm->priv;
7707 #endif
7708         SWAT_T                  *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
7709         u1Byte                  bTxPathSel=0;           //0:Path-A   1:Path-B
7710         u1Byte                  i;
7711
7712         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_InitHybridAntDiv==============>\n"));
7713
7714         //whether to do antenna diversity or not
7715 #if(DM_ODM_SUPPORT_TYPE==ODM_AP)
7716         if(priv==NULL)  return;
7717         if(!priv->pshare->rf_ft_var.antHw_enable)
7718                 return;
7719
7720         #ifdef SW_ANT_SWITCH
7721         priv->pshare->rf_ft_var.antSw_enable =0;
7722         #endif
7723 #endif
7724
7725         if((pDM_Odm->SupportICType != ODM_RTL8192C) && (pDM_Odm->SupportICType != ODM_RTL8192D))
7726                 return;
7727
7728
7729         bTxPathSel=(pDM_Odm->RFType==ODM_1T1R)?FALSE:TRUE;
7730
7731         ODM_SetBBReg(pDM_Odm,ODM_REG_BB_PWR_SAV1_11N, BIT23, 0); //No update ANTSEL during GNT_BT=1
7732         ODM_SetBBReg(pDM_Odm,ODM_REG_TX_ANT_CTRL_11N, BIT21, 1); //TX atenna selection from tx_info
7733         ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_PIN_11N, BIT23, 1); //enable LED[1:0] pin as ANTSEL
7734         ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_CTRL_11N, BIT8|BIT9, 0x01); // 0x01: left antenna, 0x02: right antenna
7735         // check HW setting: ANTSEL pin connection
7736         #if(DM_ODM_SUPPORT_TYPE==ODM_AP)
7737         ODM_Write2Byte(pDM_Odm,ODM_REG_RF_PIN_11N, (ODM_Read2Byte(pDM_Odm,0x804)&0xf0ff )| BIT(8) );    // b11-b8=0001,update RFPin setting
7738         #endif
7739
7740         // only AP support different path selection temperarly
7741         if(!bTxPathSel){                 //PATH-A
7742                 ODM_SetBBReg(pDM_Odm,ODM_REG_PIN_CTRL_11N, BIT8|BIT9, 0 ); // ANTSEL as HW control
7743                 ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_PATH_11N, BIT13, 1);         //select TX ANTESEL from path A
7744         }
7745         else    {
7746                 ODM_SetBBReg(pDM_Odm,ODM_REG_PIN_CTRL_11N, BIT24|BIT25, 0 ); // ANTSEL as HW control
7747                 ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_PATH_11N, BIT13, 0);                 //select ANTESEL from path B
7748         }
7749
7750         //Set OFDM HW RX Antenna Diversity
7751         ODM_SetBBReg(pDM_Odm,ODM_REG_ANTDIV_PARA1_11N, 0x7FF, 0x0c0); //Pwdb threshold=8dB
7752         ODM_SetBBReg(pDM_Odm,ODM_REG_ANTDIV_PARA1_11N, BIT11, 0); //Switch to another antenna by checking pwdb threshold
7753         ODM_SetBBReg(pDM_Odm,ODM_REG_ANTDIV_PARA3_11N, BIT23, 1);       // Decide final antenna by comparing 2 antennas' pwdb
7754
7755         //Set CCK HW RX Antenna Diversity
7756         ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 0); //Antenna diversity decision period = 32 sample
7757         ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA2_11N, 0xf, 0xf); //Threshold for antenna diversity. Check another antenna power if input power < ANT_lim*4
7758         ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA3_11N, BIT13, 1); //polarity ana_A=1 and ana_B=0
7759         ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA4_11N, 0x1f, 0x8); //default antenna power = inpwr*(0.5 + r_ant_step/16)
7760
7761
7762         //Enable HW Antenna Diversity
7763         if(!bTxPathSel)                 //PATH-A
7764                 ODM_SetBBReg(pDM_Odm,ODM_REG_IGI_A_11N, BIT7,1);        // Enable Hardware antenna switch
7765         else
7766                 ODM_SetBBReg(pDM_Odm,ODM_REG_IGI_B_11N, BIT7,1);        // Enable Hardware antenna switch
7767         ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA1_11N, BIT15, 1);//Enable antenna diversity
7768
7769         pDM_SWAT_Table->CurAntenna=0;                   //choose left antenna as default antenna
7770         pDM_SWAT_Table->PreAntenna=0;
7771         for(i=0; i<ASSOCIATE_ENTRY_NUM ; i++)
7772         {
7773                 pDM_SWAT_Table->CCK_Ant1_Cnt[i] = 0;
7774                 pDM_SWAT_Table->CCK_Ant2_Cnt[i] = 0;
7775                 pDM_SWAT_Table->OFDM_Ant1_Cnt[i] = 0;
7776                 pDM_SWAT_Table->OFDM_Ant2_Cnt[i] = 0;
7777                 pDM_SWAT_Table->RSSI_Ant1_Sum[i] = 0;
7778                 pDM_SWAT_Table->RSSI_Ant2_Sum[i] = 0;
7779         }
7780         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("<==============odm_InitHybridAntDiv\n"));
7781 }
7782
7783
7784 VOID
7785 odm_InitHybridAntDiv(
7786         IN PDM_ODM_T    pDM_Odm
7787         )
7788 {
7789         if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))
7790         {
7791                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("Return: Not Support HW AntDiv\n"));
7792                 return;
7793         }
7794
7795         if(pDM_Odm->SupportICType & (ODM_RTL8192C | ODM_RTL8192D))
7796         {
7797 #if ((RTL8192C_SUPPORT == 1)||(RTL8192D_SUPPORT == 1))
7798                 odm_InitHybridAntDiv_88C_92D(pDM_Odm);
7799 #endif
7800         }
7801 }
7802
7803
7804 BOOLEAN
7805 odm_StaDefAntSel(
7806         IN PDM_ODM_T    pDM_Odm,
7807         IN u4Byte               OFDM_Ant1_Cnt,
7808         IN u4Byte               OFDM_Ant2_Cnt,
7809         IN u4Byte               CCK_Ant1_Cnt,
7810         IN u4Byte               CCK_Ant2_Cnt,
7811         OUT u1Byte              *pDefAnt
7812
7813         )
7814 {
7815 #if 1
7816         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_StaDefAntSelect==============>\n"));
7817
7818         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("OFDM_Ant1_Cnt:%d, OFDM_Ant2_Cnt:%d\n",OFDM_Ant1_Cnt,OFDM_Ant2_Cnt));
7819         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("CCK_Ant1_Cnt:%d, CCK_Ant2_Cnt:%d\n",CCK_Ant1_Cnt,CCK_Ant2_Cnt));
7820
7821
7822         if(((OFDM_Ant1_Cnt+OFDM_Ant2_Cnt)==0)&&((CCK_Ant1_Cnt + CCK_Ant2_Cnt) <10)){
7823                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_StaDefAntSelect Fail: No enough packet info!\n"));
7824                 return  FALSE;
7825         }
7826
7827         if(OFDM_Ant1_Cnt || OFDM_Ant2_Cnt )     {
7828                 //if RX OFDM packet number larger than 0
7829                 if(OFDM_Ant1_Cnt > OFDM_Ant2_Cnt)
7830                         (*pDefAnt)=1;
7831                 else
7832                         (*pDefAnt)=0;
7833         }
7834         // else if RX CCK packet number larger than 10
7835         else if((CCK_Ant1_Cnt + CCK_Ant2_Cnt) >=10 )
7836         {
7837                 if(CCK_Ant1_Cnt > (5*CCK_Ant2_Cnt))
7838                         (*pDefAnt)=1;
7839                 else if(CCK_Ant2_Cnt > (5*CCK_Ant1_Cnt))
7840                         (*pDefAnt)=0;
7841                 else if(CCK_Ant1_Cnt > CCK_Ant2_Cnt)
7842                         (*pDefAnt)=0;
7843                 else
7844                         (*pDefAnt)=1;
7845
7846         }
7847
7848         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("TxAnt = %s\n",((*pDefAnt)==1)?"Ant1":"Ant2"));
7849
7850 #endif
7851         //u4Byte antsel = ODM_GetBBReg(pDM_Odm, 0xc88, bMaskByte0);
7852         //(*pDefAnt)= (u1Byte) antsel;
7853
7854
7855
7856
7857         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("<==============odm_StaDefAntSelect\n"));
7858
7859         return TRUE;
7860
7861
7862 }
7863
7864
7865 VOID
7866 odm_SetRxIdleAnt(
7867         IN      PDM_ODM_T       pDM_Odm,
7868         IN      u1Byte  Ant,
7869         IN   BOOLEAN   bDualPath
7870 )
7871 {
7872         SWAT_T                  *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
7873
7874         //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_SetRxIdleAnt==============>\n"));
7875
7876         if(Ant != pDM_SWAT_Table->RxIdleAnt)
7877         {
7878         //for path-A
7879         if(Ant==1)
7880                         ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF, 0x65a9);   //right-side antenna
7881         else
7882                         ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF, 0x569a);   //left-side antenna
7883
7884         //for path-B
7885         if(bDualPath){
7886                 if(Ant==0)
7887                                 ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF0000, 0x65a9);   //right-side antenna
7888                 else
7889                                 ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF0000, 0x569a);  //left-side antenna
7890                 }
7891         }
7892                 pDM_SWAT_Table->RxIdleAnt = Ant;
7893         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("RxIdleAnt: %s  Reg858=0x%x\n",(Ant==1)?"Ant1":"Ant2",(Ant==1)?0x65a9:0x569a));
7894
7895         //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("<==============odm_SetRxIdleAnt\n"));
7896
7897         }
7898
7899 VOID
7900 ODM_AntselStatistics_88C(
7901         IN              PDM_ODM_T               pDM_Odm,
7902         IN              u1Byte                  MacId,
7903         IN              u4Byte                  PWDBAll,
7904         IN              BOOLEAN                 isCCKrate
7905 )
7906 {
7907         SWAT_T                  *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
7908
7909         if(pDM_SWAT_Table->antsel == 1)
7910         {
7911                 if(isCCKrate)
7912                         pDM_SWAT_Table->CCK_Ant1_Cnt[MacId]++;
7913                 else
7914                 {
7915                         pDM_SWAT_Table->OFDM_Ant1_Cnt[MacId]++;
7916                         pDM_SWAT_Table->RSSI_Ant1_Sum[MacId] += PWDBAll;
7917                 }
7918         }
7919         else
7920         {
7921                 if(isCCKrate)
7922                         pDM_SWAT_Table->CCK_Ant2_Cnt[MacId]++;
7923                 else
7924                 {
7925                         pDM_SWAT_Table->OFDM_Ant2_Cnt[MacId]++;
7926                         pDM_SWAT_Table->RSSI_Ant2_Sum[MacId] += PWDBAll;
7927                 }
7928         }
7929
7930 }
7931
7932
7933
7934
7935 #if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
7936 VOID
7937 ODM_SetTxAntByTxInfo_88C_92D(
7938         IN              PDM_ODM_T               pDM_Odm,
7939         IN              pu1Byte                 pDesc,
7940         IN              u1Byte                  macId
7941 )
7942 {
7943         SWAT_T                  *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
7944         u1Byte                  antsel;
7945
7946         if(!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV))
7947                 return;
7948
7949         if(pDM_SWAT_Table->RxIdleAnt == 1)
7950                 antsel=(pDM_SWAT_Table->TxAnt[macId] == 1)?0:1;
7951         else
7952                 antsel=(pDM_SWAT_Table->TxAnt[macId] == 1)?1:0;
7953
7954         SET_TX_DESC_ANTSEL_A_92C(pDesc, antsel);
7955         //SET_TX_DESC_ANTSEL_B_92C(pDesc, antsel);
7956         //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("SET_TX_DESC_ANTSEL_A_92C=%d\n", pDM_SWAT_Table->TxAnt[macId]));
7957 }
7958 #elif(DM_ODM_SUPPORT_TYPE==ODM_CE)
7959 VOID
7960 ODM_SetTxAntByTxInfo_88C_92D(
7961         IN              PDM_ODM_T               pDM_Odm
7962 )
7963 {
7964
7965 }
7966 #elif(DM_ODM_SUPPORT_TYPE==ODM_AP)
7967 VOID
7968 ODM_SetTxAntByTxInfo_88C_92D(
7969         IN              PDM_ODM_T               pDM_Odm
7970 )
7971 {
7972
7973 }
7974 #endif
7975
7976 VOID
7977 odm_HwAntDiv_92C_92D(
7978         IN      PDM_ODM_T       pDM_Odm
7979 )
7980 {
7981         SWAT_T                  *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
7982         u4Byte                  RSSI_Min=0xFF, RSSI, RSSI_Ant1, RSSI_Ant2;
7983         u1Byte                  RxIdleAnt, i;
7984         BOOLEAN         bRet=FALSE;
7985         PSTA_INFO_T     pEntry;
7986
7987 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
7988         struct rtl8192cd_priv *priv=pDM_Odm->priv;
7989         //if test, return
7990         if(priv->pshare->rf_ft_var.CurAntenna & 0x80)
7991                 return;
7992 #endif
7993
7994         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_HwAntDiv==============>\n"));
7995
7996         if(!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV))                                    //if don't support antenna diveristy
7997         {
7998                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_HwAntDiv: Not supported!\n"));
7999                 return;
8000         }
8001
8002         if((pDM_Odm->SupportICType != ODM_RTL8192C) && (pDM_Odm->SupportICType != ODM_RTL8192D))
8003         {
8004                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("Return: IC Type is not 92C or 92D\n"));
8005                 return;
8006         }
8007
8008 #if (DM_ODM_SUPPORT_TYPE&(ODM_WIN|ODM_CE))
8009         if(!pDM_Odm->bLinked)
8010         {
8011                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("Return: bLinked is FALSE\n"));
8012                 return;
8013         }
8014 #endif
8015
8016         for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
8017         {
8018                 pEntry = pDM_Odm->pODM_StaInfo[i];
8019                 if(IS_STA_VALID(pEntry))
8020                 {
8021
8022                         RSSI_Ant1 = (pDM_SWAT_Table->OFDM_Ant1_Cnt[i] == 0)?0:(pDM_SWAT_Table->RSSI_Ant1_Sum[i]/pDM_SWAT_Table->OFDM_Ant1_Cnt[i]);
8023                         RSSI_Ant2 = (pDM_SWAT_Table->OFDM_Ant2_Cnt[i] == 0)?0:(pDM_SWAT_Table->RSSI_Ant2_Sum[i]/pDM_SWAT_Table->OFDM_Ant2_Cnt[i]);
8024
8025                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("RSSI_Ant1=%d,  RSSI_Ant2=%d\n", RSSI_Ant1, RSSI_Ant2));
8026
8027                         if(RSSI_Ant1 ||RSSI_Ant2)
8028                         {
8029 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
8030                                 if(pDM_Odm->pODM_StaInfo[i]->expire_to)
8031 #endif
8032                                 {
8033                                         RSSI = (RSSI_Ant1 < RSSI_Ant2) ? RSSI_Ant1 : RSSI_Ant2;
8034                                         if((!RSSI) || ( RSSI < RSSI_Min) ) {
8035                                                 pDM_SWAT_Table->TargetSTA = i;
8036                                                 RSSI_Min = RSSI;
8037                                         }
8038                                 }
8039         }
8040                         ///STA: found out default antenna
8041                         bRet=odm_StaDefAntSel(pDM_Odm,
8042                                                  pDM_SWAT_Table->OFDM_Ant1_Cnt[i],
8043                                                  pDM_SWAT_Table->OFDM_Ant2_Cnt[i],
8044                                                  pDM_SWAT_Table->CCK_Ant1_Cnt[i],
8045                                                  pDM_SWAT_Table->CCK_Ant2_Cnt[i],
8046                                                  &pDM_SWAT_Table->TxAnt[i]);
8047
8048                         //if Tx antenna selection: successful
8049                         if(bRet){
8050                                 pDM_SWAT_Table->RSSI_Ant1_Sum[i] = 0;
8051                                 pDM_SWAT_Table->RSSI_Ant2_Sum[i] = 0;
8052                                 pDM_SWAT_Table->OFDM_Ant1_Cnt[i] = 0;
8053                                 pDM_SWAT_Table->OFDM_Ant2_Cnt[i] = 0;
8054                                 pDM_SWAT_Table->CCK_Ant1_Cnt[i] = 0;
8055                                 pDM_SWAT_Table->CCK_Ant2_Cnt[i] = 0;
8056                         }
8057                 }
8058         }
8059
8060         //set RX Idle Ant
8061         RxIdleAnt = pDM_SWAT_Table->TxAnt[pDM_SWAT_Table->TargetSTA];
8062         odm_SetRxIdleAnt(pDM_Odm, RxIdleAnt, FALSE);
8063
8064 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
8065 #ifdef TX_SHORTCUT
8066         if (!priv->pmib->dot11OperationEntry.disable_txsc) {
8067                 plist = phead->next;
8068                 while(plist != phead)   {
8069                         pstat = list_entry(plist, struct stat_info, asoc_list);
8070                         if(pstat->expire_to) {
8071                                 for (i=0; i<TX_SC_ENTRY_NUM; i++) {
8072                                         struct tx_desc *pdesc= &(pstat->tx_sc_ent[i].hwdesc1);
8073                                         pdesc->Dword2 &= set_desc(~ (BIT(24)|BIT(25)));
8074                                         if((pstat->CurAntenna^priv->pshare->rf_ft_var.CurAntenna)&1)
8075                                                 pdesc->Dword2 |= set_desc(BIT(24)|BIT(25));
8076                                         pdesc= &(pstat->tx_sc_ent[i].hwdesc2);
8077                                         pdesc->Dword2 &= set_desc(~ (BIT(24)|BIT(25)));
8078                                         if((pstat->CurAntenna^priv->pshare->rf_ft_var.CurAntenna)&1)
8079                                                 pdesc->Dword2 |= set_desc(BIT(24)|BIT(25));
8080                                 }
8081                         }
8082
8083                         if (plist == plist->next)
8084                                 break;
8085                         plist = plist->next;
8086                 };
8087         }
8088 #endif
8089 #endif
8090
8091         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("<==============odm_HwAntDiv\n"));
8092
8093 }
8094
8095 VOID
8096 odm_HwAntDiv(
8097         IN      PDM_ODM_T       pDM_Odm
8098 )
8099 {
8100
8101         PADAPTER                pAdapter        = pDM_Odm->Adapter;
8102
8103 #if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
8104         if(pAdapter->MgntInfo.AntennaTest)
8105                 return;
8106 #endif
8107         if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))
8108         {
8109                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("Return: Not Support HW AntDiv\n"));
8110                 return;
8111         }
8112
8113         if(pDM_Odm->SupportICType & (ODM_RTL8192C | ODM_RTL8192D))
8114         {
8115 #if ((RTL8192C_SUPPORT == 1)||(RTL8192D_SUPPORT == 1))
8116                 odm_HwAntDiv_92C_92D(pDM_Odm);
8117 #endif
8118         }
8119 }
8120
8121
8122 #if(DM_ODM_SUPPORT_TYPE==ODM_AP)
8123 #if 0
8124 VOID
8125 odm_HwAntDiv(
8126         IN      PDM_ODM_T       pDM_Odm
8127 )
8128 {
8129         struct rtl8192cd_priv *priv=pDM_Odm->priv;
8130         struct stat_info        *pstat, *pstat_min=NULL;
8131         struct list_head        *phead, *plist;
8132         int rssi_min= 0xff, i;
8133         u1Byte  idleAnt=priv->pshare->rf_ft_var.CurAntenna;
8134         u1Byte  nextAnt;
8135         BOOLEAN         bRet=FALSE;
8136
8137         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_HwAntDiv==============>\n"));
8138
8139         if((!priv->pshare->rf_ft_var.antHw_enable) ||(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)))
8140                 return;
8141
8142         //if test, return
8143         if(priv->pshare->rf_ft_var.CurAntenna & 0x80)
8144                 return;
8145
8146         phead = &priv->asoc_list;
8147         plist = phead->next;
8148         ////=========================
8149         //find mimum rssi sta
8150         ////=========================
8151         while(plist != phead)   {
8152                 pstat = list_entry(plist, struct stat_info, asoc_list);
8153                 if((pstat->expire_to) && (pstat->AntRSSI[0] || pstat->AntRSSI[1])) {
8154                         int rssi = (pstat->AntRSSI[0] < pstat->AntRSSI[1]) ? pstat->AntRSSI[0] : pstat->AntRSSI[1];
8155                         if((!pstat_min) || ( rssi < rssi_min) ) {
8156                                 pstat_min = pstat;
8157                                 rssi_min = rssi;
8158                         }
8159                 }
8160                 ///STA: found out default antenna
8161                 bRet=odm_StaDefAntSel(pDM_Odm,
8162                                                 pstat->hwRxAntSel[1],
8163                                                 pstat->hwRxAntSel[0],
8164                                                 pstat->cckPktCount[1],
8165                                                 pstat->cckPktCount[0],
8166                                                 &nextAnt
8167                                                 );
8168
8169                 //if default antenna selection: successful
8170                 if(bRet){
8171                         pstat->CurAntenna = nextAnt;
8172                         //update rssi
8173                         for(i=0; i<2; i++) {
8174                                 if(pstat->cckPktCount[i]==0 && pstat->hwRxAntSel[i]==0)
8175                                         pstat->AntRSSI[i] = 0;
8176                         }
8177                         if(pstat->AntRSSI[idleAnt]==0)
8178                                 pstat->AntRSSI[idleAnt] = pstat->AntRSSI[idleAnt^1];
8179                         // reset variables
8180                         pstat->hwRxAntSel[1] = pstat->hwRxAntSel[0] =0;
8181                         pstat->cckPktCount[1]= pstat->cckPktCount[0] =0;
8182                 }
8183
8184                 if (plist == plist->next)
8185                         break;
8186                 plist = plist->next;
8187
8188         };
8189         ////=========================
8190         //Choose  RX Idle antenna according to minmum rssi
8191         ////=========================
8192         if(pstat_min)   {
8193                 if(priv->pshare->rf_ft_var.CurAntenna!=pstat_min->CurAntenna)
8194                         odm_SetRxIdleAnt(pDM_Odm,pstat_min->CurAntenna,TRUE);
8195                 priv->pshare->rf_ft_var.CurAntenna = pstat_min->CurAntenna;
8196         }
8197
8198
8199 #ifdef TX_SHORTCUT
8200         if (!priv->pmib->dot11OperationEntry.disable_txsc) {
8201                 plist = phead->next;
8202                 while(plist != phead)   {
8203                         pstat = list_entry(plist, struct stat_info, asoc_list);
8204                         if(pstat->expire_to) {
8205                                 for (i=0; i<TX_SC_ENTRY_NUM; i++) {
8206                                         struct tx_desc *pdesc= &(pstat->tx_sc_ent[i].hwdesc1);
8207                                         pdesc->Dword2 &= set_desc(~ (BIT(24)|BIT(25)));
8208                                         if((pstat->CurAntenna^priv->pshare->rf_ft_var.CurAntenna)&1)
8209                                                 pdesc->Dword2 |= set_desc(BIT(24)|BIT(25));
8210                                         pdesc= &(pstat->tx_sc_ent[i].hwdesc2);
8211                                         pdesc->Dword2 &= set_desc(~ (BIT(24)|BIT(25)));
8212                                         if((pstat->CurAntenna^priv->pshare->rf_ft_var.CurAntenna)&1)
8213                                                 pdesc->Dword2 |= set_desc(BIT(24)|BIT(25));
8214                                 }
8215                         }
8216
8217                         if (plist == plist->next)
8218                                 break;
8219                         plist = plist->next;
8220                 };
8221         }
8222 #endif
8223         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,"<==============odm_HwAntDiv\n");
8224 }
8225 #endif
8226
8227 u1Byte
8228 ODM_Diversity_AntennaSelect(
8229         IN      PDM_ODM_T       pDM_Odm,
8230         IN      u1Byte  *data
8231 )
8232 {
8233         struct rtl8192cd_priv *priv=pDM_Odm->priv;
8234
8235         int ant = _atoi(data, 16);
8236
8237         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("ODM_Diversity_AntennaSelect==============>\n"));
8238
8239         #ifdef PCIE_POWER_SAVING
8240         PCIeWakeUp(priv, POWER_DOWN_T0);
8241         #endif
8242
8243         if (ant==AUX_ANT || ant==MAIN_ANT)
8244         {
8245                 if ( !priv->pshare->rf_ft_var.antSw_select) {
8246                         ODM_Write4Byte(pDM_Odm,0x870, ODM_Read4Byte(pDM_Odm,0x870) | BIT(8)| BIT(9) );  //  ANTSEL A as SW control
8247                         ODM_Write1Byte(pDM_Odm,0xc50, ODM_Read1Byte(pDM_Odm,0xc50) & (~ BIT(7)));       // rx OFDM SW control
8248                         PHY_SetBBReg(priv, 0x860, 0x300, ant);
8249                 } else {
8250                         ODM_Write4Byte(pDM_Odm,0x870, ODM_Read4Byte(pDM_Odm,0x870) | BIT(24)| BIT(25) ); // ANTSEL B as HW control
8251                         PHY_SetBBReg(priv, 0x864, 0x300, ant);
8252                         ODM_Write1Byte(pDM_Odm,0xc58, ODM_Read1Byte(pDM_Odm,0xc58) & (~ BIT(7)));               // rx OFDM SW control
8253                 }
8254
8255                 ODM_Write1Byte(pDM_Odm,0xa01, ODM_Read1Byte(pDM_Odm,0xa01) & (~ BIT(7)));       // rx CCK SW control
8256                 ODM_Write4Byte(pDM_Odm,0x80c, ODM_Read4Byte(pDM_Odm,0x80c) & (~ BIT(21))); // select ant by tx desc
8257                 ODM_Write4Byte(pDM_Odm,0x858, 0x569a569a);
8258
8259                 priv->pshare->rf_ft_var.antHw_enable = 0;
8260                 priv->pshare->rf_ft_var.CurAntenna  = (ant%2);
8261
8262                 #ifdef SW_ANT_SWITCH
8263                 priv->pshare->rf_ft_var.antSw_enable = 0;
8264                 priv->pshare->DM_SWAT_Table.CurAntenna = ant;
8265                 priv->pshare->RSSI_test =0;
8266                 #endif
8267         }
8268         else if(ant==0){
8269
8270                 if ( !priv->pshare->rf_ft_var.antSw_select)  {
8271                         ODM_Write4Byte(pDM_Odm,0x870, ODM_Read4Byte(pDM_Odm,0x870) & ~(BIT(8)| BIT(9)) );
8272                         ODM_Write1Byte(pDM_Odm,0xc50, ODM_Read1Byte(pDM_Odm,0xc50) | BIT(7));   // OFDM HW control
8273                 } else {
8274                         ODM_Write4Byte(pDM_Odm,0x870, ODM_Read4Byte(pDM_Odm,0x870) & ~(BIT(24)| BIT(25)) );
8275                         ODM_Write1Byte(pDM_Odm,0xc58, ODM_Read1Byte(pDM_Odm,0xc58) | BIT(7));   // OFDM HW control
8276                 }
8277
8278                 ODM_Write1Byte(pDM_Odm,0xa01, ODM_Read1Byte(pDM_Odm,0xa01) | BIT(7));   // CCK HW control
8279                 ODM_Write4Byte(pDM_Odm,0x80c, ODM_Read4Byte(pDM_Odm,0x80c) | BIT(21) ); // by tx desc
8280                 priv->pshare->rf_ft_var.CurAntenna = 0;
8281                 ODM_Write4Byte(pDM_Odm,0x858, 0x569a569a);
8282                 priv->pshare->rf_ft_var.antHw_enable = 1;
8283 #ifdef SW_ANT_SWITCH
8284                 priv->pshare->rf_ft_var.antSw_enable = 0;
8285                 priv->pshare->RSSI_test =0;
8286 #endif
8287         }
8288 #ifdef SW_ANT_SWITCH
8289         else if(ant==3) {
8290                 if(!priv->pshare->rf_ft_var.antSw_enable) {
8291
8292                         dm_SW_AntennaSwitchInit(priv);
8293                         ODM_Write4Byte(pDM_Odm,0x858, 0x569a569a);
8294                         priv->pshare->lastTxOkCnt = priv->net_stats.tx_bytes;
8295                         priv->pshare->lastRxOkCnt = priv->net_stats.rx_bytes;
8296                 }
8297                 if ( !priv->pshare->rf_ft_var.antSw_select)
8298                         ODM_Write1Byte(pDM_Odm,0xc50, ODM_Read1Byte(pDM_Odm,0xc50) & (~ BIT(7)));       // rx OFDM SW control
8299                 else
8300                         ODM_Write1Byte(pDM_Odm,0xc58, ODM_Read1Byte(pDM_Odm,0xc58) & (~ BIT(7)));       // rx OFDM SW control
8301
8302                 ODM_Write1Byte(pDM_Odm,0xa01, ODM_Read1Byte(pDM_Odm,0xa01) & (~ BIT(7)));               // rx CCK SW control
8303                 ODM_Write4Byte(pDM_Odm,0x80c, ODM_Read4Byte(pDM_Odm,0x80c) & (~ BIT(21)));      // select ant by tx desc
8304                 priv->pshare->rf_ft_var.antHw_enable = 0;
8305                 priv->pshare->rf_ft_var.antSw_enable = 1;
8306
8307         }
8308 #endif
8309         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("<==============ODM_Diversity_AntennaSelect\n"));
8310
8311         return 1;
8312 }
8313 #endif
8314
8315 #else //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
8316
8317 VOID odm_InitHybridAntDiv(      IN PDM_ODM_T    pDM_Odm         ){}
8318 VOID odm_HwAntDiv(      IN      PDM_ODM_T       pDM_Odm){}
8319 #if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
8320 VOID ODM_SetTxAntByTxInfo_88C_92D(
8321         IN              PDM_ODM_T               pDM_Odm,
8322         IN              pu1Byte                 pDesc,
8323         IN              u1Byte                  macId
8324 ){}
8325 #elif(DM_ODM_SUPPORT_TYPE==ODM_CE)
8326 VOID ODM_SetTxAntByTxInfo_88C_92D(      IN              PDM_ODM_T               pDM_Odm){ }
8327 #elif(DM_ODM_SUPPORT_TYPE==ODM_AP)
8328 VOID ODM_SetTxAntByTxInfo_88C_92D(      IN              PDM_ODM_T               pDM_Odm){ }
8329 #endif
8330
8331 #endif //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
8332
8333
8334
8335 //============================================================
8336 //EDCA Turbo
8337 //============================================================
8338 VOID
8339 ODM_EdcaTurboInit(
8340         IN    PDM_ODM_T         pDM_Odm)
8341 {
8342
8343 #if ((DM_ODM_SUPPORT_TYPE == ODM_AP)||(DM_ODM_SUPPORT_TYPE==ODM_ADSL))
8344         odm_EdcaParaInit(pDM_Odm);
8345 #elif (DM_ODM_SUPPORT_TYPE==ODM_WIN)
8346         PADAPTER        Adapter = NULL;
8347         HAL_DATA_TYPE   *pHalData = NULL;
8348
8349         if(pDM_Odm->Adapter==NULL)      {
8350                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EdcaTurboInit fail!!!\n"));
8351                 return;
8352         }
8353
8354         Adapter=pDM_Odm->Adapter;
8355         pHalData=GET_HAL_DATA(Adapter);
8356
8357         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE;
8358         pDM_Odm->DM_EDCA_Table.bIsCurRDLState = FALSE;
8359         pHalData->bIsAnyNonBEPkts = FALSE;
8360
8361 #elif(DM_ODM_SUPPORT_TYPE==ODM_CE)
8362         PADAPTER        Adapter = pDM_Odm->Adapter;
8363         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE;
8364         pDM_Odm->DM_EDCA_Table.bIsCurRDLState = FALSE;
8365         Adapter->recvpriv.bIsAnyNonBEPkts =FALSE;
8366
8367 #endif
8368         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial VO PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_VO_PARAM)));
8369         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial VI PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_VI_PARAM)));
8370         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BE PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BE_PARAM)));
8371         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BK PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BK_PARAM)));
8372
8373
8374 }       // ODM_InitEdcaTurbo
8375
8376 VOID
8377 odm_EdcaTurboCheck(
8378         IN              PDM_ODM_T               pDM_Odm
8379         )
8380 {
8381         //
8382         // For AP/ADSL use prtl8192cd_priv
8383         // For CE/NIC use PADAPTER
8384         //
8385
8386         //
8387         // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
8388         // at the same time. In the stage2/3, we need to prive universal interface and merge all
8389         // HW dynamic mechanism.
8390         //
8391         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("odm_EdcaTurboCheck========================>\n"));
8392
8393         if(!(pDM_Odm->SupportAbility& ODM_MAC_EDCA_TURBO ))
8394                 return;
8395
8396         switch  (pDM_Odm->SupportPlatform)
8397         {
8398                 case    ODM_WIN:
8399
8400 #if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
8401                         odm_EdcaTurboCheckMP(pDM_Odm);
8402 #endif
8403                         break;
8404
8405                 case    ODM_CE:
8406 #if(DM_ODM_SUPPORT_TYPE==ODM_CE)
8407                         odm_EdcaTurboCheckCE(pDM_Odm);
8408 #endif
8409                         break;
8410
8411                 case    ODM_AP:
8412                 case    ODM_ADSL:
8413
8414 #if ((DM_ODM_SUPPORT_TYPE == ODM_AP)||(DM_ODM_SUPPORT_TYPE==ODM_ADSL))
8415                 odm_IotEngine(pDM_Odm);
8416 #endif
8417                         break;
8418         }
8419         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("<========================odm_EdcaTurboCheck\n"));
8420
8421 }       // odm_CheckEdcaTurbo
8422
8423 #if(DM_ODM_SUPPORT_TYPE==ODM_CE)
8424
8425
8426 VOID
8427 odm_EdcaTurboCheckCE(
8428         IN              PDM_ODM_T               pDM_Odm
8429         )
8430 {
8431
8432 #if(DM_ODM_SUPPORT_TYPE==ODM_CE)
8433
8434         PADAPTER                       Adapter = pDM_Odm->Adapter;
8435         u32     EDCA_BE_UL = 0x5ea42b;//Parameter suggested by Scott  //edca_setting_UL[pMgntInfo->IOTPeer];
8436         u32     EDCA_BE_DL = 0x5ea42b;//Parameter suggested by Scott  //edca_setting_DL[pMgntInfo->IOTPeer];
8437         u32     ICType=pDM_Odm->SupportICType;
8438         u32     IOTPeer=0;
8439         u8      WirelessMode=0xFF;                   //invalid value
8440         u32     trafficIndex;
8441         u32     edca_param;
8442         u64     cur_tx_bytes = 0;
8443         u64     cur_rx_bytes = 0;
8444         u8      bbtchange = _FALSE;
8445         u8      bBiasOnRx = _FALSE;
8446         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
8447         struct dvobj_priv               *pdvobjpriv = adapter_to_dvobj(Adapter);
8448         struct xmit_priv                *pxmitpriv = &(Adapter->xmitpriv);
8449         struct recv_priv                *precvpriv = &(Adapter->recvpriv);
8450         struct registry_priv    *pregpriv = &Adapter->registrypriv;
8451         struct mlme_ext_priv    *pmlmeext = &(Adapter->mlmeextpriv);
8452         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
8453
8454         if(pDM_Odm->bLinked != _TRUE)
8455                 goto dm_CheckEdcaTurbo_EXIT;
8456
8457         if ((pregpriv->wifi_spec == 1) )//|| (pmlmeinfo->HT_enable == 0))
8458         {
8459                 goto dm_CheckEdcaTurbo_EXIT;
8460         }
8461
8462         if(pDM_Odm->pWirelessMode!=NULL)
8463                 WirelessMode=*(pDM_Odm->pWirelessMode);
8464
8465         IOTPeer = pmlmeinfo->assoc_AP_vendor;
8466
8467         if (IOTPeer >=  HT_IOT_PEER_MAX)
8468         {
8469                 goto dm_CheckEdcaTurbo_EXIT;
8470         }
8471
8472         if(     (pDM_Odm->SupportICType == ODM_RTL8192C) ||
8473                 (pDM_Odm->SupportICType == ODM_RTL8723A) ||
8474                 (pDM_Odm->SupportICType == ODM_RTL8188E))
8475         {
8476                 if((IOTPeer == HT_IOT_PEER_RALINK)||(IOTPeer == HT_IOT_PEER_ATHEROS))
8477                         bBiasOnRx = _TRUE;
8478         }
8479
8480         // Check if the status needs to be changed.
8481         if((bbtchange) || (!precvpriv->bIsAnyNonBEPkts) )
8482         {
8483                 cur_tx_bytes = pdvobjpriv->traffic_stat.cur_tx_bytes;
8484                 cur_rx_bytes = pdvobjpriv->traffic_stat.cur_rx_bytes;
8485
8486                 //traffic, TX or RX
8487                 if(bBiasOnRx)
8488                 {
8489                         if (cur_tx_bytes > (cur_rx_bytes << 2))
8490                         { // Uplink TP is present.
8491                                 trafficIndex = UP_LINK;
8492                         }
8493                         else
8494                         { // Balance TP is present.
8495                                 trafficIndex = DOWN_LINK;
8496                         }
8497                 }
8498                 else
8499                 {
8500                         if (cur_rx_bytes > (cur_tx_bytes << 2))
8501                         { // Downlink TP is present.
8502                                 trafficIndex = DOWN_LINK;
8503                         }
8504                         else
8505                         { // Balance TP is present.
8506                                 trafficIndex = UP_LINK;
8507                         }
8508                 }
8509
8510                 //if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA))
8511                 {
8512                         if(ICType==ODM_RTL8192D)
8513                         {
8514                                 // Single PHY
8515                                 if(pDM_Odm->RFType==ODM_2T2R)
8516                                 {
8517                                         EDCA_BE_UL = 0x60a42b;    //0x5ea42b;
8518                                         EDCA_BE_DL = 0x60a42b;    //0x5ea42b;
8519                                 }
8520                                 else
8521                                 {
8522                                         EDCA_BE_UL = 0x6ea42b;
8523                                         EDCA_BE_DL = 0x6ea42b;
8524                                 }
8525                         }
8526                         else
8527                         {
8528                                 if(pDM_Odm->SupportInterface==ODM_ITRF_PCIE) {
8529                                         if((ICType==ODM_RTL8192C)&&(pDM_Odm->RFType==ODM_2T2R)) {
8530                                                 EDCA_BE_UL = 0x60a42b;
8531                                                 EDCA_BE_DL = 0x60a42b;
8532                                         }
8533                                         else
8534                                         {
8535                                                 EDCA_BE_UL = 0x6ea42b;
8536                                                 EDCA_BE_DL = 0x6ea42b;
8537                                         }
8538                                 }
8539                         }
8540
8541                         //92D txop can't be set to 0x3e for cisco1250
8542                         if((ICType!=ODM_RTL8192D) && (IOTPeer== HT_IOT_PEER_CISCO) &&(WirelessMode==ODM_WM_N24G))
8543                         {
8544                                 EDCA_BE_DL = edca_setting_DL[IOTPeer];
8545                                 EDCA_BE_UL = edca_setting_UL[IOTPeer];
8546                         }
8547                         //merge from 92s_92c_merge temp brunch v2445    20120215
8548                         else if((IOTPeer == HT_IOT_PEER_CISCO) &&((WirelessMode==ODM_WM_G)||(WirelessMode==(ODM_WM_B|ODM_WM_G))||(WirelessMode==ODM_WM_A)||(WirelessMode==ODM_WM_B)))
8549                         {
8550                                 EDCA_BE_DL = edca_setting_DL_GMode[IOTPeer];
8551                         }
8552                         else if((IOTPeer== HT_IOT_PEER_AIRGO )&& ((WirelessMode==ODM_WM_G)||(WirelessMode==ODM_WM_A)))
8553                         {
8554                                 EDCA_BE_DL = 0xa630;
8555                         }
8556                         else if(IOTPeer == HT_IOT_PEER_MARVELL)
8557                         {
8558                                 EDCA_BE_DL = edca_setting_DL[IOTPeer];
8559                                 EDCA_BE_UL = edca_setting_UL[IOTPeer];
8560                         }
8561                         else if(IOTPeer == HT_IOT_PEER_ATHEROS)
8562                         {
8563                                 // Set DL EDCA for Atheros peer to 0x3ea42b. Suggested by SD3 Wilson for ASUS TP issue.
8564                                 EDCA_BE_DL = edca_setting_DL[IOTPeer];
8565                         }
8566
8567                         if((ICType==ODM_RTL8812)||(ICType==ODM_RTL8821)||(ICType==ODM_RTL8192E))           //add 8812AU/8812AE
8568                         {
8569                                 EDCA_BE_UL = 0x5ea42b;
8570                                 EDCA_BE_DL = 0x5ea42b;
8571
8572                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("8812A: EDCA_BE_UL=0x%x EDCA_BE_DL =0x%x",EDCA_BE_UL,EDCA_BE_DL));
8573                         }
8574
8575                         if (trafficIndex == DOWN_LINK)
8576                                 edca_param = EDCA_BE_DL;
8577                         else
8578                                 edca_param = EDCA_BE_UL;
8579
8580                         rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param);
8581
8582                         pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex;
8583                 }
8584
8585                 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = _TRUE;
8586         }
8587         else
8588         {
8589                 //
8590                 // Turn Off EDCA turbo here.
8591                 // Restore original EDCA according to the declaration of AP.
8592                 //
8593                  if(pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)
8594                 {
8595                         rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE);
8596                         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = _FALSE;
8597                 }
8598         }
8599
8600 dm_CheckEdcaTurbo_EXIT:
8601         // Set variables for next time.
8602         precvpriv->bIsAnyNonBEPkts = _FALSE;
8603 #endif
8604 }
8605
8606
8607 #elif(DM_ODM_SUPPORT_TYPE==ODM_WIN)
8608 VOID
8609 odm_EdcaTurboCheckMP(
8610         IN              PDM_ODM_T               pDM_Odm
8611         )
8612 {
8613
8614
8615         PADAPTER                       Adapter = pDM_Odm->Adapter;
8616         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
8617
8618         PADAPTER                        pDefaultAdapter = GetDefaultAdapter(Adapter);
8619         PADAPTER                        pExtAdapter = GetFirstExtAdapter(Adapter);//NULL;
8620         PMGNT_INFO                      pMgntInfo = &Adapter->MgntInfo;
8621         PSTA_QOS                        pStaQos = Adapter->MgntInfo.pStaQos;
8622         //[Win7 Count Tx/Rx statistic for Extension Port] odm_CheckEdcaTurbo's Adapter is always Default. 2009.08.20, by Bohn
8623         u8Byte                          Ext_curTxOkCnt = 0;
8624         u8Byte                          Ext_curRxOkCnt = 0;
8625         //For future Win7  Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn.
8626         u1Byte TwoPortStatus = (u1Byte)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE;
8627
8628         // Keep past Tx/Rx packet count for RT-to-RT EDCA turbo.
8629         u8Byte                          curTxOkCnt = 0;
8630         u8Byte                          curRxOkCnt = 0;
8631         u4Byte                          EDCA_BE_UL = 0x5ea42b;//Parameter suggested by Scott  //edca_setting_UL[pMgntInfo->IOTPeer];
8632         u4Byte                          EDCA_BE_DL = 0x5ea42b;//Parameter suggested by Scott  //edca_setting_DL[pMgntInfo->IOTPeer];
8633         u4Byte                         EDCA_BE = 0x5ea42b;
8634         u1Byte                         IOTPeer=0;
8635         BOOLEAN                      *pbIsCurRDLState=NULL;
8636         BOOLEAN                      bLastIsCurRDLState=FALSE;
8637         BOOLEAN                          bBiasOnRx=FALSE;
8638         BOOLEAN                         bEdcaTurboOn=FALSE;
8639         u1Byte                          TxRate = 0xFF;
8640         u8Byte                          value64;
8641
8642         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("odm_EdcaTurboCheckMP========================>"));
8643         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BE PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BE_PARAM)));
8644
8645 ////===============================
8646 ////list paramter for different platform
8647 ////===============================
8648         bLastIsCurRDLState=pDM_Odm->DM_EDCA_Table.bIsCurRDLState;
8649         pbIsCurRDLState=&(pDM_Odm->DM_EDCA_Table.bIsCurRDLState);
8650
8651         //2012/09/14 MH Add
8652         if (pMgntInfo->NumNonBePkt > pMgntInfo->RegEdcaThresh && !Adapter->MgntInfo.bWiFiConfg)
8653                 pHalData->bIsAnyNonBEPkts = TRUE;
8654
8655         pMgntInfo->NumNonBePkt = 0;
8656
8657        // Caculate TX/RX TP:
8658         //curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - pMgntInfo->lastTxOkCnt;
8659         //curRxOkCnt = Adapter->RxStats.NumRxBytesUnicast - pMgntInfo->lastRxOkCnt;
8660         curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - pDM_Odm->lastTxOkCnt;
8661         curRxOkCnt = Adapter->RxStats.NumRxBytesUnicast - pDM_Odm->lastRxOkCnt;
8662         pDM_Odm->lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast;
8663         pDM_Odm->lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast;
8664
8665         if(pExtAdapter == NULL)
8666                 pExtAdapter = pDefaultAdapter;
8667
8668         Ext_curTxOkCnt = pExtAdapter->TxStats.NumTxBytesUnicast - pMgntInfo->Ext_lastTxOkCnt;
8669         Ext_curRxOkCnt = pExtAdapter->RxStats.NumRxBytesUnicast - pMgntInfo->Ext_lastRxOkCnt;
8670         GetTwoPortSharedResource(Adapter,TWO_PORT_SHARED_OBJECT__STATUS,NULL,&TwoPortStatus);
8671         //For future Win7  Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn.
8672         if(TwoPortStatus == TWO_PORT_STATUS__EXTENSION_ONLY)
8673         {
8674                 curTxOkCnt = Ext_curTxOkCnt ;
8675                 curRxOkCnt = Ext_curRxOkCnt ;
8676         }
8677         //
8678         IOTPeer=pMgntInfo->IOTPeer;
8679         bBiasOnRx=(pMgntInfo->IOTAction & HT_IOT_ACT_EDCA_BIAS_ON_RX)?TRUE:FALSE;
8680         bEdcaTurboOn=((!pHalData->bIsAnyNonBEPkts) && (!pMgntInfo->bDisableFrameBursting))?TRUE:FALSE;
8681         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("bIsAnyNonBEPkts : 0x%lx  bDisableFrameBursting : 0x%lx  \n",pHalData->bIsAnyNonBEPkts,pMgntInfo->bDisableFrameBursting));
8682
8683
8684 ////===============================
8685 ////check if edca turbo is disabled
8686 ////===============================
8687         if(odm_IsEdcaTurboDisable(pDM_Odm))
8688                 goto dm_CheckEdcaTurbo_EXIT;
8689
8690
8691 ////===============================
8692 ////remove iot case out
8693 ////===============================
8694         ODM_EdcaParaSelByIot(pDM_Odm, &EDCA_BE_UL, &EDCA_BE_DL);
8695
8696
8697 ////===============================
8698 ////Check if the status needs to be changed.
8699 ////===============================
8700         if(bEdcaTurboOn)
8701         {
8702                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("bEdcaTurboOn : 0x%x bBiasOnRx : 0x%x\n",bEdcaTurboOn,bBiasOnRx));
8703                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("curTxOkCnt : 0x%lx \n",curTxOkCnt));
8704                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("curRxOkCnt : 0x%lx \n",curRxOkCnt));
8705                 if(bBiasOnRx)
8706                         odm_EdcaChooseTrafficIdx(pDM_Odm,curTxOkCnt, curRxOkCnt,   TRUE,  pbIsCurRDLState);
8707                 else
8708                         odm_EdcaChooseTrafficIdx(pDM_Odm,curTxOkCnt, curRxOkCnt,   FALSE,  pbIsCurRDLState);
8709
8710 //modify by Guo.Mingzhi 2011-12-29
8711                         EDCA_BE=((*pbIsCurRDLState)==TRUE)?EDCA_BE_DL:EDCA_BE_UL;
8712                         if(IS_HARDWARE_TYPE_8821U(Adapter))
8713                         {
8714                                 if(pMgntInfo->RegTxDutyEnable)
8715                                 {
8716                                         //2013.01.23 LukeLee: debug for 8811AU thermal issue (reduce Tx duty cycle)
8717                                         if(!pMgntInfo->ForcedDataRate) //auto rate
8718                                         {
8719                                                 if(pDM_Odm->TxRate != 0xFF)
8720                                                         TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate);
8721                                         }
8722                                         else //force rate
8723                                         {
8724                                                 TxRate = (u1Byte) pMgntInfo->ForcedDataRate;
8725                                         }
8726
8727                                         value64 = (curRxOkCnt<<2);
8728                                         if(curTxOkCnt < value64) //Downlink
8729                                                 ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
8730                                         else //Uplink
8731                                         {
8732                                                 //DbgPrint("pDM_Odm->RFCalibrateInfo.ThermalValue = 0x%X\n", pDM_Odm->RFCalibrateInfo.ThermalValue);
8733                                                 //if(pDM_Odm->RFCalibrateInfo.ThermalValue < pHalData->EEPROMThermalMeter)
8734                                                 if((pDM_Odm->RFCalibrateInfo.ThermalValue < 0x2c) || (*pDM_Odm->pBandType == BAND_ON_2_4G))
8735                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
8736                                                 else
8737                                                 {
8738                                                         switch (TxRate)
8739                                                         {
8740                                                                 case MGN_VHT1SS_MCS6:
8741                                                                 case MGN_VHT1SS_MCS5:
8742                                                                 case MGN_MCS6:
8743                                                                 case MGN_MCS5:
8744                                                                 case MGN_48M:
8745                                                                 case MGN_54M:
8746                                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0x1ea42b);
8747                                                                 break;
8748                                                                 case MGN_VHT1SS_MCS4:
8749                                                                 case MGN_MCS4:
8750                                                                 case MGN_36M:
8751                                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa42b);
8752                                                                 break;
8753                                                                 case MGN_VHT1SS_MCS3:
8754                                                                 case MGN_MCS3:
8755                                                                 case MGN_24M:
8756                                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa47f);
8757                                                                 break;
8758                                                                 case MGN_VHT1SS_MCS2:
8759                                                                 case MGN_MCS2:
8760                                                                 case MGN_18M:
8761                                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa57f);
8762                                                                 break;
8763                                                                 case MGN_VHT1SS_MCS1:
8764                                                                 case MGN_MCS1:
8765                                                                 case MGN_9M:
8766                                                                 case MGN_12M:
8767                                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa77f);
8768                                                                 break;
8769                                                                 case MGN_VHT1SS_MCS0:
8770                                                                 case MGN_MCS0:
8771                                                                 case MGN_6M:
8772                                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa87f);
8773                                                                 break;
8774                                                                 default:
8775                                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
8776                                                                 break;
8777                                                         }
8778                                                 }
8779                                         }
8780                                 }
8781                                 else
8782                                 {
8783                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
8784                                 }
8785
8786                         }
8787                         else if (IS_HARDWARE_TYPE_8812AU(Adapter)){
8788                                 if(pMgntInfo->RegTxDutyEnable)
8789                                 {
8790                                         //2013.07.26 Wilson: debug for 8812AU thermal issue (reduce Tx duty cycle)
8791                                         // it;s the same issue as 8811AU
8792                                         if(!pMgntInfo->ForcedDataRate) //auto rate
8793                                         {
8794                                                 if(pDM_Odm->TxRate != 0xFF)
8795                                                         TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate);
8796                                         }
8797                                         else //force rate
8798                                         {
8799                                                 TxRate = (u1Byte) pMgntInfo->ForcedDataRate;
8800                                         }
8801
8802                                         value64 = (curRxOkCnt<<2);
8803                                         if(curTxOkCnt < value64) //Downlink
8804                                                 ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
8805                                         else //Uplink
8806                                         {
8807                                                 //DbgPrint("pDM_Odm->RFCalibrateInfo.ThermalValue = 0x%X\n", pDM_Odm->RFCalibrateInfo.ThermalValue);
8808                                                 //if(pDM_Odm->RFCalibrateInfo.ThermalValue < pHalData->EEPROMThermalMeter)
8809                                                 if((pDM_Odm->RFCalibrateInfo.ThermalValue < 0x2c) || (*pDM_Odm->pBandType == BAND_ON_2_4G))
8810                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
8811                                                 else
8812                                                 {
8813                                                         switch (TxRate)
8814                                                         {
8815                                                                 case MGN_VHT2SS_MCS9:
8816                                                                 case MGN_VHT1SS_MCS9:
8817                                                                 case MGN_VHT1SS_MCS8:
8818                                                                 case MGN_MCS15:
8819                                                                 case MGN_MCS7:
8820                                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0x1ea44f);
8821                                                                 case MGN_VHT2SS_MCS8:
8822                                                                 case MGN_VHT1SS_MCS7:
8823                                                                 case MGN_MCS14:
8824                                                                 case MGN_MCS6:
8825                                                                 case MGN_54M:
8826                                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa44f);
8827                                                                 case MGN_VHT2SS_MCS7:
8828                                                                 case MGN_VHT2SS_MCS6:
8829                                                                 case MGN_VHT1SS_MCS6:
8830                                                                 case MGN_VHT1SS_MCS5:
8831                                                                 case MGN_MCS13:
8832                                                                 case MGN_MCS5:
8833                                                                 case MGN_48M:
8834                                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa630);
8835                                                                 break;
8836                                                                 case MGN_VHT2SS_MCS5:
8837                                                                 case MGN_VHT2SS_MCS4:
8838                                                                 case MGN_VHT1SS_MCS4:
8839                                                                 case MGN_VHT1SS_MCS3:
8840                                                                 case MGN_MCS12:
8841                                                                 case MGN_MCS4:
8842                                                                 case MGN_MCS3:
8843                                                                 case MGN_36M:
8844                                                                 case MGN_24M:
8845                                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa730);
8846                                                                 break;
8847                                                                 case MGN_VHT2SS_MCS3:
8848                                                                 case MGN_VHT2SS_MCS2:
8849                                                                 case MGN_VHT2SS_MCS1:
8850                                                                 case MGN_VHT1SS_MCS2:
8851                                                                 case MGN_VHT1SS_MCS1:
8852                                                                 case MGN_MCS11:
8853                                                                 case MGN_MCS10:
8854                                                                 case MGN_MCS9:
8855                                                                 case MGN_MCS2:
8856                                                                 case MGN_MCS1:
8857                                                                 case MGN_18M:
8858                                                                 case MGN_12M:
8859                                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa830);
8860                                                                 break;
8861                                                                 case MGN_VHT2SS_MCS0:
8862                                                                 case MGN_VHT1SS_MCS0:
8863                                                                 case MGN_MCS0:
8864                                                                 case MGN_MCS8:
8865                                                                 case MGN_9M:
8866                                                                 case MGN_6M:
8867                                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa87f);
8868                                                                 break;
8869                                                                 default:
8870                                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
8871                                                                 break;
8872                                                         }
8873                                                 }
8874                                         }
8875                                 }
8876                                 else
8877                                 {
8878                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
8879                                 }
8880                         }
8881                         else
8882                                 ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
8883
8884                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EDCA Turbo on: EDCA_BE:0x%lx\n",EDCA_BE));
8885
8886                 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = TRUE;
8887
8888                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EDCA_BE_DL : 0x%lx  EDCA_BE_UL : 0x%lx  EDCA_BE : 0x%lx  \n",EDCA_BE_DL,EDCA_BE_UL,EDCA_BE));
8889
8890         }
8891         else
8892         {
8893                 // Turn Off EDCA turbo here.
8894                 // Restore original EDCA according to the declaration of AP.
8895                  if(pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)
8896                 {
8897                         Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AC_PARAM, GET_WMM_PARAM_ELE_SINGLE_AC_PARAM(pStaQos->WMMParamEle, AC0_BE) );
8898
8899                         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE;
8900                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Restore EDCA BE: 0x%lx  \n",pDM_Odm->WMMEDCA_BE));
8901
8902                 }
8903         }
8904
8905 ////===============================
8906 ////Set variables for next time.
8907 ////===============================
8908 dm_CheckEdcaTurbo_EXIT:
8909 #if (DM_ODM_SUPPORT_TYPE==ODM_WIN)
8910         pHalData->bIsAnyNonBEPkts = FALSE;
8911         pMgntInfo->lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast;
8912         pMgntInfo->lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast;
8913         pMgntInfo->Ext_lastTxOkCnt = pExtAdapter->TxStats.NumTxBytesUnicast;
8914         pMgntInfo->Ext_lastRxOkCnt = pExtAdapter->RxStats.NumRxBytesUnicast;
8915 #elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
8916         precvpriv->bIsAnyNonBEPkts = FALSE;
8917         pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes;
8918         precvpriv->last_rx_bytes = precvpriv->rx_bytes;
8919 #endif
8920
8921 }
8922
8923
8924 //check if edca turbo is disabled
8925 BOOLEAN
8926 odm_IsEdcaTurboDisable(
8927         IN      PDM_ODM_T       pDM_Odm
8928 )
8929 {
8930         PADAPTER                       Adapter = pDM_Odm->Adapter;
8931
8932 #if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
8933         PMGNT_INFO                      pMgntInfo = &Adapter->MgntInfo;
8934         u4Byte                          IOTPeer=pMgntInfo->IOTPeer;
8935 #elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
8936         struct registry_priv    *pregpriv = &Adapter->registrypriv;
8937         struct mlme_ext_priv    *pmlmeext = &(Adapter->mlmeextpriv);
8938         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
8939         u4Byte                         IOTPeer=pmlmeinfo->assoc_AP_vendor;
8940         u1Byte                         WirelessMode=0xFF;                   //invalid value
8941
8942         if(pDM_Odm->pWirelessMode!=NULL)
8943                 WirelessMode=*(pDM_Odm->pWirelessMode);
8944
8945 #endif
8946
8947         if(pDM_Odm->bBtDisableEdcaTurbo)
8948         {
8949                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("EdcaTurboDisable for BT!!\n"));
8950                 return TRUE;
8951         }
8952
8953         if((!(pDM_Odm->SupportAbility& ODM_MAC_EDCA_TURBO ))||
8954                 (pDM_Odm->bWIFITest)||
8955                 (IOTPeer>= HT_IOT_PEER_MAX))
8956         {
8957                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("EdcaTurboDisable\n"));
8958                 return TRUE;
8959         }
8960
8961
8962 #if (DM_ODM_SUPPORT_TYPE ==ODM_WIN)
8963         // 1. We do not turn on EDCA turbo mode for some AP that has IOT issue
8964         // 2. User may disable EDCA Turbo mode with OID settings.
8965         if(pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO){
8966                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("IOTAction:EdcaTurboDisable\n"));
8967                 return  TRUE;
8968                 }
8969
8970 #elif(DM_ODM_SUPPORT_TYPE==ODM_CE)
8971         //suggested by Jr.Luke: open TXOP for B/G/BG/A mode 2012-0215
8972         if((WirelessMode==ODM_WM_B)||(WirelessMode==(ODM_WM_B|ODM_WM_G)||(WirelessMode==ODM_WM_G)||(WirelessMode=ODM_WM_A))
8973                 ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, ODM_Read4Byte(pDM_Odm, ODM_EDCA_BE_PARAM)|0x5E0000);
8974
8975         if(pDM_Odm->SupportICType==ODM_RTL8192D)                {
8976                 if ((pregpriv->wifi_spec == 1)  || (pmlmeext->cur_wireless_mode == WIRELESS_11B)) {
8977                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("92D:EdcaTurboDisable\n"));
8978                         return TRUE;
8979                 }
8980         }
8981         else
8982         {
8983                 if((pregpriv->wifi_spec == 1) || (pmlmeinfo->HT_enable == 0)){
8984                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("Others:EdcaTurboDisable\n"));
8985                         return TRUE;
8986                 }
8987         }
8988
8989 #endif
8990
8991         return  FALSE;
8992
8993
8994 }
8995
8996 //add iot case here: for MP/CE
8997 VOID
8998 ODM_EdcaParaSelByIot(
8999         IN      PDM_ODM_T       pDM_Odm,
9000         OUT     u4Byte          *EDCA_BE_UL,
9001         OUT u4Byte              *EDCA_BE_DL
9002         )
9003 {
9004
9005         PADAPTER                       Adapter = pDM_Odm->Adapter;
9006         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
9007         u4Byte                         IOTPeer=0;
9008         u4Byte                         ICType=pDM_Odm->SupportICType;
9009         u1Byte                         WirelessMode=0xFF;                   //invalid value
9010         u4Byte                          RFType=pDM_Odm->RFType;
9011           u4Byte                         IOTPeerSubType=0;
9012
9013 #if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
9014         PMGNT_INFO                      pMgntInfo = &Adapter->MgntInfo;
9015         u1Byte                          TwoPortStatus = (u1Byte)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE;
9016
9017 #elif(DM_ODM_SUPPORT_TYPE==ODM_CE)
9018         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
9019         #ifdef CONFIG_BT_COEXIST
9020         struct btcoexist_priv   *pbtpriv = &(pHalData->bt_coexist);
9021         #endif
9022        u1Byte bbtchange =FALSE;
9023 #endif
9024
9025         if(pDM_Odm->pWirelessMode!=NULL)
9026                 WirelessMode=*(pDM_Odm->pWirelessMode);
9027
9028 ///////////////////////////////////////////////////////////
9029 ////list paramter for different platform
9030 #if (DM_ODM_SUPPORT_TYPE==ODM_WIN)
9031         IOTPeer=pMgntInfo->IOTPeer;
9032         IOTPeerSubType=pMgntInfo->IOTPeerSubtype;
9033         GetTwoPortSharedResource(Adapter,TWO_PORT_SHARED_OBJECT__STATUS,NULL,&TwoPortStatus);
9034
9035 #elif(DM_ODM_SUPPORT_TYPE==ODM_CE)
9036         IOTPeer=pmlmeinfo->assoc_AP_vendor;
9037         #ifdef CONFIG_BT_COEXIST
9038         if(pbtpriv->BT_Coexist)
9039         {
9040                 if( (pbtpriv->BT_EDCA[UP_LINK]!=0) ||  (pbtpriv->BT_EDCA[DOWN_LINK]!=0))
9041                         bbtchange = TRUE;
9042         }
9043         #endif
9044
9045 #endif
9046
9047         if(ICType==ODM_RTL8192D)
9048         {
9049                 // Single PHY
9050                 if(pDM_Odm->RFType==ODM_2T2R)
9051                 {
9052                         (*EDCA_BE_UL) = 0x60a42b;    //0x5ea42b;
9053                         (*EDCA_BE_DL) = 0x60a42b;    //0x5ea42b;
9054
9055                 }
9056                 else
9057                 {
9058                         (*EDCA_BE_UL) = 0x6ea42b;
9059                         (*EDCA_BE_DL) = 0x6ea42b;
9060                 }
9061
9062         }
9063 ////============================
9064 /// IOT case for MP
9065 ////============================
9066 #if (DM_ODM_SUPPORT_TYPE==ODM_WIN)
9067         else
9068         {
9069
9070                 if(pDM_Odm->SupportInterface==ODM_ITRF_PCIE){
9071                         if((ICType==ODM_RTL8192C)&&(pDM_Odm->RFType==ODM_2T2R))                 {
9072                                 (*EDCA_BE_UL) = 0x60a42b;
9073                                 (*EDCA_BE_DL) = 0x60a42b;
9074                         }
9075                         else
9076                         {
9077                                 (*EDCA_BE_UL) = 0x6ea42b;
9078                                 (*EDCA_BE_DL) = 0x6ea42b;
9079                         }
9080                 }
9081         }
9082
9083         if(TwoPortStatus == TWO_PORT_STATUS__EXTENSION_ONLY)
9084         {
9085                 (*EDCA_BE_UL) = 0x5ea42b;//Parameter suggested by Scott  //edca_setting_UL[ExtAdapter->MgntInfo.IOTPeer];
9086                 (*EDCA_BE_DL) = 0x5ea42b;//Parameter suggested by Scott  //edca_setting_DL[ExtAdapter->MgntInfo.IOTPeer];
9087         }
9088
9089         #if (INTEL_PROXIMITY_SUPPORT == 1)
9090         if(pMgntInfo->IntelClassModeInfo.bEnableCA == TRUE)
9091         {
9092                 (*EDCA_BE_UL) = (*EDCA_BE_DL) = 0xa44f;
9093         }
9094         else
9095         #endif
9096         {
9097                 if((!pMgntInfo->bDisableFrameBursting) &&
9098                         (pMgntInfo->IOTAction & (HT_IOT_ACT_FORCED_ENABLE_BE_TXOP|HT_IOT_ACT_AMSDU_ENABLE)))
9099                 {// To check whether we shall force turn on TXOP configuration.
9100                         if(!((*EDCA_BE_UL) & 0xffff0000))
9101                                 (*EDCA_BE_UL) |= 0x005e0000; // Force TxOP limit to 0x005e for UL.
9102                         if(!((*EDCA_BE_DL) & 0xffff0000))
9103                                 (*EDCA_BE_DL) |= 0x005e0000; // Force TxOP limit to 0x005e for DL.
9104                 }
9105
9106                 //92D txop can't be set to 0x3e for cisco1250
9107                 if((ICType!=ODM_RTL8192D) && (IOTPeer== HT_IOT_PEER_CISCO) &&(WirelessMode==ODM_WM_N24G))
9108                 {
9109                         (*EDCA_BE_DL) = edca_setting_DL[IOTPeer];
9110                         (*EDCA_BE_UL) = edca_setting_UL[IOTPeer];
9111                 }
9112                 //merge from 92s_92c_merge temp brunch v2445    20120215
9113                 else if((IOTPeer == HT_IOT_PEER_CISCO) &&((WirelessMode==ODM_WM_G)||(WirelessMode==(ODM_WM_B|ODM_WM_G))||(WirelessMode==ODM_WM_A)||(WirelessMode==ODM_WM_B)))
9114                 {
9115                         (*EDCA_BE_DL) = edca_setting_DL_GMode[IOTPeer];
9116                 }
9117                 else if((IOTPeer== HT_IOT_PEER_AIRGO )&& ((WirelessMode==ODM_WM_G)||(WirelessMode==ODM_WM_A)))
9118                 {
9119                         (*EDCA_BE_DL) = 0xa630;
9120                 }
9121
9122                 else if(IOTPeer == HT_IOT_PEER_MARVELL)
9123                 {
9124                         (*EDCA_BE_DL) = edca_setting_DL[IOTPeer];
9125                         (*EDCA_BE_UL) = edca_setting_UL[IOTPeer];
9126                 }
9127                 else if(IOTPeer == HT_IOT_PEER_ATHEROS)
9128                 {
9129                         // Set DL EDCA for Atheros peer to 0x3ea42b. Suggested by SD3 Wilson for ASUS TP issue.
9130                         (*EDCA_BE_DL) = edca_setting_DL[IOTPeer];
9131
9132                         if(ICType == ODM_RTL8821)
9133                                  (*EDCA_BE_DL) = 0x5ea630;
9134
9135                 }
9136         }
9137
9138         if((ICType == ODM_RTL8192D)&&(IOTPeerSubType == HT_IOT_PEER_LINKSYS_E4200_V1)&&((WirelessMode==ODM_WM_N5G)))
9139         {
9140                 (*EDCA_BE_DL) = 0x432b;
9141                 (*EDCA_BE_UL) = 0x432b;
9142         }
9143
9144
9145
9146         if((ICType==ODM_RTL8812)||(ICType==ODM_RTL8192E))           //add 8812AU/8812AE
9147         {
9148                 (*EDCA_BE_UL) = 0x5ea42b;
9149                 (*EDCA_BE_DL) = 0x5ea42b;
9150
9151                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("8812A: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx",(*EDCA_BE_UL),(*EDCA_BE_DL)));
9152         }
9153
9154         // Revised for Atheros DIR-655 IOT issue to improve down link TP, added by Roger, 2013.03.22.
9155         if((ICType == ODM_RTL8723A) && (IOTPeerSubType== HT_IOT_PEER_ATHEROS_DIR655) &&
9156                 (pMgntInfo->dot11CurrentChannelNumber == 6))
9157         {
9158                 (*EDCA_BE_DL) = 0xa92b;
9159         }
9160
9161 ////============================
9162 /// IOT case for CE
9163 ////============================
9164 #elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
9165
9166         if(RFType==ODM_RTL8192D)
9167         {
9168                 if((IOTPeer == HT_IOT_PEER_CISCO) &&(WirelessMode==ODM_WM_N24G))
9169                 {
9170                         (*EDCA_BE_UL) = EDCAParam[IOTPeer][UP_LINK];
9171                         (*EDCA_BE_DL)=EDCAParam[IOTPeer][DOWN_LINK];
9172                 }
9173                 else if((IOTPeer == HT_IOT_PEER_AIRGO) &&
9174                         ((WirelessMode==ODM_WM_B)||(WirelessMode==(ODM_WM_B|ODM_WM_G))))
9175                         (*EDCA_BE_DL)=0x00a630;
9176
9177                 else if((IOTPeer== HT_IOT_PEER_ATHEROS) &&
9178                                         (WirelessMode&ODM_WM_N5G) &&
9179                                         (Adapter->securitypriv.dot11PrivacyAlgrthm == _AES_ ))
9180                         (*EDCA_BE_DL)=0xa42b;
9181
9182         }
9183         //92C IOT case:
9184         else
9185         {
9186                 #ifdef CONFIG_BT_COEXIST
9187                 if(bbtchange)
9188                 {
9189                         (*EDCA_BE_UL) = pbtpriv->BT_EDCA[UP_LINK];
9190                         (*EDCA_BE_DL) = pbtpriv->BT_EDCA[DOWN_LINK];
9191                 }
9192                 else
9193                 #endif
9194                 {
9195                         if((IOTPeer == HT_IOT_PEER_CISCO) &&(WirelessMode==ODM_WM_N24G))
9196                         {
9197                                 (*EDCA_BE_UL) = EDCAParam[IOTPeer][UP_LINK];
9198                                 (*EDCA_BE_DL)=EDCAParam[IOTPeer][DOWN_LINK];
9199                         }
9200                         else
9201                         {
9202                                 (*EDCA_BE_UL)=EDCAParam[HT_IOT_PEER_UNKNOWN][UP_LINK];
9203                                 (*EDCA_BE_DL)=EDCAParam[HT_IOT_PEER_UNKNOWN][DOWN_LINK];
9204                         }
9205                 }
9206                 if(pDM_Odm->SupportInterface==ODM_ITRF_PCIE){
9207                         if((ICType==ODM_RTL8192C)&&(pDM_Odm->RFType==ODM_2T2R))
9208                         {
9209                                 (*EDCA_BE_UL) = 0x60a42b;
9210                                 (*EDCA_BE_DL) = 0x60a42b;
9211                         }
9212                         else
9213                         {
9214                                 (*EDCA_BE_UL) = 0x6ea42b;
9215                                 (*EDCA_BE_DL) = 0x6ea42b;
9216                         }
9217                 }
9218
9219         }
9220 #endif
9221
9222         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Special: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx",(*EDCA_BE_UL),(*EDCA_BE_DL)));
9223
9224 }
9225
9226
9227 VOID
9228 odm_EdcaChooseTrafficIdx(
9229         IN      PDM_ODM_T               pDM_Odm,
9230         IN      u8Byte                          cur_tx_bytes,
9231         IN      u8Byte                          cur_rx_bytes,
9232         IN      BOOLEAN                 bBiasOnRx,
9233         OUT BOOLEAN             *pbIsCurRDLState
9234         )
9235 {
9236
9237
9238         if(bBiasOnRx)
9239         {
9240
9241                 if(cur_tx_bytes>(cur_rx_bytes*4))
9242                 {
9243                         *pbIsCurRDLState=FALSE;
9244                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Uplink Traffic\n "));
9245
9246                 }
9247                 else
9248                 {
9249                         *pbIsCurRDLState=TRUE;
9250                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Balance Traffic\n"));
9251
9252                 }
9253         }
9254         else
9255         {
9256                 if(cur_rx_bytes>(cur_tx_bytes*4))
9257                 {
9258                         *pbIsCurRDLState=TRUE;
9259                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Downlink        Traffic\n"));
9260
9261                 }
9262                 else
9263                 {
9264                         *pbIsCurRDLState=FALSE;
9265                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Balance Traffic\n"));
9266                 }
9267         }
9268
9269         return ;
9270 }
9271
9272 #endif
9273
9274 #if((DM_ODM_SUPPORT_TYPE==ODM_AP)||(DM_ODM_SUPPORT_TYPE==ODM_ADSL))
9275
9276 void odm_EdcaParaInit(
9277         IN      PDM_ODM_T       pDM_Odm
9278         )
9279 {
9280         prtl8192cd_priv priv            = pDM_Odm->priv;
9281         int   mode=priv->pmib->dot11BssType.net_work_type;
9282
9283         static unsigned int slot_time, VO_TXOP, VI_TXOP, sifs_time;
9284         struct ParaRecord EDCA[4];
9285
9286          memset(EDCA, 0, 4*sizeof(struct ParaRecord));
9287
9288         sifs_time = 10;
9289         slot_time = 20;
9290
9291         if (mode & (ODM_WM_N24G|ODM_WM_N5G))
9292                 sifs_time = 16;
9293
9294         if (mode & (ODM_WM_N24G|ODM_WM_N5G| ODM_WM_G|ODM_WM_A))
9295                 slot_time = 9;
9296
9297
9298 #if((defined(RTL_MANUAL_EDCA))&&(DM_ODM_SUPPORT_TYPE==ODM_AP))
9299          if( priv->pmib->dot11QosEntry.ManualEDCA ) {
9300                  if( OPMODE & WIFI_AP_STATE )
9301                          memcpy(EDCA, priv->pmib->dot11QosEntry.AP_manualEDCA, 4*sizeof(struct ParaRecord));
9302                  else
9303                          memcpy(EDCA, priv->pmib->dot11QosEntry.STA_manualEDCA, 4*sizeof(struct ParaRecord));
9304
9305                 #ifdef WIFI_WMM
9306                 if (QOS_ENABLE)
9307                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, (EDCA[VI].TXOPlimit<< 16) | (EDCA[VI].ECWmax<< 12) | (EDCA[VI].ECWmin<< 8) | (sifs_time + EDCA[VI].AIFSN* slot_time));
9308                 else
9309                 #endif
9310                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, (EDCA[BE].TXOPlimit<< 16) | (EDCA[BE].ECWmax<< 12) | (EDCA[BE].ECWmin<< 8) | (sifs_time + EDCA[VI].AIFSN* slot_time));
9311
9312         }else
9313         #endif //RTL_MANUAL_EDCA
9314         {
9315
9316                  if(OPMODE & WIFI_AP_STATE)
9317                  {
9318                         memcpy(EDCA, rtl_ap_EDCA, 2*sizeof(struct ParaRecord));
9319
9320                         if(mode & (ODM_WM_A|ODM_WM_G|ODM_WM_N24G|ODM_WM_N5G))
9321                                 memcpy(&EDCA[VI], &rtl_ap_EDCA[VI_AG], 2*sizeof(struct ParaRecord));
9322                         else
9323                                 memcpy(&EDCA[VI], &rtl_ap_EDCA[VI], 2*sizeof(struct ParaRecord));
9324                  }
9325                  else
9326                  {
9327                         memcpy(EDCA, rtl_sta_EDCA, 2*sizeof(struct ParaRecord));
9328
9329                         if(mode & (ODM_WM_A|ODM_WM_G|ODM_WM_N24G|ODM_WM_N5G))
9330                                 memcpy(&EDCA[VI], &rtl_sta_EDCA[VI_AG], 2*sizeof(struct ParaRecord));
9331                         else
9332                                 memcpy(&EDCA[VI], &rtl_sta_EDCA[VI], 2*sizeof(struct ParaRecord));
9333                  }
9334
9335         #ifdef WIFI_WMM
9336                 if (QOS_ENABLE)
9337                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, (EDCA[VI].TXOPlimit<< 16) | (EDCA[VI].ECWmax<< 12) | (EDCA[VI].ECWmin<< 8) | (sifs_time + EDCA[VI].AIFSN* slot_time));
9338                 else
9339         #endif
9340
9341 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
9342                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM,  (EDCA[BK].ECWmax<< 12) | (EDCA[BK].ECWmin<< 8) | (sifs_time + EDCA[VI].AIFSN* slot_time));
9343 #elif(DM_ODM_SUPPORT_TYPE==ODM_ADSL)
9344                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM,  (EDCA[BK].ECWmax<< 12) | (EDCA[BK].ECWmin<< 8) | (sifs_time + 2* slot_time));
9345 #endif
9346
9347
9348         }
9349
9350         ODM_Write4Byte(pDM_Odm, ODM_EDCA_VO_PARAM, (EDCA[VO].TXOPlimit<< 16) | (EDCA[VO].ECWmax<< 12) | (EDCA[VO].ECWmin<< 8) | (sifs_time + EDCA[VO].AIFSN* slot_time));
9351         ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM,  (EDCA[BE].TXOPlimit<< 16) | (EDCA[BE].ECWmax<< 12) | (EDCA[BE].ECWmin<< 8) | (sifs_time + EDCA[BE].AIFSN* slot_time));
9352         ODM_Write4Byte(pDM_Odm, ODM_EDCA_BK_PARAM, (EDCA[BK].TXOPlimit<< 16) | (EDCA[BK].ECWmax<< 12) | (EDCA[BK].ECWmin<< 8) | (sifs_time + EDCA[BK].AIFSN* slot_time));
9353 //      ODM_Write1Byte(pDM_Odm,ACMHWCTRL, 0x00);
9354
9355         priv->pshare->iot_mode_enable = 0;
9356 #if(DM_ODM_SUPPORT_TYPE==ODM_AP)
9357         if (priv->pshare->rf_ft_var.wifi_beq_iot)
9358                 priv->pshare->iot_mode_VI_exist = 0;
9359
9360         #ifdef WMM_VIBE_PRI
9361         priv->pshare->iot_mode_BE_exist = 0;
9362         #endif
9363
9364         #ifdef LOW_TP_TXOP
9365         priv->pshare->BE_cwmax_enhance = 0;
9366         #endif
9367
9368 #elif (DM_ODM_SUPPORT_TYPE==ODM_ADSL)
9369       priv->pshare->iot_mode_BE_exist = 0;
9370 #endif
9371         priv->pshare->iot_mode_VO_exist = 0;
9372 }
9373
9374 BOOLEAN
9375 ODM_ChooseIotMainSTA(
9376         IN      PDM_ODM_T               pDM_Odm,
9377         IN      PSTA_INFO_T             pstat
9378         )
9379 {
9380         prtl8192cd_priv priv = pDM_Odm->priv;
9381         BOOLEAN         bhighTP_found_pstat=FALSE;
9382
9383         if ((GET_ROOT(priv)->up_time % 2) == 0) {
9384                 unsigned int tx_2s_avg = 0;
9385                 unsigned int rx_2s_avg = 0;
9386                 int i=0, aggReady=0;
9387                 unsigned long total_sum = (priv->pshare->current_tx_bytes+priv->pshare->current_rx_bytes);
9388
9389                 pstat->current_tx_bytes += pstat->tx_byte_cnt;
9390                 pstat->current_rx_bytes += pstat->rx_byte_cnt;
9391
9392                 if (total_sum != 0) {
9393                         if (total_sum <= 100) {
9394                         tx_2s_avg = (unsigned int)((pstat->current_tx_bytes*100) / total_sum);
9395                         rx_2s_avg = (unsigned int)((pstat->current_rx_bytes*100) / total_sum);
9396                         } else {
9397                                 tx_2s_avg = (unsigned int)(pstat->current_tx_bytes / (total_sum / 100));
9398                                 rx_2s_avg = (unsigned int)(pstat->current_rx_bytes / (total_sum / 100));
9399                         }
9400
9401                 }
9402
9403 #if(DM_ODM_SUPPORT_TYPE==ODM_ADSL)
9404                 if (pstat->ht_cap_len) {
9405                         if ((tx_2s_avg + rx_2s_avg) >=25 /*50*/) {
9406
9407                                         priv->pshare->highTP_found_pstat = pstat;
9408                                         bhighTP_found_pstat=TRUE;
9409                                 }
9410                         }
9411 #elif(DM_ODM_SUPPORT_TYPE==ODM_AP)
9412                 for(i=0; i<8; i++)
9413                         aggReady += (pstat->ADDBA_ready[i]);
9414                 if (pstat->ht_cap_len && aggReady)
9415                 {
9416                         if ((tx_2s_avg + rx_2s_avg >= 25)) {
9417                                 priv->pshare->highTP_found_pstat = pstat;
9418                         }
9419
9420                 #ifdef CLIENT_MODE
9421                         if (OPMODE & WIFI_STATION_STATE) {
9422 #if (DM_ODM_SUPPORT_TYPE &ODM_AP) && defined(USE_OUT_SRC)
9423                                 if ((pstat->IOTPeer==HT_IOT_PEER_RALINK) && ((tx_2s_avg + rx_2s_avg) >= 45))
9424 #else
9425                                 if(pstat->is_ralink_sta && ((tx_2s_avg + rx_2s_avg) >= 45))
9426 #endif
9427                                         priv->pshare->highTP_found_pstat = pstat;
9428                 }
9429                 #endif
9430         }
9431 #endif
9432         } else {
9433                 pstat->current_tx_bytes = pstat->tx_byte_cnt;
9434                 pstat->current_rx_bytes = pstat->rx_byte_cnt;
9435         }
9436
9437         return bhighTP_found_pstat;
9438 }
9439
9440
9441 #ifdef WIFI_WMM
9442 VOID
9443 ODM_IotEdcaSwitch(
9444         IN      PDM_ODM_T               pDM_Odm,
9445         IN      unsigned char           enable
9446         )
9447 {
9448         prtl8192cd_priv priv    = pDM_Odm->priv;
9449         int   mode=priv->pmib->dot11BssType.net_work_type;
9450         unsigned int slot_time = 20, sifs_time = 10, BE_TXOP = 47, VI_TXOP = 94;
9451         unsigned int vi_cw_max = 4, vi_cw_min = 3, vi_aifs;
9452
9453 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
9454         if (!(!priv->pmib->dot11OperationEntry.wifi_specific ||
9455                 ((OPMODE & WIFI_AP_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2))
9456         #ifdef CLIENT_MODE
9457                 || ((OPMODE & WIFI_STATION_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2))
9458         #endif
9459                 ))
9460                 return;
9461 #endif
9462
9463         if ((mode & (ODM_WM_N24G|ODM_WM_N5G)) && (priv->pshare->ht_sta_num
9464         #ifdef WDS
9465                 || ((OPMODE & WIFI_AP_STATE) && priv->pmib->dot11WdsInfo.wdsEnabled && priv->pmib->dot11WdsInfo.wdsNum)
9466         #endif
9467                 ))
9468                 sifs_time = 16;
9469
9470         if (mode & (ODM_WM_N24G|ODM_WM_N5G|ODM_WM_G|ODM_WM_A)) {
9471                 slot_time = 9;
9472         }
9473         else
9474         {
9475                 BE_TXOP = 94;
9476                 VI_TXOP = 188;
9477         }
9478
9479 #if (DM_ODM_SUPPORT_TYPE==ODM_ADSL)
9480         if (priv->pshare->iot_mode_VO_exist) {
9481                 // to separate AC_VI and AC_BE to avoid using the same EDCA settings
9482                 if (priv->pshare->iot_mode_BE_exist) {
9483                         vi_cw_max = 5;
9484                         vi_cw_min = 3;
9485                 } else {
9486                         vi_cw_max = 6;
9487                         vi_cw_min = 4;
9488                 }
9489         }
9490         vi_aifs = (sifs_time + ((OPMODE & WIFI_AP_STATE)?1:2) * slot_time);
9491
9492         ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, ((VI_TXOP*(1-priv->pshare->iot_mode_VO_exist)) << 16)| (vi_cw_max << 12) | (vi_cw_min << 8) | vi_aifs);
9493
9494
9495 #elif (DM_ODM_SUPPORT_TYPE==ODM_AP)
9496         if ((OPMODE & WIFI_AP_STATE) && priv->pmib->dot11OperationEntry.wifi_specific) {
9497                 if (priv->pshare->iot_mode_VO_exist) {
9498         #ifdef WMM_VIBE_PRI
9499                         if (priv->pshare->iot_mode_BE_exist)
9500                         {
9501                                 vi_cw_max = 5;
9502                                 vi_cw_min = 3;
9503                                 vi_aifs = (sifs_time + ((OPMODE & WIFI_AP_STATE)?1:2) * slot_time);
9504                         }
9505                         else
9506         #endif
9507                         {
9508                         vi_cw_max = 6;
9509                         vi_cw_min = 4;
9510                         vi_aifs = 0x2b;
9511                         }
9512                 }
9513                 else {
9514                         vi_aifs = (sifs_time + ((OPMODE & WIFI_AP_STATE)?1:2) * slot_time);
9515                 }
9516
9517                 ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, ((VI_TXOP*(1-priv->pshare->iot_mode_VO_exist)) << 16)
9518                         | (vi_cw_max << 12) | (vi_cw_min << 8) | vi_aifs);
9519         }
9520 #endif
9521
9522
9523
9524 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
9525         if (priv->pshare->rf_ft_var.wifi_beq_iot && priv->pshare->iot_mode_VI_exist)
9526                 ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (10 << 12) | (4 << 8) | 0x4f);
9527         else if(!enable)
9528 #elif(DM_ODM_SUPPORT_TYPE==ODM_ADSL)
9529         if(!enable)                                 //if iot is disable ,maintain original BEQ PARAM
9530 #endif
9531                 ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (((OPMODE & WIFI_AP_STATE)?6:10) << 12) | (4 << 8)
9532                         | (sifs_time + 3 * slot_time));
9533         else
9534         {
9535                 int txop_enlarge;
9536                 int txop;
9537                 unsigned int cw_max;
9538                 unsigned int txop_close;
9539
9540         #if((DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined LOW_TP_TXOP))
9541                         cw_max = ((priv->pshare->BE_cwmax_enhance) ? 10 : 6);
9542                         txop_close = ((priv->pshare->rf_ft_var.low_tp_txop && priv->pshare->rf_ft_var.low_tp_txop_close) ? 1 : 0);
9543
9544                         if(priv->pshare->txop_enlarge == 0xe)   //if intel case
9545                                 txop = (txop_close ? 0 : (BE_TXOP*2));
9546                         else                                                        //if other case
9547                                 txop = (txop_close ? 0: (BE_TXOP*priv->pshare->txop_enlarge));
9548         #else
9549                         cw_max=6;
9550                         if((priv->pshare->txop_enlarge==0xe)||(priv->pshare->txop_enlarge==0xd))
9551                                 txop=BE_TXOP*2;
9552                         else
9553                                 txop=BE_TXOP*priv->pshare->txop_enlarge;
9554
9555         #endif
9556
9557                 if (priv->pshare->ht_sta_num
9558         #ifdef WDS
9559                         || ((OPMODE & WIFI_AP_STATE) && (mode & (ODM_WM_N24G|ODM_WM_N5G)) &&
9560                         priv->pmib->dot11WdsInfo.wdsEnabled && priv->pmib->dot11WdsInfo.wdsNum)
9561         #endif
9562                         )
9563                         {
9564
9565                         if (priv->pshare->txop_enlarge == 0xe) {
9566                                 // is intel client, use a different edca value
9567                                 ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (txop<< 16) | (cw_max<< 12) | (4 << 8) | 0x1f);
9568                                 priv->pshare->txop_enlarge = 2;
9569                         }
9570 #if(DM_ODM_SUPPORT_TYPE==ODM_AP)
9571         #ifndef LOW_TP_TXOP
9572                          else if (priv->pshare->txop_enlarge == 0xd) {
9573                                 // is intel ralink, use a different edca value
9574                                 ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (txop << 16) | (4 << 12) | (3 << 8) | 0x19);
9575                                 priv->pshare->txop_enlarge = 2;
9576                         }
9577         #endif
9578 #endif
9579                         else
9580                         {
9581                                 if (pDM_Odm->RFType==ODM_2T2R)
9582                                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (txop << 16) |
9583                                                 (cw_max << 12) | (4 << 8) | (sifs_time + 3 * slot_time));
9584                                 else
9585                                 #if(DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined LOW_TP_TXOP)
9586                                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (txop << 16) |
9587                                                 (((priv->pshare->BE_cwmax_enhance) ? 10 : 5) << 12) | (3 << 8) | (sifs_time + 2 * slot_time));
9588                                 #else
9589                                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (txop << 16) |
9590                                                 (5 << 12) | (3 << 8) | (sifs_time + 2 * slot_time));
9591
9592                                 #endif
9593                         }
9594                 }
9595               else
9596               {
9597  #if((DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined LOW_TP_TXOP))
9598                          ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (BE_TXOP << 16) | (cw_max << 12) | (4 << 8) | (sifs_time + 3 * slot_time));
9599  #else
9600                 #if defined(CONFIG_RTL_8196D) || defined(CONFIG_RTL_8196E) || (defined(CONFIG_RTL_8197D) && !defined(CONFIG_PORT0_EXT_GIGA))
9601                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM,  (BE_TXOP*2 << 16) | (cw_max << 12) | (5 << 8) | (sifs_time + 3 * slot_time));
9602                 #else
9603                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM,  (BE_TXOP*2 << 16) | (cw_max << 12) | (4 << 8) | (sifs_time + 3 * slot_time));
9604                 #endif
9605
9606  #endif
9607               }
9608
9609         }
9610 }
9611 #endif
9612
9613 VOID
9614 odm_IotEngine(
9615         IN      PDM_ODM_T       pDM_Odm
9616         )
9617 {
9618
9619         struct rtl8192cd_priv *priv=pDM_Odm->priv;
9620         PSTA_INFO_T pstat = NULL;
9621         u4Byte i;
9622
9623 #ifdef WIFI_WMM
9624         unsigned int switch_turbo = 0;
9625 #endif
9626 ////////////////////////////////////////////////////////
9627 //  if EDCA Turbo function is not supported or Manual EDCA Setting
9628 //  then return
9629 ////////////////////////////////////////////////////////
9630         if(!(pDM_Odm->SupportAbility&ODM_MAC_EDCA_TURBO)){
9631                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("ODM_MAC_EDCA_TURBO NOT SUPPORTED\n"));
9632                 return;
9633         }
9634
9635 #if((DM_ODM_SUPPORT_TYPE==ODM_AP)&& defined(RTL_MANUAL_EDCA) && defined(WIFI_WMM))
9636         if(priv->pmib->dot11QosEntry.ManualEDCA){
9637                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("ODM_MAC_EDCA_TURBO OFF: MANUAL SETTING\n"));
9638                 return ;
9639         }
9640 #endif
9641
9642 #if !(DM_ODM_SUPPORT_TYPE &ODM_AP)
9643  //////////////////////////////////////////////////////
9644  //find high TP STA every 2s
9645 //////////////////////////////////////////////////////
9646         if ((GET_ROOT(priv)->up_time % 2) == 0)
9647                 priv->pshare->highTP_found_pstat==NULL;
9648
9649 #if 0
9650         phead = &priv->asoc_list;
9651         plist = phead->next;
9652         while(plist != phead)   {
9653                 pstat = list_entry(plist, struct stat_info, asoc_list);
9654
9655                 if(ODM_ChooseIotMainSTA(pDM_Odm, pstat));              //find the correct station
9656                         break;
9657                 if (plist == plist->next)                                          //the last plist
9658                         break;
9659                 plist = plist->next;
9660         };
9661 #endif
9662
9663         //find highTP STA
9664         for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++) {
9665                 pstat = pDM_Odm->pODM_StaInfo[i];
9666                 if(IS_STA_VALID(pstat) && (ODM_ChooseIotMainSTA(pDM_Odm, pstat)))        //find the correct station
9667                                 break;
9668         }
9669
9670  //////////////////////////////////////////////////////
9671  //if highTP STA is not found, then return
9672  //////////////////////////////////////////////////////
9673         if(priv->pshare->highTP_found_pstat==NULL)      {
9674                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("ODM_MAC_EDCA_TURBO OFF: NO HT STA FOUND\n"));
9675                 return;
9676         }
9677 #endif
9678
9679         pstat=priv->pshare->highTP_found_pstat;
9680
9681
9682 #ifdef WIFI_WMM
9683         if (QOS_ENABLE) {
9684                 if (!priv->pmib->dot11OperationEntry.wifi_specific
9685                 #if(DM_ODM_SUPPORT_TYPE==ODM_AP)
9686                         ||((OPMODE & WIFI_AP_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2))
9687                 #elif(DM_ODM_SUPPORT_TYPE==ODM_ADSL)
9688                         || (priv->pmib->dot11OperationEntry.wifi_specific == 2)
9689                 #endif
9690                         ) {
9691                         if (priv->pshare->iot_mode_enable &&
9692                                 ((priv->pshare->phw->VO_pkt_count > 50) ||
9693                                  (priv->pshare->phw->VI_pkt_count > 50) ||
9694                                  (priv->pshare->phw->BK_pkt_count > 50))) {
9695                                 priv->pshare->iot_mode_enable = 0;
9696                                 switch_turbo++;
9697                         } else if ((!priv->pshare->iot_mode_enable) &&
9698                                 ((priv->pshare->phw->VO_pkt_count < 50) &&
9699                                  (priv->pshare->phw->VI_pkt_count < 50) &&
9700                                  (priv->pshare->phw->BK_pkt_count < 50))) {
9701                                 priv->pshare->iot_mode_enable++;
9702                                 switch_turbo++;
9703                         }
9704                 }
9705
9706
9707                 #if(DM_ODM_SUPPORT_TYPE==ODM_AP)
9708                 if ((OPMODE & WIFI_AP_STATE) && priv->pmib->dot11OperationEntry.wifi_specific)
9709                 #elif (DM_ODM_SUPPORT_TYPE==ODM_ADSL)
9710                 if (priv->pmib->dot11OperationEntry.wifi_specific)
9711                 #endif
9712                 {
9713                         if (!priv->pshare->iot_mode_VO_exist && (priv->pshare->phw->VO_pkt_count > 50)) {
9714                                 priv->pshare->iot_mode_VO_exist++;
9715                                 switch_turbo++;
9716                         } else if (priv->pshare->iot_mode_VO_exist && (priv->pshare->phw->VO_pkt_count < 50)) {
9717                                 priv->pshare->iot_mode_VO_exist = 0;
9718                                 switch_turbo++;
9719                         }
9720 #if((DM_ODM_SUPPORT_TYPE==ODM_ADSL)||((DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined WMM_VIBE_PRI)))
9721                         if (priv->pshare->iot_mode_VO_exist) {
9722                                 //printk("[%s %d] BE_pkt_count=%d\n", __FUNCTION__, __LINE__, priv->pshare->phw->BE_pkt_count);
9723                                 if (!priv->pshare->iot_mode_BE_exist && (priv->pshare->phw->BE_pkt_count > 250)) {
9724                                         priv->pshare->iot_mode_BE_exist++;
9725                                         switch_turbo++;
9726                                 } else if (priv->pshare->iot_mode_BE_exist && (priv->pshare->phw->BE_pkt_count < 250)) {
9727                                         priv->pshare->iot_mode_BE_exist = 0;
9728                                         switch_turbo++;
9729                                 }
9730                         }
9731 #endif
9732
9733 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
9734                         if (priv->pshare->rf_ft_var.wifi_beq_iot)
9735                         {
9736                                 if (!priv->pshare->iot_mode_VI_exist && (priv->pshare->phw->VI_rx_pkt_count > 50)) {
9737                                         priv->pshare->iot_mode_VI_exist++;
9738                                         switch_turbo++;
9739                                 } else if (priv->pshare->iot_mode_VI_exist && (priv->pshare->phw->VI_rx_pkt_count < 50)) {
9740                                         priv->pshare->iot_mode_VI_exist = 0;
9741                                         switch_turbo++;
9742                                 }
9743                         }
9744 #endif
9745
9746                 }
9747                 else if (!pstat || pstat->rssi < priv->pshare->rf_ft_var.txop_enlarge_lower) {
9748                    if (priv->pshare->txop_enlarge) {
9749                            priv->pshare->txop_enlarge = 0;
9750                            if (priv->pshare->iot_mode_enable)
9751                                         switch_turbo++;
9752                                 }
9753                 }
9754
9755 #if(defined(CLIENT_MODE) && (DM_ODM_SUPPORT_TYPE==ODM_AP))
9756         if ((OPMODE & WIFI_STATION_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2))
9757         {
9758             if (priv->pshare->iot_mode_enable &&
9759                 (((priv->pshare->phw->VO_pkt_count > 50) ||
9760                  (priv->pshare->phw->VI_pkt_count > 50) ||
9761                  (priv->pshare->phw->BK_pkt_count > 50)) ||
9762                  (pstat && (!pstat->ADDBA_ready[0]) & (!pstat->ADDBA_ready[3]))))
9763             {
9764                 priv->pshare->iot_mode_enable = 0;
9765                 switch_turbo++;
9766             }
9767             else if ((!priv->pshare->iot_mode_enable) &&
9768                 (((priv->pshare->phw->VO_pkt_count < 50) &&
9769                  (priv->pshare->phw->VI_pkt_count < 50) &&
9770                  (priv->pshare->phw->BK_pkt_count < 50)) &&
9771                  (pstat && (pstat->ADDBA_ready[0] | pstat->ADDBA_ready[3]))))
9772             {
9773                 priv->pshare->iot_mode_enable++;
9774                 switch_turbo++;
9775             }
9776         }
9777 #endif
9778
9779                 priv->pshare->phw->VO_pkt_count = 0;
9780                 priv->pshare->phw->VI_pkt_count = 0;
9781                 priv->pshare->phw->BK_pkt_count = 0;
9782
9783         #if((DM_ODM_SUPPORT_TYPE==ODM_ADSL)||((DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined WMM_VIBE_PRI)))
9784                 priv->pshare->phw->BE_pkt_count = 0;
9785         #endif
9786
9787         #if(DM_ODM_SUPPORT_TYPE==ODM_AP)
9788                 if (priv->pshare->rf_ft_var.wifi_beq_iot)
9789                         priv->pshare->phw->VI_rx_pkt_count = 0;
9790                 #endif
9791
9792         }
9793 #endif
9794
9795         if ((priv->up_time % 2) == 0) {
9796                 /*
9797                  * decide EDCA content for different chip vendor
9798                  */
9799 #ifdef WIFI_WMM
9800         #if(DM_ODM_SUPPORT_TYPE==ODM_ADSL)
9801                 if (QOS_ENABLE && (!priv->pmib->dot11OperationEntry.wifi_specific || (priv->pmib->dot11OperationEntry.wifi_specific == 2)
9802
9803         #elif(DM_ODM_SUPPORT_TYPE==ODM_AP)
9804                 if (QOS_ENABLE && (!priv->pmib->dot11OperationEntry.wifi_specific ||
9805                         ((OPMODE & WIFI_AP_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2))
9806                 #ifdef CLIENT_MODE
9807             || ((OPMODE & WIFI_STATION_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2))
9808                 #endif
9809         #endif
9810                 ))
9811
9812                 {
9813
9814                         if (pstat && pstat->rssi >= priv->pshare->rf_ft_var.txop_enlarge_upper) {
9815 #ifdef LOW_TP_TXOP
9816 #if (DM_ODM_SUPPORT_TYPE &ODM_AP) && defined(USE_OUT_SRC)
9817                                 if (pstat->IOTPeer==HT_IOT_PEER_INTEL)
9818 #else
9819                                 if (pstat->is_intel_sta)
9820 #endif
9821                                 {
9822                                         if (priv->pshare->txop_enlarge != 0xe)
9823                                         {
9824                                                 priv->pshare->txop_enlarge = 0xe;
9825
9826                                                 if (priv->pshare->iot_mode_enable)
9827                                                         switch_turbo++;
9828                                         }
9829                                 }
9830                                 else if (priv->pshare->txop_enlarge != 2)
9831                                 {
9832                                         priv->pshare->txop_enlarge = 2;
9833                                         if (priv->pshare->iot_mode_enable)
9834                                                 switch_turbo++;
9835                                 }
9836 #else
9837                                 if (priv->pshare->txop_enlarge != 2)
9838                                 {
9839 #if (DM_ODM_SUPPORT_TYPE &ODM_AP) && defined(USE_OUT_SRC)
9840                                         if (pstat->IOTPeer==HT_IOT_PEER_INTEL)
9841 #else
9842                                         if (pstat->is_intel_sta)
9843 #endif
9844                                                 priv->pshare->txop_enlarge = 0xe;
9845 #if (DM_ODM_SUPPORT_TYPE &ODM_AP) && defined(USE_OUT_SRC)
9846                                         else if (pstat->IOTPeer==HT_IOT_PEER_RALINK)
9847 #else
9848                                         else if (pstat->is_ralink_sta)
9849 #endif
9850                                                 priv->pshare->txop_enlarge = 0xd;
9851                                         else
9852                                                 priv->pshare->txop_enlarge = 2;
9853
9854                                         if (priv->pshare->iot_mode_enable)
9855                                                 switch_turbo++;
9856                                 }
9857 #endif
9858 #if 0
9859                                 if (priv->pshare->txop_enlarge != 2)
9860                                 {
9861                                 #if(DM_ODM_SUPPORT_TYPE==ODM_AP)
9862                                         if (pstat->IOTPeer==HT_IOT_PEER_INTEL)
9863                                 #else
9864                                         if (pstat->is_intel_sta)
9865                                 #endif
9866                                                 priv->pshare->txop_enlarge = 0xe;
9867                                 #if(DM_ODM_SUPPORT_TYPE==ODM_AP)
9868                                         else if (pstat->IOTPeer==HT_IOT_PEER_RALINK)
9869                                                 priv->pshare->txop_enlarge = 0xd;
9870                                 #endif
9871                                         else
9872                                                 priv->pshare->txop_enlarge = 2;
9873                                         if (priv->pshare->iot_mode_enable)
9874                                                 switch_turbo++;
9875                                 }
9876 #endif
9877                         }
9878                         else if (!pstat || pstat->rssi < priv->pshare->rf_ft_var.txop_enlarge_lower)
9879                         {
9880                                 if (priv->pshare->txop_enlarge) {
9881                                         priv->pshare->txop_enlarge = 0;
9882                                         if (priv->pshare->iot_mode_enable)
9883                                                 switch_turbo++;
9884                                 }
9885                         }
9886
9887 #if((DM_ODM_SUPPORT_TYPE==ODM_AP)&&( defined LOW_TP_TXOP))
9888                         // for Intel IOT, need to enlarge CW MAX from 6 to 10
9889                         if (pstat && pstat->is_intel_sta && (((pstat->tx_avarage+pstat->rx_avarage)>>10) <
9890                                         priv->pshare->rf_ft_var.cwmax_enhance_thd))
9891                         {
9892                                 if (!priv->pshare->BE_cwmax_enhance && priv->pshare->iot_mode_enable)
9893                                 {
9894                                         priv->pshare->BE_cwmax_enhance = 1;
9895                                         switch_turbo++;
9896                                 }
9897                         } else {
9898                                 if (priv->pshare->BE_cwmax_enhance) {
9899                                         priv->pshare->BE_cwmax_enhance = 0;
9900                                         switch_turbo++;
9901                                 }
9902                         }
9903 #endif
9904                 }
9905 #endif
9906                 priv->pshare->current_tx_bytes = 0;
9907                 priv->pshare->current_rx_bytes = 0;
9908         }
9909
9910 #if((DM_ODM_SUPPORT_TYPE==ODM_AP)&& defined( SW_TX_QUEUE))
9911         if ((priv->assoc_num > 1) && (AMPDU_ENABLE))
9912         {
9913         if (priv->swq_txmac_chg >= priv->pshare->rf_ft_var.swq_en_highthd){
9914                         if ((priv->swq_en == 0)){
9915                                 switch_turbo++;
9916                                 if (priv->pshare->txop_enlarge == 0)
9917                                         priv->pshare->txop_enlarge = 2;
9918                                 priv->swq_en = 1;
9919                                 }
9920                         else
9921                         {
9922                                 if ((switch_turbo > 0) && (priv->pshare->txop_enlarge == 0) && (priv->pshare->iot_mode_enable != 0))
9923                                 {
9924                                         priv->pshare->txop_enlarge = 2;
9925                                         switch_turbo--;
9926                                 }
9927                         }
9928                 }
9929                 else if(priv->swq_txmac_chg <= priv->pshare->rf_ft_var.swq_dis_lowthd){
9930                         priv->swq_en = 0;
9931                 }
9932                 else if ((priv->swq_en == 1) && (switch_turbo > 0) && (priv->pshare->txop_enlarge == 0) && (priv->pshare->iot_mode_enable != 0))        {
9933                         priv->pshare->txop_enlarge = 2;
9934                         switch_turbo--;
9935                 }
9936     }
9937 #if ((DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined CONFIG_RTL_819XD))
9938     else if( (priv->assoc_num == 1) && (AMPDU_ENABLE)) {
9939         if (pstat) {
9940                         int en_thd = 14417920>>(priv->up_time % 2);
9941             if ((priv->swq_en == 0) && (pstat->current_tx_bytes > en_thd) && (pstat->current_rx_bytes > en_thd) )  { //50Mbps
9942                 priv->swq_en = 1;
9943                                 priv->swqen_keeptime = priv->up_time;
9944             }
9945             else if ((priv->swq_en == 1) && ((pstat->tx_avarage < 4587520) || (pstat->rx_avarage < 4587520))) { //35Mbps
9946                 priv->swq_en = 0;
9947                                 priv->swqen_keeptime = 0;
9948             }
9949         }
9950         else {
9951             priv->swq_en = 0;
9952                         priv->swqen_keeptime = 0;
9953         }
9954     }
9955 #endif
9956 #endif
9957
9958 #ifdef WIFI_WMM
9959 #ifdef LOW_TP_TXOP
9960         if ((!priv->pmib->dot11OperationEntry.wifi_specific || (priv->pmib->dot11OperationEntry.wifi_specific == 2))
9961                 && QOS_ENABLE) {
9962                 if (switch_turbo || priv->pshare->rf_ft_var.low_tp_txop) {
9963                         unsigned int thd_tp;
9964                         unsigned char under_thd;
9965                         unsigned int curr_tp;
9966
9967                         if (priv->pmib->dot11BssType.net_work_type & (ODM_WM_N24G|ODM_WM_N5G| ODM_WM_G))
9968                         {
9969                                 // Determine the upper bound throughput threshold.
9970                                 if (priv->pmib->dot11BssType.net_work_type & (ODM_WM_N24G|ODM_WM_N5G)) {
9971                                         if (priv->assoc_num && priv->assoc_num != priv->pshare->ht_sta_num)
9972                                                 thd_tp = priv->pshare->rf_ft_var.low_tp_txop_thd_g;
9973                                         else
9974                                                 thd_tp = priv->pshare->rf_ft_var.low_tp_txop_thd_n;
9975                                 }
9976                                 else
9977                                         thd_tp = priv->pshare->rf_ft_var.low_tp_txop_thd_g;
9978
9979                                 // Determine to close txop.
9980                                 curr_tp = (unsigned int)(priv->ext_stats.tx_avarage>>17) + (unsigned int)(priv->ext_stats.rx_avarage>>17);
9981                                 if (curr_tp <= thd_tp && curr_tp >= priv->pshare->rf_ft_var.low_tp_txop_thd_low)
9982                                         under_thd = 1;
9983                                 else
9984                                         under_thd = 0;
9985                         }
9986                         else
9987                         {
9988                                 under_thd = 0;
9989                         }
9990
9991                         if (switch_turbo)
9992                         {
9993                                 priv->pshare->rf_ft_var.low_tp_txop_close = under_thd;
9994                                 priv->pshare->rf_ft_var.low_tp_txop_count = 0;
9995                         }
9996                         else if (priv->pshare->iot_mode_enable && (priv->pshare->rf_ft_var.low_tp_txop_close != under_thd)) {
9997                                 priv->pshare->rf_ft_var.low_tp_txop_count++;
9998                                 if (priv->pshare->rf_ft_var.low_tp_txop_close) {
9999                                         priv->pshare->rf_ft_var.low_tp_txop_count = priv->pshare->rf_ft_var.low_tp_txop_delay;
10000                                 }
10001                                 if (priv->pshare->rf_ft_var.low_tp_txop_count ==priv->pshare->rf_ft_var.low_tp_txop_delay)
10002
10003                                 {
10004                                         priv->pshare->rf_ft_var.low_tp_txop_count = 0;
10005                                         priv->pshare->rf_ft_var.low_tp_txop_close = under_thd;
10006                                         switch_turbo++;
10007                                 }
10008                         }
10009                         else
10010                         {
10011                                 priv->pshare->rf_ft_var.low_tp_txop_count = 0;
10012                         }
10013                 }
10014         }
10015 #endif
10016
10017         if (switch_turbo)
10018                 ODM_IotEdcaSwitch( pDM_Odm, priv->pshare->iot_mode_enable );
10019 #endif
10020 }
10021 #endif
10022
10023
10024 #if( DM_ODM_SUPPORT_TYPE == ODM_WIN)
10025 //
10026 // 2011/07/26 MH Add an API for testing IQK fail case.
10027 //
10028 BOOLEAN
10029 ODM_CheckPowerStatus(
10030         IN      PADAPTER                Adapter)
10031 {
10032
10033         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
10034         PDM_ODM_T                       pDM_Odm = &pHalData->DM_OutSrc;
10035         RT_RF_POWER_STATE       rtState;
10036         PMGNT_INFO                      pMgntInfo       = &(Adapter->MgntInfo);
10037
10038         // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence.
10039         if (pMgntInfo->init_adpt_in_progress == TRUE)
10040         {
10041                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter"));
10042                 return  TRUE;
10043         }
10044
10045         //
10046         //      2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK.
10047         //
10048         Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState));
10049         if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff)
10050         {
10051                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n",
10052                 Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState));
10053                 return  FALSE;
10054         }
10055         return  TRUE;
10056 }
10057 #endif
10058
10059 // need to ODM CE Platform
10060 //move to here for ANT detection mechanism using
10061
10062 #if ((DM_ODM_SUPPORT_TYPE == ODM_WIN)||(DM_ODM_SUPPORT_TYPE == ODM_CE))
10063 u4Byte
10064 GetPSDData(
10065         IN PDM_ODM_T    pDM_Odm,
10066         unsigned int    point,
10067         u1Byte initial_gain_psd)
10068 {
10069         //unsigned int  val, rfval;
10070         //int   psd_report;
10071         u4Byte  psd_report;
10072
10073         //HAL_DATA_TYPE         *pHalData = GET_HAL_DATA(Adapter);
10074         //Debug Message
10075         //val = PHY_QueryBBReg(Adapter,0x908, bMaskDWord);
10076         //DbgPrint("Reg908 = 0x%x\n",val);
10077         //val = PHY_QueryBBReg(Adapter,0xDF4, bMaskDWord);
10078         //rfval = PHY_QueryRFReg(Adapter, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask);
10079         //DbgPrint("RegDF4 = 0x%x, RFReg00 = 0x%x\n",val, rfval);
10080         //DbgPrint("PHYTXON = %x, OFDMCCA_PP = %x, CCKCCA_PP = %x, RFReg00 = %x\n",
10081                 //(val&BIT25)>>25, (val&BIT14)>>14, (val&BIT15)>>15, rfval);
10082
10083         //Set DCO frequency index, offset=(40MHz/SamplePts)*point
10084         ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point);
10085
10086         //Start PSD calculation, Reg808[22]=0->1
10087         ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 1);
10088         //Need to wait for HW PSD report
10089         ODM_StallExecution(1000);
10090         ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 0);
10091         //Read PSD report, Reg8B4[15:0]
10092         psd_report = ODM_GetBBReg(pDM_Odm,0x8B4, bMaskDWord) & 0x0000FFFF;
10093
10094 #if 1//(DEV_BUS_TYPE == RT_PCI_INTERFACE) && ( (RT_PLATFORM == PLATFORM_LINUX) || (RT_PLATFORM == PLATFORM_MACOSX))
10095         psd_report = (u4Byte) (ConvertTo_dB(psd_report))+(u4Byte)(initial_gain_psd-0x1c);
10096 #else
10097         psd_report = (int) (20*log10((double)psd_report))+(int)(initial_gain_psd-0x1c);
10098 #endif
10099
10100         return psd_report;
10101
10102 }
10103
10104 u4Byte
10105 ConvertTo_dB(
10106         u4Byte  Value)
10107 {
10108         u1Byte i;
10109         u1Byte j;
10110         u4Byte dB;
10111
10112         Value = Value & 0xFFFF;
10113
10114         for (i=0;i<8;i++)
10115         {
10116                 if (Value <= dB_Invert_Table[i][11])
10117                 {
10118                         break;
10119                 }
10120         }
10121
10122         if (i >= 8)
10123         {
10124                 return (96);    // maximum 96 dB
10125         }
10126
10127         for (j=0;j<12;j++)
10128         {
10129                 if (Value <= dB_Invert_Table[i][j])
10130                 {
10131                         break;
10132                 }
10133         }
10134
10135         dB = i*12 + j + 1;
10136
10137         return (dB);
10138 }
10139
10140 #endif
10141
10142 //
10143 // LukeLee:
10144 // PSD function will be moved to FW in future IC, but now is only implemented in MP platform
10145 // So PSD function will not be incorporated to common ODM
10146 //
10147 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
10148
10149 #define AFH_PSD         1       //0:normal PSD scan, 1: only do 20 pts PSD
10150 #define MODE_40M                0       //0:20M, 1:40M
10151 #define PSD_TH2         3
10152 #define PSD_CHMIN               20   // Minimum channel number for BT AFH
10153 #define SIR_STEP_SIZE   3
10154 #define   Smooth_Size_1         5
10155 #define Smooth_TH_1     3
10156 #define   Smooth_Size_2         10
10157 #define Smooth_TH_2     4
10158 #define   Smooth_Size_3         20
10159 #define Smooth_TH_3     4
10160 #define   Smooth_Step_Size 5
10161 #define Adaptive_SIR    1
10162 //#if(RTL8723_FPGA_VERIFICATION == 1)
10163 //#define       PSD_RESCAN              1
10164 //#else
10165 //#define       PSD_RESCAN              4
10166 //#endif
10167 #define SCAN_INTERVAL   1500 //ms
10168 #define SYN_Length              5    // for 92D
10169
10170 #define LNA_Low_Gain_1                      0x64
10171 #define LNA_Low_Gain_2                      0x5A
10172 #define LNA_Low_Gain_3                      0x58
10173
10174 #define pw_th_10dB                                      0x0
10175 #define pw_th_16dB                                      0x3
10176
10177 #define FA_RXHP_TH1                           5000
10178 #define FA_RXHP_TH2                           1500
10179 #define FA_RXHP_TH3                             800
10180 #define FA_RXHP_TH4                             600
10181 #define FA_RXHP_TH5                             500
10182
10183 #define Idle_Mode                                       0
10184 #define High_TP_Mode                            1
10185 #define Low_TP_Mode                             2
10186
10187
10188 VOID
10189 odm_PSDMonitorInit(
10190         IN PDM_ODM_T    pDM_Odm)
10191 {
10192 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)|(DEV_BUS_TYPE == RT_USB_INTERFACE)
10193         //HAL_DATA_TYPE         *pHalData = GET_HAL_DATA(Adapter);
10194         //PSD Monitor Setting
10195         //Which path in ADC/DAC is turnned on for PSD: both I/Q
10196         ODM_SetBBReg(pDM_Odm, ODM_PSDREG, BIT10|BIT11, 0x3);
10197         //Ageraged number: 8
10198         ODM_SetBBReg(pDM_Odm, ODM_PSDREG, BIT12|BIT13, 0x1);
10199         pDM_Odm->bPSDinProcess = FALSE;
10200         pDM_Odm->bUserAssignLevel = FALSE;
10201         pDM_Odm->bPSDactive = FALSE;
10202         //pDM_Odm->bDMInitialGainEnable=TRUE;           //change the initialization to DIGinit
10203         //Set Debug Port
10204         //PHY_SetBBReg(Adapter, 0x908, bMaskDWord, 0x803);
10205         //PHY_SetBBReg(Adapter, 0xB34, bMaskByte0, 0x00); // pause PSD
10206         //PHY_SetBBReg(Adapter, 0xB38, bMaskByte0, 10); //rescan
10207         //PHY_SetBBReg(Adapter, 0xB38, bMaskByte2|bMaskByte3, 100); //interval
10208
10209         //PlatformSetTimer( Adapter, &pHalData->PSDTriggerTimer, 0); //ms
10210 #endif
10211 }
10212
10213 VOID
10214 PatchDCTone(
10215         IN      PDM_ODM_T       pDM_Odm,
10216         pu4Byte         PSD_report,
10217         u1Byte          initial_gain_psd
10218 )
10219 {
10220         //HAL_DATA_TYPE         *pHalData = GET_HAL_DATA(Adapter);
10221         //PADAPTER      pAdapter;
10222
10223         u4Byte  psd_report;
10224
10225         //2 Switch to CH11 to patch CH9 and CH13 DC tone
10226         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, 11);
10227
10228         if(pDM_Odm->SupportICType== ODM_RTL8192D)
10229         {
10230                 if((*(pDM_Odm->pMacPhyMode) == ODM_SMSP)||(*(pDM_Odm->pMacPhyMode) == ODM_DMSP))
10231                 {
10232                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_CHNLBW, 0x3FF, 11);
10233                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x25, 0xfffff, 0x643BC);
10234                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x26, 0xfffff, 0xFC038);
10235                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x27, 0xfffff, 0x77C1A);
10236                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2B, 0xfffff, 0x41289);
10237                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2C, 0xfffff, 0x01840);
10238                 }
10239                 else
10240                 {
10241                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x25, 0xfffff, 0x643BC);
10242                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x26, 0xfffff, 0xFC038);
10243                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x27, 0xfffff, 0x77C1A);
10244                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2B, 0xfffff, 0x41289);
10245                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2C, 0xfffff, 0x01840);
10246                 }
10247         }
10248
10249         //Ch9 DC tone patch
10250         psd_report = GetPSDData(pDM_Odm, 96, initial_gain_psd);
10251         PSD_report[50] = psd_report;
10252         //Ch13 DC tone patch
10253         psd_report = GetPSDData(pDM_Odm, 32, initial_gain_psd);
10254         PSD_report[70] = psd_report;
10255
10256         //2 Switch to CH3 to patch CH1 and CH5 DC tone
10257         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, 3);
10258
10259
10260         if(pDM_Odm->SupportICType==ODM_RTL8192D)
10261         {
10262                 if((*(pDM_Odm->pMacPhyMode) == ODM_SMSP)||(*(pDM_Odm->pMacPhyMode) == ODM_DMSP))
10263                 {
10264                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_CHNLBW, 0x3FF, 3);
10265                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_B, 0x25, 0xfffff, 0x643BC);
10266                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_B, 0x26, 0xfffff, 0xFC038);
10267                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x27, 0xfffff, 0x07C1A);
10268                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_B, 0x2B, 0xfffff, 0x61289);
10269                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_B, 0x2C, 0xfffff, 0x01C41);
10270                 }
10271                 else
10272                 {
10273                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x25, 0xfffff, 0x643BC);
10274                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x26, 0xfffff, 0xFC038);
10275                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x27, 0xfffff, 0x07C1A);
10276                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x2B, 0xfffff, 0x61289);
10277                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x2C, 0xfffff, 0x01C41);
10278                 }
10279         }
10280
10281         //Ch1 DC tone patch
10282         psd_report = GetPSDData(pDM_Odm, 96, initial_gain_psd);
10283         PSD_report[10] = psd_report;
10284         //Ch5 DC tone patch
10285         psd_report = GetPSDData(pDM_Odm, 32, initial_gain_psd);
10286         PSD_report[30] = psd_report;
10287
10288 }
10289
10290
10291 VOID
10292 GoodChannelDecision(
10293         PDM_ODM_T       pDM_Odm,
10294         pu4Byte         PSD_report,
10295         pu1Byte         PSD_bitmap,
10296         u1Byte          RSSI_BT,
10297         pu1Byte         PSD_bitmap_memory)
10298 {
10299         pRXHP_T                 pRX_HP_Table = &pDM_Odm->DM_RXHP_Table;
10300         //s4Byte        TH1 =  SSBT-0x15;    // modify TH by Neil Chen
10301         s4Byte  TH1= RSSI_BT+0x14;
10302         s4Byte  TH2 = RSSI_BT+85;
10303         //u2Byte    TH3;
10304 //      s4Byte  RegB34;
10305         u1Byte  bitmap, Smooth_size[3], Smooth_TH[3];
10306         //u1Byte        psd_bit;
10307         u4Byte  i,n,j, byte_idx, bit_idx, good_cnt, good_cnt_smoothing, Smooth_Interval[3];
10308         int             start_byte_idx,start_bit_idx,cur_byte_idx, cur_bit_idx,NOW_byte_idx ;
10309
10310 //      RegB34 = PHY_QueryBBReg(Adapter,0xB34, bMaskDWord)&0xFF;
10311
10312         if((pDM_Odm->SupportICType == ODM_RTL8192C)||(pDM_Odm->SupportICType == ODM_RTL8192D))
10313        {
10314             TH1 = RSSI_BT + 0x14;
10315         }
10316
10317         Smooth_size[0]=Smooth_Size_1;
10318         Smooth_size[1]=Smooth_Size_2;
10319         Smooth_size[2]=Smooth_Size_3;
10320         Smooth_TH[0]=Smooth_TH_1;
10321         Smooth_TH[1]=Smooth_TH_2;
10322         Smooth_TH[2]=Smooth_TH_3;
10323         Smooth_Interval[0]=16;
10324         Smooth_Interval[1]=15;
10325         Smooth_Interval[2]=13;
10326         good_cnt = 0;
10327         if(pDM_Odm->SupportICType==ODM_RTL8723A)
10328         {
10329                 //2 Threshold
10330
10331                 if(RSSI_BT >=41)
10332                         TH1 = 113;
10333                 else if(RSSI_BT >=38)   // >= -15dBm
10334                         TH1 = 105;                              //0x69
10335                 else if((RSSI_BT >=33)&(RSSI_BT <38))
10336                         TH1 = 99+(RSSI_BT-33);         //0x63
10337                 else if((RSSI_BT >=26)&(RSSI_BT<33))
10338                         TH1 = 99-(33-RSSI_BT)+2;     //0x5e
10339                 else if((RSSI_BT >=24)&(RSSI_BT<26))
10340                         TH1 = 88-((RSSI_BT-24)*3);   //0x58
10341                 else if((RSSI_BT >=18)&(RSSI_BT<24))
10342                         TH1 = 77+((RSSI_BT-18)*2);
10343                 else if((RSSI_BT >=14)&(RSSI_BT<18))
10344                         TH1 = 63+((RSSI_BT-14)*2);
10345                 else if((RSSI_BT >=8)&(RSSI_BT<14))
10346                         TH1 = 58+((RSSI_BT-8)*2);
10347                 else if((RSSI_BT >=3)&(RSSI_BT<8))
10348                         TH1 = 52+(RSSI_BT-3);
10349                 else
10350                         TH1 = 51;
10351         }
10352
10353         for (i = 0; i< 10; i++)
10354                 PSD_bitmap[i] = 0;
10355
10356
10357          // Add By Gary
10358        for (i=0; i<80; i++)
10359                 pRX_HP_Table->PSD_bitmap_RXHP[i] = 0;
10360         // End
10361
10362
10363
10364         if(pDM_Odm->SupportICType==ODM_RTL8723A)
10365         {
10366                 TH1 =TH1-SIR_STEP_SIZE;
10367         }
10368         while (good_cnt < PSD_CHMIN)
10369         {
10370                 good_cnt = 0;
10371                 if(pDM_Odm->SupportICType==ODM_RTL8723A)
10372                 {
10373                 if(TH1 ==TH2)
10374                         break;
10375                 if((TH1+SIR_STEP_SIZE) < TH2)
10376                         TH1 += SIR_STEP_SIZE;
10377                 else
10378                         TH1 = TH2;
10379                 }
10380                 else
10381                 {
10382                         if(TH1==(RSSI_BT+0x1E))
10383                              break;
10384                         if((TH1+2) < (RSSI_BT+0x1E))
10385                                 TH1+=3;
10386                         else
10387                                 TH1 = RSSI_BT+0x1E;
10388
10389                 }
10390                 ODM_RT_TRACE(pDM_Odm,COMP_PSD,DBG_LOUD,("PSD: decision threshold is: %d", TH1));
10391
10392                 for (i = 0; i< 80; i++)
10393                 {
10394                         if((s4Byte)(PSD_report[i]) < TH1)
10395                         {
10396                                 byte_idx = i / 8;
10397                                 bit_idx = i -8*byte_idx;
10398                                 bitmap = PSD_bitmap[byte_idx];
10399                                 PSD_bitmap[byte_idx] = bitmap | (u1Byte) (1 << bit_idx);
10400                         }
10401                 }
10402
10403 #if DBG
10404                 ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: before smoothing\n"));
10405                 for(n=0;n<10;n++)
10406                 {
10407                         //DbgPrint("PSD_bitmap[%u]=%x\n", n, PSD_bitmap[n]);
10408                         for (i = 0; i<8; i++)
10409                                 ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD_bitmap[%u] =   %d\n", 2402+n*8+i, (PSD_bitmap[n]&BIT(i))>>i));
10410                 }
10411 #endif
10412
10413                 //1 Start of smoothing function
10414
10415                 for (j=0;j<3;j++)
10416                 {
10417                         start_byte_idx=0;
10418                         start_bit_idx=0;
10419                         for(n=0; n<Smooth_Interval[j]; n++)
10420                         {
10421                                 good_cnt_smoothing = 0;
10422                                 cur_bit_idx = start_bit_idx;
10423                                 cur_byte_idx = start_byte_idx;
10424                                 for ( i=0; i < Smooth_size[j]; i++)
10425                                 {
10426                                         NOW_byte_idx = cur_byte_idx + (i+cur_bit_idx)/8;
10427                                         if ( (PSD_bitmap[NOW_byte_idx]& BIT( (cur_bit_idx + i)%8)) != 0)
10428                                                 good_cnt_smoothing++;
10429
10430                                 }
10431
10432                                 if( good_cnt_smoothing < Smooth_TH[j] )
10433                                 {
10434                                         cur_bit_idx = start_bit_idx;
10435                                         cur_byte_idx = start_byte_idx;
10436                                         for ( i=0; i< Smooth_size[j] ; i++)
10437                                         {
10438                                                 NOW_byte_idx = cur_byte_idx + (i+cur_bit_idx)/8;
10439                                                 PSD_bitmap[NOW_byte_idx] = PSD_bitmap[NOW_byte_idx] & (~BIT( (cur_bit_idx + i)%8));
10440                                         }
10441                                 }
10442                                 start_bit_idx =  start_bit_idx + Smooth_Step_Size;
10443                                 while ( (start_bit_idx)  > 7 )
10444                                 {
10445                                         start_byte_idx= start_byte_idx+start_bit_idx/8;
10446                                         start_bit_idx = start_bit_idx%8;
10447                                 }
10448                         }
10449
10450                         ODM_RT_TRACE(   pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: after %u smoothing", j+1));
10451                         for(n=0;n<10;n++)
10452                         {
10453                                 for (i = 0; i<8; i++)
10454                                 {
10455                                         ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD_bitmap[%u] =   %d\n", 2402+n*8+i, (PSD_bitmap[n]&BIT(i))>>i));
10456
10457                                         if ( ((PSD_bitmap[n]&BIT(i))>>i) ==1)  //----- Add By Gary
10458                                         {
10459                                            pRX_HP_Table->PSD_bitmap_RXHP[8*n+i] = 1;
10460                                         }                                                  // ------end by Gary
10461                                 }
10462                         }
10463
10464                 }
10465
10466
10467                 good_cnt = 0;
10468                 for ( i = 0; i < 10; i++)
10469                 {
10470                         for (n = 0; n < 8; n++)
10471                                 if((PSD_bitmap[i]& BIT(n)) != 0)
10472                                         good_cnt++;
10473                 }
10474                 ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: good channel cnt = %u",good_cnt));
10475         }
10476
10477         //RT_TRACE(COMP_PSD, DBG_LOUD,("PSD: SSBT=%d, TH2=%d, TH1=%d",SSBT,TH2,TH1));
10478         for (i = 0; i <10; i++)
10479                 ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: PSD_bitmap[%u]=%x",i,PSD_bitmap[i]));
10480 /*
10481         //Update bitmap memory
10482         for(i = 0; i < 80; i++)
10483         {
10484                 byte_idx = i / 8;
10485                 bit_idx = i -8*byte_idx;
10486                 psd_bit = (PSD_bitmap[byte_idx] & BIT(bit_idx)) >> bit_idx;
10487                 bitmap = PSD_bitmap_memory[i];
10488                 PSD_bitmap_memory[i] = (bitmap << 1) |psd_bit;
10489         }
10490 */
10491 }
10492
10493
10494
10495 VOID
10496 odm_PSD_Monitor(
10497         PDM_ODM_T       pDM_Odm
10498 )
10499 {
10500         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
10501         //PDM_ODM_T             pDM_Odm = &pHalData->DM_OutSrc;
10502
10503         unsigned int            pts, start_point, stop_point;
10504         u1Byte                  initial_gain ;
10505         static u1Byte           PSD_bitmap_memory[80], init_memory = 0;
10506         static u1Byte           psd_cnt=0;
10507         static u4Byte           PSD_report[80], PSD_report_tmp;
10508         static u8Byte           lastTxOkCnt=0, lastRxOkCnt=0;
10509         u1Byte                  H2C_PSD_DATA[5]={0,0,0,0,0};
10510         static u1Byte           H2C_PSD_DATA_last[5] ={0,0,0,0,0};
10511         u1Byte                  idx[20]={96,99,102,106,109,112,115,118,122,125,
10512                                         0,3,6,10,13,16,19,22,26,29};
10513         u1Byte                  n, i, channel, BBReset,tone_idx;
10514         u1Byte                  PSD_bitmap[10], SSBT=0,initial_gain_psd=0, RSSI_BT=0, initialGainUpper;
10515         s4Byte                          PSD_skip_start, PSD_skip_stop;
10516         u4Byte                  CurrentChannel, RXIQI, RxIdleLowPwr, wlan_channel;
10517         u4Byte                  ReScan, Interval, Is40MHz;
10518         u8Byte                  curTxOkCnt, curRxOkCnt;
10519         int                             cur_byte_idx, cur_bit_idx;
10520         PADAPTER                Adapter = pDM_Odm->Adapter;
10521         PMGNT_INFO              pMgntInfo = &Adapter->MgntInfo;
10522
10523         if( (*(pDM_Odm->pbScanInProcess)) ||
10524                 pDM_Odm->bLinkInProcess)
10525         {
10526                 if((pDM_Odm->SupportICType==ODM_RTL8723A)&(pDM_Odm->SupportInterface==ODM_ITRF_PCIE))
10527                 {
10528                         ODM_SetTimer( pDM_Odm, &pDM_Odm->PSDTimer, 1500); //ms
10529                         //psd_cnt=0;
10530                 }
10531                 return;
10532         }
10533
10534         if(pDM_Odm->bBtHsOperation)
10535         {
10536                 ReScan = 1;
10537                 Interval = SCAN_INTERVAL;
10538         }
10539         else
10540         {
10541         ReScan = PSD_RESCAN;
10542         Interval = SCAN_INTERVAL;
10543         }
10544
10545         //1 Initialization
10546         if(init_memory == 0)
10547         {
10548                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Init memory\n"));
10549                 for(i = 0; i < 80; i++)
10550                         PSD_bitmap_memory[i] = 0xFF; // channel is always good
10551                 init_memory = 1;
10552         }
10553         if(psd_cnt == 0)
10554         {
10555                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Enter dm_PSD_Monitor\n"));
10556                 for(i = 0; i < 80; i++)
10557                         PSD_report[i] = 0;
10558         }
10559
10560         //1 Backup Current Settings
10561         CurrentChannel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
10562 /*
10563         if(pDM_Odm->SupportICType==ODM_RTL8192D)
10564         {
10565                 //2 Record Current synthesizer parameters based on current channel
10566                 if((*pDM_Odm->MacPhyMode92D == SINGLEMAC_SINGLEPHY)||(*pDM_Odm->MacPhyMode92D == DUALMAC_SINGLEPHY))
10567                 {
10568                         SYN_RF25 = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x25, bMaskDWord);
10569                         SYN_RF26 = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x26, bMaskDWord);
10570                         SYN_RF27 = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x27, bMaskDWord);
10571                         SYN_RF2B = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x2B, bMaskDWord);
10572                         SYN_RF2C = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x2C, bMaskDWord);
10573         }
10574                 else     // DualMAC_DualPHY 2G
10575                 {
10576                         SYN_RF25 = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x25, bMaskDWord);
10577                         SYN_RF26 = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x26, bMaskDWord);
10578                         SYN_RF27 = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x27, bMaskDWord);
10579                         SYN_RF2B = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x2B, bMaskDWord);
10580                         SYN_RF2C = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x2C, bMaskDWord);
10581                 }
10582         }
10583 */
10584         //RXIQI = PHY_QueryBBReg(Adapter, 0xC14, bMaskDWord);
10585         RXIQI = ODM_GetBBReg(pDM_Odm, 0xC14, bMaskDWord);
10586
10587         //RxIdleLowPwr = (PHY_QueryBBReg(Adapter, 0x818, bMaskDWord)&BIT28)>>28;
10588         RxIdleLowPwr = (ODM_GetBBReg(pDM_Odm, 0x818, bMaskDWord)&BIT28)>>28;
10589
10590         //2???
10591         if(CHNL_RUN_ABOVE_40MHZ(pMgntInfo))
10592                 Is40MHz = TRUE;
10593         else
10594                 Is40MHz = FALSE;
10595
10596         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_PSD, DBG_LOUD,("PSD Scan Start\n"));
10597         //1 Turn off CCK
10598         //PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT24, 0);
10599         ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0);
10600         //1 Turn off TX
10601         //Pause TX Queue
10602         //PlatformEFIOWrite1Byte(Adapter, REG_TXPAUSE, 0xFF);
10603         ODM_Write1Byte(pDM_Odm,REG_TXPAUSE, 0xFF);
10604
10605         //Force RX to stop TX immediately
10606         //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13);
10607
10608         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13);
10609         //1 Turn off RX
10610         //Rx AGC off  RegC70[0]=0, RegC7C[20]=0
10611         //PHY_SetBBReg(Adapter, 0xC70, BIT0, 0);
10612         //PHY_SetBBReg(Adapter, 0xC7C, BIT20, 0);
10613
10614         ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 0);
10615         ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 0);
10616
10617
10618         //Turn off CCA
10619         //PHY_SetBBReg(Adapter, 0xC14, bMaskDWord, 0x0);
10620         ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, 0x0);
10621
10622         //BB Reset
10623         //BBReset = PlatformEFIORead1Byte(Adapter, 0x02);
10624         BBReset = ODM_Read1Byte(pDM_Odm, 0x02);
10625
10626         //PlatformEFIOWrite1Byte(Adapter, 0x02, BBReset&(~BIT0));
10627         //PlatformEFIOWrite1Byte(Adapter, 0x02, BBReset|BIT0);
10628         ODM_SetBBReg(pDM_Odm, 0x87C, BIT31, 1); //clock gated to prevent from AGC table mess
10629         ODM_Write1Byte(pDM_Odm,  0x02, BBReset&(~BIT0));
10630         ODM_Write1Byte(pDM_Odm,  0x02, BBReset|BIT0);
10631         ODM_SetBBReg(pDM_Odm, 0x87C, BIT31, 0);
10632
10633         //1 Leave RX idle low power
10634         //PHY_SetBBReg(Adapter, 0x818, BIT28, 0x0);
10635
10636         ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0);
10637         //1 Fix initial gain
10638         //if (IS_HARDWARE_TYPE_8723AE(Adapter))
10639         //RSSI_BT = pHalData->RSSI_BT;
10640        //else if((IS_HARDWARE_TYPE_8192C(Adapter))||(IS_HARDWARE_TYPE_8192D(Adapter)))      // Add by Gary
10641        //    RSSI_BT = RSSI_BT_new;
10642
10643         if((pDM_Odm->SupportICType==ODM_RTL8723A)&(pDM_Odm->SupportInterface==ODM_ITRF_PCIE))
10644         RSSI_BT=pDM_Odm->RSSI_BT;               //need to check C2H to pDM_Odm RSSI BT
10645
10646         if(RSSI_BT>=47)
10647                 RSSI_BT=47;
10648
10649         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT));
10650
10651         if(pDM_Odm->SupportICType==ODM_RTL8723A)
10652         {
10653                //Neil add--2011--10--12
10654                 //2 Initial Gain index
10655                 if(RSSI_BT >=35)   // >= -15dBm
10656                         initial_gain_psd = RSSI_BT*2;
10657                 else if((RSSI_BT >=33)&(RSSI_BT<35))
10658                         initial_gain_psd = RSSI_BT*2+6;
10659                 else if((RSSI_BT >=24)&(RSSI_BT<33))
10660                         initial_gain_psd = 70-(33-RSSI_BT);
10661                 else if((RSSI_BT >=19)&(RSSI_BT<24))
10662                         initial_gain_psd = 64-((24-RSSI_BT)*4);
10663                 else if((RSSI_BT >=14)&(RSSI_BT<19))
10664                         initial_gain_psd = 44-((18-RSSI_BT)*2);
10665                 else if((RSSI_BT >=8)&(RSSI_BT<14))
10666                         initial_gain_psd = 35-(14-RSSI_BT);
10667                 else
10668                         initial_gain_psd = 0x1B;
10669         }
10670         else
10671         {
10672
10673                 //need to do
10674                 initial_gain_psd = pDM_Odm->RSSI_Min;    // PSD report based on RSSI
10675                 //}
10676         }
10677         //if(RSSI_BT<0x17)
10678         //      RSSI_BT +=3;
10679         //DbgPrint("PSD: RSSI_BT= %d\n", RSSI_BT);
10680         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT));
10681
10682         //initialGainUpper = 0x5E;  //Modify by neil chen
10683
10684         if(pDM_Odm->bUserAssignLevel)
10685         {
10686                 pDM_Odm->bUserAssignLevel = FALSE;
10687                 initialGainUpper = 0x7f;
10688         }
10689         else
10690         {
10691                 initialGainUpper = 0x5E;
10692         }
10693
10694         /*
10695         if (initial_gain_psd < 0x1a)
10696                 initial_gain_psd = 0x1a;
10697         if (initial_gain_psd > initialGainUpper)
10698                 initial_gain_psd = initialGainUpper;
10699         */
10700
10701         //if(pDM_Odm->SupportICType==ODM_RTL8723A)
10702         SSBT = RSSI_BT  * 2 +0x3E;
10703
10704
10705         //if(IS_HARDWARE_TYPE_8723AE(Adapter))
10706         //      SSBT = RSSI_BT  * 2 +0x3E;
10707         //else if((IS_HARDWARE_TYPE_8192C(Adapter))||(IS_HARDWARE_TYPE_8192D(Adapter)))   // Add by Gary
10708         //{
10709         //      RSSI_BT = initial_gain_psd;
10710         //      SSBT = RSSI_BT;
10711         //}
10712         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: SSBT= %d\n", SSBT));
10713         ODM_RT_TRACE(   pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: initial gain= 0x%x\n", initial_gain_psd));
10714         //DbgPrint("PSD: SSBT= %d", SSBT);
10715         //need to do
10716         //pMgntInfo->bDMInitialGainEnable = FALSE;
10717         pDM_Odm->bDMInitialGainEnable = FALSE;
10718         initial_gain =(u1Byte) (ODM_GetBBReg(pDM_Odm, 0xc50, bMaskDWord) & 0x7F);
10719
10720         // make sure the initial gain is under the correct range.
10721         //initial_gain_psd &= 0x7f;
10722         ODM_Write_DIG(pDM_Odm, initial_gain_psd);
10723         //1 Turn off 3-wire
10724         ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0xF);
10725
10726         //pts value = 128, 256, 512, 1024
10727         pts = 128;
10728
10729         if(pts == 128)
10730         {
10731                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0);
10732                 start_point = 64;
10733                 stop_point = 192;
10734         }
10735         else if(pts == 256)
10736         {
10737                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x1);
10738                 start_point = 128;
10739                 stop_point = 384;
10740         }
10741         else if(pts == 512)
10742         {
10743                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x2);
10744                 start_point = 256;
10745                 stop_point = 768;
10746         }
10747         else
10748         {
10749                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x3);
10750                 start_point = 512;
10751                 stop_point = 1536;
10752         }
10753
10754
10755 //3 Skip WLAN channels if WLAN busy
10756
10757         curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - lastTxOkCnt;
10758         curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - lastRxOkCnt;
10759         lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast);
10760         lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast);
10761
10762         PSD_skip_start=80;
10763         PSD_skip_stop = 0;
10764         wlan_channel = CurrentChannel & 0x0f;
10765
10766         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD,DBG_LOUD,("PSD: current channel: %x, BW:%d \n", wlan_channel, Is40MHz));
10767         if(pDM_Odm->SupportICType==ODM_RTL8723A)
10768         {
10769                 if(pDM_Odm->bBtHsOperation)
10770                 {
10771                         if(pDM_Odm->bLinked)
10772                         {
10773                                 if(Is40MHz)
10774                                 {
10775                                         PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-2;  // Modify by Neil to add 10 chs to mask
10776                                         PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+4;
10777                                 }
10778                                 else
10779                                 {
10780                                         PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-10;  // Modify by Neil to add 10 chs to mask
10781                                         PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+18;
10782                                 }
10783                         }
10784                         else
10785                         {
10786                                 // mask for 40MHz
10787                                 PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-2;  // Modify by Neil to add 10 chs to mask
10788                                 PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+4;
10789                         }
10790                         if(PSD_skip_start < 0)
10791                                 PSD_skip_start = 0;
10792                         if(PSD_skip_stop >80)
10793                                 PSD_skip_stop = 80;
10794                 }
10795                 else
10796                 {
10797                         if((curRxOkCnt+curTxOkCnt) > 5)
10798                         {
10799                                 if(Is40MHz)
10800                                 {
10801                                         PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-2;  // Modify by Neil to add 10 chs to mask
10802                                         PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+4;
10803                                 }
10804                                 else
10805                                 {
10806                                         PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-10;  // Modify by Neil to add 10 chs to mask
10807                                         PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+18;
10808                                 }
10809
10810                                 if(PSD_skip_start < 0)
10811                                         PSD_skip_start = 0;
10812                                 if(PSD_skip_stop >80)
10813                                         PSD_skip_stop = 80;
10814                         }
10815                 }
10816         }
10817 #if 0
10818         else
10819         {
10820                 if((curRxOkCnt+curTxOkCnt) > 1000)
10821                 {
10822                         PSD_skip_start = (wlan_channel-1)*5 -Is40MHz*10;
10823                         PSD_skip_stop = PSD_skip_start + (1+Is40MHz)*20;
10824                 }
10825         }
10826 #endif  //Reove RXHP Issue
10827         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD,DBG_LOUD,("PSD: Skip tone from %d to %d \n", PSD_skip_start, PSD_skip_stop));
10828
10829         for (n=0;n<80;n++)
10830         {
10831                 if((n%20)==0)
10832                 {
10833                         channel = (n/20)*4 + 1;
10834
10835                                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, channel);
10836                                 }
10837                 tone_idx = n%20;
10838                 if ((n>=PSD_skip_start) && (n<PSD_skip_stop))
10839                 {
10840                         PSD_report[n] = SSBT;
10841                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD,DBG_LOUD,("PSD:Tone %d skipped \n", n));
10842                 }
10843                 else
10844                 {
10845                         PSD_report_tmp =  GetPSDData(pDM_Odm, idx[tone_idx], initial_gain_psd);
10846
10847                         if ( PSD_report_tmp > PSD_report[n])
10848                                 PSD_report[n] = PSD_report_tmp;
10849
10850                 }
10851         }
10852
10853         PatchDCTone(pDM_Odm, PSD_report, initial_gain_psd);
10854
10855        //----end
10856         //1 Turn on RX
10857         //Rx AGC on
10858         ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 1);
10859         ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 1);
10860         //CCK on
10861         ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 1);
10862         //1 Turn on TX
10863         //Resume TX Queue
10864
10865         ODM_Write1Byte(pDM_Odm,REG_TXPAUSE, 0x00);
10866         //Turn on 3-wire
10867         ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0x0);
10868         //1 Restore Current Settings
10869         //Resume DIG
10870         pDM_Odm->bDMInitialGainEnable = TRUE;
10871
10872         ODM_Write_DIG(pDM_Odm, initial_gain);
10873
10874         // restore originl center frequency
10875         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel);
10876
10877         //Turn on CCA
10878         ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, RXIQI);
10879         //Restore RX idle low power
10880         if(RxIdleLowPwr == TRUE)
10881                 ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 1);
10882
10883         psd_cnt++;
10884         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD:psd_cnt = %d \n",psd_cnt));
10885         if (psd_cnt < ReScan)
10886                 ODM_SetTimer(pDM_Odm, &pDM_Odm->PSDTimer, Interval);
10887         else
10888         {
10889                 psd_cnt = 0;
10890                 for(i=0;i<80;i++)
10891                         //DbgPrint("psd_report[%d]=     %d \n", 2402+i, PSD_report[i]);
10892                         RT_TRACE(       COMP_PSD, DBG_LOUD,("psd_report[%d]=     %d \n", 2402+i, PSD_report[i]));
10893
10894
10895                 GoodChannelDecision(pDM_Odm, PSD_report, PSD_bitmap,RSSI_BT, PSD_bitmap_memory);
10896
10897                 if(pDM_Odm->SupportICType==ODM_RTL8723A)
10898                 {
10899                         cur_byte_idx=0;
10900                         cur_bit_idx=0;
10901
10902                         //2 Restore H2C PSD Data to Last Data
10903                         H2C_PSD_DATA_last[0] = H2C_PSD_DATA[0];
10904                         H2C_PSD_DATA_last[1] = H2C_PSD_DATA[1];
10905                         H2C_PSD_DATA_last[2] = H2C_PSD_DATA[2];
10906                         H2C_PSD_DATA_last[3] = H2C_PSD_DATA[3];
10907                         H2C_PSD_DATA_last[4] = H2C_PSD_DATA[4];
10908
10909
10910                         //2 Translate 80bit channel map to 40bit channel
10911                         for ( i=0;i<5;i++)
10912                         {
10913                                 for(n=0;n<8;n++)
10914                                 {
10915                                         cur_byte_idx = i*2 + n/4;
10916                                         cur_bit_idx = (n%4)*2;
10917                                         if ( ((PSD_bitmap[cur_byte_idx]& BIT(cur_bit_idx)) != 0) && ((PSD_bitmap[cur_byte_idx]& BIT(cur_bit_idx+1)) != 0))
10918                                                 H2C_PSD_DATA[i] = H2C_PSD_DATA[i] | (u1Byte) (1 << n);
10919                                 }
10920                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("H2C_PSD_DATA[%d]=0x%x\n" ,i, H2C_PSD_DATA[i]));
10921                         }
10922
10923                         //3 To Compare the difference
10924                         for ( i=0;i<5;i++)
10925                         {
10926                                 if(H2C_PSD_DATA[i] !=H2C_PSD_DATA_last[i])
10927                                 {
10928                                         FillH2CCmd(Adapter, H2C_92C_PSD_RESULT, 5, H2C_PSD_DATA);
10929                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_PSD, DBG_LOUD,("Need to Update the AFH Map \n"));
10930                                         break;
10931                                 }
10932                                 else
10933                                 {
10934                                         if(i==5)
10935                                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Not need to Update\n"));
10936                                 }
10937                         }
10938                         if(pDM_Odm->bBtHsOperation)
10939                         {
10940                                 ODM_SetTimer(pDM_Odm, &pDM_Odm->PSDTimer, 10000);
10941                                 ODM_RT_TRACE(   pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Leave dm_PSD_Monitor\n"));
10942                         }
10943                         else
10944                         {
10945                                 ODM_SetTimer(pDM_Odm, &pDM_Odm->PSDTimer, 1500);
10946                                 ODM_RT_TRACE(   pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Leave dm_PSD_Monitor\n"));
10947                 }
10948         }
10949     }
10950 }
10951 /*
10952 //Neil for Get BT RSSI
10953 // Be Triggered by BT C2H CMD
10954 VOID
10955 ODM_PSDGetRSSI(
10956         IN      u1Byte  RSSI_BT)
10957 {
10958
10959
10960 }
10961
10962 */
10963
10964 VOID
10965 ODM_PSDMonitor(
10966         IN      PDM_ODM_T       pDM_Odm
10967         )
10968 {
10969         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
10970
10971         //if(IS_HARDWARE_TYPE_8723AE(Adapter))
10972
10973         if(pDM_Odm->SupportICType == ODM_RTL8723A)   //may need to add other IC type
10974         {
10975                 if(pDM_Odm->SupportInterface==ODM_ITRF_PCIE)
10976                 {
10977                         if(pDM_Odm->bBtDisabled) //need to check upper layer connection
10978                         {
10979                                 pDM_Odm->bPSDactive=FALSE;
10980                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD, ("odm_PSDMonitor, return for BT is disabled!!!\n"));
10981                                 return;
10982                         }
10983
10984                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD, ("odm_PSDMonitor\n"));
10985                 //{
10986                         pDM_Odm->bPSDinProcess = TRUE;
10987                         pDM_Odm->bPSDactive=TRUE;
10988                         odm_PSD_Monitor(pDM_Odm);
10989                         pDM_Odm->bPSDinProcess = FALSE;
10990                 }
10991         }
10992
10993 }
10994 VOID
10995 odm_PSDMonitorCallback(
10996         PRT_TIMER               pTimer
10997 )
10998 {
10999         PADAPTER                Adapter = (PADAPTER)pTimer->Adapter;
11000        HAL_DATA_TYPE    *pHalData = GET_HAL_DATA(Adapter);
11001
11002         PlatformScheduleWorkItem(&pHalData->PSDMonitorWorkitem);
11003 }
11004
11005 VOID
11006 odm_PSDMonitorWorkItemCallback(
11007     IN PVOID            pContext
11008     )
11009 {
11010         PADAPTER        Adapter = (PADAPTER)pContext;
11011         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
11012         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
11013
11014         ODM_PSDMonitor(pDM_Odm);
11015 }
11016
11017 // <20130108, Kordan> E.g., With LNA used, we make the Rx power smaller to have a better EVM. (Asked by Willis)
11018 VOID
11019 odm_RFEControl(
11020         IN      PDM_ODM_T       pDM_Odm,
11021         IN  u8Byte              RSSIVal
11022         )
11023 {
11024         PADAPTER                Adapter = (PADAPTER)pDM_Odm->Adapter;
11025     HAL_DATA_TYPE       *pHalData = GET_HAL_DATA(Adapter);
11026         static u1Byte   TRSW_HighPwr = 0;
11027
11028         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, DBG_LOUD, ("===> odm_RFEControl, RSSI = %d, TRSW_HighPwr = 0x%X, pHalData->RFEType = %d\n",
11029                          RSSIVal, TRSW_HighPwr, pHalData->RFEType ));
11030
11031     if (pHalData->RFEType == 3) {
11032
11033         pDM_Odm->RSSI_TRSW = RSSIVal;
11034
11035         if (pDM_Odm->RSSI_TRSW >= pDM_Odm->RSSI_TRSW_H)
11036                 {
11037             TRSW_HighPwr = 1; // Switch to
11038             PHY_SetBBReg(Adapter, r_ANTSEL_SW_Jaguar, BIT1|BIT0, 0x1);  // Set ANTSW=1/ANTSWB=0  for SW control
11039             PHY_SetBBReg(Adapter, r_ANTSEL_SW_Jaguar, BIT9|BIT8, 0x3);  // Set ANTSW=1/ANTSWB=0  for SW control
11040
11041         }
11042                 else if (pDM_Odm->RSSI_TRSW <= pDM_Odm->RSSI_TRSW_L)
11043         {
11044             TRSW_HighPwr = 0; // Switched back
11045             PHY_SetBBReg(Adapter, r_ANTSEL_SW_Jaguar, BIT1|BIT0, 0x1);  // Set ANTSW=1/ANTSWB=0  for SW control
11046             PHY_SetBBReg(Adapter, r_ANTSEL_SW_Jaguar, BIT9|BIT8, 0x0);  // Set ANTSW=1/ANTSWB=0  for SW control
11047
11048         }
11049     }
11050
11051
11052         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, DBG_LOUD, ("(pDM_Odm->RSSI_TRSW_H, pDM_Odm->RSSI_TRSW_L) = (%d, %d)\n", pDM_Odm->RSSI_TRSW_H, pDM_Odm->RSSI_TRSW_L));
11053         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, DBG_LOUD, ("(RSSIVal, RSSIVal, pDM_Odm->RSSI_TRSW_iso) = (%d, %d, %d)\n",
11054                                  RSSIVal, pDM_Odm->RSSI_TRSW_iso, pDM_Odm->RSSI_TRSW));
11055         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, DBG_LOUD, ("<=== odm_RFEControl, RSSI = %d, TRSW_HighPwr = 0x%X\n", RSSIVal, TRSW_HighPwr));
11056 }
11057
11058 VOID
11059 ODM_MPT_DIG(
11060         IN      PDM_ODM_T       pDM_Odm
11061         )
11062 {
11063         pDIG_T                                          pDM_DigTable = &pDM_Odm->DM_DigTable;
11064         PFALSE_ALARM_STATISTICS         pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
11065         u1Byte                                          CurrentIGI = (u1Byte)pDM_DigTable->CurIGValue;
11066         u1Byte                                          DIG_Upper = 0x40, DIG_Lower = 0x20, C50, E50;
11067         u8Byte                                          RXOK_cal;
11068         u1Byte                                          IGI_A = 0x20, IGI_B = 0x20;
11069
11070 #if ODM_FIX_2G_DIG
11071         IGI_A = 0x22;
11072         IGI_B = 0x24;
11073 #endif
11074
11075         ODM_RT_TRACE(pDM_Odm,ODM_COMP_MP, DBG_LOUD, ("===> ODM_MPT_DIG, pBandType = %d\n", *pDM_Odm->pBandType));
11076
11077         odm_FalseAlarmCounterStatistics( pDM_Odm);
11078         pDM_Odm->LastNumQryPhyStatusAll = pDM_Odm->NumQryPhyStatusAll;
11079         pDM_Odm->NumQryPhyStatusAll = pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK + pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM;
11080         RXOK_cal = pDM_Odm->NumQryPhyStatusAll - pDM_Odm->LastNumQryPhyStatusAll;
11081
11082         if (RXOK_cal == 0)
11083                 pDM_Odm->RxPWDBAve_final= 0;
11084         else
11085                 pDM_Odm->RxPWDBAve_final= pDM_Odm->RxPWDBAve/RXOK_cal;
11086
11087         pDM_Odm->RxPWDBAve = 0;
11088         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, DBG_LOUD, ("RX OK = %d\n", RXOK_cal));
11089         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, DBG_LOUD, ("pDM_Odm->RxPWDBAve_final = %d\n", pDM_Odm->RxPWDBAve_final));
11090
11091         // <20130315, Kordan> Except Cameo, we should always trun on 2.4G/5G DIG.
11092         // (Cameo fixes the IGI of 2.4G, so only DIG on 5G. Asked by James.)
11093 #if ODM_FIX_2G_DIG
11094         if (*pDM_Odm->pBandType == BAND_ON_5G){  // for 5G
11095 #else
11096         if (1){ // for both 2G/5G
11097 #endif
11098                 pDM_Odm->MPDIG_2G = FALSE;
11099                 pDM_Odm->Times_2G = 0;
11100
11101                 if (RXOK_cal >= 70 && pDM_Odm->RxPWDBAve_final<= 30)
11102                 {
11103                         if (CurrentIGI > 0x24){
11104                                 ODM_Write1Byte( pDM_Odm, rA_IGI_Jaguar, 0x24);
11105                                 ODM_Write1Byte( pDM_Odm, rB_IGI_Jaguar, 0x24);
11106                         }
11107                 }
11108                 else
11109                 {
11110                         if(pFalseAlmCnt->Cnt_all > 1000){
11111                                 CurrentIGI = CurrentIGI + 8;
11112                         }
11113                         else if(pFalseAlmCnt->Cnt_all > 200){
11114                                 CurrentIGI = CurrentIGI + 4;
11115                         }
11116                         else if (pFalseAlmCnt->Cnt_all > 50){
11117                                 CurrentIGI = CurrentIGI + 2;
11118                         }
11119                         else if (pFalseAlmCnt->Cnt_all < 2){
11120                                 CurrentIGI = CurrentIGI - 2;
11121                         }
11122
11123                         if (CurrentIGI < DIG_Lower ){
11124                                 CurrentIGI = DIG_Lower;
11125                         }
11126                         else if(CurrentIGI > DIG_Upper){
11127                                 CurrentIGI = DIG_Upper;
11128                         }
11129
11130                         pDM_DigTable->CurIGValue = CurrentIGI;
11131
11132                         ODM_Write1Byte( pDM_Odm, rA_IGI_Jaguar, (u1Byte)CurrentIGI);
11133                         ODM_Write1Byte( pDM_Odm, rB_IGI_Jaguar, (u1Byte)CurrentIGI);
11134
11135                         C50 = ODM_Read1Byte( pDM_Odm, 0xc50);
11136                         E50 = ODM_Read1Byte( pDM_Odm, 0xe50);
11137                         //pDM_Odm->MPDIG_2G = FALSE;
11138                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_MP, DBG_LOUD, ("DIG = (%x, %x), Cnt_all = %d, Cnt_Ofdm_fail = %d, Cnt_Cck_fail = %d\n", C50, E50, pFalseAlmCnt->Cnt_all, pFalseAlmCnt->Cnt_Ofdm_fail, pFalseAlmCnt->Cnt_Cck_fail));
11139                 }
11140
11141         }
11142         else
11143         {       //2G
11144                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_MP, DBG_LOUD, ("MPDIG_2G = %d,\n", pDM_Odm->MPDIG_2G));
11145
11146                 if(pDM_Odm->MPDIG_2G == FALSE){
11147                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_MP, DBG_LOUD, ("===> Fix IGI\n"));
11148                         ODM_Write1Byte( pDM_Odm, rA_IGI_Jaguar, (u1Byte)IGI_A);
11149                         ODM_Write1Byte( pDM_Odm, rB_IGI_Jaguar, (u1Byte)IGI_B);
11150                 }
11151                 if (pDM_Odm->Times_2G == 2)
11152                         pDM_Odm->MPDIG_2G = TRUE;
11153                 pDM_Odm->Times_2G++;
11154         }
11155         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, DBG_LOUD, ("pDM_Odm->RxPWDBAve_final = %d\n", pDM_Odm->RxPWDBAve_final));
11156
11157         if (pDM_Odm->SupportICType == ODM_RTL8812)
11158                 odm_RFEControl(pDM_Odm, pDM_Odm->RxPWDBAve_final);
11159
11160         ODM_SetTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer, 700);
11161
11162 }
11163
11164 VOID
11165 odm_MPT_DIGCallback(
11166         PRT_TIMER               pTimer
11167 )
11168 {
11169         PADAPTER                Adapter = (PADAPTER)pTimer->Adapter;
11170        HAL_DATA_TYPE    *pHalData = GET_HAL_DATA(Adapter);
11171           PDM_ODM_T             pDM_Odm = &pHalData->DM_OutSrc;
11172
11173
11174         #if DEV_BUS_TYPE==RT_PCI_INTERFACE
11175                 #if USE_WORKITEM
11176                         PlatformScheduleWorkItem(&pDM_Odm->MPT_DIGWorkitem);
11177                 #else
11178                         ODM_MPT_DIG(pDM_Odm);
11179                 #endif
11180         #else
11181                 PlatformScheduleWorkItem(&pDM_Odm->MPT_DIGWorkitem);
11182         #endif
11183
11184 }
11185
11186 VOID
11187 odm_MPT_DIGWorkItemCallback(
11188     IN PVOID            pContext
11189     )
11190 {
11191         PADAPTER        Adapter = (PADAPTER)pContext;
11192         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
11193         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
11194
11195         ODM_MPT_DIG(pDM_Odm);
11196 }
11197
11198
11199
11200
11201  //cosa debug tool need to modify
11202
11203 VOID
11204 ODM_PSDDbgControl(
11205         IN      PADAPTER        Adapter,
11206         IN      u4Byte          mode,
11207         IN      u4Byte          btRssi
11208         )
11209 {
11210 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
11211         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
11212         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
11213
11214         ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD, (" Monitor mode=%d, btRssi=%d\n", mode, btRssi));
11215         if(mode)
11216         {
11217                 pDM_Odm->RSSI_BT = (u1Byte)btRssi;
11218                 pDM_Odm->bUserAssignLevel = TRUE;
11219                 ODM_SetTimer( pDM_Odm, &pDM_Odm->PSDTimer, 0); //ms
11220         }
11221         else
11222         {
11223                 ODM_CancelTimer(pDM_Odm, &pDM_Odm->PSDTimer);
11224         }
11225 #endif
11226 }
11227
11228
11229 //#if(DEV_BUS_TYPE == RT_PCI_INTERFACE)|(DEV_BUS_TYPE == RT_USB_INTERFACE)
11230
11231 void    odm_RXHPInit(
11232         IN              PDM_ODM_T               pDM_Odm)
11233 {
11234 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)|(DEV_BUS_TYPE == RT_USB_INTERFACE)
11235         pRXHP_T                 pRX_HP_Table  = &pDM_Odm->DM_RXHP_Table;
11236         u1Byte                  index;
11237
11238         pRX_HP_Table->RXHP_enable = TRUE;
11239         pRX_HP_Table->RXHP_flag = 0;
11240         pRX_HP_Table->PSD_func_trigger = 0;
11241         pRX_HP_Table->Pre_IGI = 0x20;
11242         pRX_HP_Table->Cur_IGI = 0x20;
11243         pRX_HP_Table->Cur_pw_th = pw_th_10dB;
11244         pRX_HP_Table->Pre_pw_th = pw_th_10dB;
11245         for(index=0; index<80; index++)
11246                 pRX_HP_Table->PSD_bitmap_RXHP[index] = 1;
11247
11248 #if(DEV_BUS_TYPE == RT_USB_INTERFACE)
11249         pRX_HP_Table->TP_Mode = Idle_Mode;
11250 #endif
11251 #endif
11252 }
11253
11254 void odm_RXHP(
11255         IN              PDM_ODM_T               pDM_Odm)
11256 {
11257 #if( DM_ODM_SUPPORT_TYPE & (ODM_WIN))
11258 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) | (DEV_BUS_TYPE == RT_USB_INTERFACE)
11259         PADAPTER        Adapter =  pDM_Odm->Adapter;
11260         PMGNT_INFO      pMgntInfo = &(Adapter->MgntInfo);
11261         pDIG_T          pDM_DigTable = &pDM_Odm->DM_DigTable;
11262         pRXHP_T         pRX_HP_Table  = &pDM_Odm->DM_RXHP_Table;
11263        PFALSE_ALARM_STATISTICS          FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
11264
11265         u1Byte                  i, j, sum;
11266         u1Byte                  Is40MHz;
11267         s1Byte                  Intf_diff_idx, MIN_Intf_diff_idx = 16;
11268        s4Byte                   cur_channel;
11269        u1Byte                   ch_map_intf_5M[17] = {0};
11270        static u4Byte            FA_TH = 0;
11271         static u1Byte           psd_intf_flag = 0;
11272         static s4Byte           curRssi = 0;
11273        static s4Byte            preRssi = 0;
11274         static u1Byte           PSDTriggerCnt = 1;
11275
11276         u1Byte                  RX_HP_enable = (u1Byte)(ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore2, bMaskDWord)>>31);   // for debug!!
11277
11278 #if(DEV_BUS_TYPE == RT_USB_INTERFACE)
11279         static s8Byte           lastTxOkCnt = 0, lastRxOkCnt = 0;
11280        s8Byte                   curTxOkCnt, curRxOkCnt;
11281         s8Byte                  curTPOkCnt;
11282         s8Byte                  TP_Acc3, TP_Acc5;
11283         static s8Byte           TP_Buff[5] = {0};
11284         static u1Byte           pre_state = 0, pre_state_flag = 0;
11285         static u1Byte           Intf_HighTP_flag = 0, De_counter = 16;
11286         static u1Byte           TP_Degrade_flag = 0;
11287 #endif
11288         static u1Byte           LatchCnt = 0;
11289
11290         if(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8188E))
11291                 return;
11292         //AGC RX High Power Mode is only applied on 2G band in 92D!!!
11293         if(pDM_Odm->SupportICType == ODM_RTL8192D)
11294         {
11295                 if(*(pDM_Odm->pBandType) != ODM_BAND_2_4G)
11296                         return;
11297         }
11298
11299         if(!(pDM_Odm->SupportAbility==ODM_BB_RXHP))
11300                 return;
11301
11302
11303         //RX HP ON/OFF
11304         if(RX_HP_enable == 1)
11305                 pRX_HP_Table->RXHP_enable = FALSE;
11306         else
11307                 pRX_HP_Table->RXHP_enable = TRUE;
11308
11309         if(pRX_HP_Table->RXHP_enable == FALSE)
11310         {
11311                 if(pRX_HP_Table->RXHP_flag == 1)
11312                 {
11313                         pRX_HP_Table->RXHP_flag = 0;
11314                         psd_intf_flag = 0;
11315                 }
11316                 return;
11317         }
11318
11319 #if(DEV_BUS_TYPE == RT_USB_INTERFACE)
11320         //2 Record current TP for USB interface
11321         curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast)-lastTxOkCnt;
11322         curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast)-lastRxOkCnt;
11323         lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast);
11324         lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast);
11325
11326         curTPOkCnt = curTxOkCnt+curRxOkCnt;
11327         TP_Buff[0] = curTPOkCnt;    // current TP
11328         TP_Acc3 = PlatformDivision64((TP_Buff[1]+TP_Buff[2]+TP_Buff[3]), 3);
11329         TP_Acc5 = PlatformDivision64((TP_Buff[0]+TP_Buff[1]+TP_Buff[2]+TP_Buff[3]+TP_Buff[4]), 5);
11330
11331         if(TP_Acc5 < 1000)
11332                 pRX_HP_Table->TP_Mode = Idle_Mode;
11333         else if((1000 < TP_Acc5)&&(TP_Acc5 < 3750000))
11334                 pRX_HP_Table->TP_Mode = Low_TP_Mode;
11335         else
11336                 pRX_HP_Table->TP_Mode = High_TP_Mode;
11337
11338         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP TP Mode = %d\n", pRX_HP_Table->TP_Mode));
11339         // Since TP result would be sampled every 2 sec, it needs to delay 4sec to wait PSD processing.
11340         // When LatchCnt = 0, we would Get PSD result.
11341         if(TP_Degrade_flag == 1)
11342         {
11343                 LatchCnt--;
11344                 if(LatchCnt == 0)
11345                 {
11346                         TP_Degrade_flag = 0;
11347                 }
11348         }
11349         // When PSD function triggered by TP degrade 20%, and Interference Flag = 1
11350         // Set a De_counter to wait IGI = upper bound. If time is UP, the Interference flag will be pull down.
11351         if(Intf_HighTP_flag == 1)
11352         {
11353                 De_counter--;
11354                 if(De_counter == 0)
11355                 {
11356                         Intf_HighTP_flag = 0;
11357                         psd_intf_flag = 0;
11358                 }
11359         }
11360 #endif
11361
11362         //2 AGC RX High Power Mode by PSD only applied to STA Mode
11363         //3 NOT applied 1. Ad Hoc Mode.
11364         //3 NOT applied 2. AP Mode
11365         if ((pMgntInfo->mAssoc) && (!pMgntInfo->mIbss) && (!ACTING_AS_AP(Adapter)))
11366         {
11367                 Is40MHz = *(pDM_Odm->pBandWidth);
11368                 curRssi = pDM_Odm->RSSI_Min;
11369                 cur_channel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x0fff) & 0x0f;
11370                 ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP RX HP flag = %d\n", pRX_HP_Table->RXHP_flag));
11371                 ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP FA = %d\n", FalseAlmCnt->Cnt_all));
11372                 ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP cur RSSI = %d, pre RSSI=%d\n", curRssi, preRssi));
11373                 ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP current CH = %d\n", cur_channel));
11374                 ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP Is 40MHz = %d\n", Is40MHz));
11375         //2 PSD function would be triggered
11376         //3 1. Every 4 sec for PCIE
11377         //3 2. Before TP Mode (Idle TP<4kbps) for USB
11378         //3 3. After TP Mode (High TP) for USB
11379                 if((curRssi > 68) && (pRX_HP_Table->RXHP_flag == 0))    // Only RSSI>TH and RX_HP_flag=0 will Do PSD process
11380                 {
11381 #if (DEV_BUS_TYPE == RT_USB_INTERFACE)
11382                         //2 Before TP Mode ==> PSD would be trigger every 4 sec
11383                         if(pRX_HP_Table->TP_Mode == Idle_Mode)          //2.1 less wlan traffic <4kbps
11384                         {
11385 #endif
11386                                 if(PSDTriggerCnt == 1)
11387                                 {
11388                                         odm_PSD_RXHP(pDM_Odm);
11389                                         pRX_HP_Table->PSD_func_trigger = 1;
11390                                         PSDTriggerCnt = 0;
11391                                 }
11392                                 else
11393                                 {
11394                                         PSDTriggerCnt++;
11395                                 }
11396 #if(DEV_BUS_TYPE == RT_USB_INTERFACE)
11397                         }
11398                         //2 After TP Mode ==> Check if TP degrade larger than 20% would trigger PSD function
11399                         if(pRX_HP_Table->TP_Mode == High_TP_Mode)
11400                         {
11401                                 if((pre_state_flag == 0)&&(LatchCnt == 0))
11402                                 {
11403                                         // TP var < 5%
11404                                         if((((curTPOkCnt-TP_Acc3)*20)<(TP_Acc3))&&(((curTPOkCnt-TP_Acc3)*20)>(-TP_Acc3)))
11405                                         {
11406                                                 pre_state++;
11407                                                 if(pre_state == 3)      // hit pre_state condition => consecutive 3 times
11408                                                 {
11409                                                         pre_state_flag = 1;
11410                                                         pre_state = 0;
11411                                                 }
11412
11413                                         }
11414                                         else
11415                                         {
11416                                                 pre_state = 0;
11417                                         }
11418                                 }
11419                                 //3 If pre_state_flag=1 ==> start to monitor TP degrade 20%
11420                                 if(pre_state_flag == 1)
11421                                 {
11422                                         if(((TP_Acc3-curTPOkCnt)*5)>(TP_Acc3))      // degrade 20%
11423                                         {
11424                                                 odm_PSD_RXHP(pDM_Odm);
11425                                                 pRX_HP_Table->PSD_func_trigger = 1;
11426                                                 TP_Degrade_flag = 1;
11427                                                 LatchCnt = 2;
11428                                                 pre_state_flag = 0;
11429                                         }
11430                                         else if(((TP_Buff[2]-curTPOkCnt)*5)>TP_Buff[2])
11431                                         {
11432                                                 odm_PSD_RXHP(pDM_Odm);
11433                                                 pRX_HP_Table->PSD_func_trigger = 1;
11434                                                 TP_Degrade_flag = 1;
11435                                                 LatchCnt = 2;
11436                                                 pre_state_flag = 0;
11437                                         }
11438                                         else if(((TP_Buff[3]-curTPOkCnt)*5)>TP_Buff[3])
11439                                         {
11440                                                 odm_PSD_RXHP(pDM_Odm);
11441                                                 pRX_HP_Table->PSD_func_trigger = 1;
11442                                                 TP_Degrade_flag = 1;
11443                                                 LatchCnt = 2;
11444                                                 pre_state_flag = 0;
11445                                         }
11446                                 }
11447                         }
11448 #endif
11449 }
11450
11451 #if (DEV_BUS_TYPE == RT_USB_INTERFACE)
11452                 for (i=0;i<4;i++)
11453                 {
11454                         TP_Buff[4-i] = TP_Buff[3-i];
11455                 }
11456 #endif
11457                 //2 Update PSD bitmap according to PSD report
11458                 if((pRX_HP_Table->PSD_func_trigger == 1)&&(LatchCnt == 0))
11459                 {
11460                         //2 Separate 80M bandwidth into 16 group with smaller 5M BW.
11461                         for (i = 0 ; i < 16 ; i++)
11462                         {
11463                                 sum = 0;
11464                                 for(j = 0; j < 5 ; j++)
11465                                         sum += pRX_HP_Table->PSD_bitmap_RXHP[5*i + j];
11466
11467                                 if(sum < 5)
11468                                 {
11469                                         ch_map_intf_5M[i] = 1;  // interference flag
11470                                 }
11471                         }
11472                         //=============just for debug=========================
11473                         //for(i=0;i<16;i++)
11474                                 //DbgPrint("RX HP: ch_map_intf_5M[%d] = %d\n", i, ch_map_intf_5M[i]);
11475                         //===============================================
11476                         //2 Mask target channel 5M index
11477                         for(i = 0; i < (4+4*Is40MHz) ; i++)
11478                         {
11479                                 ch_map_intf_5M[cur_channel - (1+2*Is40MHz) + i] = 0;
11480                         }
11481
11482                         psd_intf_flag = 0;
11483                         for(i = 0; i < 16; i++)
11484                         {
11485                                 if(ch_map_intf_5M[i] == 1)
11486                         {
11487                                 psd_intf_flag = 1;            // interference is detected!!!
11488                                 break;
11489                                 }
11490                         }
11491
11492 #if (DEV_BUS_TYPE == RT_USB_INTERFACE)
11493                         if(pRX_HP_Table->TP_Mode!=Idle_Mode)
11494                         {
11495                                 if(psd_intf_flag == 1)     // to avoid psd_intf_flag always 1
11496                                 {
11497                                         Intf_HighTP_flag = 1;
11498                                         De_counter = 32;     // 0x1E -> 0x3E needs 32 times by each IGI step =1
11499                                 }
11500                         }
11501 #endif
11502                         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP psd_intf_flag = %d\n", psd_intf_flag));
11503                         //2 Distance between target channel and interference
11504                         for(i = 0; i < 16; i++)
11505                         {
11506                                 if(ch_map_intf_5M[i] == 1)
11507                                 {
11508                                         Intf_diff_idx = ((cur_channel+Is40MHz-(i+1))>0) ? (s1Byte)(cur_channel-2*Is40MHz-(i-2)) : (s1Byte)((i+1)-(cur_channel+2*Is40MHz));
11509                                 if(Intf_diff_idx < MIN_Intf_diff_idx)
11510                                                 MIN_Intf_diff_idx = Intf_diff_idx;    // the min difference index between interference and target
11511                                 }
11512                         }
11513                         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP MIN_Intf_diff_idx = %d\n", MIN_Intf_diff_idx));
11514                         //2 Choose False Alarm Threshold
11515                         switch (MIN_Intf_diff_idx){
11516                                 case 0:
11517                                 case 1:
11518                                 case 2:
11519                                 case 3:
11520                                         FA_TH = FA_RXHP_TH1;
11521                                 break;
11522                                 case 4:                         // CH5
11523                                 case 5:                         // CH6
11524                                         FA_TH = FA_RXHP_TH2;
11525                                 break;
11526                                 case 6:                         // CH7
11527                                 case 7:                         // CH8
11528                                         FA_TH = FA_RXHP_TH3;
11529                                         break;
11530                         case 8:                         // CH9
11531                                 case 9:                         //CH10
11532                                         FA_TH = FA_RXHP_TH4;
11533                                         break;
11534                                 case 10:
11535                                 case 11:
11536                                 case 12:
11537                                 case 13:
11538                                 case 14:
11539                                 case 15:
11540                                         FA_TH = FA_RXHP_TH5;
11541                                         break;
11542                 }
11543                         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP FA_TH = %d\n", FA_TH));
11544                         pRX_HP_Table->PSD_func_trigger = 0;
11545                 }
11546                 //1 Monitor RSSI variation to choose the suitable IGI or Exit AGC RX High Power Mode
11547                 if(pRX_HP_Table->RXHP_flag == 1)
11548                 {
11549                 if ((curRssi > 80)&&(preRssi < 80))
11550                 {
11551                                 pRX_HP_Table->Cur_IGI = LNA_Low_Gain_1;
11552                 }
11553                 else if ((curRssi < 80)&&(preRssi > 80))
11554                 {
11555                                 pRX_HP_Table->Cur_IGI = LNA_Low_Gain_2;
11556                         }
11557                 else if ((curRssi > 72)&&(preRssi < 72))
11558                         {
11559                                 pRX_HP_Table->Cur_IGI = LNA_Low_Gain_2;
11560                 }
11561                 else if ((curRssi < 72)&&( preRssi > 72))
11562                         {
11563                                 pRX_HP_Table->Cur_IGI = LNA_Low_Gain_3;
11564                 }
11565                 else if (curRssi < 68)           //RSSI is NOT large enough!!==> Exit AGC RX High Power Mode
11566                 {
11567                                 pRX_HP_Table->Cur_pw_th = pw_th_10dB;
11568                                 pRX_HP_Table->RXHP_flag = 0;    // Back to Normal DIG Mode
11569                                 psd_intf_flag = 0;
11570                         }
11571                 }
11572                 else    // pRX_HP_Table->RXHP_flag == 0
11573                 {
11574                         //1 Decide whether to enter AGC RX High Power Mode
11575                         if ((curRssi > 70) && (psd_intf_flag == 1) && (FalseAlmCnt->Cnt_all > FA_TH) &&
11576                                 (pDM_DigTable->CurIGValue == pDM_DigTable->rx_gain_range_max))
11577                         {
11578                                 if (curRssi > 80)
11579                                 {
11580                                         pRX_HP_Table->Cur_IGI = LNA_Low_Gain_1;
11581                                 }
11582                                 else if (curRssi > 72)
11583                         {
11584                                 pRX_HP_Table->Cur_IGI = LNA_Low_Gain_2;
11585                                 }
11586                                 else
11587                                 {
11588                                         pRX_HP_Table->Cur_IGI = LNA_Low_Gain_3;
11589                                 }
11590                                 pRX_HP_Table->Cur_pw_th = pw_th_16dB;           //RegC54[9:8]=2'b11: to enter AGC Flow 3
11591                                 pRX_HP_Table->First_time_enter = TRUE;
11592                                 pRX_HP_Table->RXHP_flag = 1;    //      RXHP_flag=1: AGC RX High Power Mode, RXHP_flag=0: Normal DIG Mode
11593                         }
11594                 }
11595                 preRssi = curRssi;
11596                 odm_Write_RXHP(pDM_Odm);
11597         }
11598 #endif //#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN))
11599 #endif //#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) | (DEV_BUS_TYPE == RT_USB_INTERFACE)
11600 }
11601
11602 void odm_Write_RXHP(
11603         IN      PDM_ODM_T       pDM_Odm)
11604 {
11605         pRXHP_T         pRX_HP_Table = &pDM_Odm->DM_RXHP_Table;
11606         u4Byte          currentIGI;
11607
11608         if(pRX_HP_Table->Cur_IGI != pRX_HP_Table->Pre_IGI)
11609         {
11610                 ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI);
11611                 ODM_SetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI);
11612         }
11613
11614         if(pRX_HP_Table->Cur_pw_th != pRX_HP_Table->Pre_pw_th)
11615 {
11616                 ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore2, BIT8|BIT9, pRX_HP_Table->Cur_pw_th);  // RegC54[9:8]=2'b11:  AGC Flow 3
11617         }
11618
11619         if(pRX_HP_Table->RXHP_flag == 0)
11620         {
11621                 pRX_HP_Table->Cur_IGI = 0x20;
11622         }
11623         else
11624         {
11625                 currentIGI = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0);
11626                 if(currentIGI<0x50)
11627                 {
11628                         ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI);
11629                         ODM_SetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI);
11630                 }
11631         }
11632         pRX_HP_Table->Pre_IGI = pRX_HP_Table->Cur_IGI;
11633         pRX_HP_Table->Pre_pw_th = pRX_HP_Table->Cur_pw_th;
11634
11635 }
11636
11637 VOID
11638 odm_PSD_RXHP(
11639         IN      PDM_ODM_T       pDM_Odm
11640 )
11641 {
11642         pRXHP_T                 pRX_HP_Table  = &pDM_Odm->DM_RXHP_Table;
11643         PADAPTER                Adapter =  pDM_Odm->Adapter;
11644         PMGNT_INFO              pMgntInfo = &(Adapter->MgntInfo);
11645         unsigned int            pts, start_point, stop_point, initial_gain ;
11646         static u1Byte           PSD_bitmap_memory[80], init_memory = 0;
11647         static u1Byte           psd_cnt=0;
11648         static u4Byte           PSD_report[80], PSD_report_tmp;
11649         static u8Byte           lastTxOkCnt=0, lastRxOkCnt=0;
11650         u1Byte                  idx[20]={96,99,102,106,109,112,115,118,122,125,
11651                                         0,3,6,10,13,16,19,22,26,29};
11652         u1Byte                  n, i, channel, BBReset,tone_idx;
11653         u1Byte                  PSD_bitmap[10]/*, SSBT=0*/,initial_gain_psd=0, RSSI_BT=0, initialGainUpper;
11654         s4Byte                          PSD_skip_start, PSD_skip_stop;
11655         u4Byte                  CurrentChannel, RXIQI, RxIdleLowPwr, wlan_channel;
11656         u4Byte                  ReScan, Interval, Is40MHz;
11657         u8Byte                  curTxOkCnt, curRxOkCnt;
11658         //--------------2G band synthesizer for 92D switch RF channel using-----------------
11659         u1Byte                  group_idx=0;
11660         u4Byte                  SYN_RF25=0, SYN_RF26=0, SYN_RF27=0, SYN_RF2B=0, SYN_RF2C=0;
11661         u4Byte                  SYN[5] = {0x25, 0x26, 0x27, 0x2B, 0x2C};    // synthesizer RF register for 2G channel
11662         u4Byte                  SYN_group[3][5] = {{0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},     // For CH1,2,4,9,10.11.12   {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840}
11663                                                                             {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},     // For CH3,13,14
11664                                                                             {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}};   // For Ch5,6,7,8
11665        //--------------------- Add by Gary for Debug setting ----------------------
11666         u1Byte                 RSSI_BT_new = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xB9C, 0xFF);
11667        u1Byte                 rssi_ctrl = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xB38, 0xFF);
11668        //---------------------------------------------------------------------
11669
11670         if(pMgntInfo->bScanInProgress)
11671         {
11672                 return;
11673         }
11674
11675         ReScan = PSD_RESCAN;
11676         Interval = SCAN_INTERVAL;
11677
11678
11679         //1 Initialization
11680         if(init_memory == 0)
11681         {
11682                 RT_TRACE(       COMP_PSD, DBG_LOUD,("Init memory\n"));
11683                 for(i = 0; i < 80; i++)
11684                         PSD_bitmap_memory[i] = 0xFF; // channel is always good
11685                 init_memory = 1;
11686         }
11687         if(psd_cnt == 0)
11688         {
11689                 RT_TRACE(COMP_PSD, DBG_LOUD,("Enter dm_PSD_Monitor\n"));
11690                 for(i = 0; i < 80; i++)
11691                         PSD_report[i] = 0;
11692         }
11693
11694         //1 Backup Current Settings
11695         CurrentChannel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
11696         if(pDM_Odm->SupportICType == ODM_RTL8192D)
11697         {
11698                 //2 Record Current synthesizer parameters based on current channel
11699                 if((*(pDM_Odm->pMacPhyMode)==ODM_SMSP)||(*(pDM_Odm->pMacPhyMode)==ODM_DMSP))
11700                 {
11701                         SYN_RF25 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x25, bMaskDWord);
11702                         SYN_RF26 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x26, bMaskDWord);
11703                         SYN_RF27 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x27, bMaskDWord);
11704                         SYN_RF2B = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2B, bMaskDWord);
11705                         SYN_RF2C = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2C, bMaskDWord);
11706         }
11707                 else     // DualMAC_DualPHY 2G
11708                 {
11709                         SYN_RF25 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x25, bMaskDWord);
11710                         SYN_RF26 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x26, bMaskDWord);
11711                         SYN_RF27 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x27, bMaskDWord);
11712                         SYN_RF2B = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2B, bMaskDWord);
11713                         SYN_RF2C = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2C, bMaskDWord);
11714                 }
11715         }
11716         RXIQI = ODM_GetBBReg(pDM_Odm, 0xC14, bMaskDWord);
11717         RxIdleLowPwr = (ODM_GetBBReg(pDM_Odm, 0x818, bMaskDWord)&BIT28)>>28;
11718         Is40MHz = *(pDM_Odm->pBandWidth);
11719         ODM_RT_TRACE(pDM_Odm,   COMP_PSD, DBG_LOUD,("PSD Scan Start\n"));
11720         //1 Turn off CCK
11721         ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0);
11722         //1 Turn off TX
11723         //Pause TX Queue
11724         ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF);
11725         //Force RX to stop TX immediately
11726         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13);
11727         //1 Turn off RX
11728         //Rx AGC off  RegC70[0]=0, RegC7C[20]=0
11729         ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 0);
11730         ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 0);
11731         //Turn off CCA
11732         ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, 0x0);
11733         //BB Reset
11734         ODM_SetBBReg(pDM_Odm, 0x87C, BIT31, 1); //clock gated to prevent from AGC table mess
11735         BBReset = ODM_Read1Byte(pDM_Odm, 0x02);
11736         ODM_Write1Byte(pDM_Odm, 0x02, BBReset&(~BIT0));
11737         ODM_Write1Byte(pDM_Odm, 0x02, BBReset|BIT0);
11738         ODM_SetBBReg(pDM_Odm, 0x87C, BIT31, 0);
11739         //1 Leave RX idle low power
11740         ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0);
11741         //1 Fix initial gain
11742         RSSI_BT = RSSI_BT_new;
11743         RT_TRACE(COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT));
11744
11745         if(rssi_ctrl == 1)        // just for debug!!
11746                 initial_gain_psd = RSSI_BT_new;
11747         else
11748                 initial_gain_psd = pDM_Odm->RSSI_Min;    // PSD report based on RSSI
11749
11750         RT_TRACE(COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT));
11751
11752         initialGainUpper = 0x54;
11753
11754         RSSI_BT = initial_gain_psd;
11755         //SSBT = RSSI_BT;
11756
11757         //RT_TRACE(     COMP_PSD, DBG_LOUD,("PSD: SSBT= %d\n", SSBT));
11758         RT_TRACE(       COMP_PSD, DBG_LOUD,("PSD: initial gain= 0x%x\n", initial_gain_psd));
11759
11760         pDM_Odm->bDMInitialGainEnable = FALSE;
11761         initial_gain = ODM_GetBBReg(pDM_Odm, 0xc50, bMaskDWord) & 0x7F;
11762         //ODM_SetBBReg(pDM_Odm, 0xc50, 0x7F, initial_gain_psd);
11763         ODM_Write_DIG(pDM_Odm, initial_gain_psd);
11764         //1 Turn off 3-wire
11765         ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0xF);
11766
11767         //pts value = 128, 256, 512, 1024
11768         pts = 128;
11769
11770         if(pts == 128)
11771         {
11772                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0);
11773                 start_point = 64;
11774                 stop_point = 192;
11775         }
11776         else if(pts == 256)
11777         {
11778                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x1);
11779                 start_point = 128;
11780                 stop_point = 384;
11781         }
11782         else if(pts == 512)
11783         {
11784                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x2);
11785                 start_point = 256;
11786                 stop_point = 768;
11787         }
11788         else
11789         {
11790                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x3);
11791                 start_point = 512;
11792                 stop_point = 1536;
11793         }
11794
11795
11796 //3 Skip WLAN channels if WLAN busy
11797         curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - lastTxOkCnt;
11798         curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - lastRxOkCnt;
11799         lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast);
11800         lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast);
11801
11802         PSD_skip_start=80;
11803         PSD_skip_stop = 0;
11804         wlan_channel = CurrentChannel & 0x0f;
11805
11806         RT_TRACE(COMP_PSD,DBG_LOUD,("PSD: current channel: %x, BW:%d \n", wlan_channel, Is40MHz));
11807
11808         if((curRxOkCnt+curTxOkCnt) > 1000)
11809         {
11810                 PSD_skip_start = (wlan_channel-1)*5 -Is40MHz*10;
11811                 PSD_skip_stop = PSD_skip_start + (1+Is40MHz)*20;
11812         }
11813
11814         RT_TRACE(COMP_PSD,DBG_LOUD,("PSD: Skip tone from %d to %d \n", PSD_skip_start, PSD_skip_stop));
11815
11816         for (n=0;n<80;n++)
11817         {
11818                 if((n%20)==0)
11819                 {
11820                         channel = (n/20)*4 + 1;
11821                         if(pDM_Odm->SupportICType == ODM_RTL8192D)
11822                         {
11823                                 switch(channel)
11824                                 {
11825                                         case 1:
11826                                         case 9:
11827                                                 group_idx = 0;
11828                                                 break;
11829                                         case 5:
11830                                                 group_idx = 2;
11831                                                 break;
11832                                         case 13:
11833                                                 group_idx = 1;
11834                                                 break;
11835                                 }
11836                                 if((*(pDM_Odm->pMacPhyMode)==ODM_SMSP)||(*(pDM_Odm->pMacPhyMode)==ODM_DMSP))
11837                 {
11838                                         for(i = 0; i < SYN_Length; i++)
11839                                                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, SYN[i], bMaskDWord, SYN_group[group_idx][i]);
11840
11841                                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, channel);
11842                                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_CHNLBW, 0x3FF, channel);
11843                                 }
11844                                 else  // DualMAC_DualPHY 2G
11845                         {
11846                                         for(i = 0; i < SYN_Length; i++)
11847                                                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, SYN[i], bMaskDWord, SYN_group[group_idx][i]);
11848
11849                                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, channel);
11850                                 }
11851                         }
11852                         else
11853                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, channel);
11854                         }
11855                 tone_idx = n%20;
11856                 if ((n>=PSD_skip_start) && (n<PSD_skip_stop))
11857                 {
11858                         PSD_report[n] = initial_gain_psd;//SSBT;
11859                         ODM_RT_TRACE(pDM_Odm,COMP_PSD,DBG_LOUD,("PSD:Tone %d skipped \n", n));
11860                 }
11861                 else
11862                 {
11863                         PSD_report_tmp =  GetPSDData(pDM_Odm, idx[tone_idx], initial_gain_psd);
11864
11865                         if ( PSD_report_tmp > PSD_report[n])
11866                                 PSD_report[n] = PSD_report_tmp;
11867
11868                 }
11869         }
11870
11871         PatchDCTone(pDM_Odm, PSD_report, initial_gain_psd);
11872
11873        //----end
11874         //1 Turn on RX
11875         //Rx AGC on
11876         ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 1);
11877         ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 1);
11878         //CCK on
11879         ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 1);
11880         //1 Turn on TX
11881         //Resume TX Queue
11882         ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00);
11883         //Turn on 3-wire
11884         ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0x0);
11885         //1 Restore Current Settings
11886         //Resume DIG
11887         pDM_Odm->bDMInitialGainEnable= TRUE;
11888         //ODM_SetBBReg(pDM_Odm, 0xc50, 0x7F, initial_gain);
11889         ODM_Write_DIG(pDM_Odm,(u1Byte) initial_gain);
11890         // restore originl center frequency
11891         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel);
11892         if(pDM_Odm->SupportICType == ODM_RTL8192D)
11893         {
11894                 if((*(pDM_Odm->pMacPhyMode)==ODM_SMSP)||(*(pDM_Odm->pMacPhyMode)==ODM_DMSP))
11895                 {
11896                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_CHNLBW, bMaskDWord, CurrentChannel);
11897                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x25, bMaskDWord, SYN_RF25);
11898                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x26, bMaskDWord, SYN_RF26);
11899                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x27, bMaskDWord, SYN_RF27);
11900                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2B, bMaskDWord, SYN_RF2B);
11901                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2C, bMaskDWord, SYN_RF2C);
11902                 }
11903                 else     // DualMAC_DualPHY
11904                 {
11905                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x25, bMaskDWord, SYN_RF25);
11906                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x26, bMaskDWord, SYN_RF26);
11907                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x27, bMaskDWord, SYN_RF27);
11908                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2B, bMaskDWord, SYN_RF2B);
11909                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2C, bMaskDWord, SYN_RF2C);
11910                 }
11911         }
11912         //Turn on CCA
11913         ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, RXIQI);
11914         //Restore RX idle low power
11915         if(RxIdleLowPwr == TRUE)
11916                 ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 1);
11917
11918         psd_cnt++;
11919         //gPrint("psd cnt=%d\n", psd_cnt);
11920         ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD:psd_cnt = %d \n",psd_cnt));
11921         if (psd_cnt < ReScan)
11922         {
11923                 ODM_SetTimer(pDM_Odm, &pRX_HP_Table->PSDTimer, Interval);  //ms
11924         }
11925         else
11926                         {
11927                 psd_cnt = 0;
11928                 for(i=0;i<80;i++)
11929                         RT_TRACE(       COMP_PSD, DBG_LOUD,("psd_report[%d]=     %d \n", 2402+i, PSD_report[i]));
11930                         //DbgPrint("psd_report[%d]=     %d \n", 2402+i, PSD_report[i]);
11931
11932                 GoodChannelDecision(pDM_Odm, PSD_report, PSD_bitmap,RSSI_BT, PSD_bitmap_memory);
11933
11934                         }
11935                 }
11936
11937 VOID
11938 odm_PSD_RXHPCallback(
11939         PRT_TIMER               pTimer
11940 )
11941 {
11942         PADAPTER                Adapter = (PADAPTER)pTimer->Adapter;
11943         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
11944         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
11945         pRXHP_T                 pRX_HP_Table  = &pDM_Odm->DM_RXHP_Table;
11946
11947 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
11948         #if USE_WORKITEM
11949         ODM_ScheduleWorkItem(&pRX_HP_Table->PSDTimeWorkitem);
11950         #else
11951         odm_PSD_RXHP(pDM_Odm);
11952         #endif
11953 #else
11954         ODM_ScheduleWorkItem(&pRX_HP_Table->PSDTimeWorkitem);
11955 #endif
11956
11957         }
11958
11959 VOID
11960 odm_PSD_RXHPWorkitemCallback(
11961     IN PVOID            pContext
11962     )
11963 {
11964         PADAPTER        pAdapter = (PADAPTER)pContext;
11965         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
11966         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
11967
11968         odm_PSD_RXHP(pDM_Odm);
11969 }
11970
11971 #endif //#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
11972
11973 VOID
11974 odm_PathDiversityInit(
11975         IN      PDM_ODM_T       pDM_Odm
11976 )
11977 {
11978         if(!(pDM_Odm->SupportAbility & ODM_BB_PATH_DIV))
11979         {
11980                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("Return: Not Support PathDiv\n"));
11981                 return;
11982         }
11983
11984 #if RTL8812A_SUPPORT
11985
11986         if(pDM_Odm->SupportICType & ODM_RTL8812)
11987                 ODM_PathDiversityInit_8812A(pDM_Odm);
11988 #endif
11989 }
11990
11991
11992 VOID
11993 odm_PathDiversity(
11994         IN      PDM_ODM_T       pDM_Odm
11995 )
11996 {
11997         if(!(pDM_Odm->SupportAbility & ODM_BB_PATH_DIV))
11998         {
11999                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("Return: Not Support PathDiv\n"));
12000                 return;
12001         }
12002
12003 #if RTL8812A_SUPPORT
12004
12005         if(pDM_Odm->SupportICType & ODM_RTL8812)
12006                 ODM_PathDiversity_8812A(pDM_Odm);
12007 #endif
12008 }
12009
12010
12011 //
12012 // 2011/12/02 MH Copy from MP oursrc for temporarily test.
12013 //
12014 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
12015 VOID
12016 odm_OFDMTXPathDiversity_92C(
12017         IN      PADAPTER        Adapter)
12018 {
12019 //      HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
12020         PMGNT_INFO              pMgntInfo = &(Adapter->MgntInfo);
12021         PRT_WLAN_STA    pEntry;
12022         u1Byte  i, DefaultRespPath = 0;
12023         s4Byte  MinRSSI = 0xFF;
12024         pPD_T   pDM_PDTable = &Adapter->DM_PDTable;
12025         pDM_PDTable->OFDMTXPath = 0;
12026
12027         //1 Default Port
12028         if(pMgntInfo->mAssoc)
12029         {
12030                 RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: Default port RSSI[0]=%d, RSSI[1]=%d\n",
12031                         Adapter->RxStats.RxRSSIPercentage[0], Adapter->RxStats.RxRSSIPercentage[1]));
12032                 if(Adapter->RxStats.RxRSSIPercentage[0] > Adapter->RxStats.RxRSSIPercentage[1])
12033                 {
12034                         pDM_PDTable->OFDMTXPath = pDM_PDTable->OFDMTXPath & (~BIT0);
12035                         MinRSSI =  Adapter->RxStats.RxRSSIPercentage[1];
12036                         DefaultRespPath = 0;
12037                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: Default port Select Path-0\n"));
12038                 }
12039                 else
12040                 {
12041                         pDM_PDTable->OFDMTXPath =  pDM_PDTable->OFDMTXPath | BIT0;
12042                         MinRSSI =  Adapter->RxStats.RxRSSIPercentage[0];
12043                         DefaultRespPath = 1;
12044                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: Default port Select Path-1\n"));
12045                 }
12046                 //RT_TRACE(     COMP_SWAS, DBG_LOUD, ("pDM_PDTable->OFDMTXPath =0x%x\n",pDM_PDTable->OFDMTXPath));
12047         }
12048         //1 Extension Port
12049         for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
12050         {
12051                 if(IsAPModeExist(Adapter)  && GetFirstExtAdapter(Adapter) != NULL)
12052                         pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i);
12053                 else
12054                         pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i);
12055
12056                 if(pEntry!=NULL)
12057                 {
12058                         if(pEntry->bAssociated)
12059                         {
12060                                 RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: MACID=%d, RSSI_0=%d, RSSI_1=%d\n",
12061                                         pEntry->AssociatedMacId, pEntry->rssi_stat.RxRSSIPercentage[0], pEntry->rssi_stat.RxRSSIPercentage[1]));
12062
12063                                 if(pEntry->rssi_stat.RxRSSIPercentage[0] > pEntry->rssi_stat.RxRSSIPercentage[1])
12064                                 {
12065                                         pDM_PDTable->OFDMTXPath = pDM_PDTable->OFDMTXPath & ~(BIT(pEntry->AssociatedMacId));
12066                                         //pHalData->TXPath = pHalData->TXPath & ~(1<<(pEntry->AssociatedMacId));
12067                                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: MACID=%d Select Path-0\n", pEntry->AssociatedMacId));
12068                                         if(pEntry->rssi_stat.RxRSSIPercentage[1] < MinRSSI)
12069                                         {
12070                                                 MinRSSI = pEntry->rssi_stat.RxRSSIPercentage[1];
12071                                                 DefaultRespPath = 0;
12072                                         }
12073                                 }
12074                                 else
12075                                 {
12076                                         pDM_PDTable->OFDMTXPath = pDM_PDTable->OFDMTXPath | BIT(pEntry->AssociatedMacId);
12077                                         //pHalData->TXPath = pHalData->TXPath | (1 << (pEntry->AssociatedMacId));
12078                                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: MACID=%d Select Path-1\n", pEntry->AssociatedMacId));
12079                                         if(pEntry->rssi_stat.RxRSSIPercentage[0] < MinRSSI)
12080                                         {
12081                                                 MinRSSI = pEntry->rssi_stat.RxRSSIPercentage[0];
12082                                                 DefaultRespPath = 1;
12083                                         }
12084                                 }
12085                         }
12086                 }
12087                 else
12088                 {
12089                         break;
12090                 }
12091         }
12092
12093         pDM_PDTable->OFDMDefaultRespPath = DefaultRespPath;
12094 }
12095
12096
12097 BOOLEAN
12098 odm_IsConnected_92C(
12099         IN      PADAPTER        Adapter
12100 )
12101 {
12102         PRT_WLAN_STA    pEntry;
12103         PMGNT_INFO              pMgntInfo = &(Adapter->MgntInfo);
12104         u4Byte          i;
12105         BOOLEAN         bConnected=FALSE;
12106
12107         if(pMgntInfo->mAssoc)
12108         {
12109                 bConnected = TRUE;
12110         }
12111         else
12112         {
12113                 for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
12114                 {
12115                         if(IsAPModeExist(Adapter)  && GetFirstExtAdapter(Adapter) != NULL)
12116                                 pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i);
12117                         else
12118                                 pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i);
12119
12120                         if(pEntry!=NULL)
12121                         {
12122                                 if(pEntry->bAssociated)
12123                                 {
12124                                         bConnected = TRUE;
12125                                         break;
12126                                 }
12127                         }
12128                         else
12129                         {
12130                                 break;
12131                         }
12132                 }
12133         }
12134         return  bConnected;
12135 }
12136
12137
12138 VOID
12139 odm_ResetPathDiversity_92C(
12140                 IN      PADAPTER        Adapter
12141 )
12142 {
12143         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
12144         pPD_T   pDM_PDTable = &Adapter->DM_PDTable;
12145         PRT_WLAN_STA    pEntry;
12146         u4Byte  i,j;
12147
12148         pHalData->RSSI_test = FALSE;
12149         pDM_PDTable->CCK_Pkt_Cnt = 0;
12150         pDM_PDTable->OFDM_Pkt_Cnt = 0;
12151         pHalData->CCK_Pkt_Cnt =0;
12152         pHalData->OFDM_Pkt_Cnt =0;
12153
12154         if(pDM_PDTable->CCKPathDivEnable == TRUE)
12155                 PHY_SetBBReg(Adapter, rCCK0_AFESetting  , 0x0F000000, 0x01); //RX path = PathAB
12156
12157         for(i=0; i<2; i++)
12158         {
12159                 pDM_PDTable->RSSI_CCK_Path_cnt[i]=0;
12160                 pDM_PDTable->RSSI_CCK_Path[i] = 0;
12161         }
12162         for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
12163         {
12164                 if(IsAPModeExist(Adapter)  && GetFirstExtAdapter(Adapter) != NULL)
12165                         pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i);
12166                 else
12167                         pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i);
12168
12169                 if(pEntry!=NULL)
12170                 {
12171                         pEntry->rssi_stat.CCK_Pkt_Cnt = 0;
12172                         pEntry->rssi_stat.OFDM_Pkt_Cnt = 0;
12173                         for(j=0; j<2; j++)
12174                         {
12175                                 pEntry->rssi_stat.RSSI_CCK_Path_cnt[j] = 0;
12176                                 pEntry->rssi_stat.RSSI_CCK_Path[j] = 0;
12177                         }
12178                 }
12179                 else
12180                         break;
12181         }
12182 }
12183
12184
12185 VOID
12186 odm_CCKTXPathDiversity_92C(
12187         IN      PADAPTER        Adapter
12188 )
12189 {
12190         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
12191         PMGNT_INFO              pMgntInfo = &(Adapter->MgntInfo);
12192         PRT_WLAN_STA    pEntry;
12193         s4Byte  MinRSSI = 0xFF;
12194         u1Byte  i, DefaultRespPath = 0;
12195 //      BOOLEAN bBModePathDiv = FALSE;
12196         pPD_T   pDM_PDTable = &Adapter->DM_PDTable;
12197
12198         //1 Default Port
12199         if(pMgntInfo->mAssoc)
12200         {
12201                 if(pHalData->OFDM_Pkt_Cnt == 0)
12202                 {
12203                         for(i=0; i<2; i++)
12204                         {
12205                                 if(pDM_PDTable->RSSI_CCK_Path_cnt[i] > 1) //Because the first packet is discarded
12206                                         pDM_PDTable->RSSI_CCK_Path[i] = pDM_PDTable->RSSI_CCK_Path[i] / (pDM_PDTable->RSSI_CCK_Path_cnt[i]-1);
12207                                 else
12208                                         pDM_PDTable->RSSI_CCK_Path[i] = 0;
12209                         }
12210                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: pDM_PDTable->RSSI_CCK_Path[0]=%d, pDM_PDTable->RSSI_CCK_Path[1]=%d\n",
12211                                 pDM_PDTable->RSSI_CCK_Path[0], pDM_PDTable->RSSI_CCK_Path[1]));
12212                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: pDM_PDTable->RSSI_CCK_Path_cnt[0]=%d, pDM_PDTable->RSSI_CCK_Path_cnt[1]=%d\n",
12213                                 pDM_PDTable->RSSI_CCK_Path_cnt[0], pDM_PDTable->RSSI_CCK_Path_cnt[1]));
12214
12215                         if(pDM_PDTable->RSSI_CCK_Path[0] > pDM_PDTable->RSSI_CCK_Path[1])
12216                         {
12217                                 pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath & (~BIT0);
12218                                 MinRSSI =  pDM_PDTable->RSSI_CCK_Path[1];
12219                                 DefaultRespPath = 0;
12220                                 RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Default port Select CCK Path-0\n"));
12221                         }
12222                         else if(pDM_PDTable->RSSI_CCK_Path[0] < pDM_PDTable->RSSI_CCK_Path[1])
12223                         {
12224                                 pDM_PDTable->CCKTXPath =  pDM_PDTable->CCKTXPath | BIT0;
12225                                 MinRSSI =  pDM_PDTable->RSSI_CCK_Path[0];
12226                                 DefaultRespPath = 1;
12227                                 RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Default port Select CCK Path-1\n"));
12228                         }
12229                         else
12230                         {
12231                                 if((pDM_PDTable->RSSI_CCK_Path[0] != 0) && (pDM_PDTable->RSSI_CCK_Path[0] < MinRSSI))
12232                                 {
12233                                         pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath & (~BIT0);
12234                                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Default port Select CCK Path-0\n"));
12235                                         MinRSSI =  pDM_PDTable->RSSI_CCK_Path[1];
12236                                         DefaultRespPath = 0;
12237                                 }
12238                                 else
12239                                 {
12240                                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Default port unchange CCK Path\n"));
12241                                 }
12242                         }
12243                 }
12244                 else //Follow OFDM decision
12245                 {
12246                         pDM_PDTable->CCKTXPath = (pDM_PDTable->CCKTXPath & (~BIT0)) | (pDM_PDTable->OFDMTXPath &BIT0);
12247                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Follow OFDM decision, Default port Select CCK Path-%d\n",
12248                                 pDM_PDTable->CCKTXPath &BIT0));
12249                 }
12250         }
12251         //1 Extension Port
12252         for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
12253         {
12254                 if(IsAPModeExist(Adapter)  && GetFirstExtAdapter(Adapter) != NULL)
12255                         pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i);
12256                 else
12257                         pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i);
12258
12259                 if(pEntry!=NULL)
12260                 {
12261                         if(pEntry->bAssociated)
12262                         {
12263                                 if(pEntry->rssi_stat.OFDM_Pkt_Cnt == 0)
12264                                 {
12265                                         u1Byte j=0;
12266                                         for(j=0; j<2; j++)
12267                                         {
12268                                                 if(pEntry->rssi_stat.RSSI_CCK_Path_cnt[j] > 1)
12269                                                         pEntry->rssi_stat.RSSI_CCK_Path[j] = pEntry->rssi_stat.RSSI_CCK_Path[j] / (pEntry->rssi_stat.RSSI_CCK_Path_cnt[j]-1);
12270                                                 else
12271                                                         pEntry->rssi_stat.RSSI_CCK_Path[j] = 0;
12272                                         }
12273                                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d, RSSI_CCK0=%d, RSSI_CCK1=%d\n",
12274                                                 pEntry->AssociatedMacId, pEntry->rssi_stat.RSSI_CCK_Path[0], pEntry->rssi_stat.RSSI_CCK_Path[1]));
12275
12276                                         if(pEntry->rssi_stat.RSSI_CCK_Path[0] >pEntry->rssi_stat.RSSI_CCK_Path[1])
12277                                         {
12278                                                 pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath & ~(BIT(pEntry->AssociatedMacId));
12279                                                 RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d Select CCK Path-0\n", pEntry->AssociatedMacId));
12280                                                 if(pEntry->rssi_stat.RSSI_CCK_Path[1] < MinRSSI)
12281                                                 {
12282                                                         MinRSSI = pEntry->rssi_stat.RSSI_CCK_Path[1];
12283                                                         DefaultRespPath = 0;
12284                                                 }
12285                                         }
12286                                         else if(pEntry->rssi_stat.RSSI_CCK_Path[0] <pEntry->rssi_stat.RSSI_CCK_Path[1])
12287                                         {
12288                                                 pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath | BIT(pEntry->AssociatedMacId);
12289                                                 RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d Select CCK Path-1\n", pEntry->AssociatedMacId));
12290                                                 if(pEntry->rssi_stat.RSSI_CCK_Path[0] < MinRSSI)
12291                                                 {
12292                                                         MinRSSI = pEntry->rssi_stat.RSSI_CCK_Path[0];
12293                                                         DefaultRespPath = 1;
12294                                                 }
12295                                         }
12296                                         else
12297                                         {
12298                                                 if((pEntry->rssi_stat.RSSI_CCK_Path[0] != 0) && (pEntry->rssi_stat.RSSI_CCK_Path[0] < MinRSSI))
12299                                                 {
12300                                                         pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath & ~(BIT(pEntry->AssociatedMacId));
12301                                                         MinRSSI = pEntry->rssi_stat.RSSI_CCK_Path[1];
12302                                                         DefaultRespPath = 0;
12303                                                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d Select CCK Path-0\n", pEntry->AssociatedMacId));
12304                                                 }
12305                                                 else
12306                                                 {
12307                                                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d unchange CCK Path\n", pEntry->AssociatedMacId));
12308                                                 }
12309                                         }
12310                                 }
12311                                 else //Follow OFDM decision
12312                                 {
12313                                         pDM_PDTable->CCKTXPath = (pDM_PDTable->CCKTXPath & (~(BIT(pEntry->AssociatedMacId)))) | (pDM_PDTable->OFDMTXPath & BIT(pEntry->AssociatedMacId));
12314                                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Follow OFDM decision, MACID=%d Select CCK Path-%d\n",
12315                                                 pEntry->AssociatedMacId, (pDM_PDTable->CCKTXPath & BIT(pEntry->AssociatedMacId))>>(pEntry->AssociatedMacId)));
12316                                 }
12317                         }
12318                 }
12319                 else
12320                 {
12321                         break;
12322                 }
12323         }
12324
12325         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C:MinRSSI=%d\n",MinRSSI));
12326
12327         if(MinRSSI == 0xFF)
12328                 DefaultRespPath = pDM_PDTable->CCKDefaultRespPath;
12329
12330         pDM_PDTable->CCKDefaultRespPath = DefaultRespPath;
12331 }
12332
12333
12334
12335 VOID
12336 odm_PathDiversityAfterLink_92C(
12337         IN      PADAPTER        Adapter
12338 )
12339 {
12340         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
12341         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
12342         pPD_T           pDM_PDTable = &Adapter->DM_PDTable;
12343         u1Byte          DefaultRespPath=0;
12344
12345         if((!IS_92C_SERIAL(pHalData->VersionID)) || (pHalData->PathDivCfg != 1) || (pHalData->eRFPowerState == eRfOff))
12346         {
12347                 if(pHalData->PathDivCfg == 0)
12348                 {
12349                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("No ODM_TXPathDiversity()\n"));
12350                 }
12351                 else
12352                 {
12353                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("2T ODM_TXPathDiversity()\n"));
12354                 }
12355                 return;
12356         }
12357         if(!odm_IsConnected_92C(Adapter))
12358         {
12359                 RT_TRACE(       COMP_SWAS, DBG_LOUD, ("ODM_TXPathDiversity(): No Connections\n"));
12360                 return;
12361         }
12362
12363
12364         if(pDM_PDTable->TrainingState == 0)
12365         {
12366                 RT_TRACE(       COMP_SWAS, DBG_LOUD, ("ODM_TXPathDiversity() ==>\n"));
12367                 odm_OFDMTXPathDiversity_92C(Adapter);
12368
12369                 if((pDM_PDTable->CCKPathDivEnable == TRUE) && (pDM_PDTable->OFDM_Pkt_Cnt < 100))
12370                 {
12371                         //RT_TRACE(     COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: TrainingState=0\n"));
12372
12373                         if(pDM_PDTable->CCK_Pkt_Cnt > 300)
12374                                 pDM_PDTable->Timer = 20;
12375                         else if(pDM_PDTable->CCK_Pkt_Cnt > 100)
12376                                 pDM_PDTable->Timer = 60;
12377                         else
12378                                 pDM_PDTable->Timer = 250;
12379                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: timer=%d\n",pDM_PDTable->Timer));
12380
12381                         PHY_SetBBReg(Adapter, rCCK0_AFESetting  , 0x0F000000, 0x00); // RX path = PathA
12382                         pDM_PDTable->TrainingState = 1;
12383                         pHalData->RSSI_test = TRUE;
12384                         ODM_SetTimer( pDM_Odm, &pDM_Odm->CCKPathDiversityTimer, pDM_PDTable->Timer); //ms
12385                 }
12386                 else
12387                 {
12388                         pDM_PDTable->CCKTXPath = pDM_PDTable->OFDMTXPath;
12389                         DefaultRespPath = pDM_PDTable->OFDMDefaultRespPath;
12390                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_SetRespPath_92C: Skip odm_CCKTXPathDiversity_92C, DefaultRespPath is OFDM\n"));
12391                         odm_SetRespPath_92C(Adapter, DefaultRespPath);
12392                         odm_ResetPathDiversity_92C(Adapter);
12393                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("ODM_TXPathDiversity() <==\n"));
12394                 }
12395         }
12396         else if(pDM_PDTable->TrainingState == 1)
12397         {
12398                 //RT_TRACE(     COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: TrainingState=1\n"));
12399                 PHY_SetBBReg(Adapter, rCCK0_AFESetting  , 0x0F000000, 0x05); // RX path = PathB
12400                 pDM_PDTable->TrainingState = 2;
12401                 ODM_SetTimer( pDM_Odm, &pDM_Odm->CCKPathDiversityTimer, pDM_PDTable->Timer); //ms
12402         }
12403         else
12404         {
12405                 //RT_TRACE(     COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: TrainingState=2\n"));
12406                 pDM_PDTable->TrainingState = 0;
12407                 odm_CCKTXPathDiversity_92C(Adapter);
12408                 if(pDM_PDTable->OFDM_Pkt_Cnt != 0)
12409                 {
12410                         DefaultRespPath = pDM_PDTable->OFDMDefaultRespPath;
12411                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_SetRespPath_92C: DefaultRespPath is OFDM\n"));
12412                 }
12413                 else
12414                 {
12415                         DefaultRespPath = pDM_PDTable->CCKDefaultRespPath;
12416                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_SetRespPath_92C: DefaultRespPath is CCK\n"));
12417                 }
12418                 odm_SetRespPath_92C(Adapter, DefaultRespPath);
12419                 odm_ResetPathDiversity_92C(Adapter);
12420                 RT_TRACE(       COMP_SWAS, DBG_LOUD, ("ODM_TXPathDiversity() <==\n"));
12421         }
12422
12423 }
12424
12425
12426
12427 VOID
12428 odm_CCKTXPathDiversityCallback(
12429         PRT_TIMER               pTimer
12430 )
12431 {
12432 #if USE_WORKITEM
12433        PADAPTER Adapter = (PADAPTER)pTimer->Adapter;
12434        HAL_DATA_TYPE    *pHalData = GET_HAL_DATA(Adapter);
12435            PDM_ODM_T            pDM_Odm = &pHalData->DM_OutSrc;
12436 #else
12437         PADAPTER        Adapter = (PADAPTER)pTimer->Adapter;
12438 #endif
12439
12440 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
12441 #if USE_WORKITEM
12442         PlatformScheduleWorkItem(&pDM_Odm->CCKPathDiversityWorkitem);
12443 #else
12444         odm_PathDiversityAfterLink_92C(Adapter);
12445 #endif
12446 #else
12447         PlatformScheduleWorkItem(&pDM_Odm->CCKPathDiversityWorkitem);
12448 #endif
12449
12450 }
12451
12452
12453 VOID
12454 odm_CCKTXPathDiversityWorkItemCallback(
12455     IN PVOID            pContext
12456     )
12457 {
12458         PADAPTER        Adapter = (PADAPTER)pContext;
12459
12460         odm_CCKTXPathDiversity_92C(Adapter);
12461 }
12462
12463
12464 VOID
12465 ODM_CCKPathDiversityChkPerPktRssi(
12466         PADAPTER                Adapter,
12467         BOOLEAN                 bIsDefPort,
12468         BOOLEAN                 bMatchBSSID,
12469         PRT_WLAN_STA    pEntry,
12470         PRT_RFD                 pRfd,
12471         pu1Byte                 pDesc
12472         )
12473 {
12474         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
12475         BOOLEAN                 bCount = FALSE;
12476         pPD_T   pDM_PDTable = &Adapter->DM_PDTable;
12477         //BOOLEAN       isCCKrate = RX_HAL_IS_CCK_RATE_92C(pDesc);
12478 #if DEV_BUS_TYPE != RT_SDIO_INTERFACE
12479         BOOLEAN isCCKrate = RX_HAL_IS_CCK_RATE(Adapter, pDesc);
12480 #else  //below code would be removed if we have verified SDIO
12481         BOOLEAN isCCKrate = IS_HARDWARE_TYPE_8188E(Adapter) ? RX_HAL_IS_CCK_RATE_88E(pDesc) : RX_HAL_IS_CCK_RATE_92C(pDesc);
12482 #endif
12483
12484         if((pHalData->PathDivCfg != 1) || (pHalData->RSSI_test == FALSE))
12485                 return;
12486
12487         if(pHalData->RSSI_target==NULL && bIsDefPort && bMatchBSSID)
12488                 bCount = TRUE;
12489         else if(pHalData->RSSI_target!=NULL && pEntry!=NULL && pHalData->RSSI_target==pEntry)
12490                 bCount = TRUE;
12491
12492         if(bCount && isCCKrate)
12493         {
12494                 if(pDM_PDTable->TrainingState == 1 )
12495                 {
12496                         if(pEntry)
12497                         {
12498                                 if(pEntry->rssi_stat.RSSI_CCK_Path_cnt[0] != 0)
12499                                         pEntry->rssi_stat.RSSI_CCK_Path[0] += pRfd->Status.RxPWDBAll;
12500                                 pEntry->rssi_stat.RSSI_CCK_Path_cnt[0]++;
12501                         }
12502                         else
12503                         {
12504                                 if(pDM_PDTable->RSSI_CCK_Path_cnt[0] != 0)
12505                                         pDM_PDTable->RSSI_CCK_Path[0] += pRfd->Status.RxPWDBAll;
12506                                 pDM_PDTable->RSSI_CCK_Path_cnt[0]++;
12507                         }
12508                 }
12509                 else if(pDM_PDTable->TrainingState == 2 )
12510                 {
12511                         if(pEntry)
12512                         {
12513                                 if(pEntry->rssi_stat.RSSI_CCK_Path_cnt[1] != 0)
12514                                         pEntry->rssi_stat.RSSI_CCK_Path[1] += pRfd->Status.RxPWDBAll;
12515                                 pEntry->rssi_stat.RSSI_CCK_Path_cnt[1]++;
12516                         }
12517                         else
12518                         {
12519                                 if(pDM_PDTable->RSSI_CCK_Path_cnt[1] != 0)
12520                                         pDM_PDTable->RSSI_CCK_Path[1] += pRfd->Status.RxPWDBAll;
12521                                 pDM_PDTable->RSSI_CCK_Path_cnt[1]++;
12522                         }
12523                 }
12524         }
12525 }
12526
12527
12528 BOOLEAN
12529 ODM_PathDiversityBeforeLink92C(
12530         //IN    PADAPTER        Adapter
12531         IN              PDM_ODM_T               pDM_Odm
12532         )
12533 {
12534 #if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM)
12535         PADAPTER                Adapter = pDM_Odm->Adapter;
12536         HAL_DATA_TYPE*  pHalData = NULL;
12537         PMGNT_INFO              pMgntInfo = NULL;
12538         //pSWAT_T               pDM_SWAT_Table = &Adapter->DM_SWAT_Table;
12539         pPD_T                   pDM_PDTable = NULL;
12540
12541         s1Byte                  Score = 0;
12542         PRT_WLAN_BSS    pTmpBssDesc;
12543         PRT_WLAN_BSS    pTestBssDesc;
12544
12545         u1Byte                  target_chnl = 0;
12546         u1Byte                  index;
12547
12548         if (pDM_Odm->Adapter == NULL)  //For BSOD when plug/unplug fast.  //By YJ,120413
12549         {       // The ODM structure is not initialized.
12550                 return FALSE;
12551         }
12552         pHalData = GET_HAL_DATA(Adapter);
12553         pMgntInfo = &Adapter->MgntInfo;
12554         pDM_PDTable = &Adapter->DM_PDTable;
12555
12556         // Condition that does not need to use path diversity.
12557         if((!IS_92C_SERIAL(pHalData->VersionID)) || (pHalData->PathDivCfg!=1) || pMgntInfo->AntennaTest )
12558         {
12559                 RT_TRACE(COMP_SWAS, DBG_LOUD,
12560                                 ("ODM_PathDiversityBeforeLink92C(): No PathDiv Mechanism before link.\n"));
12561                 return FALSE;
12562         }
12563
12564         // Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF.
12565         PlatformAcquireSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
12566         if(pHalData->eRFPowerState!=eRfOn || pMgntInfo->RFChangeInProgress || pMgntInfo->bMediaConnect)
12567         {
12568                 PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
12569
12570                 RT_TRACE(COMP_SWAS, DBG_LOUD,
12571                                 ("ODM_PathDiversityBeforeLink92C(): RFChangeInProgress(%x), eRFPowerState(%x)\n",
12572                                 pMgntInfo->RFChangeInProgress,
12573                                 pHalData->eRFPowerState));
12574
12575                 //pDM_SWAT_Table->SWAS_NoLink_State = 0;
12576                 pDM_PDTable->PathDiv_NoLink_State = 0;
12577
12578                 return FALSE;
12579         }
12580         else
12581         {
12582                 PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
12583         }
12584
12585         //1 Run AntDiv mechanism "Before Link" part.
12586         //if(pDM_SWAT_Table->SWAS_NoLink_State == 0)
12587         if(pDM_PDTable->PathDiv_NoLink_State == 0)
12588         {
12589                 //1 Prepare to do Scan again to check current antenna state.
12590
12591                 // Set check state to next step.
12592                 //pDM_SWAT_Table->SWAS_NoLink_State = 1;
12593                 pDM_PDTable->PathDiv_NoLink_State = 1;
12594
12595                 // Copy Current Scan list.
12596                 Adapter->MgntInfo.tmpNumBssDesc = pMgntInfo->NumBssDesc;
12597                 PlatformMoveMemory((PVOID)Adapter->MgntInfo.tmpbssDesc, (PVOID)pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC);
12598
12599                 // Switch Antenna to another one.
12600                 if(pDM_PDTable->DefaultRespPath == 0)
12601                 {
12602                         PHY_SetBBReg(Adapter, rCCK0_AFESetting  , 0x0F000000, 0x05); // TRX path = PathB
12603                         odm_SetRespPath_92C(Adapter, 1);
12604                         pDM_PDTable->OFDMTXPath = 0xFFFFFFFF;
12605                         pDM_PDTable->CCKTXPath = 0xFFFFFFFF;
12606                 }
12607                 else
12608                 {
12609                         PHY_SetBBReg(Adapter, rCCK0_AFESetting  , 0x0F000000, 0x00); // TRX path = PathA
12610                         odm_SetRespPath_92C(Adapter, 0);
12611                         pDM_PDTable->OFDMTXPath = 0x0;
12612                         pDM_PDTable->CCKTXPath = 0x0;
12613                 }
12614 #if 0
12615
12616                 pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna;
12617                 pDM_SWAT_Table->CurAntenna = (pDM_SWAT_Table->CurAntenna==Antenna_A)?Antenna_B:Antenna_A;
12618
12619                 RT_TRACE(COMP_SWAS, DBG_LOUD,
12620                         ("ODM_SwAntDivCheckBeforeLink: Change to Ant(%s) for testing.\n", (pDM_SWAT_Table->CurAntenna==Antenna_A)?"A":"B"));
12621                 //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, DM_SWAT_Table.CurAntenna);
12622                 pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 & 0xfffffcff) | (pDM_SWAT_Table->CurAntenna<<8));
12623                 PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg860);
12624 #endif
12625
12626                 // Go back to scan function again.
12627                 RT_TRACE(COMP_SWAS, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C: Scan one more time\n"));
12628                 pMgntInfo->ScanStep=0;
12629                 target_chnl = odm_SwAntDivSelectScanChnl(Adapter);
12630                 odm_SwAntDivConstructScanChnl(Adapter, target_chnl);
12631                 PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5);
12632
12633                 return TRUE;
12634         }
12635         else
12636         {
12637                 //1 ScanComple() is called after antenna swiched.
12638                 //1 Check scan result and determine which antenna is going
12639                 //1 to be used.
12640
12641                 for(index=0; index<Adapter->MgntInfo.tmpNumBssDesc; index++)
12642                 {
12643                         pTmpBssDesc = &(Adapter->MgntInfo.tmpbssDesc[index]);
12644                         pTestBssDesc = &(pMgntInfo->bssDesc[index]);
12645
12646                         if(PlatformCompareMemory(pTestBssDesc->bdBssIdBuf, pTmpBssDesc->bdBssIdBuf, 6)!=0)
12647                         {
12648                                 RT_TRACE(COMP_SWAS, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C(): ERROR!! This shall not happen.\n"));
12649                                 continue;
12650                         }
12651
12652                         if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower)
12653                         {
12654                                 RT_TRACE(COMP_SWAS, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C: Compare scan entry: Score++\n"));
12655                                 RT_PRINT_STR(COMP_SWAS, DBG_LOUD, "SSID: ", pTestBssDesc->bdSsIdBuf, pTestBssDesc->bdSsIdLen);
12656                                 RT_TRACE(COMP_SWAS, DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
12657
12658                                 Score++;
12659                                 PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS));
12660                         }
12661                         else if(pTmpBssDesc->RecvSignalPower < pTestBssDesc->RecvSignalPower)
12662                         {
12663                                 RT_TRACE(COMP_SWAS, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C: Compare scan entry: Score--\n"));
12664                                 RT_PRINT_STR(COMP_SWAS, DBG_LOUD, "SSID: ", pTestBssDesc->bdSsIdBuf, pTestBssDesc->bdSsIdLen);
12665                                 RT_TRACE(COMP_SWAS, DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
12666                                 Score--;
12667                         }
12668
12669                 }
12670
12671                 if(pMgntInfo->NumBssDesc!=0 && Score<=0)
12672                 {
12673                         RT_TRACE(COMP_SWAS, DBG_LOUD,
12674                                 ("ODM_PathDiversityBeforeLink92C(): DefaultRespPath=%d\n", pDM_PDTable->DefaultRespPath));
12675
12676                         //pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna;
12677                 }
12678                 else
12679                 {
12680                         RT_TRACE(COMP_SWAS, DBG_LOUD,
12681                                 ("ODM_PathDiversityBeforeLink92C(): DefaultRespPath=%d\n", pDM_PDTable->DefaultRespPath));
12682
12683                         if(pDM_PDTable->DefaultRespPath == 0)
12684                         {
12685                                 pDM_PDTable->OFDMTXPath = 0xFFFFFFFF;
12686                                 pDM_PDTable->CCKTXPath = 0xFFFFFFFF;
12687                                 odm_SetRespPath_92C(Adapter, 1);
12688                         }
12689                         else
12690                         {
12691                                 pDM_PDTable->OFDMTXPath = 0x0;
12692                                 pDM_PDTable->CCKTXPath = 0x0;
12693                                 odm_SetRespPath_92C(Adapter, 0);
12694                         }
12695                         PHY_SetBBReg(Adapter, rCCK0_AFESetting  , 0x0F000000, 0x01); // RX path = PathAB
12696
12697                         //pDM_SWAT_Table->CurAntenna = pDM_SWAT_Table->PreAntenna;
12698
12699                         //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, DM_SWAT_Table.CurAntenna);
12700                         //pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 & 0xfffffcff) | (pDM_SWAT_Table->CurAntenna<<8));
12701                         //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg860);
12702                 }
12703
12704                 // Check state reset to default and wait for next time.
12705                 //pDM_SWAT_Table->SWAS_NoLink_State = 0;
12706                 pDM_PDTable->PathDiv_NoLink_State = 0;
12707
12708                 return FALSE;
12709         }
12710 #else
12711                 return  FALSE;
12712 #endif
12713
12714 }
12715
12716
12717 //Neil Chen---2011--06--22
12718 //----92D Path Diversity----//
12719 //#ifdef PathDiv92D
12720 //==================================
12721 //3 Path Diversity
12722 //==================================
12723 //
12724 // 20100514 Luke/Joseph:
12725 // Add new function for antenna diversity after link.
12726 // This is the main function of antenna diversity after link.
12727 // This function is called in HalDmWatchDog() and ODM_SwAntDivChkAntSwitchCallback().
12728 // HalDmWatchDog() calls this function with SWAW_STEP_PEAK to initialize the antenna test.
12729 // In SWAW_STEP_PEAK, another antenna and a 500ms timer will be set for testing.
12730 // After 500ms, ODM_SwAntDivChkAntSwitchCallback() calls this function to compare the signal just
12731 // listened on the air with the RSSI of original antenna.
12732 // It chooses the antenna with better RSSI.
12733 // There is also a aged policy for error trying. Each error trying will cost more 5 seconds waiting
12734 // penalty to get next try.
12735 //
12736 //
12737 // 20100503 Joseph:
12738 // Add new function SwAntDivCheck8192C().
12739 // This is the main function of Antenna diversity function before link.
12740 // Mainly, it just retains last scan result and scan again.
12741 // After that, it compares the scan result to see which one gets better RSSI.
12742 // It selects antenna with better receiving power and returns better scan result.
12743 //
12744
12745
12746 //
12747 // 20100514 Luke/Joseph:
12748 // This function is used to gather the RSSI information for antenna testing.
12749 // It selects the RSSI of the peer STA that we want to know.
12750 //
12751 VOID
12752 ODM_PathDivChkPerPktRssi(
12753         PADAPTER                Adapter,
12754         BOOLEAN                 bIsDefPort,
12755         BOOLEAN                 bMatchBSSID,
12756         PRT_WLAN_STA    pEntry,
12757         PRT_RFD                 pRfd
12758         )
12759 {
12760         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
12761         BOOLEAN                 bCount = FALSE;
12762         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
12763         pSWAT_T                 pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
12764
12765         if(pHalData->RSSI_target==NULL && bIsDefPort && bMatchBSSID)
12766                 bCount = TRUE;
12767         else if(pHalData->RSSI_target!=NULL && pEntry!=NULL && pHalData->RSSI_target==pEntry)
12768                 bCount = TRUE;
12769
12770         if(bCount)
12771         {
12772                 //1 RSSI for SW Antenna Switch
12773                 if(pDM_SWAT_Table->CurAntenna == MAIN_ANT)
12774                 {
12775                         pHalData->RSSI_sum_A += pRfd->Status.RxPWDBAll;
12776                         pHalData->RSSI_cnt_A++;
12777                 }
12778                 else
12779                 {
12780                         pHalData->RSSI_sum_B += pRfd->Status.RxPWDBAll;
12781                         pHalData->RSSI_cnt_B++;
12782
12783                 }
12784         }
12785 }
12786
12787
12788
12789 //
12790 // 20100514 Luke/Joseph:
12791 // Add new function to reset antenna diversity state after link.
12792 //
12793 VOID
12794 ODM_PathDivRestAfterLink(
12795         IN      PDM_ODM_T               pDM_Odm
12796         )
12797 {
12798         PADAPTER                Adapter=pDM_Odm->Adapter;
12799         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
12800         pSWAT_T                 pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
12801
12802         pHalData->RSSI_cnt_A = 0;
12803         pHalData->RSSI_cnt_B = 0;
12804         pHalData->RSSI_test = FALSE;
12805         pDM_SWAT_Table->try_flag = 0x0;       // NOT 0xff
12806         pDM_SWAT_Table->RSSI_Trying = 0;
12807         pDM_SWAT_Table->SelectAntennaMap=0xAA;
12808         pDM_SWAT_Table->CurAntenna = MAIN_ANT;
12809 }
12810
12811
12812 //
12813 // 20100514 Luke/Joseph:
12814 // Callback function for 500ms antenna test trying.
12815 //
12816 VOID
12817 odm_PathDivChkAntSwitchCallback(
12818         PRT_TIMER               pTimer
12819 )
12820 {
12821         PADAPTER                Adapter = (PADAPTER)pTimer->Adapter;
12822         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
12823         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
12824
12825 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
12826
12827 #if USE_WORKITEM
12828         PlatformScheduleWorkItem(&pDM_Odm->PathDivSwitchWorkitem);
12829 #else
12830         odm_PathDivChkAntSwitch(pDM_Odm);
12831 #endif
12832 #else
12833         PlatformScheduleWorkItem(&pDM_Odm->PathDivSwitchWorkitem);
12834 #endif
12835
12836 //odm_SwAntDivChkAntSwitch(Adapter, SWAW_STEP_DETERMINE);
12837
12838 }
12839
12840
12841 VOID
12842 odm_PathDivChkAntSwitchWorkitemCallback(
12843     IN PVOID            pContext
12844     )
12845 {
12846         PADAPTER        pAdapter = (PADAPTER)pContext;
12847         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
12848         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
12849
12850         odm_PathDivChkAntSwitch(pDM_Odm);
12851 }
12852
12853
12854  //MAC0_ACCESS_PHY1
12855
12856 // 2011-06-22 Neil Chen & Gary Hsin
12857 // Refer to Jr.Luke's SW ANT DIV
12858 // 92D Path Diversity Main function
12859 // refer to 88C software antenna diversity
12860 //
12861 VOID
12862 odm_PathDivChkAntSwitch(
12863         PDM_ODM_T               pDM_Odm
12864         //PADAPTER              Adapter,
12865         //u1Byte                        Step
12866 )
12867 {
12868         PADAPTER                Adapter = pDM_Odm->Adapter;
12869         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
12870         PMGNT_INFO              pMgntInfo = &Adapter->MgntInfo;
12871
12872
12873         pSWAT_T                 pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
12874         s4Byte                  curRSSI=100, RSSI_A, RSSI_B;
12875         u1Byte                  nextAntenna=AUX_ANT;
12876         static u8Byte           lastTxOkCnt=0, lastRxOkCnt=0;
12877         u8Byte                  curTxOkCnt, curRxOkCnt;
12878         static u8Byte           TXByteCnt_A=0, TXByteCnt_B=0, RXByteCnt_A=0, RXByteCnt_B=0;
12879         u8Byte                  CurByteCnt=0, PreByteCnt=0;
12880         static u1Byte           TrafficLoad = TRAFFIC_LOW;
12881         u1Byte                  Score_A=0, Score_B=0;
12882         u1Byte                  i=0x0;
12883        // Neil Chen
12884        static u1Byte        pathdiv_para=0x0;
12885        static u1Byte        switchfirsttime=0x00;
12886         // u1Byte                 regB33 = (u1Byte) PHY_QueryBBReg(Adapter, 0xB30,BIT27);
12887         u1Byte                  regB33 = (u1Byte)ODM_GetBBReg(pDM_Odm, PATHDIV_REG, BIT27);
12888
12889
12890        //u1Byte                 reg637 =0x0;
12891        static u1Byte        fw_value=0x0;
12892         //u8Byte                        curTxOkCnt_tmp, curRxOkCnt_tmp;
12893        PADAPTER            BuddyAdapter = Adapter->BuddyAdapter;     // another adapter MAC
12894         // Path Diversity   //Neil Chen--2011--06--22
12895
12896         //u1Byte                 PathDiv_Trigger = (u1Byte) PHY_QueryBBReg(Adapter, 0xBA0,BIT31);
12897         u1Byte                 PathDiv_Trigger = (u1Byte) ODM_GetBBReg(pDM_Odm, PATHDIV_TRI,BIT31);
12898         u1Byte                 PathDiv_Enable = pHalData->bPathDiv_Enable;
12899
12900
12901         //DbgPrint("Path Div PG Value:%x \n",PathDiv_Enable);
12902        if((BuddyAdapter==NULL)||(!PathDiv_Enable)||(PathDiv_Trigger)||(pHalData->CurrentBandType == BAND_ON_2_4G))
12903        {
12904            return;
12905        }
12906         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD,("===================>odm_PathDivChkAntSwitch()\n"));
12907
12908        // The first time to switch path excluding 2nd, 3rd, ....etc....
12909         if(switchfirsttime==0)
12910         {
12911             if(regB33==0)
12912             {
12913                pDM_SWAT_Table->CurAntenna = MAIN_ANT;    // Default MAC0_5G-->Path A (current antenna)
12914             }
12915         }
12916
12917         // Condition that does not need to use antenna diversity.
12918         if(pDM_Odm->SupportICType != ODM_RTL8192D)
12919         {
12920                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_PathDiversityMechanims(): No PathDiv Mechanism.\n"));
12921                 return;
12922         }
12923
12924         // Radio off: Status reset to default and return.
12925         if(pHalData->eRFPowerState==eRfOff)
12926         {
12927                 //ODM_SwAntDivRestAfterLink(Adapter);
12928                 return;
12929         }
12930
12931        /*
12932         // Handling step mismatch condition.
12933         // Peak step is not finished at last time. Recover the variable and check again.
12934         if(     Step != pDM_SWAT_Table->try_flag        )
12935         {
12936                 ODM_SwAntDivRestAfterLink(Adapter);
12937         } */
12938
12939         if(pDM_SWAT_Table->try_flag == 0xff)
12940         {
12941                 // Select RSSI checking target
12942                 if(pMgntInfo->mAssoc && !ACTING_AS_AP(Adapter))
12943                 {
12944                         // Target: Infrastructure mode AP.
12945                         pHalData->RSSI_target = NULL;
12946                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_PathDivMechanism(): RSSI_target is DEF AP!\n"));
12947                 }
12948                 else
12949                 {
12950                         u1Byte                  index = 0;
12951                         PRT_WLAN_STA    pEntry = NULL;
12952                         PADAPTER                pTargetAdapter = NULL;
12953
12954                         if(     pMgntInfo->mIbss || ACTING_AS_AP(Adapter) )
12955                         {
12956                                 // Target: AP/IBSS peer.
12957                                 pTargetAdapter = Adapter;
12958                         }
12959                         else if(IsAPModeExist(Adapter)  && GetFirstExtAdapter(Adapter) != NULL)
12960                         {
12961                                 // Target: VWIFI peer.
12962                                 pTargetAdapter = GetFirstExtAdapter(Adapter);
12963                         }
12964
12965                         if(pTargetAdapter != NULL)
12966                         {
12967                                 for(index=0; index<ODM_ASSOCIATE_ENTRY_NUM; index++)
12968                                 {
12969                                         pEntry = AsocEntry_EnumStation(pTargetAdapter, index);
12970                                         if(pEntry != NULL)
12971                                         {
12972                                                 if(pEntry->bAssociated)
12973                                                         break;
12974                                         }
12975                                 }
12976                         }
12977
12978                         if(pEntry == NULL)
12979                         {
12980                                 ODM_PathDivRestAfterLink(pDM_Odm);
12981                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): No Link.\n"));
12982                                 return;
12983                         }
12984                         else
12985                         {
12986                                 pHalData->RSSI_target = pEntry;
12987                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): RSSI_target is PEER STA\n"));
12988                         }
12989                 }
12990
12991                 pHalData->RSSI_cnt_A = 0;
12992                 pHalData->RSSI_cnt_B = 0;
12993                 pDM_SWAT_Table->try_flag = 0;
12994                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): Set try_flag to 0 prepare for peak!\n"));
12995                 return;
12996         }
12997         else
12998         {
12999                // 1st step
13000                 curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - lastTxOkCnt;
13001                 curRxOkCnt = Adapter->RxStats.NumRxBytesUnicast - lastRxOkCnt;
13002                 lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast;
13003                 lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast;
13004
13005                 if(pDM_SWAT_Table->try_flag == 1)   // Training State
13006                 {
13007                         if(pDM_SWAT_Table->CurAntenna == MAIN_ANT)
13008                         {
13009                                 TXByteCnt_A += curTxOkCnt;
13010                                 RXByteCnt_A += curRxOkCnt;
13011                         }
13012                         else
13013                         {
13014                                 TXByteCnt_B += curTxOkCnt;
13015                                 RXByteCnt_B += curRxOkCnt;
13016                         }
13017
13018                         nextAntenna = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? AUX_ANT : MAIN_ANT;
13019                         pDM_SWAT_Table->RSSI_Trying--;
13020                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: RSSI_Trying = %d\n",pDM_SWAT_Table->RSSI_Trying));
13021                         if(pDM_SWAT_Table->RSSI_Trying == 0)
13022                         {
13023                                 CurByteCnt = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? (TXByteCnt_A+RXByteCnt_A) : (TXByteCnt_B+RXByteCnt_B);
13024                                 PreByteCnt = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? (TXByteCnt_B+RXByteCnt_B) : (TXByteCnt_A+RXByteCnt_A);
13025
13026                                 if(TrafficLoad == TRAFFIC_HIGH)
13027                                 {
13028                                         //CurByteCnt = PlatformDivision64(CurByteCnt, 9);
13029                                         PreByteCnt =PreByteCnt*9;
13030                                 }
13031                                 else if(TrafficLoad == TRAFFIC_LOW)
13032                                 {
13033                                         //CurByteCnt = PlatformDivision64(CurByteCnt, 2);
13034                                         PreByteCnt =PreByteCnt*2;
13035                                 }
13036                                 if(pHalData->RSSI_cnt_A > 0)
13037                                         RSSI_A = pHalData->RSSI_sum_A/pHalData->RSSI_cnt_A;
13038                                 else
13039                                         RSSI_A = 0;
13040                                 if(pHalData->RSSI_cnt_B > 0)
13041                                         RSSI_B = pHalData->RSSI_sum_B/pHalData->RSSI_cnt_B;
13042                              else
13043                                         RSSI_B = 0;
13044                                 curRSSI = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? RSSI_A : RSSI_B;
13045                                 pDM_SWAT_Table->PreRSSI =  (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? RSSI_B : RSSI_A;
13046                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: PreRSSI = %d, CurRSSI = %d\n",pDM_SWAT_Table->PreRSSI, curRSSI));
13047                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: preAntenna= %s, curAntenna= %s \n",
13048                                 (pDM_SWAT_Table->PreAntenna == MAIN_ANT?"MAIN":"AUX"), (pDM_SWAT_Table->CurAntenna == MAIN_ANT?"MAIN":"AUX")));
13049                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: RSSI_A= %d, RSSI_cnt_A = %d, RSSI_B= %d, RSSI_cnt_B = %d\n",
13050                                         RSSI_A, pHalData->RSSI_cnt_A, RSSI_B, pHalData->RSSI_cnt_B));
13051                         }
13052
13053                 }
13054                 else   // try_flag=0
13055                 {
13056
13057                         if(pHalData->RSSI_cnt_A > 0)
13058                                 RSSI_A = pHalData->RSSI_sum_A/pHalData->RSSI_cnt_A;
13059                         else
13060                                 RSSI_A = 0;
13061                         if(pHalData->RSSI_cnt_B > 0)
13062                                 RSSI_B = pHalData->RSSI_sum_B/pHalData->RSSI_cnt_B;
13063                         else
13064                                 RSSI_B = 0;
13065                         curRSSI = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? RSSI_A : RSSI_B;
13066                         pDM_SWAT_Table->PreRSSI =  (pDM_SWAT_Table->PreAntenna == MAIN_ANT)? RSSI_A : RSSI_B;
13067                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: PreRSSI = %d, CurRSSI = %d\n", pDM_SWAT_Table->PreRSSI, curRSSI));
13068                        ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: preAntenna= %s, curAntenna= %s \n",
13069                         (pDM_SWAT_Table->PreAntenna == MAIN_ANT?"MAIN":"AUX"), (pDM_SWAT_Table->CurAntenna == MAIN_ANT?"MAIN":"AUX")));
13070
13071                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: RSSI_A= %d, RSSI_cnt_A = %d, RSSI_B= %d, RSSI_cnt_B = %d\n",
13072                                 RSSI_A, pHalData->RSSI_cnt_A, RSSI_B, pHalData->RSSI_cnt_B));
13073                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Ekul:curTxOkCnt = %d\n", curTxOkCnt));
13074                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Ekul:curRxOkCnt = %d\n", curRxOkCnt));
13075                 }
13076
13077                 //1 Trying State
13078                 if((pDM_SWAT_Table->try_flag == 1)&&(pDM_SWAT_Table->RSSI_Trying == 0))
13079                 {
13080
13081                         if(pDM_SWAT_Table->TestMode == TP_MODE)
13082                         {
13083                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: TestMode = TP_MODE"));
13084                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH= TRY:CurByteCnt = %"i64fmt"d,", CurByteCnt));
13085                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH= TRY:PreByteCnt = %"i64fmt"d\n",PreByteCnt));
13086                                 if(CurByteCnt < PreByteCnt)
13087                                 {
13088                                         if(pDM_SWAT_Table->CurAntenna == MAIN_ANT)
13089                                                 pDM_SWAT_Table->SelectAntennaMap=pDM_SWAT_Table->SelectAntennaMap<<1;
13090                                         else
13091                                                 pDM_SWAT_Table->SelectAntennaMap=(pDM_SWAT_Table->SelectAntennaMap<<1)+1;
13092                                 }
13093                                 else
13094                                 {
13095                                         if(pDM_SWAT_Table->CurAntenna == MAIN_ANT)
13096                                                 pDM_SWAT_Table->SelectAntennaMap=(pDM_SWAT_Table->SelectAntennaMap<<1)+1;
13097                                         else
13098                                                 pDM_SWAT_Table->SelectAntennaMap=pDM_SWAT_Table->SelectAntennaMap<<1;
13099                                 }
13100                                 for (i= 0; i<8; i++)
13101                                 {
13102                                         if(((pDM_SWAT_Table->SelectAntennaMap>>i)&BIT0) == 1)
13103                                                 Score_A++;
13104                                         else
13105                                                 Score_B++;
13106                                 }
13107                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("SelectAntennaMap=%x\n ",pDM_SWAT_Table->SelectAntennaMap));
13108                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Score_A=%d, Score_B=%d\n", Score_A, Score_B));
13109
13110                                 if(pDM_SWAT_Table->CurAntenna == MAIN_ANT)
13111                                 {
13112                                         nextAntenna = (Score_A >= Score_B)?MAIN_ANT:AUX_ANT;
13113                                 }
13114                                 else
13115                                 {
13116                                         nextAntenna = (Score_B >= Score_A)?AUX_ANT:MAIN_ANT;
13117                                 }
13118                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: nextAntenna=%s\n",(nextAntenna==MAIN_ANT)?"MAIN":"AUX"));
13119                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: preAntenna= %s, curAntenna= %s \n",
13120                                 (pDM_SWAT_Table->PreAntenna == MAIN_ANT?"MAIN":"AUX"), (pDM_SWAT_Table->CurAntenna == MAIN_ANT?"MAIN":"AUX")));
13121
13122                                 if(nextAntenna != pDM_SWAT_Table->CurAntenna)
13123                                 {
13124                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Switch back to another antenna"));
13125                                 }
13126                                 else
13127                                 {
13128                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: current anntena is good\n"));
13129                                 }
13130                         }
13131
13132
13133                         if(pDM_SWAT_Table->TestMode == RSSI_MODE)
13134                         {
13135                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: TestMode = RSSI_MODE"));
13136                                 pDM_SWAT_Table->SelectAntennaMap=0xAA;
13137                                 if(curRSSI < pDM_SWAT_Table->PreRSSI) //Current antenna is worse than previous antenna
13138                                 {
13139                                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("SWAS: Switch back to another antenna"));
13140                                         nextAntenna = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)?AUX_ANT : MAIN_ANT;
13141                                 }
13142                                 else // current anntena is good
13143                                 {
13144                                         nextAntenna =pDM_SWAT_Table->CurAntenna;
13145                                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("SWAS: current anntena is good\n"));
13146                                 }
13147                         }
13148
13149                         pDM_SWAT_Table->try_flag = 0;
13150                         pHalData->RSSI_test = FALSE;
13151                         pHalData->RSSI_sum_A = 0;
13152                         pHalData->RSSI_cnt_A = 0;
13153                         pHalData->RSSI_sum_B = 0;
13154                         pHalData->RSSI_cnt_B = 0;
13155                         TXByteCnt_A = 0;
13156                         TXByteCnt_B = 0;
13157                         RXByteCnt_A = 0;
13158                         RXByteCnt_B = 0;
13159
13160                 }
13161
13162                 //1 Normal State
13163                 else if(pDM_SWAT_Table->try_flag == 0)
13164                 {
13165                         if(TrafficLoad == TRAFFIC_HIGH)
13166                         {
13167                                 if ((curTxOkCnt+curRxOkCnt) > 3750000)//if(PlatformDivision64(curTxOkCnt+curRxOkCnt, 2) > 1875000)
13168                                         TrafficLoad = TRAFFIC_HIGH;
13169                                 else
13170                                         TrafficLoad = TRAFFIC_LOW;
13171                         }
13172                         else if(TrafficLoad == TRAFFIC_LOW)
13173                                 {
13174                                 if ((curTxOkCnt+curRxOkCnt) > 3750000)//if(PlatformDivision64(curTxOkCnt+curRxOkCnt, 2) > 1875000)
13175                                         TrafficLoad = TRAFFIC_HIGH;
13176                                 else
13177                                         TrafficLoad = TRAFFIC_LOW;
13178                         }
13179                         if(TrafficLoad == TRAFFIC_HIGH)
13180                                 pDM_SWAT_Table->bTriggerAntennaSwitch = 0;
13181                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Normal:TrafficLoad = %llu\n", curTxOkCnt+curRxOkCnt));
13182
13183                         //Prepare To Try Antenna
13184                                 nextAntenna = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? AUX_ANT : MAIN_ANT;
13185                                 pDM_SWAT_Table->try_flag = 1;
13186                                 pHalData->RSSI_test = TRUE;
13187                         if((curRxOkCnt+curTxOkCnt) > 1000)
13188                         {
13189 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
13190                             pDM_SWAT_Table->RSSI_Trying = 4;
13191 #else
13192                             pDM_SWAT_Table->RSSI_Trying = 2;
13193 #endif
13194                                 pDM_SWAT_Table->TestMode = TP_MODE;
13195                         }
13196                         else
13197                         {
13198                                 pDM_SWAT_Table->RSSI_Trying = 2;
13199                                 pDM_SWAT_Table->TestMode = RSSI_MODE;
13200
13201                         }
13202
13203                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("SWAS: Normal State -> Begin Trying!\n"));
13204                         pHalData->RSSI_sum_A = 0;
13205                         pHalData->RSSI_cnt_A = 0;
13206                         pHalData->RSSI_sum_B = 0;
13207                         pHalData->RSSI_cnt_B = 0;
13208                 } // end of try_flag=0
13209         }
13210
13211         //1 4.Change TRX antenna
13212         if(nextAntenna != pDM_SWAT_Table->CurAntenna)
13213         {
13214
13215                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Change TX Antenna!\n "));
13216                 //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, nextAntenna); for 88C
13217                 if(nextAntenna==MAIN_ANT)
13218                 {
13219                     ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Next Antenna is RF PATH A\n "));
13220                     pathdiv_para = 0x02;   //02 to switchback to RF path A
13221                     fw_value = 0x03;
13222 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
13223                  odm_PathDiversity_8192D(pDM_Odm, pathdiv_para);
13224 #else
13225                  ODM_FillH2CCmd(Adapter, ODM_H2C_PathDiv,1,(pu1Byte)(&fw_value));
13226 #endif
13227                 }
13228                else if(nextAntenna==AUX_ANT)
13229                {
13230                    ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Next Antenna is RF PATH B\n "));
13231                    if(switchfirsttime==0)  // First Time To Enter Path Diversity
13232                    {
13233                        switchfirsttime=0x01;
13234                       pathdiv_para = 0x00;
13235                           fw_value=0x00;    // to backup RF Path A Releated Registers
13236
13237 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
13238                      odm_PathDiversity_8192D(pDM_Odm, pathdiv_para);
13239 #else
13240                      ODM_FillH2CCmd(Adapter, ODM_H2C_PathDiv,1,(pu1Byte)(&fw_value));
13241                      //for(u1Byte n=0; n<80,n++)
13242                      //{
13243                      //delay_us(500);
13244                           ODM_delay_ms(500);
13245                      odm_PathDiversity_8192D(pDM_Odm, pathdiv_para);
13246
13247                          fw_value=0x01;         // to backup RF Path A Releated Registers
13248                      ODM_FillH2CCmd(Adapter, ODM_H2C_PathDiv,1,(pu1Byte)(&fw_value));
13249 #endif
13250                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: FIRST TIME To DO PATH SWITCH!\n "));
13251                    }
13252                     else
13253                     {
13254                         pathdiv_para = 0x01;
13255                          fw_value = 0x02;
13256 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
13257                      odm_PathDiversity_8192D(pDM_Odm, pathdiv_para);
13258 #else
13259                      ODM_FillH2CCmd(Adapter, ODM_H2C_PathDiv,1,(pu1Byte)(&fw_value));
13260 #endif
13261                     }
13262                }
13263            //   odm_PathDiversity_8192D(Adapter, pathdiv_para);
13264         }
13265
13266         //1 5.Reset Statistics
13267         pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna;
13268         pDM_SWAT_Table->CurAntenna = nextAntenna;
13269         pDM_SWAT_Table->PreRSSI = curRSSI;
13270
13271         //1 6.Set next timer
13272
13273         if(pDM_SWAT_Table->RSSI_Trying == 0)
13274                 return;
13275
13276         if(pDM_SWAT_Table->RSSI_Trying%2 == 0)
13277         {
13278                 if(pDM_SWAT_Table->TestMode == TP_MODE)
13279                 {
13280                         if(TrafficLoad == TRAFFIC_HIGH)
13281                         {
13282 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
13283                                 ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 10 ); //ms
13284                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 10 ms\n"));
13285 #else
13286                                 ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 20 ); //ms
13287                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 20 ms\n"));
13288 #endif
13289                         }
13290                         else if(TrafficLoad == TRAFFIC_LOW)
13291                         {
13292                                 ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 50 ); //ms
13293                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 50 ms\n"));
13294                         }
13295                 }
13296                 else   // TestMode == RSSI_MODE
13297                 {
13298                         ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 500 ); //ms
13299                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 500 ms\n"));
13300                 }
13301         }
13302         else
13303         {
13304                 if(pDM_SWAT_Table->TestMode == TP_MODE)
13305                 {
13306                         if(TrafficLoad == TRAFFIC_HIGH)
13307
13308 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
13309                                 ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 90 ); //ms
13310                                 //ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 90 ms\n"));
13311 #else
13312                                 ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 180); //ms
13313 #endif
13314                         else if(TrafficLoad == TRAFFIC_LOW)
13315                                 ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 100 ); //ms
13316                 }
13317                 else
13318                         ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 500 ); //ms
13319         }
13320 }
13321
13322 //==================================================
13323 //3 PathDiv End
13324 //==================================================
13325
13326 VOID
13327 odm_SetRespPath_92C(
13328         IN      PADAPTER        Adapter,
13329         IN      u1Byte  DefaultRespPath
13330         )
13331 {
13332         pPD_T   pDM_PDTable = &Adapter->DM_PDTable;
13333
13334         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_SetRespPath_92C: Select Response Path=%d\n",DefaultRespPath));
13335         if(DefaultRespPath != pDM_PDTable->DefaultRespPath)
13336         {
13337                 if(DefaultRespPath == 0)
13338                 {
13339                         PlatformEFIOWrite1Byte(Adapter, 0x6D8, (PlatformEFIORead1Byte(Adapter, 0x6D8)&0xc0)|0x15);
13340                 }
13341                 else
13342                 {
13343                         PlatformEFIOWrite1Byte(Adapter, 0x6D8, (PlatformEFIORead1Byte(Adapter, 0x6D8)&0xc0)|0x2A);
13344                 }
13345         }
13346         pDM_PDTable->DefaultRespPath = DefaultRespPath;
13347 }
13348
13349
13350 VOID
13351 ODM_FillTXPathInTXDESC(
13352                 IN      PADAPTER        Adapter,
13353                 IN      PRT_TCB         pTcb,
13354                 IN      pu1Byte         pDesc
13355 )
13356 {
13357         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
13358         u4Byte  TXPath;
13359         pPD_T   pDM_PDTable = &Adapter->DM_PDTable;
13360
13361         //2011.09.05  Add by Luke Lee for path diversity
13362         if(pHalData->PathDivCfg == 1)
13363         {
13364                 TXPath = (pDM_PDTable->OFDMTXPath >> pTcb->macId) & BIT0;
13365                 //RT_TRACE(     COMP_SWAS, DBG_LOUD, ("Fill TXDESC: macID=%d, TXPath=%d\n", pTcb->macId, TXPath));
13366                 //SET_TX_DESC_TX_ANT_CCK(pDesc,TXPath);
13367                 if(TXPath == 0)
13368                 {
13369                         SET_TX_DESC_TX_ANTL_92C(pDesc,1);
13370                         SET_TX_DESC_TX_ANT_HT_92C(pDesc,1);
13371                 }
13372                 else
13373                 {
13374                         SET_TX_DESC_TX_ANTL_92C(pDesc,2);
13375                         SET_TX_DESC_TX_ANT_HT_92C(pDesc,2);
13376                 }
13377                 TXPath = (pDM_PDTable->CCKTXPath >> pTcb->macId) & BIT0;
13378                 if(TXPath == 0)
13379                 {
13380                         SET_TX_DESC_TX_ANT_CCK_92C(pDesc,1);
13381                 }
13382                 else
13383                 {
13384                         SET_TX_DESC_TX_ANT_CCK_92C(pDesc,2);
13385                 }
13386         }
13387 }
13388
13389 //Only for MP //Neil Chen--2012--0502--
13390 VOID
13391 odm_PathDivInit_92D(
13392 IN      PDM_ODM_T       pDM_Odm)
13393 {
13394         pPATHDIV_PARA   pathIQK = &pDM_Odm->pathIQK;
13395
13396         pathIQK->org_2g_RegC14=0x0;
13397         pathIQK->org_2g_RegC4C=0x0;
13398         pathIQK->org_2g_RegC80=0x0;
13399         pathIQK->org_2g_RegC94=0x0;
13400         pathIQK->org_2g_RegCA0=0x0;
13401         pathIQK->org_5g_RegC14=0x0;
13402         pathIQK->org_5g_RegCA0=0x0;
13403         pathIQK->org_5g_RegE30=0x0;
13404         pathIQK->swt_2g_RegC14=0x0;
13405         pathIQK->swt_2g_RegC4C=0x0;
13406         pathIQK->swt_2g_RegC80=0x0;
13407         pathIQK->swt_2g_RegC94=0x0;
13408         pathIQK->swt_2g_RegCA0=0x0;
13409         pathIQK->swt_5g_RegC14=0x0;
13410         pathIQK->swt_5g_RegCA0=0x0;
13411         pathIQK->swt_5g_RegE30=0x0;
13412
13413 }
13414
13415 #endif  // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
13416
13417 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))
13418
13419 VOID
13420 odm_PHY_SaveAFERegisters(
13421         IN      PDM_ODM_T       pDM_Odm,
13422         IN      pu4Byte         AFEReg,
13423         IN      pu4Byte         AFEBackup,
13424         IN      u4Byte          RegisterNum
13425         )
13426 {
13427         u4Byte  i;
13428
13429         //RT_DISP(FINIT, INIT_IQK, ("Save ADDA parameters.\n"));
13430         for( i = 0 ; i < RegisterNum ; i++){
13431                 AFEBackup[i] = ODM_GetBBReg(pDM_Odm, AFEReg[i], bMaskDWord);
13432         }
13433 }
13434
13435 VOID
13436 odm_PHY_ReloadAFERegisters(
13437         IN      PDM_ODM_T       pDM_Odm,
13438         IN      pu4Byte         AFEReg,
13439         IN      pu4Byte         AFEBackup,
13440         IN      u4Byte          RegiesterNum
13441         )
13442 {
13443         u4Byte  i;
13444
13445         //RT_DISP(FINIT, INIT_IQK, ("Reload ADDA power saving parameters !\n"));
13446         for(i = 0 ; i < RegiesterNum; i++)
13447         {
13448
13449                 ODM_SetBBReg(pDM_Odm, AFEReg[i], bMaskDWord, AFEBackup[i]);
13450         }
13451 }
13452
13453 //
13454 // Description:
13455 //      Set Single/Dual Antenna default setting for products that do not do detection in advance.
13456 //
13457 // Added by Joseph, 2012.03.22
13458 //
13459 VOID
13460 ODM_SingleDualAntennaDefaultSetting(
13461         IN              PDM_ODM_T               pDM_Odm
13462         )
13463 {
13464         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
13465         PADAPTER        pAdapter         =  pDM_Odm->Adapter;
13466         u1Byte btAntNum = 2;
13467 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
13468         btAntNum=BT_GetPgAntNum(pAdapter);
13469 #elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
13470 #ifdef CONFIG_BT_COEXIST
13471         btAntNum = hal_btcoex_GetPgAntNum(pAdapter);
13472 #endif
13473 #endif
13474
13475         // Set default antenna A and B status
13476         if(btAntNum == 2)
13477         {
13478                 pDM_SWAT_Table->ANTA_ON=TRUE;
13479                 pDM_SWAT_Table->ANTB_ON=TRUE;
13480                 //RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("Dual antenna\n"));
13481         }
13482 #ifdef CONFIG_BT_COEXIST
13483         else if(btAntNum == 1)
13484         {// Set antenna A as default
13485                 pDM_SWAT_Table->ANTA_ON=TRUE;
13486                 pDM_SWAT_Table->ANTB_ON=FALSE;
13487                 //RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("Single antenna\n"));
13488         }
13489         else
13490         {
13491                 //RT_ASSERT(FALSE, ("Incorrect antenna number!!\n"));
13492         }
13493 #endif
13494 }
13495
13496
13497
13498 //2 8723A ANT DETECT
13499 //
13500 // Description:
13501 //      Implement IQK single tone for RF DPK loopback and BB PSD scanning.
13502 //      This function is cooperated with BB team Neil.
13503 //
13504 // Added by Roger, 2011.12.15
13505 //
13506 BOOLEAN
13507 ODM_SingleDualAntennaDetection(
13508         IN              PDM_ODM_T               pDM_Odm,
13509         IN              u1Byte                  mode
13510         )
13511 {
13512         PADAPTER        pAdapter         =  pDM_Odm->Adapter;
13513         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
13514         u4Byte          CurrentChannel,RfLoopReg;
13515         u1Byte          n;
13516         u4Byte          Reg88c, Regc08, Reg874, Regc50, Reg948=0, Regb2c=0, Reg92c=0, AFE_rRx_Wait_CCA=0;
13517         u1Byte          initial_gain = 0x5a;
13518         u4Byte          PSD_report_tmp;
13519         u4Byte          AntA_report = 0x0, AntB_report = 0x0,AntO_report=0x0;
13520         BOOLEAN         bResult = TRUE;
13521         u4Byte          AFE_Backup[16];
13522         u4Byte          AFE_REG_8723A[16] = {
13523                                         rRx_Wait_CCA,   rTx_CCK_RFON,
13524                                         rTx_CCK_BBON,   rTx_OFDM_RFON,
13525                                         rTx_OFDM_BBON,  rTx_To_Rx,
13526                                         rTx_To_Tx,              rRx_CCK,
13527                                         rRx_OFDM,               rRx_Wait_RIFS,
13528                                         rRx_TO_Rx,              rStandby,
13529                                         rSleep,                 rPMPD_ANAEN,
13530                                         rFPGA0_XCD_SwitchControl, rBlue_Tooth};
13531
13532         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection()============> \n"));
13533
13534
13535         if(!(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8192C|ODM_RTL8723B)))
13536                 return bResult;
13537
13538         // Retrieve antenna detection registry info, added by Roger, 2012.11.27.
13539         if(!IS_ANT_DETECT_SUPPORT_SINGLE_TONE(pAdapter))
13540                 return bResult;
13541
13542         if(pDM_Odm->SupportICType == ODM_RTL8192C)
13543         {
13544                 //Which path in ADC/DAC is turnned on for PSD: both I/Q
13545                 ODM_SetBBReg(pDM_Odm, 0x808, BIT10|BIT11, 0x3);
13546                 //Ageraged number: 8
13547                 ODM_SetBBReg(pDM_Odm, 0x808, BIT12|BIT13, 0x1);
13548                 //pts = 128;
13549                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0);
13550         }
13551
13552         //1 Backup Current RF/BB Settings
13553
13554         CurrentChannel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask);
13555         RfLoopReg = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask);
13556         if(!(pDM_Odm->SupportICType == ODM_RTL8723B))
13557         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_A);  // change to Antenna A
13558 #if (RTL8723B_SUPPORT == 1)
13559         else
13560         {
13561                 Reg92c = ODM_GetBBReg(pDM_Odm, 0x92c, bMaskDWord);
13562                 Reg948 = ODM_GetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord);
13563                 Regb2c = ODM_GetBBReg(pDM_Odm, AGC_table_select, bMaskDWord);
13564                 ODM_SetBBReg(pDM_Odm, rDPDT_control, 0x3, 0x1);
13565                 ODM_SetBBReg(pDM_Odm, rfe_ctrl_anta_src, 0xff, 0x77);
13566                 ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0x3ff, 0x000);
13567                 ODM_SetBBReg(pDM_Odm, AGC_table_select, BIT31, 0x0);
13568         }
13569 #endif
13570         ODM_StallExecution(10);
13571
13572         //Store A Path Register 88c, c08, 874, c50
13573         Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord);
13574         Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord);
13575         Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord);
13576         Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord);
13577
13578         // Store AFE Registers
13579         if(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8192C))
13580         odm_PHY_SaveAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
13581         else if(pDM_Odm->SupportICType == ODM_RTL8723B)
13582                 AFE_rRx_Wait_CCA = ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA,bMaskDWord);
13583
13584         //Set PSD 128 pts
13585         ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0);  //128 pts
13586
13587         // To SET CH1 to do
13588         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x7401);     //Channel 1
13589
13590         // AFE all on step
13591         if(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8192C))
13592         {
13593                 ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x6FDB25A4);
13594                 ODM_SetBBReg(pDM_Odm, rTx_CCK_RFON, bMaskDWord, 0x6FDB25A4);
13595                 ODM_SetBBReg(pDM_Odm, rTx_CCK_BBON, bMaskDWord, 0x6FDB25A4);
13596                 ODM_SetBBReg(pDM_Odm, rTx_OFDM_RFON, bMaskDWord, 0x6FDB25A4);
13597                 ODM_SetBBReg(pDM_Odm, rTx_OFDM_BBON, bMaskDWord, 0x6FDB25A4);
13598                 ODM_SetBBReg(pDM_Odm, rTx_To_Rx, bMaskDWord, 0x6FDB25A4);
13599                 ODM_SetBBReg(pDM_Odm, rTx_To_Tx, bMaskDWord, 0x6FDB25A4);
13600                 ODM_SetBBReg(pDM_Odm, rRx_CCK, bMaskDWord, 0x6FDB25A4);
13601                 ODM_SetBBReg(pDM_Odm, rRx_OFDM, bMaskDWord, 0x6FDB25A4);
13602                 ODM_SetBBReg(pDM_Odm, rRx_Wait_RIFS, bMaskDWord, 0x6FDB25A4);
13603                 ODM_SetBBReg(pDM_Odm, rRx_TO_Rx, bMaskDWord, 0x6FDB25A4);
13604                 ODM_SetBBReg(pDM_Odm, rStandby, bMaskDWord, 0x6FDB25A4);
13605                 ODM_SetBBReg(pDM_Odm, rSleep, bMaskDWord, 0x6FDB25A4);
13606                 ODM_SetBBReg(pDM_Odm, rPMPD_ANAEN, bMaskDWord, 0x6FDB25A4);
13607                 ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_SwitchControl, bMaskDWord, 0x6FDB25A4);
13608                 ODM_SetBBReg(pDM_Odm, rBlue_Tooth, bMaskDWord, 0x6FDB25A4);
13609         }
13610         else if(pDM_Odm->SupportICType == ODM_RTL8723B)
13611         {
13612                 ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x01c00016);
13613         }
13614
13615         // 3 wire Disable
13616         ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0);
13617
13618         //BB IQK Setting
13619         ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4);
13620         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000);
13621
13622         //IQK setting tone@ 4.34Mhz
13623         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C);
13624         ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
13625
13626         //Page B init
13627         ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00080000);
13628         ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000);
13629         ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
13630         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
13631         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82150008);
13632         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28150008);
13633         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0);
13634
13635         //RF loop Setting
13636         if(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8192C))
13637         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0, 0xFFFFF, 0x50008);
13638
13639         //IQK Single tone start
13640         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
13641         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
13642         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
13643
13644         ODM_StallExecution(10000);
13645
13646         // PSD report of antenna A
13647         PSD_report_tmp=0x0;
13648         for (n=0;n<2;n++)
13649         {
13650                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
13651                 if(PSD_report_tmp >AntA_report)
13652                         AntA_report=PSD_report_tmp;
13653         }
13654
13655          // change to Antenna B
13656         if(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8192C))
13657                 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_B);
13658 #if (RTL8723B_SUPPORT == 1)
13659         else if(pDM_Odm->SupportICType == ODM_RTL8723B)
13660                 ODM_SetBBReg(pDM_Odm, rDPDT_control, 0x3, 0x2);
13661 #endif
13662
13663         ODM_StallExecution(10);
13664
13665         // PSD report of antenna B
13666         PSD_report_tmp=0x0;
13667         for (n=0;n<2;n++)
13668         {
13669                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
13670                 if(PSD_report_tmp > AntB_report)
13671                         AntB_report=PSD_report_tmp;
13672         }
13673
13674         // change to open case
13675         if(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8192C))
13676                 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, 0);  // change to Antenna A
13677 #if (RTL8723B_SUPPORT == 1)
13678         else if(pDM_Odm->SupportICType == ODM_RTL8723B)
13679                 ODM_SetBBReg(pDM_Odm, rDPDT_control, 0x3, 0x0);
13680 #endif
13681
13682         ODM_StallExecution(10);
13683
13684         // PSD report of open case
13685         PSD_report_tmp=0x0;
13686         for (n=0;n<2;n++)
13687         {
13688                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
13689                 if(PSD_report_tmp > AntO_report)
13690                         AntO_report=PSD_report_tmp;
13691         }
13692
13693         //Close IQK Single Tone function
13694         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
13695
13696         //1 Return to antanna A
13697         if(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8192C))
13698                 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_A);  // change to Antenna A
13699 #if (RTL8723B_SUPPORT == 1)
13700         else if(pDM_Odm->SupportICType == ODM_RTL8723B)
13701         {
13702                 // external DPDT
13703                 ODM_SetBBReg(pDM_Odm, rDPDT_control, bMaskDWord, Reg92c);
13704
13705                 //internal S0/S1
13706                 ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord, Reg948);
13707                 ODM_SetBBReg(pDM_Odm, AGC_table_select, bMaskDWord, Regb2c);
13708         }
13709 #endif
13710         ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c);
13711         ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, Regc08);
13712         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874);
13713         ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7F, 0x40);
13714         ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord, Regc50);
13715         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,CurrentChannel);
13716         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask,RfLoopReg);
13717
13718         //Reload AFE Registers
13719         if(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8192C))
13720         odm_PHY_ReloadAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
13721         else if(pDM_Odm->SupportICType == ODM_RTL8723B)
13722                 ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, AFE_rRx_Wait_CCA);
13723
13724         if(pDM_Odm->SupportICType == ODM_RTL8723A)
13725         {
13726                 //2 Test Ant B based on Ant A is ON
13727                 if(mode==ANTTESTB)
13728                 {
13729                         if(AntA_report >=       100)
13730                         {
13731                                 if(AntB_report > (AntA_report+1))
13732                                 {
13733                                         pDM_SWAT_Table->ANTB_ON=FALSE;
13734                                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n"));
13735                                 }
13736                                 else
13737                                 {
13738                                         pDM_SWAT_Table->ANTB_ON=TRUE;
13739                                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna is A and B\n"));
13740                                 }
13741                         }
13742                         else
13743                         {
13744                                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
13745                                 pDM_SWAT_Table->ANTB_ON=FALSE; // Set Antenna B off as default
13746                                 bResult = FALSE;
13747                         }
13748                 }
13749                 //2 Test Ant A and B based on DPDT Open
13750                 else if(mode==ANTTESTALL)
13751                 {
13752                         if((AntO_report >=100) && (AntO_report <=118))
13753                         {
13754                                 if(AntA_report > (AntO_report+1))
13755                                 {
13756                                         pDM_SWAT_Table->ANTA_ON=FALSE;
13757                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant A is OFF\n"));
13758                                 }
13759                                 else
13760                                 {
13761                                         pDM_SWAT_Table->ANTA_ON=TRUE;
13762                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant A is ON\n"));
13763                                 }
13764
13765                                 if(AntB_report > (AntO_report+2))
13766                                 {
13767                                         pDM_SWAT_Table->ANTB_ON=FALSE;
13768                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant B is OFF\n"));
13769                                 }
13770                                 else
13771                                 {
13772                                         pDM_SWAT_Table->ANTB_ON=TRUE;
13773                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant B is ON\n"));
13774                                 }
13775
13776                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d \n", 2416, AntA_report));
13777                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d \n", 2416, AntB_report));
13778                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_O[%d]= %d \n", 2416, AntO_report));
13779
13780                                 pDM_Odm->AntDetectedInfo.bAntDetected= TRUE;
13781                                 pDM_Odm->AntDetectedInfo.dBForAntA = AntA_report;
13782                                 pDM_Odm->AntDetectedInfo.dBForAntB = AntB_report;
13783                                 pDM_Odm->AntDetectedInfo.dBForAntO = AntO_report;
13784
13785                                 }
13786                         else
13787                                 {
13788                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("return FALSE!!\n"));
13789                                 bResult = FALSE;
13790                         }
13791                 }
13792         }
13793         else if(pDM_Odm->SupportICType == ODM_RTL8192C)
13794         {
13795                 if(AntA_report >=       100)
13796                 {
13797                         if(AntB_report > (AntA_report+2))
13798                         {
13799                                 pDM_SWAT_Table->ANTA_ON=FALSE;
13800                                 pDM_SWAT_Table->ANTB_ON=TRUE;
13801                                 ODM_SetBBReg(pDM_Odm,  rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B);
13802                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna B\n"));
13803                         }
13804                         else if(AntA_report > (AntB_report+2))
13805                         {
13806                                 pDM_SWAT_Table->ANTA_ON=TRUE;
13807                                 pDM_SWAT_Table->ANTB_ON=FALSE;
13808                                 ODM_SetBBReg(pDM_Odm,  rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A);
13809                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n"));
13810                         }
13811                         else
13812                         {
13813                                 pDM_SWAT_Table->ANTA_ON=TRUE;
13814                                 pDM_SWAT_Table->ANTB_ON=TRUE;
13815                                 RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna \n"));
13816                         }
13817                 }
13818                 else
13819                 {
13820                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
13821                         pDM_SWAT_Table->ANTA_ON=TRUE; // Set Antenna A on as default
13822                         pDM_SWAT_Table->ANTB_ON=FALSE; // Set Antenna B off as default
13823                         bResult = FALSE;
13824                 }
13825         }
13826         else if(pDM_Odm->SupportICType == ODM_RTL8723B)
13827         {
13828                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d \n", 2416, AntA_report));
13829                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d \n", 2416, AntB_report));
13830                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_O[%d]= %d \n", 2416, AntO_report));
13831
13832                 //2 Test Ant B based on Ant A is ON
13833                 if(mode==ANTTESTB)
13834                 {
13835                         if(AntA_report >=100 && AntA_report <= 116)
13836                         {
13837                                 if(AntB_report >= (AntA_report+4) && AntB_report > 116)
13838                                 {
13839                                         pDM_SWAT_Table->ANTB_ON=FALSE;
13840                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n"));
13841                                 }
13842                                 else if(AntB_report >=100 && AntB_report <= 116)
13843                                 {
13844                                         pDM_SWAT_Table->ANTB_ON=TRUE;
13845                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna is A and B\n"));
13846                                 }
13847                                 else
13848                                 {
13849                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
13850                                         pDM_SWAT_Table->ANTB_ON=FALSE; // Set Antenna B off as default
13851                                         bResult = FALSE;
13852                                 }
13853                         }
13854                         else
13855                         {
13856                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
13857                                 pDM_SWAT_Table->ANTB_ON=FALSE; // Set Antenna B off as default
13858                                 bResult = FALSE;
13859                         }
13860                 }
13861                 //2 Test Ant A and B based on DPDT Open
13862                 else if(mode==ANTTESTALL)
13863                 {
13864                         if((AntA_report >= 100) && (AntB_report >= 100) && (AntA_report <= 120) && (AntB_report <= 120))
13865                         {
13866                                 if((AntA_report - AntB_report < 2) || (AntB_report - AntA_report < 2))
13867                                 {
13868                                         pDM_SWAT_Table->ANTA_ON=TRUE;
13869                                         pDM_SWAT_Table->ANTB_ON=TRUE;
13870                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SingleDualAntennaDetection(): Dual Antenna\n"));
13871                                 }
13872                                 else if(((AntA_report - AntB_report >= 2) && (AntA_report - AntB_report <= 4)) ||
13873                                         ((AntB_report - AntA_report >= 2) && (AntB_report - AntA_report <= 4)))
13874                                 {
13875                                         pDM_SWAT_Table->ANTA_ON=FALSE;
13876                                         pDM_SWAT_Table->ANTB_ON=FALSE;
13877                                         bResult = FALSE;
13878                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
13879                                 }
13880                                 else
13881                                 {
13882                                         pDM_SWAT_Table->ANTA_ON = TRUE;
13883                                         pDM_SWAT_Table->ANTB_ON=FALSE;
13884                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SingleDualAntennaDetection(): Single Antenna A\n"));
13885                                 }
13886
13887                                 pDM_Odm->AntDetectedInfo.bAntDetected= TRUE;
13888                                 pDM_Odm->AntDetectedInfo.dBForAntA = AntA_report;
13889                                 pDM_Odm->AntDetectedInfo.dBForAntB = AntB_report;
13890                                 pDM_Odm->AntDetectedInfo.dBForAntO = AntO_report;
13891
13892                         }
13893                         else
13894                         {
13895                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("return FALSE!!\n"));
13896                                 bResult = FALSE;
13897                         }
13898                 }
13899         }
13900
13901         return bResult;
13902
13903 }
13904
13905
13906 #endif   // end odm_CE
13907
13908 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))
13909
13910 VOID
13911 odm_Set_RA_DM_ARFB_by_Noisy(
13912         IN      PDM_ODM_T       pDM_Odm
13913 )
13914 {
13915         //DbgPrint("DM_ARFB ====> \n");
13916         if (pDM_Odm->bNoisyState){
13917                 ODM_Write4Byte(pDM_Odm,0x430,0x00000000);
13918                 ODM_Write4Byte(pDM_Odm,0x434,0x05040200);
13919                 //DbgPrint("DM_ARFB ====> Noisy State\n");
13920         }
13921         else{
13922                 ODM_Write4Byte(pDM_Odm,0x430,0x02010000);
13923                 ODM_Write4Byte(pDM_Odm,0x434,0x07050403);
13924                 //DbgPrint("DM_ARFB ====> Clean State\n");
13925         }
13926
13927 }
13928
13929 VOID
13930 ODM_UpdateNoisyState(
13931         IN      PDM_ODM_T       pDM_Odm,
13932         IN      BOOLEAN         bNoisyStateFromC2H
13933         )
13934 {
13935         //DbgPrint("Get C2H Command! NoisyState=0x%x\n ", bNoisyStateFromC2H);
13936         if(pDM_Odm->SupportICType == ODM_RTL8821  || pDM_Odm->SupportICType == ODM_RTL8812  ||
13937            pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8188E)
13938         {
13939                 pDM_Odm->bNoisyState = bNoisyStateFromC2H;
13940         }
13941         odm_Set_RA_DM_ARFB_by_Noisy(pDM_Odm);
13942 };
13943
13944 u4Byte
13945 Set_RA_DM_Ratrbitmap_by_Noisy(
13946         IN      PDM_ODM_T       pDM_Odm,
13947         IN      WIRELESS_MODE   WirelessMode,
13948         IN      u4Byte                  ratr_bitmap,
13949         IN      u1Byte                  rssi_level
13950 )
13951 {
13952         u4Byte ret_bitmap = ratr_bitmap;
13953         switch (WirelessMode)
13954         {
13955                 case WIRELESS_MODE_AC_24G :
13956                 case WIRELESS_MODE_AC_5G :
13957                 case WIRELESS_MODE_AC_ONLY:
13958                         if (pDM_Odm->bNoisyState){ // in Noisy State
13959                                 if (rssi_level==1)
13960                                         ret_bitmap&=0xfe3f0e08;
13961                                 else if (rssi_level==2)
13962                                         ret_bitmap&=0xff3f8f8c;
13963                                 else if (rssi_level==3)
13964                                         ret_bitmap&=0xffffffcc ;
13965                                 else
13966                                         ret_bitmap&=0xffffffff ;
13967                         }
13968                         else{                                   // in SNR State
13969                                 if (rssi_level==1){
13970                                         ret_bitmap&=0xfc3e0c08;
13971                                 }
13972                                 else if (rssi_level==2){
13973                                         ret_bitmap&=0xfe3f0e08;
13974                                 }
13975                                 else if (rssi_level==3){
13976                                         ret_bitmap&=0xffbfefcc;
13977                                 }
13978                                 else{
13979                                         ret_bitmap&=0x0fffffff;
13980                                 }
13981                         }
13982                         break;
13983                 case WIRELESS_MODE_B:
13984                 case WIRELESS_MODE_A:
13985                 case WIRELESS_MODE_G:
13986                 case WIRELESS_MODE_N_24G:
13987                 case WIRELESS_MODE_N_5G:
13988                         if (pDM_Odm->bNoisyState){
13989                                 if (rssi_level==1)
13990                                         ret_bitmap&=0x0f0e0c08;
13991                                 else if (rssi_level==2)
13992                                         ret_bitmap&=0x0f8f0e0c;
13993                                 else if (rssi_level==3)
13994                                         ret_bitmap&=0x0fefefcc ;
13995                                 else
13996                                         ret_bitmap&=0xffffffff ;
13997                         }
13998                         else{
13999                                 if (rssi_level==1){
14000                                         ret_bitmap&=0x0f8f0e08;
14001                                 }
14002                                 else if (rssi_level==2){
14003                                         ret_bitmap&=0x0fcf8f8c;
14004                                 }
14005                                 else if (rssi_level==3){
14006                                         ret_bitmap&=0x0fffffcc;
14007                                 }
14008                                 else{
14009                                         ret_bitmap&=0x0fffffff;
14010                                 }
14011                         }
14012                         break;
14013                 default:
14014                         break;
14015         }
14016         //DbgPrint("DM_RAMask ====> rssi_LV = %d, BITMAP = %x \n", rssi_level, ret_bitmap);
14017         return ret_bitmap;
14018
14019 }
14020
14021
14022
14023 VOID
14024 ODM_UpdateInitRate(
14025         IN      PDM_ODM_T       pDM_Odm,
14026         IN      u1Byte          Rate
14027         )
14028 {
14029         u1Byte                  p = 0;
14030
14031         ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Get C2H Command! Rate=0x%x\n", Rate));
14032
14033         if(pDM_Odm->SupportICType == ODM_RTL8821  || pDM_Odm->SupportICType == ODM_RTL8812  ||
14034            pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8188E)
14035         {
14036                 pDM_Odm->TxRate = Rate;
14037 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
14038         #if DEV_BUS_TYPE==RT_PCI_INTERFACE
14039                 #if USE_WORKITEM
14040                 PlatformScheduleWorkItem(&pDM_Odm->RaRptWorkitem);
14041                 #else
14042                 if(pDM_Odm->SupportICType == ODM_RTL8821)
14043                 {
14044                         ODM_TxPwrTrackSetPwr8821A(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0);
14045                 }
14046                 else if(pDM_Odm->SupportICType == ODM_RTL8812)
14047                 {
14048                         for (p = ODM_RF_PATH_A; p < MAX_PATH_NUM_8812A; p++)
14049                         {
14050                                 ODM_TxPwrTrackSetPwr8812A(pDM_Odm, MIX_MODE, p, 0);
14051                         }
14052                 }
14053                 else if(pDM_Odm->SupportICType == ODM_RTL8723B)
14054                 {
14055                         ODM_TxPwrTrackSetPwr_8723B(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0);
14056                 }
14057                 else if(pDM_Odm->SupportICType == ODM_RTL8192E)
14058                 {
14059                         for (p = ODM_RF_PATH_A; p < MAX_PATH_NUM_8192E; p++)
14060                         {
14061                                 ODM_TxPwrTrackSetPwr92E(pDM_Odm, MIX_MODE, p, 0);
14062                         }
14063                 }
14064                 else if(pDM_Odm->SupportICType == ODM_RTL8188E)
14065                 {
14066                         ODM_TxPwrTrackSetPwr88E(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0);
14067                 }
14068                 #endif
14069         #else
14070                 PlatformScheduleWorkItem(&pDM_Odm->RaRptWorkitem);
14071         #endif
14072 #endif
14073         }
14074         else
14075                 return;
14076 }
14077
14078 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
14079 VOID
14080 ODM_UpdateInitRateWorkItemCallback(
14081     IN PVOID            pContext
14082     )
14083 {
14084         PADAPTER        Adapter = (PADAPTER)pContext;
14085         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
14086         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
14087
14088         u1Byte                  p = 0;
14089
14090         if(pDM_Odm->SupportICType == ODM_RTL8821)
14091         {
14092                 ODM_TxPwrTrackSetPwr8821A(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0);
14093         }
14094         else if(pDM_Odm->SupportICType == ODM_RTL8812)
14095         {
14096                 for (p = ODM_RF_PATH_A; p < MAX_PATH_NUM_8812A; p++)    //DOn't know how to include &c
14097                 {
14098                         ODM_TxPwrTrackSetPwr8812A(pDM_Odm, MIX_MODE, p, 0);
14099                 }
14100         }
14101         else if(pDM_Odm->SupportICType == ODM_RTL8723B)
14102         {
14103                         ODM_TxPwrTrackSetPwr_8723B(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0);
14104         }
14105         else if(pDM_Odm->SupportICType == ODM_RTL8192E)
14106         {
14107                 for (p = ODM_RF_PATH_A; p < MAX_PATH_NUM_8192E; p++)    //DOn't know how to include &c
14108                 {
14109                         ODM_TxPwrTrackSetPwr92E(pDM_Odm, MIX_MODE, p, 0);
14110                 }
14111         }
14112         else if(pDM_Odm->SupportICType == ODM_RTL8188E)
14113         {
14114                         ODM_TxPwrTrackSetPwr88E(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0);
14115         }
14116 }
14117 #endif
14118 #endif
14119
14120 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
14121 /* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */
14122 void odm_dtc(PDM_ODM_T pDM_Odm)
14123 {
14124 #ifdef CONFIG_DM_RESP_TXAGC
14125         #define DTC_BASE            35  /* RSSI higher than this value, start to decade TX power */
14126         #define DTC_DWN_BASE       (DTC_BASE-5) /* RSSI lower than this value, start to increase TX power */
14127
14128         /* RSSI vs TX power step mapping: decade TX power */
14129         static const u8 dtc_table_down[]={
14130                 DTC_BASE,
14131                 (DTC_BASE+5),
14132                 (DTC_BASE+10),
14133                 (DTC_BASE+15),
14134                 (DTC_BASE+20),
14135                 (DTC_BASE+25)
14136         };
14137
14138         /* RSSI vs TX power step mapping: increase TX power */
14139         static const u8 dtc_table_up[]={
14140                 DTC_DWN_BASE,
14141                 (DTC_DWN_BASE-5),
14142                 (DTC_DWN_BASE-10),
14143                 (DTC_DWN_BASE-15),
14144                 (DTC_DWN_BASE-15),
14145                 (DTC_DWN_BASE-20),
14146                 (DTC_DWN_BASE-20),
14147                 (DTC_DWN_BASE-25),
14148                 (DTC_DWN_BASE-25),
14149                 (DTC_DWN_BASE-30),
14150                 (DTC_DWN_BASE-35)
14151         };
14152
14153         u8 i;
14154         u8 dtc_steps=0;
14155         u8 sign;
14156         u8 resp_txagc=0;
14157
14158         #if 0
14159         /* As DIG is disabled, DTC is also disable */
14160         if(!(pDM_Odm->SupportAbility & ODM_XXXXXX))
14161                 return;
14162         #endif
14163
14164         if (DTC_BASE < pDM_Odm->RSSI_Min) {
14165                 /* need to decade the CTS TX power */
14166                 sign = 1;
14167                 for (i=0;i<ARRAY_SIZE(dtc_table_down);i++)
14168                 {
14169                         if ((dtc_table_down[i] >= pDM_Odm->RSSI_Min) || (dtc_steps >= 6))
14170                                 break;
14171                         else
14172                                 dtc_steps++;
14173                 }
14174         }
14175 #if 0
14176         else if (DTC_DWN_BASE > pDM_Odm->RSSI_Min)
14177         {
14178                 /* needs to increase the CTS TX power */
14179                 sign = 0;
14180                 dtc_steps = 1;
14181                 for (i=0;i<ARRAY_SIZE(dtc_table_up);i++)
14182                 {
14183                         if ((dtc_table_up[i] <= pDM_Odm->RSSI_Min) || (dtc_steps>=10))
14184                                 break;
14185                         else
14186                                 dtc_steps++;
14187                 }
14188         }
14189 #endif
14190         else
14191         {
14192                 sign = 0;
14193                 dtc_steps = 0;
14194         }
14195
14196         resp_txagc = dtc_steps | (sign << 4);
14197         resp_txagc = resp_txagc | (resp_txagc << 5);
14198         ODM_Write1Byte(pDM_Odm, 0x06d9, resp_txagc);
14199
14200         DBG_871X("%s RSSI_Min:%u, set RESP_TXAGC to %s %u\n",
14201                 __func__, pDM_Odm->RSSI_Min, sign?"minus":"plus", dtc_steps);
14202 #endif /* CONFIG_RESP_TXAGC_ADJUST */
14203 }
14204
14205 #endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
14206