drivers/net/wireless/rockchip_wlan/rtl8188eu/include/Hal8192DPhyCfg.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 /*****************************************************************************
  21  *
  22  * Module:      __INC_HAL8192DPHYCFG_H
  23  *
  24  *
  25  * Note:
  26  *
  27  *
  28  * Export:      Constants, macro, functions(API), global variables(None).
  29  *
  30  * Abbrev:
  31  *
  32  * History:
  33  *              Data            Who             Remark
  34  *      08/07/2007  MHC         1. Porting from 9x series PHYCFG.h.
  35  *                                                      2. Reorganize code architecture.
  36  *
  37  *****************************************************************************/
  38  /* Check to see if the file has been included already.  */
  39 #ifndef __INC_HAL8192DPHYCFG_H
  40 #define __INC_HAL8192DPHYCFG_H
  41
  42
  43 /*--------------------------Define Parameters-------------------------------*/
  44 #define LOOP_LIMIT                              5
  45 #define MAX_STALL_TIME                  50              //us
  46 #define AntennaDiversityValue   0x80    //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80)
  47 #define MAX_TXPWR_IDX_NMODE_92S 63
  48 #define Reset_Cnt_Limit                 3
  49
  50
  51 #ifdef CONFIG_PCI_HCI
  52 #define SET_RTL8192SE_RF_SLEEP(_pAdapter)                                                       \
  53 {                                                                                                                                       \
  54         u1Byte          u1bTmp;                                                                                         \
  55         u1bTmp = PlatformEFIORead1Byte(_pAdapter, REG_LDOV12D_CTRL);            \
  56         u1bTmp |= BIT0;                                                                                                 \
  57         PlatformEFIOWrite1Byte(_pAdapter, REG_LDOV12D_CTRL, u1bTmp);            \
  58         PlatformEFIOWrite1Byte(_pAdapter, REG_SPS_OCP_CFG, 0x0);                                \
  59         PlatformEFIOWrite1Byte(_pAdapter, TXPAUSE, 0xFF);                               \
  60         PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC);                                \
  61         delay_us(100);                                                                                                  \
  62         PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC);                                \
  63         PlatformEFIOWrite1Byte(_pAdapter, PHY_CCA, 0x0);                                \
  64         delay_us(10);                                                                                                   \
  65         PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x37FC);                                \
  66         delay_us(10);                                                                                                   \
  67         PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC);                                \
  68         delay_us(10);                                                                                                   \
  69         PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC);                                \
  70 }
  71 #endif
  72
  73
  74 /*--------------------------Define Parameters-------------------------------*/
  75
  76
  77 /*------------------------------Define structure----------------------------*/
  78
  79 #define CHANNEL_GROUP_MAX_2G            3
  80 #define CHANNEL_GROUP_IDX_5GL           3
  81 #define CHANNEL_GROUP_IDX_5GM           6
  82 #define CHANNEL_GROUP_IDX_5GH           9
  83 #define CHANNEL_GROUP_MAX_5G            9
  84 #define CHANNEL_MAX_NUMBER_2G           14
  85
  86 typedef enum _MACPHY_MODE_CHANGE_ACTION{
  87         DMDP2DMSP = 0,
  88         DMSP2DMDP = 1,
  89         DMDP2SMSP = 2,
  90         SMSP2DMDP = 3,
  91         DMSP2SMSP = 4,
  92         SMSP2DMSP = 5,
  93         MAXACTION
  94 }MACPHY_MODE_CHANGE_ACTION,*PMACPHY_MODE_CHANGE_ACTION;
  95
  96
  97
  98 /* BB/RF related */
  99
 100 /*------------------------------Define structure----------------------------*/
 101
 102
 103 /*------------------------Export global variable----------------------------*/
 104 /*------------------------Export global variable----------------------------*/
 105
 106
 107 /*------------------------Export Marco Definition---------------------------*/
 108
 109 /*--------------------------Exported Function prototype---------------------*/
 110 //
 111 // BB and RF register read/write
 112 //
 113 void    PHY_SetBBReg1Byte8192D( IN      PADAPTER        Adapter,
 114                                                                 IN      u32             RegAddr,
 115                                                                 IN      u32             BitMask,
 116                                                                 IN      u32             Data    );
 117 u32     PHY_QueryBBReg8192D(    IN      PADAPTER        Adapter,
 118                                                                 IN      u32             RegAddr,
 119                                                                 IN      u32             BitMask );
 120 void    PHY_SetBBReg8192D(      IN      PADAPTER        Adapter,
 121                                                                 IN      u32             RegAddr,
 122                                                                 IN      u32             BitMask,
 123                                                                 IN      u32             Data    );
 124 u32     PHY_QueryRFReg8192D(    IN      PADAPTER        Adapter,
 125                                                                 IN      u8                              eRFPath,
 126                                                                 IN      u32                             RegAddr,
 127                                                                 IN      u32                             BitMask );
 128 void    PHY_SetRFReg8192D(      IN      PADAPTER                Adapter,
 129                                                                 IN      u8                              eRFPath,
 130                                                                 IN      u32                             RegAddr,
 131                                                                 IN      u32                             BitMask,
 132                                                                 IN      u32                             Data    );
 133
 134 //
 135 // Initialization related function
 136 //
 137 /* MAC/BB/RF HAL config */
 138 extern  int     PHY_MACConfig8192D(     IN      PADAPTER        Adapter );
 139 extern  int     PHY_BBConfig8192D(      IN      PADAPTER        Adapter );
 140 extern  int     PHY_RFConfig8192D(      IN      PADAPTER        Adapter );
 141 /* RF config */
 142 int     rtl8192d_PHY_ConfigRFWithParaFile(      IN      PADAPTER        Adapter,
 143                                                                                                 IN      u8*                     pFileName,
 144                                                                                                 IN      u8                      eRFPath);
 145 int     rtl8192d_PHY_ConfigRFWithHeaderFile(    IN      PADAPTER                Adapter,
 146                                                                                                 IN      RF_CONTENT              Content,
 147                                                                                                 IN      u8                              eRFPath);
 148 /* BB/RF readback check for making sure init OK */
 149 int     rtl8192d_PHY_CheckBBAndRFOK(    IN      PADAPTER                Adapter,
 150                                                                                         IN      HW_BLOCK_E              CheckBlock,
 151                                                                                         IN      u8                              eRFPath   );
 152 /* Read initi reg value for tx power setting. */
 153 void    rtl8192d_PHY_GetHWRegOriginalValue(     IN      PADAPTER                Adapter );
 154
 155 //
 156 // RF Power setting
 157 //
 158 //extern        BOOLEAN PHY_SetRFPowerState(IN  PADAPTER                        Adapter,
 159 //                                                                      IN      RT_RF_POWER_STATE       eRFPowerState);
 160
 161 //
 162 // BB TX Power R/W
 163 //
 164 void    PHY_GetTxPowerLevel8192D(       IN      PADAPTER                Adapter,
 165                                                                                         OUT s32*                powerlevel      );
 166 void    PHY_SetTxPowerLevel8192D(       IN      PADAPTER                Adapter,
 167                                                                                         IN      u8                      channel );
 168 BOOLEAN PHY_UpdateTxPowerDbm8192D(      IN      PADAPTER        Adapter,
 169                                                                                         IN      int             powerInDbm      );
 170
 171 //
 172 VOID
 173 PHY_ScanOperationBackup8192D(IN PADAPTER        Adapter,
 174                                                                                 IN      u8              Operation       );
 175
 176 //
 177 // Switch bandwidth for 8192S
 178 //
 179 //void  PHY_SetBWModeCallback8192C(     IN      PRT_TIMER               pTimer  );
 180 void    PHY_SetBWMode8192D(     IN      PADAPTER                        pAdapter,
 181                                                                         IN      CHANNEL_WIDTH   ChnlWidth,
 182                                                                         IN      unsigned char   Offset  );
 183
 184 //
 185 // Set FW CMD IO for 8192S.
 186 //
 187 //extern        BOOLEAN HalSetIO8192C(  IN      PADAPTER                        Adapter,
 188 //                                                                      IN      IO_TYPE                         IOType);
 189
 190 //
 191 // Set A2 entry to fw for 8192S
 192 //
 193 extern  void FillA2Entry8192C(          IN      PADAPTER                        Adapter,
 194                                                                                 IN      u8                              index,
 195                                                                                 IN      u8*                             val);
 196
 197
 198 //
 199 // channel switch related funciton
 200 //
 201 //extern        void    PHY_SwChnlCallback8192C(        IN      PRT_TIMER               pTimer  );
 202 void    PHY_SwChnl8192D(        IN      PADAPTER                pAdapter,
 203                                                                         IN      u8                      channel );
 204
 205 VOID
 206 PHY_SetSwChnlBWMode8192D(
 207         IN      PADAPTER                        Adapter,
 208         IN      u8                                      channel,
 209         IN      CHANNEL_WIDTH   Bandwidth,
 210         IN      u8                                      Offset40,
 211         IN      u8                                      Offset80
 212 );
 213
 214 //
 215 // BB/MAC/RF other monitor API
 216 //
 217 void    PHY_SetMonitorMode8192D(IN      PADAPTER        pAdapter,
 218                                                                                 IN      BOOLEAN         bEnableMonitorMode      );
 219
 220 BOOLEAN PHY_CheckIsLegalRfPath8192D(IN  PADAPTER        pAdapter,
 221                                                                                         IN      u32             eRFPath );
 222
 223
 224 //
 225 // Modify the value of the hw register when beacon interval be changed.
 226 //
 227 void
 228 rtl8192d_PHY_SetBeaconHwReg(    IN      PADAPTER                Adapter,
 229                                         IN      u16                     BeaconInterval  );
 230
 231
 232 extern  VOID
 233 PHY_SwitchEphyParameter(
 234         IN      PADAPTER                        Adapter
 235         );
 236
 237 extern  VOID
 238 PHY_EnableHostClkReq(
 239         IN      PADAPTER                        Adapter
 240         );
 241
 242 BOOLEAN
 243 SetAntennaConfig92C(
 244         IN      PADAPTER        Adapter,
 245         IN      u8              DefaultAnt
 246         );
 247
 248 VOID
 249 PHY_UpdateBBRFConfiguration8192D(
 250         IN PADAPTER Adapter,
 251         IN BOOLEAN bisBandSwitch
 252 );
 253
 254 VOID PHY_ReadMacPhyMode92D(
 255         IN PADAPTER     Adapter,
 256         IN BOOLEAN      AutoloadFail
 257 );
 258
 259 VOID PHY_ConfigMacPhyMode92D(
 260         IN PADAPTER     Adapter
 261 );
 262
 263 VOID PHY_ConfigMacPhyModeInfo92D(
 264         IN PADAPTER     Adapter
 265 );
 266
 267 VOID PHY_ConfigMacCoexist_RFPage92D(
 268         IN PADAPTER     Adapter
 269 );
 270
 271 VOID
 272 rtl8192d_PHY_InitRxSetting(
 273         IN      PADAPTER Adapter
 274 );
 275
 276
 277 VOID
 278 rtl8192d_PHY_SetRFPathSwitch(IN PADAPTER        pAdapter, IN    BOOLEAN         bMain);
 279
 280 VOID
 281 HalChangeCCKStatus8192D(
 282         IN      PADAPTER        Adapter,
 283         IN      BOOLEAN         bCCKDisable
 284 );
 285
 286 VOID
 287 PHY_InitPABias92D(IN    PADAPTER Adapter);
 288
 289 /*--------------------------Exported Function prototype---------------------*/
 290
 291 #define PHY_SetBBReg1Byte(Adapter, RegAddr, BitMask, Data) PHY_SetBBReg1Byte8192D((Adapter), (RegAddr), (BitMask), (Data))
 292 #endif  // __INC_HAL8192SPHYCFG_H
 293