drivers/net/wireless/rockchip_wlan/rtl8188eu/hal/rtl8188e/usb/usb_halinit.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #define _HCI_HAL_INIT_C_
  21
  22 #include <drv_types.h>
  23 #include <rtl8188e_hal.h>
  24 #include "hal_com_h2c.h"
  25
  26 #ifndef CONFIG_USB_HCI
  27
  28 #error "CONFIG_USB_HCI shall be on!\n"
  29
  30 #endif
  31
  32
  33 static VOID
  34 _ConfigNormalChipOutEP_8188E(
  35         IN      PADAPTER        pAdapter,
  36         IN      u8              NumOutPipe
  37         )
  38 {
  39         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(pAdapter);
  40
  41         switch(NumOutPipe){
  42                 case    3:
  43                                 pHalData->OutEpQueueSel=TX_SELE_HQ| TX_SELE_LQ|TX_SELE_NQ;
  44                                 pHalData->OutEpNumber=3;
  45                                 break;
  46                 case    2:
  47                                 pHalData->OutEpQueueSel=TX_SELE_HQ| TX_SELE_NQ;
  48                                 pHalData->OutEpNumber=2;
  49                                 break;
  50                 case    1:
  51                                 pHalData->OutEpQueueSel=TX_SELE_HQ;
  52                                 pHalData->OutEpNumber=1;
  53                                 break;
  54                 default:
  55                                 break;
  56
  57         }
  58         DBG_871X("%s OutEpQueueSel(0x%02x), OutEpNumber(%d) \n",__FUNCTION__,pHalData->OutEpQueueSel,pHalData->OutEpNumber );
  59
  60 }
  61
  62 static BOOLEAN HalUsbSetQueuePipeMapping8188EUsb(
  63         IN      PADAPTER        pAdapter,
  64         IN      u8              NumInPipe,
  65         IN      u8              NumOutPipe
  66         )
  67 {
  68         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(pAdapter);
  69         BOOLEAN                 result          = _FALSE;
  70
  71         _ConfigNormalChipOutEP_8188E(pAdapter, NumOutPipe);
  72
  73         // Normal chip with one IN and one OUT doesn't have interrupt IN EP.
  74         if(1 == pHalData->OutEpNumber){
  75                 if(1 != NumInPipe){
  76                         return result;
  77                 }
  78         }
  79
  80         // All config other than above support one Bulk IN and one Interrupt IN.
  81         //if(2 != NumInPipe){
  82         //      return result;
  83         //}
  84
  85         result = Hal_MappingOutPipe(pAdapter, NumOutPipe);
  86
  87         return result;
  88
  89 }
  90
  91 void rtl8188eu_interface_configure(_adapter *padapter)
  92 {
  93         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(padapter);
  94         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
  95
  96         if (IS_HIGH_SPEED_USB(padapter))
  97         {
  98                 pHalData->UsbBulkOutSize = USB_HIGH_SPEED_BULK_SIZE;//512 bytes
  99         }
 100         else
 101         {
 102                 pHalData->UsbBulkOutSize = USB_FULL_SPEED_BULK_SIZE;//64 bytes
 103         }
 104
 105         pHalData->interfaceIndex = pdvobjpriv->InterfaceNumber;
 106
 107 #ifdef CONFIG_USB_TX_AGGREGATION
 108         pHalData->UsbTxAggMode          = 1;
 109         pHalData->UsbTxAggDescNum       = 0x1;  // only 4 bits
 110 #endif
 111
 112 #ifdef CONFIG_USB_RX_AGGREGATION
 113         pHalData->UsbRxAggMode          = USB_RX_AGG_DMA;// USB_RX_AGG_DMA;
 114         pHalData->UsbRxAggBlockCount    = 8; //unit : 512b
 115         pHalData->UsbRxAggBlockTimeout  = 0x6;
 116         pHalData->UsbRxAggPageCount     = 48; //uint :128 b //0x0A;     // 10 = MAX_RX_DMA_BUFFER_SIZE/2/pHalData->UsbBulkOutSize
 117         pHalData->UsbRxAggPageTimeout   = 0x4; //6, absolute time = 34ms/(2^6)
 118 #endif
 119
 120         HalUsbSetQueuePipeMapping8188EUsb(padapter,
 121                                 pdvobjpriv->RtNumInPipes, pdvobjpriv->RtNumOutPipes);
 122
 123 }
 124
 125 static u32 _InitPowerOn_8188EU(_adapter *padapter)
 126 {
 127         u16 value16;
 128         // HW Power on sequence
 129         u8 bMacPwrCtrlOn=_FALSE;
 130
 131
 132         rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
 133         if(bMacPwrCtrlOn == _TRUE)
 134                 return _SUCCESS;
 135
 136         if(!HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_PWR_ON_FLOW))
 137         {
 138                 DBG_871X(KERN_ERR "%s: run power on flow fail\n", __func__);
 139                 return _FAIL;
 140         }
 141
 142         // Enable MAC DMA/WMAC/SCHEDULE/SEC block
 143         // Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31.
 144         rtw_write16(padapter, REG_CR, 0x00);  //suggseted by zhouzhou, by page, 20111230
 145
 146
 147                 // Enable MAC DMA/WMAC/SCHEDULE/SEC block
 148         value16 = rtw_read16(padapter, REG_CR);
 149         value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
 150                                 | PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN);
 151         // for SDIO - Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31.
 152
 153         rtw_write16(padapter, REG_CR, value16);
 154
 155         bMacPwrCtrlOn = _TRUE;
 156         rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
 157
 158
 159         return _SUCCESS;
 160
 161 }
 162
 163
 164 static void _dbg_dump_macreg(_adapter *padapter)
 165 {
 166         u32 offset = 0;
 167         u32 val32 = 0;
 168         u32 index =0 ;
 169         for(index=0;index<64;index++)
 170         {
 171                 offset = index*4;
 172                 val32 = rtw_read32(padapter,offset);
 173                 DBG_8192C("offset : 0x%02x ,val:0x%08x\n",offset,val32);
 174         }
 175 }
 176
 177
 178 static void _InitPABias(_adapter *padapter)
 179 {
 180         HAL_DATA_TYPE           *pHalData       = GET_HAL_DATA(padapter);
 181         u8                      pa_setting;
 182         BOOLEAN         is92C = IS_92C_SERIAL(pHalData->VersionID);
 183
 184         //FIXED PA current issue
 185         //efuse_one_byte_read(padapter, 0x1FA, &pa_setting);
 186         pa_setting = EFUSE_Read1Byte(padapter, 0x1FA);
 187
 188         //RT_TRACE(COMP_INIT, DBG_LOUD, ("_InitPABias 0x1FA 0x%x \n",pa_setting));
 189
 190         if(!(pa_setting & BIT0))
 191         {
 192                 PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
 193                 PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
 194                 PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
 195                 PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
 196                 //RT_TRACE(COMP_INIT, DBG_LOUD, ("PA BIAS path A\n"));
 197         }
 198
 199         if(!(pa_setting & BIT1) && is92C)
 200         {
 201                 PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0x0F406);
 202                 PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0x4F406);
 203                 PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0x8F406);
 204                 PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0xCF406);
 205                 //RT_TRACE(COMP_INIT, DBG_LOUD, ("PA BIAS path B\n"));
 206         }
 207
 208         if(!(pa_setting & BIT4))
 209         {
 210                 pa_setting = rtw_read8(padapter, 0x16);
 211                 pa_setting &= 0x0F;
 212                 rtw_write8(padapter, 0x16, pa_setting | 0x80);
 213                 rtw_write8(padapter, 0x16, pa_setting | 0x90);
 214         }
 215 }
 216 #ifdef CONFIG_BT_COEXIST
 217 static void _InitBTCoexist(_adapter *padapter)
 218 {
 219         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(padapter);
 220         struct btcoexist_priv   *pbtpriv = &(pHalData->bt_coexist);
 221         u8 u1Tmp;
 222
 223         if(pbtpriv->BT_Coexist && pbtpriv->BT_CoexistType == BT_CSR_BC4)
 224         {
 225
 226 //#if MP_DRIVER != 1
 227         if (padapter->registrypriv.mp_mode == 0)
 228         {
 229                 if(pbtpriv->BT_Ant_isolation)
 230                 {
 231                         rtw_write8( padapter,REG_GPIO_MUXCFG, 0xa0);
 232                         DBG_8192C("BT write 0x%x = 0x%x\n", REG_GPIO_MUXCFG, 0xa0);
 233                 }
 234         }
 235 //#endif
 236
 237                 u1Tmp = rtw_read8(padapter, 0x4fd) & BIT0;
 238                 u1Tmp = u1Tmp |
 239                                 ((pbtpriv->BT_Ant_isolation==1)?0:BIT1) |
 240                                 ((pbtpriv->BT_Service==BT_SCO)?0:BIT2);
 241                 rtw_write8( padapter, 0x4fd, u1Tmp);
 242                 DBG_8192C("BT write 0x%x = 0x%x for non-isolation\n", 0x4fd, u1Tmp);
 243
 244
 245                 rtw_write32(padapter, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
 246                 DBG_8192C("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
 247
 248                 rtw_write32(padapter, REG_BT_COEX_TABLE+8, 0xffbd0040);
 249                 DBG_8192C("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE+8, 0xffbd0040);
 250
 251                 rtw_write32(padapter,  REG_BT_COEX_TABLE+0xc, 0x40000010);
 252                 DBG_8192C("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE+0xc, 0x40000010);
 253
 254                 //Config to 1T1R
 255                 u1Tmp =  rtw_read8(padapter,rOFDM0_TRxPathEnable);
 256                 u1Tmp &= ~(BIT1);
 257                 rtw_write8( padapter, rOFDM0_TRxPathEnable, u1Tmp);
 258                 DBG_8192C("BT write 0xC04 = 0x%x\n", u1Tmp);
 259
 260                 u1Tmp = rtw_read8(padapter, rOFDM1_TRxPathEnable);
 261                 u1Tmp &= ~(BIT1);
 262                 rtw_write8( padapter, rOFDM1_TRxPathEnable, u1Tmp);
 263                 DBG_8192C("BT write 0xD04 = 0x%x\n", u1Tmp);
 264
 265         }
 266 }
 267 #endif
 268
 269
 270
 271 //---------------------------------------------------------------
 272 //
 273 //      MAC init functions
 274 //
 275 //---------------------------------------------------------------
 276 static VOID
 277 _SetMacID(
 278         IN  PADAPTER Adapter, u8* MacID
 279         )
 280 {
 281         u32 i;
 282         for(i=0 ; i< MAC_ADDR_LEN ; i++){
 283 #ifdef  CONFIG_CONCURRENT_MODE
 284                 if(Adapter->iface_type == IFACE_PORT1)
 285                         rtw_write32(Adapter, REG_MACID1+i, MacID[i]);
 286                 else
 287 #endif
 288                 rtw_write32(Adapter, REG_MACID+i, MacID[i]);
 289         }
 290 }
 291
 292 static VOID
 293 _SetBSSID(
 294         IN  PADAPTER Adapter, u8* BSSID
 295         )
 296 {
 297         u32 i;
 298         for(i=0 ; i< MAC_ADDR_LEN ; i++){
 299 #ifdef  CONFIG_CONCURRENT_MODE
 300                 if(Adapter->iface_type == IFACE_PORT1)
 301                         rtw_write32(Adapter, REG_BSSID1+i, BSSID[i]);
 302                 else
 303 #endif
 304                 rtw_write32(Adapter, REG_BSSID+i, BSSID[i]);
 305         }
 306 }
 307
 308
 309 // Shall USB interface init this?
 310 static VOID
 311 _InitInterrupt(
 312         IN  PADAPTER Adapter
 313         )
 314 {
 315         u32     imr,imr_ex;
 316         u8  usb_opt;
 317         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 318
 319         //HISR write one to clear
 320         rtw_write32(Adapter, REG_HISR_88E, 0xFFFFFFFF);
 321         // HIMR -
 322         imr = IMR_PSTIMEOUT_88E | IMR_TBDER_88E | IMR_CPWM_88E | IMR_CPWM2_88E ;
 323         rtw_write32(Adapter, REG_HIMR_88E, imr);
 324         pHalData->IntrMask[0]=imr;
 325
 326         imr_ex = IMR_TXERR_88E | IMR_RXERR_88E | IMR_TXFOVW_88E |IMR_RXFOVW_88E;
 327         rtw_write32(Adapter, REG_HIMRE_88E, imr_ex);
 328         pHalData->IntrMask[1]=imr_ex;
 329
 330 #ifdef CONFIG_SUPPORT_USB_INT
 331         // REG_USB_SPECIAL_OPTION - BIT(4)
 332         // 0; Use interrupt endpoint to upload interrupt pkt
 333         // 1; Use bulk endpoint to upload interrupt pkt,
 334         usb_opt = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION);
 335
 336         if((IS_FULL_SPEED_USB(Adapter))
 337                 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
 338                 || pHalData->RtIntInPipe == 0x05
 339                 #endif
 340         )
 341                 usb_opt = usb_opt & (~INT_BULK_SEL);
 342         else
 343                 usb_opt = usb_opt | (INT_BULK_SEL);
 344
 345         rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, usb_opt );
 346
 347 #endif//CONFIG_SUPPORT_USB_INT
 348
 349 }
 350
 351
 352 static VOID
 353 _InitQueueReservedPage(
 354         IN  PADAPTER Adapter
 355         )
 356 {
 357         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
 358         struct registry_priv    *pregistrypriv = &Adapter->registrypriv;
 359         u32                     outEPNum        = (u32)pHalData->OutEpNumber;
 360         u32                     numHQ           = 0;
 361         u32                     numLQ           = 0;
 362         u32                     numNQ           = 0;
 363         u32                     numPubQ = 0x00;
 364         u32                     value32;
 365         u8                      value8;
 366         BOOLEAN                 bWiFiConfig     = pregistrypriv->wifi_spec;
 367
 368         if(bWiFiConfig || pregistrypriv->qos_opt_enable)
 369         {
 370                 if (pHalData->OutEpQueueSel & TX_SELE_HQ)
 371                         numHQ =  WMM_NORMAL_PAGE_NUM_HPQ_88E;
 372
 373                 if (pHalData->OutEpQueueSel & TX_SELE_LQ)
 374                         numLQ = WMM_NORMAL_PAGE_NUM_LPQ_88E;
 375
 376                 // NOTE: This step shall be proceed before writting REG_RQPN.
 377                 if (pHalData->OutEpQueueSel & TX_SELE_NQ)
 378                         numNQ = WMM_NORMAL_PAGE_NUM_NPQ_88E;
 379         }
 380         else
 381         {
 382                 if(pHalData->OutEpQueueSel & TX_SELE_HQ)
 383                         numHQ = NORMAL_PAGE_NUM_HPQ_88E;
 384
 385                 if(pHalData->OutEpQueueSel & TX_SELE_LQ)
 386                         numLQ = NORMAL_PAGE_NUM_LPQ_88E;
 387
 388                 // NOTE: This step shall be proceed before writting REG_RQPN.
 389                 if(pHalData->OutEpQueueSel & TX_SELE_NQ)
 390                         numNQ = NORMAL_PAGE_NUM_NPQ_88E;
 391         }
 392
 393         value8 = (u8)_NPQ(numNQ);
 394         rtw_write8(Adapter, REG_RQPN_NPQ, value8);
 395
 396         numPubQ = TX_TOTAL_PAGE_NUMBER_88E - numHQ - numLQ - numNQ;
 397
 398         // TX DMA
 399         value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
 400         rtw_write32(Adapter, REG_RQPN, value32);
 401 }
 402
 403 static VOID
 404 _InitTxBufferBoundary(
 405         IN PADAPTER Adapter,
 406         IN u8 txpktbuf_bndy
 407         )
 408 {
 409         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 410         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
 411
 412         //u16   txdmactrl;
 413
 414         rtw_write8(Adapter, REG_BCNQ_BDNY, txpktbuf_bndy);
 415         rtw_write8(Adapter, REG_MGQ_BDNY, txpktbuf_bndy);
 416         rtw_write8(Adapter, REG_WMAC_LBK_BF_HD, txpktbuf_bndy);
 417         rtw_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy);
 418         rtw_write8(Adapter, REG_TDECTRL+1, txpktbuf_bndy);
 419
 420 }
 421
 422 static VOID
 423 _InitPageBoundary(
 424         IN  PADAPTER Adapter
 425         )
 426 {
 427         // RX Page Boundary
 428         //
 429         u16 rxff_bndy = MAX_RX_DMA_BUFFER_SIZE_88E-1;
 430
 431         #if 0
 432
 433         // RX Page Boundary
 434         //srand(static_cast<unsigned int>(time(NULL)) );
 435         if(bSupportRemoteWakeUp)
 436         {
 437                 Offset = MAX_RX_DMA_BUFFER_SIZE_88E+MAX_TX_REPORT_BUFFER_SIZE-MAX_SUPPORT_WOL_PATTERN_NUM(Adapter)*WKFMCAM_SIZE;
 438                 Offset = Offset / 128; // RX page size = 128 byte
 439                 rxff_bndy= (Offset*128) -1;
 440         }
 441         else
 442
 443         #endif
 444         rtw_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
 445 }
 446
 447
 448 static VOID
 449 _InitNormalChipRegPriority(
 450         IN      PADAPTER        Adapter,
 451         IN      u16             beQ,
 452         IN      u16             bkQ,
 453         IN      u16             viQ,
 454         IN      u16             voQ,
 455         IN      u16             mgtQ,
 456         IN      u16             hiQ
 457         )
 458 {
 459         u16 value16     = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
 460
 461         value16 |=      _TXDMA_BEQ_MAP(beQ)     | _TXDMA_BKQ_MAP(bkQ) |
 462                                 _TXDMA_VIQ_MAP(viQ)     | _TXDMA_VOQ_MAP(voQ) |
 463                                 _TXDMA_MGQ_MAP(mgtQ)| _TXDMA_HIQ_MAP(hiQ);
 464
 465         rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
 466 }
 467
 468 static VOID
 469 _InitNormalChipOneOutEpPriority(
 470         IN      PADAPTER Adapter
 471         )
 472 {
 473         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 474
 475         u16     value = 0;
 476         switch(pHalData->OutEpQueueSel)
 477         {
 478                 case TX_SELE_HQ:
 479                         value = QUEUE_HIGH;
 480                         break;
 481                 case TX_SELE_LQ:
 482                         value = QUEUE_LOW;
 483                         break;
 484                 case TX_SELE_NQ:
 485                         value = QUEUE_NORMAL;
 486                         break;
 487                 default:
 488                         //RT_ASSERT(FALSE,("Shall not reach here!\n"));
 489                         break;
 490         }
 491
 492         _InitNormalChipRegPriority(Adapter,
 493                                                                 value,
 494                                                                 value,
 495                                                                 value,
 496                                                                 value,
 497                                                                 value,
 498                                                                 value
 499                                                                 );
 500
 501 }
 502
 503 static VOID
 504 _InitNormalChipTwoOutEpPriority(
 505         IN      PADAPTER Adapter
 506         )
 507 {
 508         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 509         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 510         u16                     beQ,bkQ,viQ,voQ,mgtQ,hiQ;
 511
 512
 513         u16     valueHi = 0;
 514         u16     valueLow = 0;
 515
 516         switch(pHalData->OutEpQueueSel)
 517         {
 518                 case (TX_SELE_HQ | TX_SELE_LQ):
 519                         valueHi = QUEUE_HIGH;
 520                         valueLow = QUEUE_LOW;
 521                         break;
 522                 case (TX_SELE_NQ | TX_SELE_LQ):
 523                         valueHi = QUEUE_NORMAL;
 524                         valueLow = QUEUE_LOW;
 525                         break;
 526                 case (TX_SELE_HQ | TX_SELE_NQ):
 527                         valueHi = QUEUE_HIGH;
 528                         valueLow = QUEUE_NORMAL;
 529                         break;
 530                 default:
 531                         //RT_ASSERT(FALSE,("Shall not reach here!\n"));
 532                         break;
 533         }
 534
 535         if(!pregistrypriv->wifi_spec ){
 536                 beQ             = valueLow;
 537                 bkQ             = valueLow;
 538                 viQ             = valueHi;
 539                 voQ             = valueHi;
 540                 mgtQ    = valueHi;
 541                 hiQ             = valueHi;
 542         }
 543         else{//for WMM ,CONFIG_OUT_EP_WIFI_MODE
 544                 beQ             = valueLow;
 545                 bkQ             = valueHi;
 546                 viQ             = valueHi;
 547                 voQ             = valueLow;
 548                 mgtQ    = valueHi;
 549                 hiQ             = valueHi;
 550         }
 551
 552         _InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
 553
 554 }
 555
 556 static VOID
 557 _InitNormalChipThreeOutEpPriority(
 558         IN      PADAPTER Adapter
 559         )
 560 {
 561         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 562         u16                     beQ,bkQ,viQ,voQ,mgtQ,hiQ;
 563
 564         if(!pregistrypriv->wifi_spec ){// typical setting
 565                 beQ             = QUEUE_LOW;
 566                 bkQ             = QUEUE_LOW;
 567                 viQ             = QUEUE_NORMAL;
 568                 voQ             = QUEUE_HIGH;
 569                 mgtQ    = QUEUE_HIGH;
 570                 hiQ             = QUEUE_HIGH;
 571         }
 572         else{// for WMM
 573                 beQ             = QUEUE_LOW;
 574                 bkQ             = QUEUE_NORMAL;
 575                 viQ             = QUEUE_NORMAL;
 576                 voQ             = QUEUE_HIGH;
 577                 mgtQ    = QUEUE_HIGH;
 578                 hiQ             = QUEUE_HIGH;
 579         }
 580         _InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
 581 }
 582
 583 static VOID
 584 _InitQueuePriority(
 585         IN      PADAPTER Adapter
 586         )
 587 {
 588         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 589
 590         switch(pHalData->OutEpNumber)
 591         {
 592                 case 1:
 593                         _InitNormalChipOneOutEpPriority(Adapter);
 594                         break;
 595                 case 2:
 596                         _InitNormalChipTwoOutEpPriority(Adapter);
 597                         break;
 598                 case 3:
 599                         _InitNormalChipThreeOutEpPriority(Adapter);
 600                         break;
 601                 default:
 602                         //RT_ASSERT(FALSE,("Shall not reach here!\n"));
 603                         break;
 604         }
 605
 606
 607 }
 608
 609
 610
 611 static VOID
 612 _InitHardwareDropIncorrectBulkOut(
 613         IN  PADAPTER Adapter
 614         )
 615 {
 616 #ifdef ENABLE_USB_DROP_INCORRECT_OUT
 617         u32     value32 = rtw_read32(Adapter, REG_TXDMA_OFFSET_CHK);
 618         value32 |= DROP_DATA_EN;
 619         rtw_write32(Adapter, REG_TXDMA_OFFSET_CHK, value32);
 620 #endif
 621 }
 622
 623 static VOID
 624 _InitNetworkType(
 625         IN  PADAPTER Adapter
 626         )
 627 {
 628         u32     value32;
 629
 630         value32 = rtw_read32(Adapter, REG_CR);
 631         // TODO: use the other function to set network type
 632         value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
 633
 634         rtw_write32(Adapter, REG_CR, value32);
 635 //      RASSERT(pIoBase->rtw_read8(REG_CR + 2) == 0x2);
 636 }
 637
 638
 639 static VOID
 640 _InitDriverInfoSize(
 641         IN  PADAPTER    Adapter,
 642         IN      u8              drvInfoSize
 643         )
 644 {
 645         rtw_write8(Adapter,REG_RX_DRVINFO_SZ, drvInfoSize);
 646 }
 647
 648 static VOID
 649 _InitWMACSetting(
 650         IN  PADAPTER Adapter
 651         )
 652 {
 653         //u4Byte                        value32;
 654         //u16                   value16;
 655         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 656
 657         //pHalData->ReceiveConfig = AAP | APM | AM | AB | APP_ICV | ADF | AMF | APP_FCS | HTC_LOC_CTRL | APP_MIC | APP_PHYSTS;
 658         //pHalData->ReceiveConfig =
 659         //RCR_AAP | RCR_APM | RCR_AM | RCR_AB |RCR_CBSSID_DATA| RCR_CBSSID_BCN| RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | RCR_APP_PHYSTS;
 660          // don't turn on AAP, it will allow all packets to driver
 661         pHalData->ReceiveConfig = RCR_APM | RCR_AM | RCR_AB |RCR_CBSSID_DATA| RCR_CBSSID_BCN| RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | RCR_APP_PHYST_RXFF;
 662
 663 #if (1 == RTL8188E_RX_PACKET_INCLUDE_CRC)
 664         pHalData->ReceiveConfig |= ACRC32;
 665 #endif
 666
 667         // some REG_RCR will be modified later by phy_ConfigMACWithHeaderFile()
 668         rtw_write32(Adapter, REG_RCR, pHalData->ReceiveConfig);
 669
 670         // Accept all multicast address
 671         rtw_write32(Adapter, REG_MAR, 0xFFFFFFFF);
 672         rtw_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF);
 673
 674
 675         // Accept all data frames
 676         //value16 = 0xFFFF;
 677         //rtw_write16(Adapter, REG_RXFLTMAP2, value16);
 678
 679         // 2010.09.08 hpfan
 680         // Since ADF is removed from RCR, ps-poll will not be indicate to driver,
 681         // RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll.
 682         //value16 = 0x400;
 683         //rtw_write16(Adapter, REG_RXFLTMAP1, value16);
 684
 685         // Accept all management frames
 686         //value16 = 0xFFFF;
 687         //rtw_write16(Adapter, REG_RXFLTMAP0, value16);
 688
 689         //enable RX_SHIFT bits
 690         //rtw_write8(Adapter, REG_TRXDMA_CTRL, rtw_read8(Adapter, REG_TRXDMA_CTRL)|BIT(1));
 691
 692 }
 693
 694 static VOID
 695 _InitAdaptiveCtrl(
 696         IN  PADAPTER Adapter
 697         )
 698 {
 699         u16     value16;
 700         u32     value32;
 701
 702         // Response Rate Set
 703         value32 = rtw_read32(Adapter, REG_RRSR);
 704         value32 &= ~RATE_BITMAP_ALL;
 705         value32 |= RATE_RRSR_CCK_ONLY_1M;
 706         rtw_write32(Adapter, REG_RRSR, value32);
 707
 708         // CF-END Threshold
 709         //m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1);
 710
 711         // SIFS (used in NAV)
 712         value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
 713         rtw_write16(Adapter, REG_SPEC_SIFS, value16);
 714
 715         // Retry Limit
 716         value16 = _LRL(0x30) | _SRL(0x30);
 717         rtw_write16(Adapter, REG_RL, value16);
 718
 719 }
 720
 721 static VOID
 722 _InitRateFallback(
 723         IN  PADAPTER Adapter
 724         )
 725 {
 726         // Set Data Auto Rate Fallback Retry Count register.
 727         rtw_write32(Adapter, REG_DARFRC, 0x00000000);
 728         rtw_write32(Adapter, REG_DARFRC+4, 0x10080404);
 729         rtw_write32(Adapter, REG_RARFRC, 0x04030201);
 730         rtw_write32(Adapter, REG_RARFRC+4, 0x08070605);
 731
 732 }
 733
 734
 735 static VOID
 736 _InitEDCA(
 737         IN  PADAPTER Adapter
 738         )
 739 {
 740         // Set Spec SIFS (used in NAV)
 741         rtw_write16(Adapter,REG_SPEC_SIFS, 0x100a);
 742         rtw_write16(Adapter,REG_MAC_SPEC_SIFS, 0x100a);
 743
 744         // Set SIFS for CCK
 745         rtw_write16(Adapter,REG_SIFS_CTX, 0x100a);
 746
 747         // Set SIFS for OFDM
 748         rtw_write16(Adapter,REG_SIFS_TRX, 0x100a);
 749
 750         // TXOP
 751         rtw_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B);
 752         rtw_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F);
 753         rtw_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324);
 754         rtw_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226);
 755 }
 756
 757
 758 static VOID
 759 _InitBeaconMaxError(
 760         IN  PADAPTER    Adapter,
 761         IN      BOOLEAN         InfraMode
 762         )
 763 {
 764
 765 }
 766
 767
 768 #ifdef CONFIG_LED
 769 static void _InitHWLed(PADAPTER Adapter)
 770 {
 771         struct led_priv *pledpriv = &(Adapter->ledpriv);
 772
 773         if( pledpriv->LedStrategy != HW_LED)
 774                 return;
 775
 776 // HW led control
 777 // to do ....
 778 //must consider cases of antenna diversity/ commbo card/solo card/mini card
 779
 780 }
 781 #endif //CONFIG_LED
 782
 783 static VOID
 784 _InitRDGSetting(
 785         IN      PADAPTER Adapter
 786         )
 787 {
 788         rtw_write8(Adapter,REG_RD_CTRL,0xFF);
 789         rtw_write16(Adapter, REG_RD_NAV_NXT, 0x200);
 790         rtw_write8(Adapter,REG_RD_RESP_PKT_TH,0x05);
 791 }
 792
 793 static VOID
 794 _InitRxSetting(
 795         IN      PADAPTER Adapter
 796         )
 797 {
 798         rtw_write32(Adapter, REG_MACID, 0x87654321);
 799         rtw_write32(Adapter, 0x0700, 0x87654321);
 800 }
 801
 802 static VOID
 803 _InitRetryFunction(
 804         IN  PADAPTER Adapter
 805         )
 806 {
 807         u8      value8;
 808
 809         value8 = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL);
 810         value8 |= EN_AMPDU_RTY_NEW;
 811         rtw_write8(Adapter, REG_FWHW_TXQ_CTRL, value8);
 812
 813         // Set ACK timeout
 814         rtw_write8(Adapter, REG_ACKTO, 0x40);
 815 }
 816
 817 /*-----------------------------------------------------------------------------
 818  * Function:    usb_AggSettingTxUpdate()
 819  *
 820  * Overview:    Seperate TX/RX parameters update independent for TP detection and
 821  *                      dynamic TX/RX aggreagtion parameters update.
 822  *
 823  * Input:                       PADAPTER
 824  *
 825  * Output/Return:       NONE
 826  *
 827  * Revised History:
 828  *      When            Who             Remark
 829  *      12/10/2010      MHC             Seperate to smaller function.
 830  *
 831  *---------------------------------------------------------------------------*/
 832 static VOID
 833 usb_AggSettingTxUpdate(
 834         IN      PADAPTER                        Adapter
 835         )
 836 {
 837 #ifdef CONFIG_USB_TX_AGGREGATION
 838         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 839         //PMGNT_INFO            pMgntInfo = &(Adapter->MgntInfo);
 840         u32                     value32;
 841
 842         if(Adapter->registrypriv.wifi_spec)
 843                 pHalData->UsbTxAggMode = _FALSE;
 844
 845         if(pHalData->UsbTxAggMode){
 846                 value32 = rtw_read32(Adapter, REG_TDECTRL);
 847                 value32 = value32 & ~(BLK_DESC_NUM_MASK << BLK_DESC_NUM_SHIFT);
 848                 value32 |= ((pHalData->UsbTxAggDescNum & BLK_DESC_NUM_MASK) << BLK_DESC_NUM_SHIFT);
 849
 850                 rtw_write32(Adapter, REG_TDECTRL, value32);
 851         }
 852
 853 #endif
 854 }       // usb_AggSettingTxUpdate
 855
 856
 857 /*-----------------------------------------------------------------------------
 858  * Function:    usb_AggSettingRxUpdate()
 859  *
 860  * Overview:    Seperate TX/RX parameters update independent for TP detection and
 861  *                      dynamic TX/RX aggreagtion parameters update.
 862  *
 863  * Input:                       PADAPTER
 864  *
 865  * Output/Return:       NONE
 866  *
 867  * Revised History:
 868  *      When            Who             Remark
 869  *      12/10/2010      MHC             Seperate to smaller function.
 870  *
 871  *---------------------------------------------------------------------------*/
 872 static VOID
 873 usb_AggSettingRxUpdate(
 874         IN      PADAPTER                        Adapter
 875         )
 876 {
 877 #ifdef CONFIG_USB_RX_AGGREGATION
 878         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 879         //PMGNT_INFO            pMgntInfo = &(Adapter->MgntInfo);
 880         u8                      valueDMA;
 881         u8                      valueUSB;
 882
 883         valueDMA = rtw_read8(Adapter, REG_TRXDMA_CTRL);
 884         valueUSB = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION);
 885
 886         switch(pHalData->UsbRxAggMode)
 887         {
 888                 case USB_RX_AGG_DMA:
 889                         valueDMA |= RXDMA_AGG_EN;
 890                         valueUSB &= ~USB_AGG_EN;
 891                         break;
 892                 case USB_RX_AGG_USB:
 893                         valueDMA &= ~RXDMA_AGG_EN;
 894                         valueUSB |= USB_AGG_EN;
 895                         break;
 896                 case USB_RX_AGG_MIX:
 897                         valueDMA |= RXDMA_AGG_EN;
 898                         valueUSB |= USB_AGG_EN;
 899                         break;
 900                 case USB_RX_AGG_DISABLE:
 901                 default:
 902                         valueDMA &= ~RXDMA_AGG_EN;
 903                         valueUSB &= ~USB_AGG_EN;
 904                         break;
 905         }
 906
 907         rtw_write8(Adapter, REG_TRXDMA_CTRL, valueDMA);
 908         rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, valueUSB);
 909
 910         switch(pHalData->UsbRxAggMode)
 911         {
 912                 case USB_RX_AGG_DMA:
 913                         rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, pHalData->UsbRxAggPageCount);
 914                         rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH+1, pHalData->UsbRxAggPageTimeout);
 915                         break;
 916                 case USB_RX_AGG_USB:
 917                         rtw_write8(Adapter, REG_USB_AGG_TH, pHalData->UsbRxAggBlockCount);
 918                         rtw_write8(Adapter, REG_USB_AGG_TO, pHalData->UsbRxAggBlockTimeout);
 919                         break;
 920                 case USB_RX_AGG_MIX:
 921                         rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, pHalData->UsbRxAggPageCount);
 922                         rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH+1, (pHalData->UsbRxAggPageTimeout& 0x1F));//0x280[12:8]
 923
 924                         rtw_write8(Adapter, REG_USB_AGG_TH, pHalData->UsbRxAggBlockCount);
 925                         rtw_write8(Adapter, REG_USB_AGG_TO, pHalData->UsbRxAggBlockTimeout);
 926
 927                         break;
 928                 case USB_RX_AGG_DISABLE:
 929                 default:
 930                         // TODO:
 931                         break;
 932         }
 933
 934         switch(PBP_128)
 935         {
 936                 case PBP_128:
 937                         pHalData->HwRxPageSize = 128;
 938                         break;
 939                 case PBP_64:
 940                         pHalData->HwRxPageSize = 64;
 941                         break;
 942                 case PBP_256:
 943                         pHalData->HwRxPageSize = 256;
 944                         break;
 945                 case PBP_512:
 946                         pHalData->HwRxPageSize = 512;
 947                         break;
 948                 case PBP_1024:
 949                         pHalData->HwRxPageSize = 1024;
 950                         break;
 951                 default:
 952                         //RT_ASSERT(FALSE, ("RX_PAGE_SIZE_REG_VALUE definition is incorrect!\n"));
 953                         break;
 954         }
 955 #endif
 956 }       // usb_AggSettingRxUpdate
 957
 958 static VOID
 959 InitUsbAggregationSetting(
 960         IN  PADAPTER Adapter
 961         )
 962 {
 963         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 964
 965         // Tx aggregation setting
 966         usb_AggSettingTxUpdate(Adapter);
 967
 968         // Rx aggregation setting
 969         usb_AggSettingRxUpdate(Adapter);
 970
 971         // 201/12/10 MH Add for USB agg mode dynamic switch.
 972         pHalData->UsbRxHighSpeedMode = _FALSE;
 973 }
 974 VOID
 975 HalRxAggr8188EUsb(
 976         IN  PADAPTER Adapter,
 977         IN BOOLEAN      Value
 978         )
 979 {
 980 #if 0//USB_RX_AGGREGATION_92C
 981
 982         PMGNT_INFO              pMgntInfo = &Adapter->MgntInfo;
 983         u1Byte                  valueDMATimeout;
 984         u1Byte                  valueDMAPageCount;
 985         u1Byte                  valueUSBTimeout;
 986         u1Byte                  valueUSBBlockCount;
 987
 988         // selection to prevent bad TP.
 989         if( IS_WIRELESS_MODE_B(Adapter) || IS_WIRELESS_MODE_G(Adapter) || IS_WIRELESS_MODE_A(Adapter)|| pMgntInfo->bWiFiConfg)
 990         {
 991                 // 2010.04.27 hpfan
 992                 // Adjust RxAggrTimeout to close to zero disable RxAggr, suggested by designer
 993                 // Timeout value is calculated by 34 / (2^n)
 994                 valueDMATimeout = 0x0f;
 995                 valueDMAPageCount = 0x01;
 996                 valueUSBTimeout = 0x0f;
 997                 valueUSBBlockCount = 0x01;
 998                 rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_PGTO, (pu1Byte)&valueDMATimeout);
 999                 rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_PGTH, (pu1Byte)&valueDMAPageCount);
1000                 rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTO, (pu1Byte)&valueUSBTimeout);
1001                 rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTH, (pu1Byte)&valueUSBBlockCount);
1002         }
1003         else
1004         {
1005                 rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTO, (pu1Byte)&pMgntInfo->RegRxAggBlockTimeout);
1006                 rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTH, (pu1Byte)&pMgntInfo->RegRxAggBlockCount);
1007         }
1008
1009 #endif
1010 }
1011
1012 /*-----------------------------------------------------------------------------
1013  * Function:    USB_AggModeSwitch()
1014  *
1015  * Overview:    When RX traffic is more than 40M, we need to adjust some parameters to increase
1016  *                      RX speed by increasing batch indication size. This will decrease TCP ACK speed, we
1017  *                      need to monitor the influence of FTP/network share.
1018  *                      For TX mode, we are still ubder investigation.
1019  *
1020  * Input:               PADAPTER
1021  *
1022  * Output:              NONE
1023  *
1024  * Return:              NONE
1025  *
1026  * Revised History:
1027  *      When            Who             Remark
1028  *      12/10/2010      MHC             Create Version 0.
1029  *
1030  *---------------------------------------------------------------------------*/
1031 VOID
1032 USB_AggModeSwitch(
1033         IN      PADAPTER                        Adapter
1034         )
1035 {
1036 #if 0
1037         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1038         PMGNT_INFO              pMgntInfo = &(Adapter->MgntInfo);
1039
1040         //pHalData->UsbRxHighSpeedMode = FALSE;
1041         // How to measure the RX speed? We assume that when traffic is more than
1042         if (pMgntInfo->bRegAggDMEnable == FALSE)
1043         {
1044                 return; // Inf not support.
1045         }
1046
1047
1048         if (pMgntInfo->LinkDetectInfo.bHigherBusyRxTraffic == TRUE &&
1049                 pHalData->UsbRxHighSpeedMode == FALSE)
1050         {
1051                 pHalData->UsbRxHighSpeedMode = TRUE;
1052                 RT_TRACE(COMP_INIT, DBG_LOUD, ("UsbAggModeSwitchCheck to HIGH\n"));
1053         }
1054         else if (pMgntInfo->LinkDetectInfo.bHigherBusyRxTraffic == FALSE &&
1055                 pHalData->UsbRxHighSpeedMode == TRUE)
1056         {
1057                 pHalData->UsbRxHighSpeedMode = FALSE;
1058                 RT_TRACE(COMP_INIT, DBG_LOUD, ("UsbAggModeSwitchCheck to LOW\n"));
1059         }
1060         else
1061         {
1062                 return;
1063         }
1064
1065
1066 #if USB_RX_AGGREGATION_92C
1067         if (pHalData->UsbRxHighSpeedMode == TRUE)
1068         {
1069                 // 2010/12/10 MH The parameter is tested by SD1 engineer and SD3 channel emulator.
1070                 // USB mode
1071 #if (RT_PLATFORM == PLATFORM_LINUX)
1072                 if (pMgntInfo->LinkDetectInfo.bTxBusyTraffic)
1073                 {
1074                         pHalData->RxAggBlockCount       = 16;
1075                         pHalData->RxAggBlockTimeout     = 7;
1076                 }
1077                 else
1078 #endif
1079                 {
1080                         pHalData->RxAggBlockCount       = 40;
1081                         pHalData->RxAggBlockTimeout     = 5;
1082                 }
1083                 // Mix mode
1084                 pHalData->RxAggPageCount        = 72;
1085                 pHalData->RxAggPageTimeout      = 6;
1086         }
1087         else
1088         {
1089                 // USB mode
1090                 pHalData->RxAggBlockCount       = pMgntInfo->RegRxAggBlockCount;
1091                 pHalData->RxAggBlockTimeout     = pMgntInfo->RegRxAggBlockTimeout;
1092                 // Mix mode
1093                 pHalData->RxAggPageCount                = pMgntInfo->RegRxAggPageCount;
1094                 pHalData->RxAggPageTimeout      = pMgntInfo->RegRxAggPageTimeout;
1095         }
1096
1097         if (pHalData->RxAggBlockCount > MAX_RX_AGG_BLKCNT)
1098                 pHalData->RxAggBlockCount = MAX_RX_AGG_BLKCNT;
1099 #if (OS_WIN_FROM_VISTA(OS_VERSION)) || (RT_PLATFORM == PLATFORM_LINUX)  // do not support WINXP to prevent usbehci.sys BSOD
1100         if (IS_WIRELESS_MODE_N_24G(Adapter) || IS_WIRELESS_MODE_N_5G(Adapter))
1101         {
1102                 //
1103                 // 2010/12/24 MH According to V1012 QC IOT test, XP BSOD happen when running chariot test
1104                 // with the aggregation dynamic change!! We need to disable the function to prevent it is broken
1105                 // in usbehci.sys.
1106                 //
1107                 usb_AggSettingRxUpdate_8188E(Adapter);
1108
1109                 // 2010/12/27 MH According to designer's suggstion, we can only modify Timeout value. Otheriwse
1110                 // there might many HW incorrect behavior, the XP BSOD at usbehci.sys may be relative to the
1111                 // issue. Base on the newest test, we can not enable block cnt > 30, otherwise XP usbehci.sys may
1112                 // BSOD.
1113         }
1114 #endif
1115
1116 #endif
1117 #endif
1118 }       // USB_AggModeSwitch
1119
1120 static VOID
1121 _InitOperationMode(
1122         IN      PADAPTER                        Adapter
1123         )
1124 {
1125 #if 0//gtest
1126         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(Adapter);
1127         u1Byte                          regBwOpMode = 0;
1128         u4Byte                          regRATR = 0, regRRSR = 0;
1129
1130
1131         //1 This part need to modified according to the rate set we filtered!!
1132         //
1133         // Set RRSR, RATR, and REG_BWOPMODE registers
1134         //
1135         switch(Adapter->RegWirelessMode)
1136         {
1137                 case WIRELESS_MODE_B:
1138                         regBwOpMode = BW_OPMODE_20MHZ;
1139                         regRATR = RATE_ALL_CCK;
1140                         regRRSR = RATE_ALL_CCK;
1141                         break;
1142                 case WIRELESS_MODE_A:
1143                         regBwOpMode = BW_OPMODE_5G |BW_OPMODE_20MHZ;
1144                         regRATR = RATE_ALL_OFDM_AG;
1145                         regRRSR = RATE_ALL_OFDM_AG;
1146                         break;
1147                 case WIRELESS_MODE_G:
1148                         regBwOpMode = BW_OPMODE_20MHZ;
1149                         regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1150                         regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1151                         break;
1152                 case WIRELESS_MODE_AUTO:
1153                         if (Adapter->bInHctTest)
1154                         {
1155                             regBwOpMode = BW_OPMODE_20MHZ;
1156                             regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1157                             regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1158                         }
1159                         else
1160                         {
1161                             regBwOpMode = BW_OPMODE_20MHZ;
1162                             regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
1163                             regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1164                         }
1165                         break;
1166                 case WIRELESS_MODE_N_24G:
1167                         // It support CCK rate by default.
1168                         // CCK rate will be filtered out only when associated AP does not support it.
1169                         regBwOpMode = BW_OPMODE_20MHZ;
1170                                 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
1171                                 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1172                         break;
1173                 case WIRELESS_MODE_N_5G:
1174                         regBwOpMode = BW_OPMODE_5G;
1175                         regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
1176                         regRRSR = RATE_ALL_OFDM_AG;
1177                         break;
1178
1179                 default: //for MacOSX compiler warning.
1180                         break;
1181         }
1182
1183         // Ziv ????????
1184         //PlatformEFIOWrite4Byte(Adapter, REG_INIRTS_RATE_SEL, regRRSR);
1185         PlatformEFIOWrite1Byte(Adapter, REG_BWOPMODE, regBwOpMode);
1186 #endif
1187 }
1188
1189
1190  static VOID
1191 _InitBeaconParameters(
1192         IN  PADAPTER Adapter
1193         )
1194 {
1195         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1196
1197         rtw_write16(Adapter, REG_BCN_CTRL, 0x1010);
1198
1199         // TODO: Remove these magic number
1200         rtw_write16(Adapter, REG_TBTT_PROHIBIT,0x6404);// ms
1201         rtw_write8(Adapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME_8188E);// 5ms
1202         rtw_write8(Adapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME_8188E); // 2ms
1203
1204         // Suggested by designer timchen. Change beacon AIFS to the largest number
1205         // beacause test chip does not contension before sending beacon. by tynli. 2009.11.03
1206         rtw_write16(Adapter, REG_BCNTCFG, 0x660F);
1207
1208         pHalData->RegBcnCtrlVal = rtw_read8(Adapter, REG_BCN_CTRL);
1209         pHalData->RegTxPause = rtw_read8(Adapter, REG_TXPAUSE);
1210         pHalData->RegFwHwTxQCtrl = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL+2);
1211         pHalData->RegReg542 = rtw_read8(Adapter, REG_TBTT_PROHIBIT+2);
1212         pHalData->RegCR_1 = rtw_read8(Adapter, REG_CR+1);
1213 }
1214
1215 static VOID
1216 _InitRFType(
1217         IN      PADAPTER Adapter
1218         )
1219 {
1220         struct registry_priv     *pregpriv = &Adapter->registrypriv;
1221         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
1222         BOOLEAN                 is92CU          = IS_92C_SERIAL(pHalData->VersionID);
1223
1224 #if     DISABLE_BB_RF
1225         pHalData->rf_chip       = RF_PSEUDO_11N;
1226         return;
1227 #endif
1228
1229         pHalData->rf_chip       = RF_6052;
1230
1231         if(_FALSE == is92CU){
1232                 pHalData->rf_type = RF_1T1R;
1233                 DBG_8192C("Set RF Chip ID to RF_6052 and RF type to 1T1R.\n");
1234                 return;
1235         }
1236
1237         // TODO: Consider that EEPROM set 92CU to 1T1R later.
1238         // Force to overwrite setting according to chip version. Ignore EEPROM setting.
1239         //pHalData->RF_Type = is92CU ? RF_2T2R : RF_1T1R;
1240         MSG_8192C("Set RF Chip ID to RF_6052 and RF type to %d.\n", pHalData->rf_type);
1241
1242 }
1243
1244
1245 static VOID
1246 _BeaconFunctionEnable(
1247         IN      PADAPTER                Adapter,
1248         IN      BOOLEAN                 Enable,
1249         IN      BOOLEAN                 Linked
1250         )
1251 {
1252         rtw_write8(Adapter, REG_BCN_CTRL, (BIT4 | BIT3 | BIT1));
1253         //SetBcnCtrlReg(Adapter, (BIT4 | BIT3 | BIT1), 0x00);
1254         //RT_TRACE(COMP_BEACON, DBG_LOUD, ("_BeaconFunctionEnable 0x550 0x%x\n", PlatformEFIORead1Byte(Adapter, 0x550)));
1255
1256         rtw_write8(Adapter, REG_RD_CTRL+1, 0x6F);
1257 }
1258
1259
1260 // Set CCK and OFDM Block "ON"
1261 static VOID _BBTurnOnBlock(
1262         IN      PADAPTER                Adapter
1263         )
1264 {
1265 #if (DISABLE_BB_RF)
1266         return;
1267 #endif
1268
1269         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
1270         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
1271 }
1272
1273 static VOID _RfPowerSave(
1274         IN      PADAPTER                Adapter
1275         )
1276 {
1277 #if 0
1278         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
1279         PMGNT_INFO              pMgntInfo       = &(Adapter->MgntInfo);
1280         u1Byte                  eRFPath;
1281
1282 #if (DISABLE_BB_RF)
1283         return;
1284 #endif
1285
1286         if(pMgntInfo->RegRfOff == TRUE){ // User disable RF via registry.
1287                 RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter8192CUsb(): Turn off RF for RegRfOff.\n"));
1288                 MgntActSet_RF_State(Adapter, eRfOff, RF_CHANGE_BY_SW);
1289                 // Those action will be discard in MgntActSet_RF_State because off the same state
1290                 for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
1291                         PHY_SetRFReg(Adapter, eRFPath, 0x4, 0xC00, 0x0);
1292         }
1293         else if(pMgntInfo->RfOffReason > RF_CHANGE_BY_PS){ // H/W or S/W RF OFF before sleep.
1294                 RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter8192CUsb(): Turn off RF for RfOffReason(%ld).\n", pMgntInfo->RfOffReason));
1295                 MgntActSet_RF_State(Adapter, eRfOff, pMgntInfo->RfOffReason);
1296         }
1297         else{
1298                 pHalData->eRFPowerState = eRfOn;
1299                 pMgntInfo->RfOffReason = 0;
1300                 if(Adapter->bInSetPower || Adapter->bResetInProgress)
1301                         PlatformUsbEnableInPipes(Adapter);
1302                 RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter8192CUsb(): RF is on.\n"));
1303         }
1304 #endif
1305 }
1306
1307 enum {
1308         Antenna_Lfet = 1,
1309         Antenna_Right = 2,
1310 };
1311
1312 static VOID
1313 _InitAntenna_Selection(IN       PADAPTER Adapter)
1314 {
1315
1316         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
1317
1318         if(pHalData->AntDivCfg==0)
1319                 return;
1320         DBG_8192C("==>  %s ....\n",__FUNCTION__);
1321
1322         rtw_write32(Adapter, REG_LEDCFG0, rtw_read32(Adapter, REG_LEDCFG0)|BIT23);
1323         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);
1324
1325         if(PHY_QueryBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300) == MAIN_ANT)
1326                 pHalData->CurAntenna = MAIN_ANT;
1327         else
1328                 pHalData->CurAntenna = AUX_ANT;
1329         DBG_8192C("%s,Cur_ant:(%x)%s\n",__FUNCTION__,pHalData->CurAntenna,(pHalData->CurAntenna == MAIN_ANT)?"MAIN_ANT":"AUX_ANT");
1330
1331
1332 }
1333
1334 //
1335 // 2010/08/26 MH Add for selective suspend mode check.
1336 // If Efuse 0x0e bit1 is not enabled, we can not support selective suspend for Minicard and
1337 // slim card.
1338 //
1339 static VOID
1340 HalDetectSelectiveSuspendMode(
1341         IN PADAPTER                             Adapter
1342         )
1343 {
1344 #if 0
1345         u8      tmpvalue;
1346         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1347         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(Adapter);
1348
1349         // If support HW radio detect, we need to enable WOL ability, otherwise, we
1350         // can not use FW to notify host the power state switch.
1351
1352         EFUSE_ShadowRead(Adapter, 1, EEPROM_USB_OPTIONAL1, (u32 *)&tmpvalue);
1353
1354         DBG_8192C("HalDetectSelectiveSuspendMode(): SS ");
1355         if(tmpvalue & BIT1)
1356         {
1357                 DBG_8192C("Enable\n");
1358         }
1359         else
1360         {
1361                 DBG_8192C("Disable\n");
1362                 pdvobjpriv->RegUsbSS = _FALSE;
1363         }
1364
1365         // 2010/09/01 MH According to Dongle Selective Suspend INF. We can switch SS mode.
1366         if (pdvobjpriv->RegUsbSS && !SUPPORT_HW_RADIO_DETECT(pHalData))
1367         {
1368                 //PMGNT_INFO                            pMgntInfo = &(Adapter->MgntInfo);
1369
1370                 //if (!pMgntInfo->bRegDongleSS)
1371                 //{
1372                 //      RT_TRACE(COMP_INIT, DBG_LOUD, ("Dongle disable SS\n"));
1373                         pdvobjpriv->RegUsbSS = _FALSE;
1374                 //}
1375         }
1376 #endif
1377 }       // HalDetectSelectiveSuspendMode
1378 /*-----------------------------------------------------------------------------
1379  * Function:    HwSuspendModeEnable92Cu()
1380  *
1381  * Overview:    HW suspend mode switch.
1382  *
1383  * Input:               NONE
1384  *
1385  * Output:      NONE
1386  *
1387  * Return:      NONE
1388  *
1389  * Revised History:
1390  *      When            Who             Remark
1391  *      08/23/2010      MHC             HW suspend mode switch test..
1392  *---------------------------------------------------------------------------*/
1393 static VOID
1394 HwSuspendModeEnable_88eu(
1395         IN      PADAPTER        pAdapter,
1396         IN      u8                      Type
1397         )
1398 {
1399         //PRT_USB_DEVICE                pDevice = GET_RT_USB_DEVICE(pAdapter);
1400         u16     reg = rtw_read16(pAdapter, REG_GPIO_MUXCFG);
1401
1402         //if (!pDevice->RegUsbSS)
1403         {
1404                 return;
1405         }
1406
1407         //
1408         // 2010/08/23 MH According to Alfred's suggestion, we need to to prevent HW
1409         // to enter suspend mode automatically. Otherwise, it will shut down major power
1410         // domain and 8051 will stop. When we try to enter selective suspend mode, we
1411         // need to prevent HW to enter D2 mode aumotmatically. Another way, Host will
1412         // issue a S10 signal to power domain. Then it will cleat SIC setting(from Yngli).
1413         // We need to enable HW suspend mode when enter S3/S4 or disable. We need
1414         // to disable HW suspend mode for IPS/radio_off.
1415         //
1416         //RT_TRACE(COMP_RF, DBG_LOUD, ("HwSuspendModeEnable92Cu = %d\n", Type));
1417         if (Type == _FALSE)
1418         {
1419                 reg |= BIT14;
1420                 //RT_TRACE(COMP_RF, DBG_LOUD, ("REG_GPIO_MUXCFG = %x\n", reg));
1421                 rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
1422                 reg |= BIT12;
1423                 //RT_TRACE(COMP_RF, DBG_LOUD, ("REG_GPIO_MUXCFG = %x\n", reg));
1424                 rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
1425         }
1426         else
1427         {
1428                 reg &= (~BIT12);
1429                 rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
1430                 reg &= (~BIT14);
1431                 rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
1432         }
1433
1434 }       // HwSuspendModeEnable92Cu
1435 rt_rf_power_state RfOnOffDetect(IN      PADAPTER pAdapter )
1436 {
1437         struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(pAdapter);
1438         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(pAdapter);
1439         u8      val8;
1440         rt_rf_power_state rfpowerstate = rf_off;
1441
1442         if(pwrctl->bHWPowerdown)
1443         {
1444                 val8 = rtw_read8(pAdapter, REG_HSISR);
1445                 DBG_8192C("pwrdown, 0x5c(BIT7)=%02x\n", val8);
1446                 rfpowerstate = (val8 & BIT7) ? rf_off: rf_on;
1447         }
1448         else // rf on/off
1449         {
1450                 rtw_write8(     pAdapter, REG_MAC_PINMUX_CFG,rtw_read8(pAdapter, REG_MAC_PINMUX_CFG)&~(BIT3));
1451                 val8 = rtw_read8(pAdapter, REG_GPIO_IO_SEL);
1452                 DBG_8192C("GPIO_IN=%02x\n", val8);
1453                 rfpowerstate = (val8 & BIT3) ? rf_on : rf_off;
1454         }
1455         return rfpowerstate;
1456 }       // HalDetectPwrDownMode
1457
1458 void _ps_open_RF(_adapter *padapter);
1459
1460 u32 rtl8188eu_hal_init(PADAPTER Adapter)
1461 {
1462         u8      value8 = 0;
1463         u16  value16;
1464         u8      txpktbuf_bndy;
1465         u32     status = _SUCCESS;
1466         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
1467         struct pwrctrl_priv             *pwrctrlpriv = adapter_to_pwrctl(Adapter);
1468         struct registry_priv    *pregistrypriv = &Adapter->registrypriv;
1469
1470         rt_rf_power_state               eRfPowerStateToSet;
1471 #ifdef CONFIG_BT_COEXIST
1472         struct btcoexist_priv   *pbtpriv = &(pHalData->bt_coexist);
1473 #endif
1474
1475         u32 init_start_time = rtw_get_current_time();
1476
1477
1478 #ifdef DBG_HAL_INIT_PROFILING
1479
1480         enum HAL_INIT_STAGES {
1481                 HAL_INIT_STAGES_BEGIN = 0,
1482                 HAL_INIT_STAGES_INIT_PW_ON,
1483                 HAL_INIT_STAGES_MISC01,
1484                 HAL_INIT_STAGES_DOWNLOAD_FW,
1485                 HAL_INIT_STAGES_MAC,
1486                 HAL_INIT_STAGES_BB,
1487                 HAL_INIT_STAGES_RF,
1488                 HAL_INIT_STAGES_EFUSE_PATCH,
1489                 HAL_INIT_STAGES_INIT_LLTT,
1490
1491                 HAL_INIT_STAGES_MISC02,
1492                 HAL_INIT_STAGES_TURN_ON_BLOCK,
1493                 HAL_INIT_STAGES_INIT_SECURITY,
1494                 HAL_INIT_STAGES_MISC11,
1495                 HAL_INIT_STAGES_INIT_HAL_DM,
1496                 //HAL_INIT_STAGES_RF_PS,
1497                 HAL_INIT_STAGES_IQK,
1498                 HAL_INIT_STAGES_PW_TRACK,
1499                 HAL_INIT_STAGES_LCK,
1500                 //HAL_INIT_STAGES_MISC21,
1501                 //HAL_INIT_STAGES_INIT_PABIAS,
1502                 #ifdef CONFIG_BT_COEXIST
1503                 HAL_INIT_STAGES_BT_COEXIST,
1504                 #endif
1505                 //HAL_INIT_STAGES_ANTENNA_SEL,
1506                 //HAL_INIT_STAGES_MISC31,
1507                 HAL_INIT_STAGES_END,
1508                 HAL_INIT_STAGES_NUM
1509         };
1510
1511         char * hal_init_stages_str[] = {
1512                 "HAL_INIT_STAGES_BEGIN",
1513                 "HAL_INIT_STAGES_INIT_PW_ON",
1514                 "HAL_INIT_STAGES_MISC01",
1515                 "HAL_INIT_STAGES_DOWNLOAD_FW",
1516                 "HAL_INIT_STAGES_MAC",
1517                 "HAL_INIT_STAGES_BB",
1518                 "HAL_INIT_STAGES_RF",
1519                 "HAL_INIT_STAGES_EFUSE_PATCH",
1520                 "HAL_INIT_STAGES_INIT_LLTT",
1521                 "HAL_INIT_STAGES_MISC02",
1522                 "HAL_INIT_STAGES_TURN_ON_BLOCK",
1523                 "HAL_INIT_STAGES_INIT_SECURITY",
1524                 "HAL_INIT_STAGES_MISC11",
1525                 "HAL_INIT_STAGES_INIT_HAL_DM",
1526                 //"HAL_INIT_STAGES_RF_PS",
1527                 "HAL_INIT_STAGES_IQK",
1528                 "HAL_INIT_STAGES_PW_TRACK",
1529                 "HAL_INIT_STAGES_LCK",
1530                 //"HAL_INIT_STAGES_MISC21",
1531                 #ifdef CONFIG_BT_COEXIST
1532                 "HAL_INIT_STAGES_BT_COEXIST",
1533                 #endif
1534                 //"HAL_INIT_STAGES_ANTENNA_SEL",
1535                 //"HAL_INIT_STAGES_MISC31",
1536                 "HAL_INIT_STAGES_END",
1537         };
1538
1539         int hal_init_profiling_i;
1540         u32 hal_init_stages_timestamp[HAL_INIT_STAGES_NUM]; //used to record the time of each stage's starting point
1541
1542         for(hal_init_profiling_i=0;hal_init_profiling_i<HAL_INIT_STAGES_NUM;hal_init_profiling_i++)
1543                 hal_init_stages_timestamp[hal_init_profiling_i]=0;
1544
1545         #define HAL_INIT_PROFILE_TAG(stage) hal_init_stages_timestamp[(stage)]=rtw_get_current_time();
1546 #else
1547         #define HAL_INIT_PROFILE_TAG(stage) do {} while(0)
1548 #endif //DBG_HAL_INIT_PROFILING
1549
1550
1551
1552 _func_enter_;
1553
1554 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN);
1555
1556 #ifdef CONFIG_WOWLAN
1557
1558         pwrctrlpriv->wowlan_wake_reason = rtw_read8(Adapter, REG_WOWLAN_WAKE_REASON);
1559         DBG_8192C("%s wowlan_wake_reason: 0x%02x\n",
1560                                 __func__, pwrctrlpriv->wowlan_wake_reason);
1561
1562         if(rtw_read8(Adapter, REG_MCUFWDL)&BIT7){ /*&&
1563                 (pwrctrlpriv->wowlan_wake_reason & FWDecisionDisconnect)) {*/
1564                 u8 reg_val=0;
1565                 DBG_8192C("+Reset Entry+\n");
1566                 rtw_write8(Adapter, REG_MCUFWDL, 0x00);
1567                 _8051Reset88E(Adapter);
1568                 //reset BB
1569                 reg_val = rtw_read8(Adapter, REG_SYS_FUNC_EN);
1570                 reg_val &= ~(BIT(0) | BIT(1));
1571                 rtw_write8(Adapter, REG_SYS_FUNC_EN, reg_val);
1572                 //reset RF
1573                 rtw_write8(Adapter, REG_RF_CTRL, 0);
1574                 //reset TRX path
1575                 rtw_write16(Adapter, REG_CR, 0);
1576                 //reset MAC, Digital Core
1577                 reg_val = rtw_read8(Adapter, REG_SYS_FUNC_EN+1);
1578                 reg_val &= ~(BIT(4) | BIT(7));
1579                 rtw_write8(Adapter, REG_SYS_FUNC_EN+1, reg_val);
1580                 reg_val = rtw_read8(Adapter, REG_SYS_FUNC_EN+1);
1581                 reg_val |= BIT(4) | BIT(7);
1582                 rtw_write8(Adapter, REG_SYS_FUNC_EN+1, reg_val);
1583                 DBG_8192C("-Reset Entry-\n");
1584         }
1585 #endif //CONFIG_WOWLAN
1586
1587         if(pwrctrlpriv->bkeepfwalive)
1588         {
1589                 _ps_open_RF(Adapter);
1590
1591                 if(pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized){
1592 //                      PHY_IQCalibrate(padapter, _TRUE);
1593                         PHY_IQCalibrate_8188E(Adapter,_TRUE);
1594                 }
1595                 else
1596                 {
1597 //                      PHY_IQCalibrate(padapter, _FALSE);
1598                         PHY_IQCalibrate_8188E(Adapter,_FALSE);
1599                         pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = _TRUE;
1600                 }
1601
1602 //              dm_CheckTXPowerTracking(padapter);
1603 //              PHY_LCCalibrate(padapter);
1604                 ODM_TXPowerTrackingCheck(&pHalData->odmpriv );
1605                 PHY_LCCalibrate_8188E(&pHalData->odmpriv );
1606
1607                 goto exit;
1608         }
1609
1610
1611 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
1612         status = _InitPowerOn_8188EU(Adapter);
1613         if(status == _FAIL){
1614                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init power on!\n"));
1615                 goto exit;
1616         }
1617
1618         // Set RF type for BB/RF configuration
1619         _InitRFType(Adapter);//->_ReadRFType()
1620
1621         // Save target channel
1622         // <Roger_Notes> Current Channel will be updated again later.
1623         pHalData->CurrentChannel = 6;//default set to 6
1624         if(pwrctrlpriv->reg_rfoff == _TRUE){
1625                 pwrctrlpriv->rf_pwrstate = rf_off;
1626         }
1627
1628         // 2010/08/09 MH We need to check if we need to turnon or off RF after detecting
1629         // HW GPIO pin. Before PHY_RFConfig8192C.
1630         //HalDetectPwrDownMode(Adapter);
1631         // 2010/08/26 MH If Efuse does not support sective suspend then disable the function.
1632         //HalDetectSelectiveSuspendMode(Adapter);
1633
1634         if (!pregistrypriv->wifi_spec) {
1635                 txpktbuf_bndy = TX_PAGE_BOUNDARY_88E;
1636         } else {
1637                 // for WMM
1638                 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_88E;
1639         }
1640
1641 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01);
1642         _InitQueueReservedPage(Adapter);
1643         _InitQueuePriority(Adapter);
1644         _InitPageBoundary(Adapter);
1645         _InitTransferPageSize(Adapter);
1646
1647 #ifdef CONFIG_IOL_IOREG_CFG
1648         _InitTxBufferBoundary(Adapter, 0);
1649 #endif
1650
1651
1652
1653 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
1654 #if (MP_DRIVER == 1)
1655         if (Adapter->registrypriv.mp_mode == 1)
1656         {
1657                 _InitRxSetting(Adapter);
1658         }
1659 #endif  //MP_DRIVER == 1
1660         {
1661         #if 0
1662                 Adapter->bFWReady = _FALSE; //because no fw for test chip
1663                 pHalData->fw_ractrl = _FALSE;
1664         #else
1665
1666
1667                 status = rtl8188e_FirmwareDownload(Adapter, _FALSE);
1668
1669                 if (status != _SUCCESS) {
1670                         DBG_871X("%s: Download Firmware failed!!\n", __FUNCTION__);
1671                         Adapter->bFWReady = _FALSE;
1672                         pHalData->fw_ractrl = _FALSE;
1673                         return status;
1674                 } else {
1675                         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter8192CSdio(): Download Firmware Success!!\n"));
1676                         Adapter->bFWReady = _TRUE;
1677                         pHalData->fw_ractrl = _FALSE;
1678                 }
1679         #endif
1680         }
1681
1682
1683         rtl8188e_InitializeFirmwareVars(Adapter);
1684
1685
1686 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC);
1687 #if (HAL_MAC_ENABLE == 1)
1688         status = PHY_MACConfig8188E(Adapter);
1689         if(status == _FAIL)
1690         {
1691                 DBG_871X(" ### Failed to init MAC ...... \n ");
1692                 goto exit;
1693         }
1694 #endif
1695
1696         //
1697         //d. Initialize BB related configurations.
1698         //
1699 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB);
1700 #if (HAL_BB_ENABLE == 1)
1701         status = PHY_BBConfig8188E(Adapter);
1702         if(status == _FAIL)
1703         {
1704                 DBG_871X(" ### Failed to init BB ...... \n ");
1705                 goto exit;
1706         }
1707 #endif
1708
1709
1710 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF);
1711 #if (HAL_RF_ENABLE == 1)
1712         status = PHY_RFConfig8188E(Adapter);
1713         if(status == _FAIL)
1714         {
1715                 DBG_871X(" ### Failed to init RF ...... \n ");
1716                 goto exit;
1717         }
1718 #endif
1719
1720 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_EFUSE_PATCH);
1721 #if defined(CONFIG_IOL_EFUSE_PATCH)
1722         status = rtl8188e_iol_efuse_patch(Adapter);
1723         if(status == _FAIL){
1724                 DBG_871X("%s  rtl8188e_iol_efuse_patch failed \n",__FUNCTION__);
1725                 goto exit;
1726         }
1727 #endif
1728
1729         _InitTxBufferBoundary(Adapter, txpktbuf_bndy);
1730
1731 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT);
1732         status =  InitLLTTable(Adapter, txpktbuf_bndy);
1733         if(status == _FAIL){
1734                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init LLT table\n"));
1735                 goto exit;
1736         }
1737
1738 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
1739         // Get Rx PHY status in order to report RSSI and others.
1740         _InitDriverInfoSize(Adapter, DRVINFO_SZ);
1741
1742         _InitInterrupt(Adapter);
1743         hal_init_macaddr(Adapter);//set mac_address
1744         _InitNetworkType(Adapter);//set msr
1745         _InitWMACSetting(Adapter);
1746         _InitAdaptiveCtrl(Adapter);
1747         _InitEDCA(Adapter);
1748         //_InitRateFallback(Adapter);//just follow MP Team ???Georgia
1749         _InitRetryFunction(Adapter);
1750         InitUsbAggregationSetting(Adapter);
1751         _InitOperationMode(Adapter);//todo
1752         _InitBeaconParameters(Adapter);
1753         _InitBeaconMaxError(Adapter, _TRUE);
1754
1755         //
1756         // Init CR MACTXEN, MACRXEN after setting RxFF boundary REG_TRXFF_BNDY to patch
1757         // Hw bug which Hw initials RxFF boundry size to a value which is larger than the real Rx buffer size in 88E.
1758         //
1759         // Enable MACTXEN/MACRXEN block
1760         value16 = rtw_read16(Adapter, REG_CR);
1761         value16 |= (MACTXEN | MACRXEN);
1762         rtw_write8(Adapter, REG_CR, value16);
1763
1764         _InitHardwareDropIncorrectBulkOut(Adapter);
1765
1766
1767         if(pHalData->bRDGEnable){
1768                 _InitRDGSetting(Adapter);
1769         }
1770
1771 #if (RATE_ADAPTIVE_SUPPORT==1)
1772         {//Enable TX Report
1773                 //Enable Tx Report Timer
1774                 value8 = rtw_read8(Adapter, REG_TX_RPT_CTRL);
1775                 rtw_write8(Adapter,  REG_TX_RPT_CTRL, (value8|BIT1|BIT0));
1776                 //Set MAX RPT MACID
1777                 rtw_write8(Adapter,  REG_TX_RPT_CTRL+1, 2);//FOR sta mode ,0: bc/mc ,1:AP
1778                 //Tx RPT Timer. Unit: 32us
1779                 rtw_write16(Adapter, REG_TX_RPT_TIME, 0xCdf0);
1780         }
1781 #endif
1782
1783 #if 0
1784         if(pHTInfo->bRDGEnable){
1785                 _InitRDGSetting_8188E(Adapter);
1786         }
1787 #endif
1788
1789 #ifdef CONFIG_TX_EARLY_MODE
1790         if( pHalData->bEarlyModeEnable)
1791         {
1792                 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,("EarlyMode Enabled!!!\n"));
1793
1794                 value8 = rtw_read8(Adapter, REG_EARLY_MODE_CONTROL);
1795 #if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1
1796                 value8 = value8|0x1f;
1797 #else
1798                 value8 = value8|0xf;
1799 #endif
1800                 rtw_write8(Adapter, REG_EARLY_MODE_CONTROL, value8);
1801
1802                 rtw_write8(Adapter, REG_EARLY_MODE_CONTROL+3, 0x80);
1803
1804                 value8 = rtw_read8(Adapter, REG_TCR+1);
1805                 value8 = value8|0x40;
1806                 rtw_write8(Adapter,REG_TCR+1, value8);
1807         }
1808         else
1809 #endif
1810         {
1811                 rtw_write8(Adapter, REG_EARLY_MODE_CONTROL, 0);
1812         }
1813
1814         rtw_write32(Adapter,REG_MACID_NO_LINK_0,0xFFFFFFFF);
1815         rtw_write32(Adapter,REG_MACID_NO_LINK_1,0xFFFFFFFF);
1816
1817 #if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_TX_MCAST2UNI)
1818
1819 #ifdef CONFIG_CHECK_AC_LIFETIME
1820         // Enable lifetime check for the four ACs
1821         rtw_write8(Adapter, REG_LIFETIME_CTRL, 0x0F);
1822 #endif  // CONFIG_CHECK_AC_LIFETIME
1823
1824 #ifdef CONFIG_TX_MCAST2UNI
1825         rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400);  // unit: 256us. 256ms
1826         rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400);  // unit: 256us. 256ms
1827 #else   // CONFIG_TX_MCAST2UNI
1828         rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x3000);  // unit: 256us. 3s
1829         rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x3000);  // unit: 256us. 3s
1830 #endif  // CONFIG_TX_MCAST2UNI
1831 #endif  // CONFIG_CONCURRENT_MODE || CONFIG_TX_MCAST2UNI
1832
1833
1834 #ifdef CONFIG_LED
1835         _InitHWLed(Adapter);
1836 #endif //CONFIG_LED
1837
1838
1839         //
1840         // Joseph Note: Keep RfRegChnlVal for later use.
1841         //
1842         pHalData->RfRegChnlVal[0] = PHY_QueryRFReg(Adapter, 0, RF_CHNLBW, bRFRegOffsetMask);
1843         pHalData->RfRegChnlVal[1] = PHY_QueryRFReg(Adapter, 1, RF_CHNLBW, bRFRegOffsetMask);
1844
1845 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK);
1846         _BBTurnOnBlock(Adapter);
1847         //NicIFSetMacAddress(padapter, padapter->PermanentAddress);
1848
1849 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY);
1850         invalidate_cam_all(Adapter);
1851
1852 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11);
1853         // 2010/12/17 MH We need to set TX power according to EFUSE content at first.
1854         PHY_SetTxPowerLevel8188E(Adapter, pHalData->CurrentChannel);
1855
1856 // Move by Neo for USB SS to below setp
1857 //_RfPowerSave(Adapter);
1858
1859         _InitAntenna_Selection(Adapter);
1860
1861         //
1862         // Disable BAR, suggested by Scott
1863         // 2010.04.09 add by hpfan
1864         //
1865         rtw_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff);
1866
1867         // HW SEQ CTRL
1868         //set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM.
1869         rtw_write8(Adapter,REG_HWSEQ_CTRL, 0xFF);
1870
1871         if(pregistrypriv->wifi_spec)
1872                 rtw_write16(Adapter,REG_FAST_EDCA_CTRL ,0);
1873
1874         //Nav limit , suggest by scott
1875         rtw_write8(Adapter, 0x652, 0x0);
1876
1877 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
1878         rtl8188e_InitHalDm(Adapter);
1879
1880 #if (MP_DRIVER == 1)
1881         if (Adapter->registrypriv.mp_mode == 1)
1882         {
1883                 Adapter->mppriv.channel = pHalData->CurrentChannel;
1884                 MPT_InitializeAdapter(Adapter, Adapter->mppriv.channel);
1885         }
1886         else
1887 #endif  //#if (MP_DRIVER == 1)
1888         {
1889         //
1890         // 2010/08/11 MH Merge from 8192SE for Minicard init. We need to confirm current radio status
1891         // and then decide to enable RF or not.!!!??? For Selective suspend mode. We may not
1892         // call init_adapter. May cause some problem??
1893         //
1894         // Fix the bug that Hw/Sw radio off before S3/S4, the RF off action will not be executed
1895         // in MgntActSet_RF_State() after wake up, because the value of pHalData->eRFPowerState
1896         // is the same as eRfOff, we should change it to eRfOn after we config RF parameters.
1897         // Added by tynli. 2010.03.30.
1898         pwrctrlpriv->rf_pwrstate = rf_on;
1899
1900 #if 0  //to do
1901         RT_CLEAR_PS_LEVEL(pwrctrlpriv, RT_RF_OFF_LEVL_HALT_NIC);
1902 #if 1 //Todo
1903         // 20100326 Joseph: Copy from GPIOChangeRFWorkItemCallBack() function to check HW radio on/off.
1904         // 20100329 Joseph: Revise and integrate the HW/SW radio off code in initialization.
1905
1906         eRfPowerStateToSet = (rt_rf_power_state) RfOnOffDetect(Adapter);
1907         pwrctrlpriv->rfoff_reason |= eRfPowerStateToSet==rf_on ? RF_CHANGE_BY_INIT : RF_CHANGE_BY_HW;
1908         pwrctrlpriv->rfoff_reason |= (pwrctrlpriv->reg_rfoff) ? RF_CHANGE_BY_SW : 0;
1909
1910         if(pwrctrlpriv->rfoff_reason&RF_CHANGE_BY_HW)
1911                 pwrctrlpriv->b_hw_radio_off = _TRUE;
1912
1913         DBG_8192C("eRfPowerStateToSet=%d\n", eRfPowerStateToSet);
1914
1915         if(pwrctrlpriv->reg_rfoff == _TRUE)
1916         {       // User disable RF via registry.
1917                 DBG_8192C("InitializeAdapter8192CU(): Turn off RF for RegRfOff.\n");
1918                 //MgntActSet_RF_State(Adapter, rf_off, RF_CHANGE_BY_SW, _TRUE);
1919
1920                 // Those action will be discard in MgntActSet_RF_State because off the same state
1921                 //for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
1922                         //PHY_SetRFReg(Adapter, eRFPath, 0x4, 0xC00, 0x0);
1923         }
1924         else if(pwrctrlpriv->rfoff_reason > RF_CHANGE_BY_PS)
1925         {       // H/W or S/W RF OFF before sleep.
1926                 DBG_8192C(" Turn off RF for RfOffReason(%x) ----------\n", pwrctrlpriv->rfoff_reason);
1927                 //pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT;
1928                 pwrctrlpriv->rf_pwrstate = rf_on;
1929                 //MgntActSet_RF_State(Adapter, rf_off, pwrctrlpriv->rfoff_reason, _TRUE);
1930         }
1931         else
1932         {
1933                 // Perform GPIO polling to find out current RF state. added by Roger, 2010.04.09.
1934                 if(pHalData->BoardType == BOARD_MINICARD /*&& (Adapter->MgntInfo.PowerSaveControl.bGpioRfSw)*/)
1935                 {
1936                         DBG_8192C("InitializeAdapter8192CU(): RF=%d \n", eRfPowerStateToSet);
1937                         if (eRfPowerStateToSet == rf_off)
1938                         {
1939                                 //MgntActSet_RF_State(Adapter, rf_off, RF_CHANGE_BY_HW, _TRUE);
1940                                 pwrctrlpriv->b_hw_radio_off = _TRUE;
1941                         }
1942                         else
1943                         {
1944                                 pwrctrlpriv->rf_pwrstate = rf_off;
1945                                 pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT;
1946                                 pwrctrlpriv->b_hw_radio_off = _FALSE;
1947                                 //MgntActSet_RF_State(Adapter, rf_on, pwrctrlpriv->rfoff_reason, _TRUE);
1948                         }
1949                 }
1950                 else
1951                 {
1952                         pwrctrlpriv->rf_pwrstate = rf_off;
1953                         pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT;
1954                         //MgntActSet_RF_State(Adapter, rf_on, pwrctrlpriv->rfoff_reason, _TRUE);
1955                 }
1956
1957                 pwrctrlpriv->rfoff_reason = 0;
1958                 pwrctrlpriv->b_hw_radio_off = _FALSE;
1959                 pwrctrlpriv->rf_pwrstate = rf_on;
1960                 rtw_led_control(Adapter, LED_CTL_POWER_ON);
1961
1962         }
1963
1964         // 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c.
1965         // Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1.
1966         if(pHalData->pwrdown && eRfPowerStateToSet == rf_off)
1967         {
1968                 // Enable register area 0x0-0xc.
1969                 rtw_write8(Adapter, REG_RSV_CTRL, 0x0);
1970
1971                 //
1972                 // <Roger_Notes> We should configure HW PDn source for WiFi ONLY, and then
1973                 // our HW will be set in power-down mode if PDn source from all  functions are configured.
1974                 // 2010.10.06.
1975                 //
1976                 //if(IS_HARDWARE_TYPE_8723AU(Adapter))
1977                 //{
1978                 //      u1bTmp = rtw_read8(Adapter, REG_MULTI_FUNC_CTRL);
1979                 //      rtw_write8(Adapter, REG_MULTI_FUNC_CTRL, (u1bTmp|WL_HWPDN_EN));
1980                 //}
1981                 //else
1982                 //{
1983                         rtw_write16(Adapter, REG_APS_FSMCO, 0x8812);
1984                 //}
1985         }
1986         //DrvIFIndicateCurrentPhyStatus(Adapter); // 2010/08/17 MH Disable to prevent BSOD.
1987 #endif
1988 #endif
1989
1990
1991         // enable Tx report.
1992         rtw_write8(Adapter,  REG_FWHW_TXQ_CTRL+1, 0x0F);
1993
1994         // Suggested by SD1 pisa. Added by tynli. 2011.10.21.
1995         rtw_write8(Adapter, REG_EARLY_MODE_CONTROL+3, 0x01);//Pretx_en, for WEP/TKIP SEC
1996
1997         //tynli_test_tx_report.
1998         rtw_write16(Adapter, REG_TX_RPT_TIME, 0x3DF0);
1999         //RT_TRACE(COMP_INIT, DBG_TRACE, ("InitializeAdapter8188EUsb() <====\n"));
2000
2001         //enable tx DMA to drop the redundate data of packet
2002         rtw_write16(Adapter,REG_TXDMA_OFFSET_CHK, (rtw_read16(Adapter,REG_TXDMA_OFFSET_CHK) | DROP_DATA_EN));
2003
2004 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK);
2005         // 2010/08/26 MH Merge from 8192CE.
2006         if(pwrctrlpriv->rf_pwrstate == rf_on)
2007         {
2008                 if(pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized){
2009                         PHY_IQCalibrate_8188E(Adapter,_TRUE);
2010                 }
2011                 else
2012                 {
2013                         PHY_IQCalibrate_8188E(Adapter,_FALSE);
2014                         pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = _TRUE;
2015                 }
2016
2017 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK);
2018
2019                 ODM_TXPowerTrackingCheck(&pHalData->odmpriv );
2020
2021
2022 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK);
2023                 PHY_LCCalibrate_8188E(&pHalData->odmpriv );
2024         }
2025 }
2026
2027 //HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS);
2028 //      _InitPABias(Adapter);
2029         rtw_write8(Adapter, REG_USB_HRPWM, 0);
2030
2031 #ifdef CONFIG_XMIT_ACK
2032         //ack for xmit mgmt frames.
2033         rtw_write32(Adapter, REG_FWHW_TXQ_CTRL, rtw_read32(Adapter, REG_FWHW_TXQ_CTRL)|BIT(12));
2034 #endif //CONFIG_XMIT_ACK
2035
2036 exit:
2037 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END);
2038
2039         DBG_871X("%s in %dms\n", __FUNCTION__, rtw_get_passing_time_ms(init_start_time));
2040
2041         #ifdef DBG_HAL_INIT_PROFILING
2042         hal_init_stages_timestamp[HAL_INIT_STAGES_END]=rtw_get_current_time();
2043
2044         for(hal_init_profiling_i=0;hal_init_profiling_i<HAL_INIT_STAGES_NUM-1;hal_init_profiling_i++) {
2045                 DBG_871X("DBG_HAL_INIT_PROFILING: %35s, %u, %5u, %5u\n"
2046                         , hal_init_stages_str[hal_init_profiling_i]
2047                         , hal_init_stages_timestamp[hal_init_profiling_i]
2048                         , (hal_init_stages_timestamp[hal_init_profiling_i+1]-hal_init_stages_timestamp[hal_init_profiling_i])
2049                         , rtw_get_time_interval_ms(hal_init_stages_timestamp[hal_init_profiling_i], hal_init_stages_timestamp[hal_init_profiling_i+1])
2050                 );
2051         }
2052         #endif
2053
2054
2055 _func_exit_;
2056
2057         return status;
2058 }
2059
2060 void _ps_open_RF(_adapter *padapter) {
2061         //here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified
2062         //phy_SsPwrSwitch92CU(padapter, rf_on, 1);
2063 }
2064
2065 void _ps_close_RF(_adapter *padapter){
2066         //here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified
2067         //phy_SsPwrSwitch92CU(padapter, rf_off, 1);
2068 }
2069
2070
2071 VOID
2072 hal_poweroff_8188eu(
2073         IN      PADAPTER                        Adapter
2074 )
2075 {
2076
2077         u8      val8;
2078         u16     val16;
2079         u32     val32;
2080         u8 bMacPwrCtrlOn = _FALSE;
2081
2082         rtw_hal_get_hwreg(Adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
2083         if(bMacPwrCtrlOn == _FALSE)
2084                 return ;
2085
2086         RT_TRACE(COMP_INIT, DBG_LOUD, ("%s\n",__FUNCTION__));
2087
2088         //Stop Tx Report Timer. 0x4EC[Bit1]=b'0
2089         val8 = rtw_read8(Adapter, REG_TX_RPT_CTRL);
2090         rtw_write8(Adapter, REG_TX_RPT_CTRL, val8&(~BIT1));
2091
2092         // stop rx
2093         rtw_write8(Adapter, REG_CR, 0x0);
2094
2095         // Run LPS WL RFOFF flow
2096         HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_LPS_ENTER_FLOW);
2097
2098
2099         // 2. 0x1F[7:0] = 0             // turn off RF
2100         //rtw_write8(Adapter, REG_RF_CTRL, 0x00);
2101
2102         val8 = rtw_read8(Adapter, REG_MCUFWDL);
2103         if ((val8 & RAM_DL_SEL) && Adapter->bFWReady) //8051 RAM code
2104         {
2105                 //rtl8723a_FirmwareSelfReset(padapter);
2106                 //_8051Reset88E(padapter);
2107
2108                 // Reset MCU 0x2[10]=0.
2109                 val8 = rtw_read8(Adapter, REG_SYS_FUNC_EN+1);
2110                 val8 &= ~BIT(2);        // 0x2[10], FEN_CPUEN
2111                 rtw_write8(Adapter, REG_SYS_FUNC_EN+1, val8);
2112         }
2113
2114         //val8 = rtw_read8(Adapter, REG_SYS_FUNC_EN+1);
2115         //val8 &= ~BIT(2);      // 0x2[10], FEN_CPUEN
2116         //rtw_write8(Adapter, REG_SYS_FUNC_EN+1, val8);
2117
2118         // MCUFWDL 0x80[1:0]=0
2119         // reset MCU ready status
2120         rtw_write8(Adapter, REG_MCUFWDL, 0);
2121
2122         //YJ,add,111212
2123         //Disable 32k
2124         val8 = rtw_read8(Adapter, REG_32K_CTRL);
2125         rtw_write8(Adapter, REG_32K_CTRL, val8&(~BIT0));
2126
2127         // Card disable power action flow
2128         HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_DISABLE_FLOW);
2129
2130         // Reset MCU IO Wrapper
2131         val8 = rtw_read8(Adapter, REG_RSV_CTRL+1);
2132         rtw_write8(Adapter, REG_RSV_CTRL+1, (val8&(~BIT3)));
2133         val8 = rtw_read8(Adapter, REG_RSV_CTRL+1);
2134         rtw_write8(Adapter, REG_RSV_CTRL+1, val8|BIT3);
2135
2136 #if 0
2137         // 7. RSV_CTRL 0x1C[7:0] = 0x0E                 // lock ISO/CLK/Power control register
2138         rtw_write8(Adapter, REG_RSV_CTRL, 0x0e);
2139 #endif
2140 #if 1
2141         //YJ,test add, 111207. For Power Consumption.
2142         val8 = rtw_read8(Adapter, GPIO_IN);
2143         rtw_write8(Adapter, GPIO_OUT, val8);
2144         rtw_write8(Adapter, GPIO_IO_SEL, 0xFF);//Reg0x46
2145
2146         val8 = rtw_read8(Adapter, REG_GPIO_IO_SEL);
2147         //rtw_write8(Adapter, REG_GPIO_IO_SEL, (val8<<4)|val8);
2148         rtw_write8(Adapter, REG_GPIO_IO_SEL, (val8<<4));
2149         val8 = rtw_read8(Adapter, REG_GPIO_IO_SEL+1);
2150         rtw_write8(Adapter, REG_GPIO_IO_SEL+1, val8|0x0F);//Reg0x43
2151         rtw_write32(Adapter, REG_BB_PAD_CTRL, 0x00080808);//set LNA ,TRSW,EX_PA Pin to output mode
2152 #endif
2153
2154         Adapter->bFWReady = _FALSE;
2155
2156         bMacPwrCtrlOn = _FALSE;
2157         rtw_hal_set_hwreg(Adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
2158 }
2159 static void rtl8192cu_hw_power_down(_adapter *padapter)
2160 {
2161         // 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c.
2162         // Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1.
2163
2164         // Enable register area 0x0-0xc.
2165         rtw_write8(padapter,REG_RSV_CTRL, 0x0);
2166         rtw_write16(padapter, REG_APS_FSMCO, 0x8812);
2167 }
2168
2169 u32 rtl8188eu_hal_deinit(PADAPTER Adapter)
2170  {
2171         struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(Adapter);
2172         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2173         DBG_8192C("==> %s \n",__FUNCTION__);
2174
2175 #ifdef CONFIG_SUPPORT_USB_INT
2176         rtw_write32(Adapter, REG_HIMR_88E, IMR_DISABLED_88E);
2177         rtw_write32(Adapter, REG_HIMRE_88E, IMR_DISABLED_88E);
2178 #endif
2179
2180  #ifdef SUPPORT_HW_RFOFF_DETECTED
2181         DBG_8192C("bkeepfwalive(%x)\n", pwrctl->bkeepfwalive);
2182         if(pwrctl->bkeepfwalive)
2183         {
2184                 _ps_close_RF(Adapter);
2185                 if((pwrctl->bHWPwrPindetect) && (pwrctl->bHWPowerdown))
2186                         rtl8192cu_hw_power_down(Adapter);
2187         }
2188         else
2189 #endif
2190         {
2191                 if(Adapter->hw_init_completed == _TRUE){
2192                         hal_poweroff_8188eu(Adapter);
2193
2194                         if((pwrctl->bHWPwrPindetect ) && (pwrctl->bHWPowerdown))
2195                                 rtl8192cu_hw_power_down(Adapter);
2196
2197                 }
2198         }
2199         return _SUCCESS;
2200  }
2201
2202
2203 unsigned int rtl8188eu_inirp_init(PADAPTER Adapter)
2204 {
2205         u8 i;
2206         struct recv_buf *precvbuf;
2207         uint    status;
2208         struct dvobj_priv *pdev= adapter_to_dvobj(Adapter);
2209         struct intf_hdl * pintfhdl=&Adapter->iopriv.intf;
2210         struct recv_priv *precvpriv = &(Adapter->recvpriv);
2211         u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
2212 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
2213         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2214         u32 (*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr);
2215 #endif
2216
2217 _func_enter_;
2218
2219         _read_port = pintfhdl->io_ops._read_port;
2220
2221         status = _SUCCESS;
2222
2223         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("===> usb_inirp_init \n"));
2224
2225         precvpriv->ff_hwaddr = RECV_BULK_IN_ADDR;
2226
2227         //issue Rx irp to receive data
2228         precvbuf = (struct recv_buf *)precvpriv->precv_buf;
2229         for(i=0; i<NR_RECVBUFF; i++)
2230         {
2231                 if(_read_port(pintfhdl, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf) == _FALSE )
2232                 {
2233                         RT_TRACE(_module_hci_hal_init_c_,_drv_err_,("usb_rx_init: usb_read_port error \n"));
2234                         status = _FAIL;
2235                         goto exit;
2236                 }
2237
2238                 precvbuf++;
2239                 precvpriv->free_recv_buf_queue_cnt--;
2240         }
2241
2242 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
2243         if(pHalData->RtIntInPipe != 0x05)
2244         {
2245                 status = _FAIL;
2246                 DBG_871X("%s =>Warning !! Have not USB Int-IN pipe,  pHalData->RtIntInPipe(%d)!!!\n",__FUNCTION__,pHalData->RtIntInPipe);
2247                 goto exit;
2248         }
2249         _read_interrupt = pintfhdl->io_ops._read_interrupt;
2250         if(_read_interrupt(pintfhdl, RECV_INT_IN_ADDR) == _FALSE )
2251         {
2252                 RT_TRACE(_module_hci_hal_init_c_,_drv_err_,("usb_rx_init: usb_read_interrupt error \n"));
2253                 status = _FAIL;
2254         }
2255 #endif
2256
2257 exit:
2258
2259         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("<=== usb_inirp_init \n"));
2260
2261 _func_exit_;
2262
2263         return status;
2264
2265 }
2266
2267 unsigned int rtl8188eu_inirp_deinit(PADAPTER Adapter)
2268 {
2269         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("\n ===> usb_rx_deinit \n"));
2270
2271         rtw_read_port_cancel(Adapter);
2272
2273         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("\n <=== usb_rx_deinit \n"));
2274
2275         return _SUCCESS;
2276 }
2277
2278
2279
2280 //-------------------------------------------------------------------------
2281 //
2282 //      EEPROM Power index mapping
2283 //
2284 //-------------------------------------------------------------------------
2285
2286
2287 //-------------------------------------------------------------------
2288 //
2289 //      EEPROM/EFUSE Content Parsing
2290 //
2291 //-------------------------------------------------------------------
2292 static VOID
2293 _ReadBoardType(
2294         IN      PADAPTER        Adapter,
2295         IN      u8*             PROMContent,
2296         IN      BOOLEAN         AutoloadFail
2297         )
2298 {
2299
2300 }
2301
2302
2303 static VOID
2304 _ReadLEDSetting(
2305         IN      PADAPTER        Adapter,
2306         IN      u8*             PROMContent,
2307         IN      BOOLEAN         AutoloadFail
2308         )
2309 {
2310         struct led_priv *pledpriv = &(Adapter->ledpriv);
2311         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2312         EEPROM_EFUSE_PRIV       *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
2313 #ifdef CONFIG_SW_LED
2314         pledpriv->bRegUseLed = _TRUE;
2315
2316         switch(pEEPROM->CustomerID)
2317         {
2318                 default:
2319                         pledpriv->LedStrategy = SW_LED_MODE1;
2320                         break;
2321         }
2322         pHalData->bLedOpenDrain = _TRUE;// Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16.
2323 #else // HW LED
2324         pledpriv->LedStrategy = HW_LED;
2325 #endif //CONFIG_SW_LED
2326 }
2327
2328 static VOID
2329 _ReadRFSetting(
2330         IN      PADAPTER        Adapter,
2331         IN      u8*     PROMContent,
2332         IN      BOOLEAN         AutoloadFail
2333         )
2334 {
2335 }
2336
2337 static VOID
2338 hal_InitPGData(
2339         IN      PADAPTER        pAdapter,
2340         IN      OUT     u8              *PROMContent
2341         )
2342 {
2343 #if 0
2344         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter);
2345         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
2346         u32     i;
2347         u16     value16;
2348
2349         if(_FALSE == pEEPROM->bautoload_fail_flag)
2350         { // autoload OK.
2351                 if (_TRUE == pEEPROM->EepromOrEfuse)
2352                 {
2353                         // Read all Content from EEPROM or EFUSE.
2354                         for(i = 0; i < HWSET_MAX_SIZE_88E; i += 2)
2355                         {
2356                                 //value16 = EF2Byte(ReadEEprom(pAdapter, (u2Byte) (i>>1)));
2357                                 //*((u16 *)(&PROMContent[i])) = value16;
2358                         }
2359                 }
2360                 else
2361                 {
2362                         // Read EFUSE real map to shadow.
2363                         EFUSE_ShadowMapUpdate(pAdapter, EFUSE_WIFI, _FALSE);
2364                         _rtw_memcpy((void*)PROMContent, (void*)pEEPROM->efuse_eeprom_data, HWSET_MAX_SIZE_88E);
2365                 }
2366         }
2367         else
2368         {//autoload fail
2369                 //RT_TRACE(COMP_INIT, DBG_LOUD, ("AutoLoad Fail reported from CR9346!!\n"));
2370                 pEEPROM->bautoload_fail_flag = _TRUE;
2371                 //update to default value 0xFF
2372                 if (_FALSE == pEEPROM->EepromOrEfuse)
2373                 EFUSE_ShadowMapUpdate(pAdapter, EFUSE_WIFI, _FALSE);
2374         }
2375 #endif
2376 }
2377 static void
2378 Hal_EfuseParsePIDVID_8188EU(
2379         IN      PADAPTER                pAdapter,
2380         IN      u8*                             hwinfo,
2381         IN      BOOLEAN                 AutoLoadFail
2382         )
2383 {
2384
2385         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
2386
2387         if( !AutoLoadFail )
2388         {
2389                 // VID, PID
2390                 pHalData->EEPROMVID = EF2Byte( *(u16 *)&hwinfo[EEPROM_VID_88EU] );
2391                 pHalData->EEPROMPID = EF2Byte( *(u16 *)&hwinfo[EEPROM_PID_88EU] );
2392
2393                 // Customer ID, 0x00 and 0xff are reserved for Realtek.
2394                 pHalData->EEPROMCustomerID = *(u8 *)&hwinfo[EEPROM_CustomID_88E];
2395                 pHalData->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID;
2396
2397         }
2398         else
2399         {
2400                 pHalData->EEPROMVID                     = EEPROM_Default_VID;
2401                 pHalData->EEPROMPID                     = EEPROM_Default_PID;
2402
2403                 // Customer ID, 0x00 and 0xff are reserved for Realtek.
2404                 pHalData->EEPROMCustomerID              = EEPROM_Default_CustomerID;
2405                 pHalData->EEPROMSubCustomerID   = EEPROM_Default_SubCustomerID;
2406
2407         }
2408
2409         DBG_871X("VID = 0x%04X, PID = 0x%04X\n", pHalData->EEPROMVID, pHalData->EEPROMPID);
2410         DBG_871X("Customer ID: 0x%02X, SubCustomer ID: 0x%02X\n", pHalData->EEPROMCustomerID, pHalData->EEPROMSubCustomerID);
2411 }
2412
2413 static void
2414 Hal_EfuseParseMACAddr_8188EU(
2415         IN      PADAPTER                padapter,
2416         IN      u8*                     hwinfo,
2417         IN      BOOLEAN                 AutoLoadFail
2418         )
2419 {
2420         u16                     i, usValue;
2421         u8                      sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x88, 0x02};
2422         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
2423
2424         if (AutoLoadFail)
2425         {
2426 //              sMacAddr[5] = (u1Byte)GetRandomNumber(1, 254);
2427                 for (i=0; i<6; i++)
2428                         pEEPROM->mac_addr[i] = sMacAddr[i];
2429         }
2430         else
2431         {
2432                 //Read Permanent MAC address
2433                 _rtw_memcpy(pEEPROM->mac_addr, &hwinfo[EEPROM_MAC_ADDR_88EU], ETH_ALEN);
2434
2435         }
2436 //      NicIFSetMacAddress(pAdapter, pAdapter->PermanentAddress);
2437
2438         RT_TRACE(_module_hci_hal_init_c_, _drv_notice_,
2439                  ("Hal_EfuseParseMACAddr_8188ES: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
2440                   pEEPROM->mac_addr[0], pEEPROM->mac_addr[1],
2441                   pEEPROM->mac_addr[2], pEEPROM->mac_addr[3],
2442                   pEEPROM->mac_addr[4], pEEPROM->mac_addr[5]));
2443 }
2444
2445
2446 static void
2447 Hal_CustomizeByCustomerID_8188EU(
2448         IN      PADAPTER                padapter
2449         )
2450 {
2451 #if 0
2452         EEPROM_EFUSE_PRIV       *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
2453         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);
2454
2455         // For customized behavior.
2456         if((pHalData->EEPROMVID == 0x103C) && (pHalData->EEPROMVID == 0x1629))// HP Lite-On for RTL8188CUS Slim Combo.
2457                 pEEPROM->CustomerID = RT_CID_819x_HP;
2458
2459         // Decide CustomerID according to VID/DID or EEPROM
2460         switch(pHalData->EEPROMCustomerID)
2461         {
2462                 case EEPROM_CID_DEFAULT:
2463                         if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3308))
2464                                 pEEPROM->CustomerID = RT_CID_DLINK;
2465                         else if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3309))
2466                                 pEEPROM->CustomerID = RT_CID_DLINK;
2467                         else if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x330a))
2468                                 pEEPROM->CustomerID = RT_CID_DLINK;
2469                         break;
2470                 case EEPROM_CID_WHQL:
2471                         padapter->bInHctTest = TRUE;
2472
2473                         pMgntInfo->bSupportTurboMode = FALSE;
2474                         pMgntInfo->bAutoTurboBy8186 = FALSE;
2475
2476                         pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
2477                         pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
2478                         pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
2479                         pMgntInfo->PowerSaveControl.bLeisurePsModeBackup =FALSE;
2480                         pMgntInfo->keepAliveLevel = 0;
2481
2482                         padapter->bUnloadDriverwhenS3S4 = FALSE;
2483                         break;
2484                 default:
2485                         pEEPROM->CustomerID = RT_CID_DEFAULT;
2486                         break;
2487
2488         }
2489
2490         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Mgnt Customer ID: 0x%02x\n", pEEPROM->CustomerID));
2491
2492         hal_CustomizedBehavior_8723U(padapter);
2493 #endif
2494 }
2495
2496 #ifdef CONFIG_EFUSE_CONFIG_FILE
2497 static u32 Hal_readPGDataFromConfigFile(
2498         PADAPTER        padapter)
2499 {
2500         u32 i;
2501         struct file *fp;
2502         mm_segment_t fs;
2503         u8 temp[3];
2504         loff_t pos = 0;
2505         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
2506         u8      *PROMContent = pEEPROM->efuse_eeprom_data;
2507
2508
2509         temp[2] = 0; // add end of string '\0'
2510
2511         fp = filp_open("/system/etc/wifi/wifi_efuse.map", O_RDWR,  0644);
2512         if (IS_ERR(fp)) {
2513                 pEEPROM->bloadfile_fail_flag = _TRUE;
2514                 DBG_871X("Error, Efuse configure file doesn't exist.\n");
2515                 return _FAIL;
2516         }
2517
2518         fs = get_fs();
2519         set_fs(KERNEL_DS);
2520
2521         DBG_871X("Efuse configure file:\n");
2522         for (i=0; i<HWSET_MAX_SIZE_88E; i++) {
2523                 vfs_read(fp, temp, 2, &pos);
2524                 PROMContent[i] = simple_strtoul(temp, NULL, 16 );
2525                 pos += 1; // Filter the space character
2526                 DBG_871X("%02X \n", PROMContent[i]);
2527         }
2528         DBG_871X("\n");
2529         set_fs(fs);
2530
2531         filp_close(fp, NULL);
2532
2533         pEEPROM->bloadfile_fail_flag = _FALSE;
2534
2535         return _SUCCESS;
2536 }
2537
2538 static void
2539 Hal_ReadMACAddrFromFile_8188EU(
2540         PADAPTER                padapter
2541         )
2542 {
2543         u32 i;
2544         struct file *fp;
2545         mm_segment_t fs;
2546         u8 source_addr[18];
2547         loff_t pos = 0;
2548         u32 curtime = rtw_get_current_time();
2549         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
2550         u8 *head, *end;
2551
2552         u8 null_mac_addr[ETH_ALEN] = {0, 0, 0,0, 0, 0};
2553         u8 multi_mac_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
2554
2555         _rtw_memset(source_addr, 0, 18);
2556         _rtw_memset(pEEPROM->mac_addr, 0, ETH_ALEN);
2557
2558         fp = filp_open("/data/wifimac.txt", O_RDWR,  0644);
2559         if (IS_ERR(fp)) {
2560                 pEEPROM->bloadmac_fail_flag = _TRUE;
2561                 DBG_871X("Error, wifi mac address file doesn't exist.\n");
2562         } else {
2563                 fs = get_fs();
2564                 set_fs(KERNEL_DS);
2565
2566                 DBG_871X("wifi mac address:\n");
2567                 vfs_read(fp, source_addr, 18, &pos);
2568                 source_addr[17] = ':';
2569
2570                 head = end = source_addr;
2571                 for (i=0; i<ETH_ALEN; i++) {
2572                         while (end && (*end != ':') )
2573                                 end++;
2574
2575                         if (end && (*end == ':') )
2576                                 *end = '\0';
2577
2578                         pEEPROM->mac_addr[i] = simple_strtoul(head, NULL, 16 );
2579
2580                         if (end) {
2581                                 end++;
2582                                 head = end;
2583                         }
2584                         DBG_871X("%02x \n", pEEPROM->mac_addr[i]);
2585                 }
2586                 DBG_871X("\n");
2587                 set_fs(fs);
2588                 pEEPROM->bloadmac_fail_flag = _FALSE;
2589                 filp_close(fp, NULL);
2590         }
2591
2592         if ( (_rtw_memcmp(pEEPROM->mac_addr, null_mac_addr, ETH_ALEN)) ||
2593                 (_rtw_memcmp(pEEPROM->mac_addr, multi_mac_addr, ETH_ALEN)) ) {
2594                 pEEPROM->mac_addr[0] = 0x00;
2595                 pEEPROM->mac_addr[1] = 0xe0;
2596                 pEEPROM->mac_addr[2] = 0x4c;
2597                 pEEPROM->mac_addr[3] = (u8)(curtime & 0xff) ;
2598                 pEEPROM->mac_addr[4] = (u8)((curtime>>8) & 0xff) ;
2599                 pEEPROM->mac_addr[5] = (u8)((curtime>>16) & 0xff) ;
2600         }
2601
2602         DBG_871X("Hal_ReadMACAddrFromFile_8188ES: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
2603                   pEEPROM->mac_addr[0], pEEPROM->mac_addr[1],
2604                   pEEPROM->mac_addr[2], pEEPROM->mac_addr[3],
2605                   pEEPROM->mac_addr[4], pEEPROM->mac_addr[5]);
2606 }
2607 #endif //CONFIG_EFUSE_CONFIG_FILE
2608
2609
2610 static VOID
2611 readAdapterInfo_8188EU(
2612         IN      PADAPTER        padapter
2613         )
2614 {
2615 #if 1
2616         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
2617
2618         /* parse the eeprom/efuse content */
2619         Hal_EfuseParseIDCode88E(padapter, pEEPROM->efuse_eeprom_data);
2620         Hal_EfuseParsePIDVID_8188EU(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
2621 #ifdef CONFIG_EFUSE_CONFIG_FILE
2622         Hal_ReadMACAddrFromFile_8188EU(padapter);
2623 #else //CONFIG_EFUSE_CONFIG_FILE
2624         Hal_EfuseParseMACAddr_8188EU(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
2625 #endif //CONFIG_EFUSE_CONFIG_FILE
2626
2627         Hal_ReadPowerSavingMode88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
2628         Hal_ReadTxPowerInfo88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
2629         Hal_EfuseParseEEPROMVer88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
2630         rtl8188e_EfuseParseChnlPlan(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
2631         Hal_EfuseParseXtal_8188E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
2632         Hal_EfuseParseCustomerID88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
2633         Hal_ReadAntennaDiversity88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
2634         Hal_EfuseParseBoardType88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
2635         Hal_ReadThermalMeter_88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
2636
2637         //
2638         // The following part initialize some vars by PG info.
2639         //
2640         Hal_InitChannelPlan(padapter);
2641 #if defined(CONFIG_WOWLAN) && defined(CONFIG_SDIO_HCI)
2642         Hal_DetectWoWMode(padapter);
2643 #endif //CONFIG_WOWLAN && CONFIG_SDIO_HCI
2644         Hal_CustomizeByCustomerID_8188EU(padapter);
2645
2646         _ReadLEDSetting(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
2647
2648 #else
2649
2650 #ifdef CONFIG_INTEL_PROXIM
2651                 /* for intel proximity */
2652         if (pHalData->rf_type== RF_1T1R) {
2653                 Adapter->proximity.proxim_support = _TRUE;
2654         } else if (pHalData->rf_type== RF_2T2R) {
2655                 if ((pHalData->EEPROMPID == 0x8186) &&
2656                         (pHalData->EEPROMVID== 0x0bda))
2657                 Adapter->proximity.proxim_support = _TRUE;
2658         } else {
2659                 Adapter->proximity.proxim_support = _FALSE;
2660         }
2661 #endif //CONFIG_INTEL_PROXIM
2662 #endif
2663 }
2664
2665 static void _ReadPROMContent(
2666         IN PADAPTER             Adapter
2667         )
2668 {
2669         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
2670         u8                      eeValue;
2671
2672         /* check system boot selection */
2673         eeValue = rtw_read8(Adapter, REG_9346CR);
2674         pEEPROM->EepromOrEfuse          = (eeValue & BOOT_FROM_EEPROM) ? _TRUE : _FALSE;
2675         pEEPROM->bautoload_fail_flag    = (eeValue & EEPROM_EN) ? _FALSE : _TRUE;
2676
2677
2678         DBG_8192C("Boot from %s, Autoload %s !\n", (pEEPROM->EepromOrEfuse ? "EEPROM" : "EFUSE"),
2679                                 (pEEPROM->bautoload_fail_flag ? "Fail" : "OK") );
2680
2681         //pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE;
2682 #ifdef CONFIG_EFUSE_CONFIG_FILE
2683         Hal_readPGDataFromConfigFile(Adapter);
2684 #else //CONFIG_EFUSE_CONFIG_FILE
2685         Hal_InitPGData88E(Adapter);
2686 #endif  //CONFIG_EFUSE_CONFIG_FILE
2687         readAdapterInfo_8188EU(Adapter);
2688 }
2689
2690
2691
2692 static VOID
2693 _ReadRFType(
2694         IN      PADAPTER        Adapter
2695         )
2696 {
2697         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2698
2699 #if DISABLE_BB_RF
2700         pHalData->rf_chip = RF_PSEUDO_11N;
2701 #else
2702         pHalData->rf_chip = RF_6052;
2703 #endif
2704 }
2705
2706 static int _ReadAdapterInfo8188EU(PADAPTER      Adapter)
2707 {
2708         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2709         u32 start=rtw_get_current_time();
2710
2711         MSG_8192C("====> %s\n", __FUNCTION__);
2712
2713         //Efuse_InitSomeVar(Adapter);
2714
2715         //if(IS_HARDWARE_TYPE_8723A(Adapter))
2716         //      _EfuseCellSel(Adapter);
2717
2718         _ReadRFType(Adapter);//rf_chip -> _InitRFType()
2719         _ReadPROMContent(Adapter);
2720
2721         //MSG_8192C("%s()(done), rf_chip=0x%x, rf_type=0x%x\n",  __FUNCTION__, pHalData->rf_chip, pHalData->rf_type);
2722
2723         MSG_8192C("<==== %s in %d ms\n", __FUNCTION__, rtw_get_passing_time_ms(start));
2724
2725         return _SUCCESS;
2726 }
2727
2728
2729 static void ReadAdapterInfo8188EU(PADAPTER Adapter)
2730 {
2731         // Read EEPROM size before call any EEPROM function
2732         Adapter->EepromAddressSize = GetEEPROMSize8188E(Adapter);
2733
2734         _ReadAdapterInfo8188EU(Adapter);
2735 }
2736
2737
2738 #define GPIO_DEBUG_PORT_NUM 0
2739 static void rtl8192cu_trigger_gpio_0(_adapter *padapter)
2740 {
2741 #ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ
2742         u32 gpioctrl;
2743         DBG_8192C("==> trigger_gpio_0...\n");
2744         rtw_write16_async(padapter,REG_GPIO_PIN_CTRL,0);
2745         rtw_write8_async(padapter,REG_GPIO_PIN_CTRL+2,0xFF);
2746         gpioctrl = (BIT(GPIO_DEBUG_PORT_NUM)<<24 )|(BIT(GPIO_DEBUG_PORT_NUM)<<16);
2747         rtw_write32_async(padapter,REG_GPIO_PIN_CTRL,gpioctrl);
2748         gpioctrl |= (BIT(GPIO_DEBUG_PORT_NUM)<<8);
2749         rtw_write32_async(padapter,REG_GPIO_PIN_CTRL,gpioctrl);
2750         DBG_8192C("<=== trigger_gpio_0...\n");
2751 #endif
2752 }
2753
2754 static void ResumeTxBeacon(_adapter *padapter)
2755 {
2756         HAL_DATA_TYPE*  pHalData = GET_HAL_DATA(padapter);
2757
2758         // 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value
2759         // which should be read from register to a global variable.
2760
2761         rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl) | BIT6);
2762         pHalData->RegFwHwTxQCtrl |= BIT6;
2763         rtw_write8(padapter, REG_TBTT_PROHIBIT+1, 0xff);
2764         pHalData->RegReg542 |= BIT0;
2765         rtw_write8(padapter, REG_TBTT_PROHIBIT+2, pHalData->RegReg542);
2766 }
2767 void UpdateInterruptMask8188EU(PADAPTER padapter,u8 bHIMR0 ,u32 AddMSR, u32 RemoveMSR)
2768 {
2769         HAL_DATA_TYPE *pHalData;
2770
2771         u32 *himr;
2772         pHalData = GET_HAL_DATA(padapter);
2773
2774         if(bHIMR0)
2775                 himr = &(pHalData->IntrMask[0]);
2776         else
2777                 himr = &(pHalData->IntrMask[1]);
2778
2779         if (AddMSR)
2780                 *himr |= AddMSR;
2781
2782         if (RemoveMSR)
2783                 *himr &= (~RemoveMSR);
2784
2785         if(bHIMR0)
2786                 rtw_write32(padapter, REG_HIMR_88E, *himr);
2787         else
2788                 rtw_write32(padapter, REG_HIMRE_88E, *himr);
2789
2790 }
2791
2792 static void StopTxBeacon(_adapter *padapter)
2793 {
2794         HAL_DATA_TYPE*  pHalData = GET_HAL_DATA(padapter);
2795
2796         // 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value
2797         // which should be read from register to a global variable.
2798
2799         rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl) & (~BIT6));
2800         pHalData->RegFwHwTxQCtrl &= (~BIT6);
2801         rtw_write8(padapter, REG_TBTT_PROHIBIT+1, 0x64);
2802         pHalData->RegReg542 &= ~(BIT0);
2803         rtw_write8(padapter, REG_TBTT_PROHIBIT+2, pHalData->RegReg542);
2804
2805          //todo: CheckFwRsvdPageContent(Adapter);  // 2010.06.23. Added by tynli.
2806
2807 }
2808
2809
2810 static void hw_var_set_opmode(PADAPTER Adapter, u8 variable, u8* val)
2811 {
2812         u8      val8;
2813         u8      mode = *((u8 *)val);
2814         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2815
2816 #ifdef CONFIG_CONCURRENT_MODE
2817         if(Adapter->iface_type == IFACE_PORT1)
2818         {
2819                 // disable Port1 TSF update
2820                 rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(4));
2821
2822                 // set net_type
2823                 val8 = rtw_read8(Adapter, MSR)&0x03;
2824                 val8 |= (mode<<2);
2825                 rtw_write8(Adapter, MSR, val8);
2826
2827                 DBG_871X("%s()-%d mode = %d\n", __FUNCTION__, __LINE__, mode);
2828
2829                 if((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_))
2830                 {
2831                         if(!check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE))
2832                         {
2833                                 #ifdef CONFIG_INTERRUPT_BASED_TXBCN
2834
2835                                 #ifdef  CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
2836                                 rtw_write8(Adapter, REG_DRVERLYINT, 0x05);//restore early int time to 5ms
2837                                 UpdateInterruptMask8188EU(Adapter,_TRUE, 0, IMR_BCNDMAINT0_88E);
2838                                 #endif // CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
2839
2840                                 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
2841                                 UpdateInterruptMask8188EU(Adapter,_TRUE ,0, (IMR_TBDER_88E|IMR_TBDOK_88E));
2842                                 #endif// CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
2843
2844                                 #endif //CONFIG_INTERRUPT_BASED_TXBCN
2845
2846
2847                                 StopTxBeacon(Adapter);
2848                         }
2849
2850                         rtw_write8(Adapter,REG_BCN_CTRL_1, 0x11);//disable atim wnd and disable beacon function
2851                         //rtw_write8(Adapter,REG_BCN_CTRL_1, 0x18);
2852                 }
2853                 else if((mode == _HW_STATE_ADHOC_) /*|| (mode == _HW_STATE_AP_)*/)
2854                 {
2855                         ResumeTxBeacon(Adapter);
2856                         rtw_write8(Adapter,REG_BCN_CTRL_1, 0x1a);
2857                         //BIT4 - If set 0, hw will clr bcnq when tx becon ok/fail or port 1
2858                         rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM)|BIT(3)|BIT(4));
2859                 }
2860                 else if(mode == _HW_STATE_AP_)
2861                 {
2862 #ifdef CONFIG_INTERRUPT_BASED_TXBCN
2863                         #ifdef  CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
2864                         UpdateInterruptMask8188EU(Adapter,_TRUE ,IMR_BCNDMAINT0_88E, 0);
2865                         #endif//CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
2866
2867                         #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
2868                         UpdateInterruptMask8188EU(Adapter,_TRUE ,(IMR_TBDER_88E|IMR_TBDOK_88E), 0);
2869                         #endif//CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
2870
2871 #endif //CONFIG_INTERRUPT_BASED_TXBCN
2872
2873                         ResumeTxBeacon(Adapter);
2874
2875                         rtw_write8(Adapter, REG_BCN_CTRL_1, 0x12);
2876
2877                         //Set RCR
2878                         //rtw_write32(padapter, REG_RCR, 0x70002a8e);//CBSSID_DATA must set to 0
2879                         //rtw_write32(Adapter, REG_RCR, 0x7000228e);//CBSSID_DATA must set to 0
2880                         rtw_write32(Adapter, REG_RCR, 0x7000208e);//CBSSID_DATA must set to 0,reject ICV_ERR packet
2881                         //enable to rx data frame
2882                         rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
2883                         //enable to rx ps-poll
2884                         rtw_write16(Adapter, REG_RXFLTMAP1, 0x0400);
2885
2886                         //Beacon Control related register for first time
2887                         rtw_write8(Adapter, REG_BCNDMATIM, 0x02); // 2ms
2888
2889                         //rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF);
2890                         rtw_write8(Adapter, REG_ATIMWND_1, 0x0a); // 10ms for port1
2891                         rtw_write16(Adapter, REG_BCNTCFG, 0x00);
2892                         rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0xff04);
2893                         rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);// +32767 (~32ms)
2894
2895                         //reset TSF2
2896                         rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1));
2897
2898
2899                         //BIT4 - If set 0, hw will clr bcnq when tx becon ok/fail or port 1
2900                         rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM)|BIT(3)|BIT(4));
2901                         //enable BCN1 Function for if2
2902                         //don't enable update TSF1 for if2 (due to TSF update when beacon/probe rsp are received)
2903                         rtw_write8(Adapter, REG_BCN_CTRL_1, (DIS_TSF_UDT0_NORMAL_CHIP|EN_BCN_FUNCTION | EN_TXBCN_RPT|BIT(1)));
2904
2905 #ifdef CONFIG_CONCURRENT_MODE
2906                         if(check_buddy_fwstate(Adapter, WIFI_FW_NULL_STATE))
2907                                 rtw_write8(Adapter, REG_BCN_CTRL,
2908                                         rtw_read8(Adapter, REG_BCN_CTRL) & ~EN_BCN_FUNCTION);
2909 #endif
2910                         //BCN1 TSF will sync to BCN0 TSF with offset(0x518) if if1_sta linked
2911                         //rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(5));
2912                         //rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(3));
2913
2914                         //dis BCN0 ATIM  WND if if1 is station
2915                         rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(0));
2916
2917 #ifdef CONFIG_TSF_RESET_OFFLOAD
2918                         // Reset TSF for STA+AP concurrent mode
2919                         if ( check_buddy_fwstate(Adapter, (WIFI_STATION_STATE|WIFI_ASOC_STATE)) ) {
2920                                 if (reset_tsf(Adapter, IFACE_PORT1) == _FALSE)
2921                                         DBG_871X("ERROR! %s()-%d: Reset port1 TSF fail\n",
2922                                                 __FUNCTION__, __LINE__);
2923                         }
2924 #endif  // CONFIG_TSF_RESET_OFFLOAD
2925                 }
2926         }
2927         else
2928 #endif //CONFIG_CONCURRENT_MODE
2929         {
2930                 // disable Port0 TSF update
2931                 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
2932
2933                 // set net_type
2934                 val8 = rtw_read8(Adapter, MSR)&0x0c;
2935                 val8 |= mode;
2936                 rtw_write8(Adapter, MSR, val8);
2937
2938                 DBG_871X("%s()-%d mode = %d\n", __FUNCTION__, __LINE__, mode);
2939
2940                 if((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_))
2941                 {
2942 #ifdef CONFIG_CONCURRENT_MODE
2943                         if(!check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE))
2944 #endif //CONFIG_CONCURRENT_MODE
2945                         {
2946                         #ifdef CONFIG_INTERRUPT_BASED_TXBCN
2947                                 #ifdef  CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
2948                                 rtw_write8(Adapter, REG_DRVERLYINT, 0x05);//restore early int time to 5ms
2949                                 UpdateInterruptMask8188EU(Adapter,_TRUE, 0, IMR_BCNDMAINT0_88E);
2950                                 #endif//CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
2951
2952                                 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
2953                                 UpdateInterruptMask8188EU(Adapter,_TRUE ,0, (IMR_TBDER_88E|IMR_TBDOK_88E));
2954                                 #endif //CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
2955
2956                         #endif //CONFIG_INTERRUPT_BASED_TXBCN
2957                                 StopTxBeacon(Adapter);
2958                         }
2959
2960                         rtw_write8(Adapter,REG_BCN_CTRL, 0x19);//disable atim wnd
2961                         //rtw_write8(Adapter,REG_BCN_CTRL, 0x18);
2962                 }
2963                 else if((mode == _HW_STATE_ADHOC_) /*|| (mode == _HW_STATE_AP_)*/)
2964                 {
2965                         ResumeTxBeacon(Adapter);
2966                         rtw_write8(Adapter,REG_BCN_CTRL, 0x1a);
2967                         //BIT3 - If set 0, hw will clr bcnq when tx becon ok/fail or port 0
2968                         rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM)|BIT(3)|BIT(4));
2969                 }
2970                 else if(mode == _HW_STATE_AP_)
2971                 {
2972
2973 #ifdef CONFIG_INTERRUPT_BASED_TXBCN
2974                         #ifdef  CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
2975                         UpdateInterruptMask8188EU(Adapter,_TRUE ,IMR_BCNDMAINT0_88E, 0);
2976                         #endif//CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
2977
2978                         #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
2979                         UpdateInterruptMask8188EU(Adapter,_TRUE ,(IMR_TBDER_88E|IMR_TBDOK_88E), 0);
2980                         #endif//CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
2981
2982 #endif //CONFIG_INTERRUPT_BASED_TXBCN
2983
2984
2985                         ResumeTxBeacon(Adapter);
2986
2987                         rtw_write8(Adapter, REG_BCN_CTRL, 0x12);
2988
2989                         //Set RCR
2990                         //rtw_write32(padapter, REG_RCR, 0x70002a8e);//CBSSID_DATA must set to 0
2991                         //rtw_write32(Adapter, REG_RCR, 0x7000228e);//CBSSID_DATA must set to 0
2992                         rtw_write32(Adapter, REG_RCR, 0x7000208e);//CBSSID_DATA must set to 0,reject ICV_ERR packet
2993                         //enable to rx data frame
2994                         rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
2995                         //enable to rx ps-poll
2996                         rtw_write16(Adapter, REG_RXFLTMAP1, 0x0400);
2997
2998                         //Beacon Control related register for first time
2999                         rtw_write8(Adapter, REG_BCNDMATIM, 0x02); // 2ms
3000
3001                         //rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF);
3002                         rtw_write8(Adapter, REG_ATIMWND, 0x0a); // 10ms
3003                         rtw_write16(Adapter, REG_BCNTCFG, 0x00);
3004                         rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0xff04);
3005                         rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);// +32767 (~32ms)
3006
3007                         //reset TSF
3008                         rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(0));
3009
3010                         //BIT3 - If set 0, hw will clr bcnq when tx becon ok/fail or port 0
3011                         rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM)|BIT(3)|BIT(4));
3012
3013                         //enable BCN0 Function for if1
3014                         //don't enable update TSF0 for if1 (due to TSF update when beacon/probe rsp are received)
3015                         #if defined(CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR)
3016                         rtw_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT0_NORMAL_CHIP|EN_BCN_FUNCTION | EN_TXBCN_RPT|BIT(1)));
3017                         #else
3018                         rtw_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT0_NORMAL_CHIP|EN_BCN_FUNCTION |BIT(1)));
3019                         #endif
3020
3021 #ifdef CONFIG_CONCURRENT_MODE
3022                         if(check_buddy_fwstate(Adapter, WIFI_FW_NULL_STATE))
3023                                 rtw_write8(Adapter, REG_BCN_CTRL_1,
3024                                         rtw_read8(Adapter, REG_BCN_CTRL_1) & ~EN_BCN_FUNCTION);
3025 #endif
3026
3027                         //dis BCN1 ATIM  WND if if2 is station
3028                         rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(0));
3029 #ifdef CONFIG_TSF_RESET_OFFLOAD
3030                         // Reset TSF for STA+AP concurrent mode
3031                         if ( check_buddy_fwstate(Adapter, (WIFI_STATION_STATE|WIFI_ASOC_STATE)) ) {
3032                                 if (reset_tsf(Adapter, IFACE_PORT0) == _FALSE)
3033                                         DBG_871X("ERROR! %s()-%d: Reset port0 TSF fail\n",
3034                                                 __FUNCTION__, __LINE__);
3035                         }
3036 #endif  // CONFIG_TSF_RESET_OFFLOAD
3037                 }
3038         }
3039
3040 }
3041
3042 static void hw_var_set_macaddr(PADAPTER Adapter, u8 variable, u8* val)
3043 {
3044         u8 idx = 0;
3045         u32 reg_macid;
3046
3047 #ifdef CONFIG_CONCURRENT_MODE
3048         if(Adapter->iface_type == IFACE_PORT1)
3049         {
3050                 reg_macid = REG_MACID1;
3051         }
3052         else
3053 #endif
3054         {
3055                 reg_macid = REG_MACID;
3056         }
3057
3058         for(idx = 0 ; idx < 6; idx++)
3059         {
3060                 rtw_write8(Adapter, (reg_macid+idx), val[idx]);
3061         }
3062
3063 }
3064
3065 static void hw_var_set_bssid(PADAPTER Adapter, u8 variable, u8* val)
3066 {
3067         u8      idx = 0;
3068         u32 reg_bssid;
3069
3070 #ifdef CONFIG_CONCURRENT_MODE
3071         if(Adapter->iface_type == IFACE_PORT1)
3072         {
3073                 reg_bssid = REG_BSSID1;
3074         }
3075         else
3076 #endif
3077         {
3078                 reg_bssid = REG_BSSID;
3079         }
3080
3081         for(idx = 0 ; idx < 6; idx++)
3082         {
3083                 rtw_write8(Adapter, (reg_bssid+idx), val[idx]);
3084         }
3085
3086 }
3087
3088 static void hw_var_set_bcn_func(PADAPTER Adapter, u8 variable, u8* val)
3089 {
3090         u32 bcn_ctrl_reg;
3091
3092 #ifdef CONFIG_CONCURRENT_MODE
3093         if(Adapter->iface_type == IFACE_PORT1)
3094         {
3095                 bcn_ctrl_reg = REG_BCN_CTRL_1;
3096         }
3097         else
3098 #endif
3099         {
3100                 bcn_ctrl_reg = REG_BCN_CTRL;
3101         }
3102
3103         if(*((u8 *)val))
3104         {
3105                 rtw_write8(Adapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT));
3106         }
3107         else
3108         {
3109                 rtw_write8(Adapter, bcn_ctrl_reg, rtw_read8(Adapter, bcn_ctrl_reg)&(~(EN_BCN_FUNCTION | EN_TXBCN_RPT)));
3110         }
3111
3112
3113 }
3114
3115 static void hw_var_set_correct_tsf(PADAPTER Adapter, u8 variable, u8* val)
3116 {
3117 #ifdef CONFIG_CONCURRENT_MODE
3118         u64     tsf;
3119         struct mlme_ext_priv    *pmlmeext = &Adapter->mlmeextpriv;
3120         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
3121         PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter;
3122
3123         //tsf = pmlmeext->TSFValue - ((u32)pmlmeext->TSFValue % (pmlmeinfo->bcn_interval*1024)) -1024; //us
3124         tsf = pmlmeext->TSFValue - rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024)) -1024; //us
3125
3126         if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
3127         {
3128                 //pHalData->RegTxPause |= STOP_BCNQ;BIT(6)
3129                 //rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)|BIT(6)));
3130                 StopTxBeacon(Adapter);
3131         }
3132
3133         if(Adapter->iface_type == IFACE_PORT1)
3134         {
3135                 //disable related TSF function
3136                 rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(3)));
3137
3138                 rtw_write32(Adapter, REG_TSFTR1, tsf);
3139                 rtw_write32(Adapter, REG_TSFTR1+4, tsf>>32);
3140
3141
3142                 //enable related TSF function
3143                 rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(3));
3144
3145                 // Update buddy port's TSF if it is SoftAP for beacon TX issue!
3146                 if ( (pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE
3147                         && check_buddy_fwstate(Adapter, WIFI_AP_STATE)
3148                 ) {
3149                         //disable related TSF function
3150                         rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(3)));
3151
3152                         rtw_write32(Adapter, REG_TSFTR, tsf);
3153                         rtw_write32(Adapter, REG_TSFTR+4, tsf>>32);
3154
3155                         //enable related TSF function
3156                         rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(3));
3157 #ifdef CONFIG_TSF_RESET_OFFLOAD
3158                 // Update buddy port's TSF(TBTT) if it is SoftAP for beacon TX issue!
3159                         if (reset_tsf(Adapter, IFACE_PORT0) == _FALSE)
3160                                 DBG_871X("ERROR! %s()-%d: Reset port0 TSF fail\n",
3161                                         __FUNCTION__, __LINE__);
3162
3163 #endif  // CONFIG_TSF_RESET_OFFLOAD
3164                 }
3165
3166
3167         }
3168         else
3169         {
3170                 //disable related TSF function
3171                 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(3)));
3172
3173                 rtw_write32(Adapter, REG_TSFTR, tsf);
3174                 rtw_write32(Adapter, REG_TSFTR+4, tsf>>32);
3175
3176                 //enable related TSF function
3177                 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(3));
3178
3179                 // Update buddy port's TSF if it is SoftAP for beacon TX issue!
3180                 if ( (pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE
3181                         && check_buddy_fwstate(Adapter, WIFI_AP_STATE)
3182                 ) {
3183                         //disable related TSF function
3184                         rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(3)));
3185
3186                         rtw_write32(Adapter, REG_TSFTR1, tsf);
3187                         rtw_write32(Adapter, REG_TSFTR1+4, tsf>>32);
3188
3189                         //enable related TSF function
3190                         rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(3));
3191 #ifdef CONFIG_TSF_RESET_OFFLOAD
3192                 // Update buddy port's TSF if it is SoftAP for beacon TX issue!
3193                         if (reset_tsf(Adapter, IFACE_PORT1) == _FALSE)
3194                                 DBG_871X("ERROR! %s()-%d: Reset port1 TSF fail\n",
3195                                         __FUNCTION__, __LINE__);
3196 #endif  // CONFIG_TSF_RESET_OFFLOAD
3197                 }
3198
3199         }
3200
3201
3202         if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
3203         {
3204                 //pHalData->RegTxPause  &= (~STOP_BCNQ);
3205                 //rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)&(~BIT(6))));
3206                 ResumeTxBeacon(Adapter);
3207         }
3208 #endif
3209 }
3210
3211 static void hw_var_set_mlme_disconnect(PADAPTER Adapter, u8 variable, u8* val)
3212 {
3213 #ifdef CONFIG_CONCURRENT_MODE
3214         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
3215         PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter;
3216
3217
3218         if(check_buddy_mlmeinfo_state(Adapter, _HW_STATE_NOLINK_))
3219                 rtw_write16(Adapter, REG_RXFLTMAP2, 0x00);
3220
3221
3222         if(Adapter->iface_type == IFACE_PORT1)
3223         {
3224                 //reset TSF1
3225                 rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1));
3226
3227                 //disable update TSF1
3228                 rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(4));
3229
3230                 // disable Port1's beacon function
3231                 rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(3)));
3232         }
3233         else
3234         {
3235                 //reset TSF
3236                 rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(0));
3237
3238                 //disable update TSF
3239                 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
3240         }
3241 #endif
3242 }
3243
3244 static void hw_var_set_mlme_sitesurvey(PADAPTER Adapter, u8 variable, u8* val)
3245 {
3246 #ifdef CONFIG_CONCURRENT_MODE
3247         struct mlme_priv *pmlmepriv=&(Adapter->mlmepriv);
3248         struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
3249         struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
3250         u32     value_rcr, rcr_clear_bit, value_rxfltmap2;
3251
3252 #ifdef CONFIG_FIND_BEST_CHANNEL
3253         rcr_clear_bit = (RCR_CBSSID_BCN | RCR_CBSSID_DATA);
3254         // Recieve all data frames
3255          value_rxfltmap2 = 0xFFFF;
3256 #else /* CONFIG_FIND_BEST_CHANNEL */
3257         rcr_clear_bit = RCR_CBSSID_BCN;
3258         //config RCR to receive different BSSID & not to receive data frame
3259         value_rxfltmap2 = 0;
3260 #endif /* CONFIG_FIND_BEST_CHANNEL */
3261
3262         if( (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
3263                 #ifdef CONFIG_CONCURRENT_MODE
3264                 || (check_buddy_fwstate(Adapter, WIFI_AP_STATE) == _TRUE)
3265                 #endif
3266         ){
3267                 rcr_clear_bit = RCR_CBSSID_BCN;
3268         }
3269 #ifdef CONFIG_TDLS
3270         // TDLS will clear RCR_CBSSID_DATA bit for connection.
3271         else if (Adapter->tdlsinfo.link_established == _TRUE)
3272         {
3273                 rcr_clear_bit = RCR_CBSSID_BCN;
3274         }
3275 #endif // CONFIG_TDLS
3276
3277         value_rcr = rtw_read32(Adapter, REG_RCR);
3278         if(*((u8 *)val))//under sitesurvey
3279         {
3280                 value_rcr &= ~(rcr_clear_bit);
3281                 rtw_write32(Adapter, REG_RCR, value_rcr);
3282                 rtw_write16(Adapter, REG_RXFLTMAP2, value_rxfltmap2);
3283
3284                 //disable update TSF
3285                 if((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE)
3286                 {
3287                         if(Adapter->iface_type == IFACE_PORT1)
3288                         {
3289                                 rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(4));
3290                         }
3291                         else
3292                         {
3293                                 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
3294                         }
3295                 }
3296
3297                 if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) &&
3298                         check_buddy_fwstate(Adapter, _FW_LINKED))
3299                 {
3300                         StopTxBeacon(Adapter);
3301                 }
3302         }
3303         else//sitesurvey done
3304         {
3305                 //enable to rx data frame
3306                 //write32(Adapter, REG_RCR, read32(padapter, REG_RCR)|RCR_ADF);
3307                 if(check_fwstate(pmlmepriv, (_FW_LINKED|WIFI_AP_STATE))
3308                         || check_buddy_fwstate(Adapter, (_FW_LINKED|WIFI_AP_STATE)))
3309                         rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF);
3310
3311                 //enable update TSF
3312                 if(Adapter->iface_type == IFACE_PORT1)
3313                         rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(4)));
3314                 else
3315                         rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
3316
3317                 value_rcr |= rcr_clear_bit;
3318                 rtw_write32(Adapter, REG_RCR, value_rcr);
3319
3320                 if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) &&
3321                         check_buddy_fwstate(Adapter, _FW_LINKED))
3322                 {
3323                         ResumeTxBeacon(Adapter);
3324                 }
3325         }
3326 #endif
3327 }
3328
3329 static void hw_var_set_mlme_join(PADAPTER Adapter, u8 variable, u8* val)
3330 {
3331 #ifdef CONFIG_CONCURRENT_MODE
3332         u8      RetryLimit = 0x30;
3333         u8      type = *((u8 *)val);
3334         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
3335         struct mlme_priv        *pmlmepriv = &Adapter->mlmepriv;
3336         EEPROM_EFUSE_PRIV       *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
3337
3338         if(type == 0) // prepare to join
3339         {
3340                 if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) &&
3341                         check_buddy_fwstate(Adapter, _FW_LINKED))
3342                 {
3343                         StopTxBeacon(Adapter);
3344                 }
3345
3346                 //enable to rx data frame.Accept all data frame
3347                 //rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF);
3348                 rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF);
3349
3350                 if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE))
3351                         rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN);
3352                 else
3353                         rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
3354
3355                 if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
3356                 {
3357                         RetryLimit = (pEEPROM->CustomerID == RT_CID_CCX) ? 7 : 48;
3358                 }
3359                 else // Ad-hoc Mode
3360                 {
3361                         RetryLimit = 0x7;
3362                 }
3363         }
3364         else if(type == 1) //joinbss_event call back when join res < 0
3365         {
3366                 if(check_buddy_mlmeinfo_state(Adapter, _HW_STATE_NOLINK_))
3367                         rtw_write16(Adapter, REG_RXFLTMAP2,0x00);
3368
3369                 if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) &&
3370                         check_buddy_fwstate(Adapter, _FW_LINKED))
3371                 {
3372                         ResumeTxBeacon(Adapter);
3373
3374                         //reset TSF 1/2 after ResumeTxBeacon
3375                         rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1)|BIT(0));
3376
3377                 }
3378         }
3379         else if(type == 2) //sta add event call back
3380         {
3381
3382                 //enable update TSF
3383                 if(Adapter->iface_type == IFACE_PORT1)
3384                         rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(4)));
3385                 else
3386                         rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
3387
3388
3389                 if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE))
3390                 {
3391                         //fixed beacon issue for 8191su...........
3392                         rtw_write8(Adapter,0x542 ,0x02);
3393                         RetryLimit = 0x7;
3394                 }
3395
3396
3397                 if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) &&
3398                         check_buddy_fwstate(Adapter, _FW_LINKED))
3399                 {
3400                         ResumeTxBeacon(Adapter);
3401
3402                         //reset TSF 1/2 after ResumeTxBeacon
3403                         rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1)|BIT(0));
3404                 }
3405
3406         }
3407
3408         rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT);
3409
3410 #endif
3411 }
3412
3413 void SetHwReg8188EU(PADAPTER Adapter, u8 variable, u8* val)
3414 {
3415         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3416         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
3417         DM_ODM_T                *podmpriv = &pHalData->odmpriv;
3418 _func_enter_;
3419
3420         switch(variable)
3421         {
3422                 case HW_VAR_MEDIA_STATUS:
3423                         {
3424                                 u8 val8;
3425
3426                                 val8 = rtw_read8(Adapter, MSR)&0x0c;
3427                                 val8 |= *((u8 *)val);
3428                                 rtw_write8(Adapter, MSR, val8);
3429                         }
3430                         break;
3431                 case HW_VAR_MEDIA_STATUS1:
3432                         {
3433                                 u8 val8;
3434
3435                                 val8 = rtw_read8(Adapter, MSR)&0x03;
3436                                 val8 |= *((u8 *)val) <<2;
3437                                 rtw_write8(Adapter, MSR, val8);
3438                         }
3439                         break;
3440                 case HW_VAR_SET_OPMODE:
3441                         hw_var_set_opmode(Adapter, variable, val);
3442                         break;
3443                 case HW_VAR_MAC_ADDR:
3444                         hw_var_set_macaddr(Adapter, variable, val);
3445                         break;
3446                 case HW_VAR_BSSID:
3447                         hw_var_set_bssid(Adapter, variable, val);
3448                         break;
3449                 case HW_VAR_TXPAUSE:
3450                         rtw_write8(Adapter, REG_TXPAUSE, *((u8 *)val));
3451                         break;
3452                 case HW_VAR_BCN_FUNC:
3453                         hw_var_set_bcn_func(Adapter, variable, val);
3454                         break;
3455                 case HW_VAR_CORRECT_TSF:
3456 #ifdef CONFIG_CONCURRENT_MODE
3457                         hw_var_set_correct_tsf(Adapter, variable, val);
3458 #else
3459                         {
3460                                 u64     tsf;
3461                                 struct mlme_ext_priv    *pmlmeext = &Adapter->mlmeextpriv;
3462                                 struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
3463
3464                                 //tsf = pmlmeext->TSFValue - ((u32)pmlmeext->TSFValue % (pmlmeinfo->bcn_interval*1024)) -1024; //us
3465                                 tsf = pmlmeext->TSFValue - rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024)) -1024; //us
3466
3467                                 if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
3468                                 {
3469                                         //pHalData->RegTxPause |= STOP_BCNQ;BIT(6)
3470                                         //rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)|BIT(6)));
3471                                         StopTxBeacon(Adapter);
3472                                 }
3473
3474                                 //disable related TSF function
3475                                 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(3)));
3476
3477                                 rtw_write32(Adapter, REG_TSFTR, tsf);
3478                                 rtw_write32(Adapter, REG_TSFTR+4, tsf>>32);
3479
3480                                 //enable related TSF function
3481                                 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(3));
3482
3483
3484                                 if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
3485                                 {
3486                                         //pHalData->RegTxPause  &= (~STOP_BCNQ);
3487                                         //rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)&(~BIT(6))));
3488                                         ResumeTxBeacon(Adapter);
3489                                 }
3490                         }
3491 #endif
3492                         break;
3493                 case HW_VAR_CHECK_BSSID:
3494                         if(*((u8 *)val))
3495                         {
3496                                 rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
3497                         }
3498                         else
3499                         {
3500                                 u32     val32;
3501
3502                                 val32 = rtw_read32(Adapter, REG_RCR);
3503
3504                                 val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
3505
3506                                 rtw_write32(Adapter, REG_RCR, val32);
3507                         }
3508                         break;
3509                 case HW_VAR_MLME_DISCONNECT:
3510 #ifdef CONFIG_CONCURRENT_MODE
3511                         hw_var_set_mlme_disconnect(Adapter, variable, val);
3512 #else
3513                         {
3514                                 //Set RCR to not to receive data frame when NO LINK state
3515                                 //rtw_write32(Adapter, REG_RCR, rtw_read32(padapter, REG_RCR) & ~RCR_ADF);
3516                                 //reject all data frames
3517                                 rtw_write16(Adapter, REG_RXFLTMAP2,0x00);
3518
3519                                 //reset TSF
3520                                 rtw_write8(Adapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1)));
3521
3522                                 //disable update TSF
3523                                 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
3524                         }
3525 #endif
3526                         break;
3527                 case HW_VAR_MLME_SITESURVEY:
3528 #ifdef CONFIG_CONCURRENT_MODE
3529                         hw_var_set_mlme_sitesurvey(Adapter, variable,  val);
3530 #else
3531                         {
3532                                 u32 value_rcr, rcr_clear_bit, value_rxfltmap2;
3533 #ifdef CONFIG_FIND_BEST_CHANNEL
3534
3535                                 rcr_clear_bit = (RCR_CBSSID_BCN | RCR_CBSSID_DATA);
3536
3537                                 // Recieve all data frames
3538                                 value_rxfltmap2 = 0xFFFF;
3539
3540 #else /* CONFIG_FIND_BEST_CHANNEL */
3541
3542                                 rcr_clear_bit = RCR_CBSSID_BCN;
3543
3544                                 //config RCR to receive different BSSID & not to receive data frame
3545                                 value_rxfltmap2 = 0;
3546
3547 #endif /* CONFIG_FIND_BEST_CHANNEL */
3548
3549                                 if (check_fwstate(&Adapter->mlmepriv, WIFI_AP_STATE) == _TRUE) {
3550                                         rcr_clear_bit = RCR_CBSSID_BCN;
3551                                 }
3552         #ifdef CONFIG_TDLS
3553                                 // TDLS will clear RCR_CBSSID_DATA bit for connection.
3554                                 else if (Adapter->tdlsinfo.link_established == _TRUE) {
3555                                         rcr_clear_bit = RCR_CBSSID_BCN;
3556                                 }
3557         #endif // CONFIG_TDLS
3558
3559                                 value_rcr = rtw_read32(Adapter, REG_RCR);
3560                                 if(*((u8 *)val))//under sitesurvey
3561                                 {
3562                                         //config RCR to receive different BSSID & not to receive data frame
3563                                         value_rcr &= ~(rcr_clear_bit);
3564                                         rtw_write32(Adapter, REG_RCR, value_rcr);
3565                                         rtw_write16(Adapter, REG_RXFLTMAP2, value_rxfltmap2);
3566
3567                                         //disable update TSF
3568                                         rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
3569                                 }
3570                                 else//sitesurvey done
3571                                 {
3572                                         struct mlme_ext_priv    *pmlmeext = &Adapter->mlmeextpriv;
3573                                         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
3574
3575                                         if ((is_client_associated_to_ap(Adapter) == _TRUE) ||
3576                                                 ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) )
3577                                         {
3578                                                 //enable to rx data frame
3579                                                 //rtw_write32(Adapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF);
3580                                                 rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF);
3581
3582                                                 //enable update TSF
3583                                                 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
3584                                         }
3585                                         else if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
3586                                         {
3587                                                 //rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_ADF);
3588                                                 rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF);
3589
3590                                                 //enable update TSF
3591                                                 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
3592                                         }
3593
3594                                         value_rcr |= rcr_clear_bit;
3595                                         if(((pmlmeinfo->state&0x03) != WIFI_FW_AP_STATE) && (Adapter->in_cta_test)) {
3596                                                 u32 v = rtw_read32(Adapter, REG_RCR);
3597                                                 v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN );//| RCR_ADF
3598                                                 rtw_write32(Adapter, REG_RCR, v);
3599                                         } else {
3600                                                 rtw_write32(Adapter, REG_RCR, value_rcr);
3601                                         }
3602                                 }
3603                         }
3604 #endif
3605                         break;
3606                 case HW_VAR_MLME_JOIN:
3607 #ifdef CONFIG_CONCURRENT_MODE
3608                         hw_var_set_mlme_join(Adapter, variable,  val);
3609 #else
3610                         {
3611                                 u8      RetryLimit = 0x30;
3612                                 u8      type = *((u8 *)val);
3613                                 struct mlme_priv        *pmlmepriv = &Adapter->mlmepriv;
3614                                 EEPROM_EFUSE_PRIV       *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
3615
3616                                 if(type == 0) // prepare to join
3617                                 {
3618                                         //enable to rx data frame.Accept all data frame
3619                                         //rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF);
3620                                         rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF);
3621
3622                                         if(Adapter->in_cta_test)
3623                                         {
3624                                                 u32 v = rtw_read32(Adapter, REG_RCR);
3625                                                 v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN );//| RCR_ADF
3626                                                 rtw_write32(Adapter, REG_RCR, v);
3627                                         }
3628                                         else
3629                                         {
3630                                                 rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
3631                                         }
3632
3633                                         if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
3634                                         {
3635                                                 RetryLimit = (pEEPROM->CustomerID == RT_CID_CCX) ? 7 : 48;
3636                                         }
3637                                         else // Ad-hoc Mode
3638                                         {
3639                                                 RetryLimit = 0x7;
3640                                         }
3641                                 }
3642                                 else if(type == 1) //joinbss_event call back when join res < 0
3643                                 {
3644                                         rtw_write16(Adapter, REG_RXFLTMAP2,0x00);
3645                                 }
3646                                 else if(type == 2) //sta add event call back
3647                                 {
3648                                         //enable update TSF
3649                                         rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
3650
3651                                         if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE))
3652                                         {
3653                                                 RetryLimit = 0x7;
3654                                         }
3655                                 }
3656
3657                                 rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT);
3658                         }
3659 #endif
3660                         break;
3661                 case HW_VAR_ON_RCR_AM:
3662                         rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_AM);
3663                         DBG_871X("%s, %d, RCR= %x \n", __FUNCTION__,__LINE__, rtw_read32(Adapter, REG_RCR));
3664                         break;
3665               case HW_VAR_OFF_RCR_AM:
3666                         rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)& (~RCR_AM));
3667                         DBG_871X("%s, %d, RCR= %x \n", __FUNCTION__,__LINE__, rtw_read32(Adapter, REG_RCR));
3668                         break;
3669                 case HW_VAR_BEACON_INTERVAL:
3670                         rtw_write16(Adapter, REG_BCN_INTERVAL, *((u16 *)val));
3671 #ifdef  CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
3672                         {
3673                                 struct mlme_ext_priv    *pmlmeext = &Adapter->mlmeextpriv;
3674                                 struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
3675                                 u16 bcn_interval =      *((u16 *)val);
3676                                 if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE){
3677                                         DBG_8192C("%s==> bcn_interval:%d, eraly_int:%d \n",__FUNCTION__,bcn_interval,bcn_interval>>1);
3678                                         rtw_write8(Adapter, REG_DRVERLYINT, bcn_interval>>1);// 50ms for sdio
3679                                 }
3680                         }
3681 #endif//CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
3682
3683                         break;
3684                 case HW_VAR_SLOT_TIME:
3685                         {
3686                                 rtw_write8(Adapter, REG_SLOT, val[0]);
3687                         }
3688                         break;
3689                 case HW_VAR_ACK_PREAMBLE:
3690                         {
3691                                 u8      regTmp;
3692                                 u8      bShortPreamble = *( (PBOOLEAN)val );
3693                                 // Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily)
3694                                 regTmp = (pHalData->nCur40MhzPrimeSC)<<5;
3695                                 rtw_write8(Adapter, REG_RRSR+2, regTmp);
3696
3697                                 regTmp = rtw_read8(Adapter,REG_WMAC_TRXPTCL_CTL+2);
3698                                 if(bShortPreamble)
3699                                         regTmp |= BIT1;
3700                                 else
3701                                         regTmp &= (~BIT1);
3702                                 rtw_write8(Adapter,REG_WMAC_TRXPTCL_CTL+2,regTmp);
3703                         }
3704                         break;
3705                 case HW_VAR_CAM_EMPTY_ENTRY:
3706                         {
3707                                 u8      ucIndex = *((u8 *)val);
3708                                 u8      i;
3709                                 u32     ulCommand=0;
3710                                 u32     ulContent=0;
3711                                 u32     ulEncAlgo=CAM_AES;
3712
3713                                 for(i=0;i<CAM_CONTENT_COUNT;i++)
3714                                 {
3715                                         // filled id in CAM config 2 byte
3716                                         if( i == 0)
3717                                         {
3718                                                 ulContent |=(ucIndex & 0x03) | ((u16)(ulEncAlgo)<<2);
3719                                                 //ulContent |= CAM_VALID;
3720                                         }
3721                                         else
3722                                         {
3723                                                 ulContent = 0;
3724                                         }
3725                                         // polling bit, and No Write enable, and address
3726                                         ulCommand= CAM_CONTENT_COUNT*ucIndex+i;
3727                                         ulCommand= ulCommand | CAM_POLLINIG|CAM_WRITE;
3728                                         // write content 0 is equall to mark invalid
3729                                         rtw_write32(Adapter, WCAMI, ulContent);  //delay_ms(40);
3730                                         //RT_TRACE(COMP_SEC, DBG_LOUD, ("CAM_empty_entry(): WRITE A4: %lx \n",ulContent));
3731                                         rtw_write32(Adapter, RWCAM, ulCommand);  //delay_ms(40);
3732                                         //RT_TRACE(COMP_SEC, DBG_LOUD, ("CAM_empty_entry(): WRITE A0: %lx \n",ulCommand));
3733                                 }
3734                         }
3735                         break;
3736                 case HW_VAR_CAM_INVALID_ALL:
3737                         rtw_write32(Adapter, RWCAM, BIT(31)|BIT(30));
3738                         break;
3739                 case HW_VAR_CAM_WRITE:
3740                         {
3741                                 u32     cmd;
3742                                 u32     *cam_val = (u32 *)val;
3743                                 rtw_write32(Adapter, WCAMI, cam_val[0]);
3744
3745                                 cmd = CAM_POLLINIG | CAM_WRITE | cam_val[1];
3746                                 rtw_write32(Adapter, RWCAM, cmd);
3747                         }
3748                         break;
3749                 case HW_VAR_AC_PARAM_VO:
3750                         rtw_write32(Adapter, REG_EDCA_VO_PARAM, ((u32 *)(val))[0]);
3751                         break;
3752                 case HW_VAR_AC_PARAM_VI:
3753                         rtw_write32(Adapter, REG_EDCA_VI_PARAM, ((u32 *)(val))[0]);
3754                         break;
3755                 case HW_VAR_AC_PARAM_BE:
3756                         pHalData->AcParam_BE = ((u32 *)(val))[0];
3757                         rtw_write32(Adapter, REG_EDCA_BE_PARAM, ((u32 *)(val))[0]);
3758                         break;
3759                 case HW_VAR_AC_PARAM_BK:
3760                         rtw_write32(Adapter, REG_EDCA_BK_PARAM, ((u32 *)(val))[0]);
3761                         break;
3762                 case HW_VAR_ACM_CTRL:
3763                         {
3764                                 u8      acm_ctrl = *((u8 *)val);
3765                                 u8      AcmCtrl = rtw_read8( Adapter, REG_ACMHWCTRL);
3766
3767                                 if(acm_ctrl > 1)
3768                                         AcmCtrl = AcmCtrl | 0x1;
3769
3770                                 if(acm_ctrl & BIT(3))
3771                                         AcmCtrl |= AcmHw_VoqEn;
3772                                 else
3773                                         AcmCtrl &= (~AcmHw_VoqEn);
3774
3775                                 if(acm_ctrl & BIT(2))
3776                                         AcmCtrl |= AcmHw_ViqEn;
3777                                 else
3778                                         AcmCtrl &= (~AcmHw_ViqEn);
3779
3780                                 if(acm_ctrl & BIT(1))
3781                                         AcmCtrl |= AcmHw_BeqEn;
3782                                 else
3783                                         AcmCtrl &= (~AcmHw_BeqEn);
3784
3785                                 DBG_871X("[HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl );
3786                                 rtw_write8(Adapter, REG_ACMHWCTRL, AcmCtrl );
3787                         }
3788                         break;
3789                 case HW_VAR_AMPDU_MIN_SPACE:
3790                         {
3791                                 u8      MinSpacingToSet;
3792                                 u8      SecMinSpace;
3793
3794                                 MinSpacingToSet = *((u8 *)val);
3795                                 if(MinSpacingToSet <= 7)
3796                                 {
3797                                         switch(Adapter->securitypriv.dot11PrivacyAlgrthm)
3798                                         {
3799                                                 case _NO_PRIVACY_:
3800                                                 case _AES_:
3801                                                         SecMinSpace = 0;
3802                                                         break;
3803
3804                                                 case _WEP40_:
3805                                                 case _WEP104_:
3806                                                 case _TKIP_:
3807                                                 case _TKIP_WTMIC_:
3808                                                         SecMinSpace = 6;
3809                                                         break;
3810                                                 default:
3811                                                         SecMinSpace = 7;
3812                                                         break;
3813                                         }
3814
3815                                         if(MinSpacingToSet < SecMinSpace){
3816                                                 MinSpacingToSet = SecMinSpace;
3817                                         }
3818
3819                                         //RT_TRACE(COMP_MLME, DBG_LOUD, ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", Adapter->MgntInfo.MinSpaceCfg));
3820                                         rtw_write8(Adapter, REG_AMPDU_MIN_SPACE, (rtw_read8(Adapter, REG_AMPDU_MIN_SPACE) & 0xf8) | MinSpacingToSet);
3821                                 }
3822                         }
3823                         break;
3824                 case HW_VAR_AMPDU_FACTOR:
3825                         {
3826                                 u8      RegToSet_Normal[4]={0x41,0xa8,0x72, 0xb9};
3827                                 u8      RegToSet_BT[4]={0x31,0x74,0x42, 0x97};
3828                                 u8      FactorToSet;
3829                                 u8      *pRegToSet;
3830                                 u8      index = 0;
3831
3832 #ifdef CONFIG_BT_COEXIST
3833                                 if(     (pHalData->bt_coexist.BT_Coexist) &&
3834                                         (pHalData->bt_coexist.BT_CoexistType == BT_CSR_BC4) )
3835                                         pRegToSet = RegToSet_BT; // 0x97427431;
3836                                 else
3837 #endif
3838                                         pRegToSet = RegToSet_Normal; // 0xb972a841;
3839
3840                                 FactorToSet = *((u8 *)val);
3841                                 if(FactorToSet <= 3)
3842                                 {
3843                                         FactorToSet = (1<<(FactorToSet + 2));
3844                                         if(FactorToSet>0xf)
3845                                                 FactorToSet = 0xf;
3846
3847                                         for(index=0; index<4; index++)
3848                                         {
3849                                                 if((pRegToSet[index] & 0xf0) > (FactorToSet<<4))
3850                                                         pRegToSet[index] = (pRegToSet[index] & 0x0f) | (FactorToSet<<4);
3851
3852                                                 if((pRegToSet[index] & 0x0f) > FactorToSet)
3853                                                         pRegToSet[index] = (pRegToSet[index] & 0xf0) | (FactorToSet);
3854
3855                                                 rtw_write8(Adapter, (REG_AGGLEN_LMT+index), pRegToSet[index]);
3856                                         }
3857
3858                                         //RT_TRACE(COMP_MLME, DBG_LOUD, ("Set HW_VAR_AMPDU_FACTOR: %#x\n", FactorToSet));
3859                                 }
3860                         }
3861                         break;
3862                 case HW_VAR_RXDMA_AGG_PG_TH:
3863                         #ifdef CONFIG_USB_RX_AGGREGATION
3864                         {
3865                                 u8      threshold = *((u8 *)val);
3866                                 if( threshold == 0)
3867                                 {
3868                                         threshold = pHalData->UsbRxAggPageCount;
3869                                 }
3870                                 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, threshold);
3871                         }
3872                         #endif
3873                         break;
3874                 case HW_VAR_SET_RPWM:
3875 #ifdef CONFIG_LPS_LCLK
3876                         {
3877                                 u8      ps_state = *((u8 *)val);
3878                                 //rpwm value only use BIT0(clock bit) ,BIT6(Ack bit), and BIT7(Toggle bit) for 88e.
3879                                 //BIT0 value - 1: 32k, 0:40MHz.
3880                                 //BIT6 value - 1: report cpwm value after success set, 0:do not report.
3881                                 //BIT7 value - Toggle bit change.
3882                                 //modify by Thomas. 2012/4/2.
3883                                 ps_state = ps_state & 0xC1;
3884                                 //DBG_871X("##### Change RPWM value to = %x for switch clk #####\n",ps_state);
3885                                 rtw_write8(Adapter, REG_USB_HRPWM, ps_state);
3886                         }
3887 #endif
3888                         break;
3889                 case HW_VAR_H2C_FW_PWRMODE:
3890                         {
3891                                 u8      psmode = (*(u8 *)val);
3892
3893                                 // Forece leave RF low power mode for 1T1R to prevent conficting setting in Fw power
3894                                 // saving sequence. 2010.06.07. Added by tynli. Suggested by SD3 yschang.
3895                                 if( (psmode != PS_MODE_ACTIVE) && (!IS_92C_SERIAL(pHalData->VersionID)))
3896                                 {
3897                                         ODM_RF_Saving(podmpriv, _TRUE);
3898                                 }
3899                                 rtl8188e_set_FwPwrMode_cmd(Adapter, psmode);
3900                         }
3901                         break;
3902                 case HW_VAR_H2C_FW_JOINBSSRPT:
3903                     {
3904                                 u8      mstatus = (*(u8 *)val);
3905                                 rtl8188e_set_FwJoinBssReport_cmd(Adapter, mstatus);
3906                         }
3907                         break;
3908 #ifdef CONFIG_P2P_PS
3909                 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
3910                         {
3911                                 u8      p2p_ps_state = (*(u8 *)val);
3912                                 rtl8188e_set_p2p_ps_offload_cmd(Adapter, p2p_ps_state);
3913                         }
3914                         break;
3915 #endif //CONFIG_P2P_PS
3916 #ifdef CONFIG_TDLS
3917                 case HW_VAR_TDLS_WRCR:
3918                         rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)&(~RCR_CBSSID_DATA ));
3919                         break;
3920                 case HW_VAR_TDLS_INIT_CH_SEN:
3921                         {
3922                                 rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)&(~ RCR_CBSSID_DATA )&(~RCR_CBSSID_BCN ));
3923                                 rtw_write16(Adapter, REG_RXFLTMAP2,0xffff);
3924
3925                                 //disable update TSF
3926                                 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
3927                         }
3928                         break;
3929                 case HW_VAR_TDLS_DONE_CH_SEN:
3930                         {
3931                                 //enable update TSF
3932                                 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~ BIT(4)));
3933                                 rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|(RCR_CBSSID_BCN ));
3934                         }
3935                         break;
3936                 case HW_VAR_TDLS_RS_RCR:
3937                         rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|(RCR_CBSSID_DATA));
3938                         break;
3939 #endif //CONFIG_TDLS
3940                 case HW_VAR_INITIAL_GAIN:
3941                         {
3942                                 DIG_T   *pDigTable = &podmpriv->DM_DigTable;
3943                                 u32             rx_gain = ((u32 *)(val))[0];
3944
3945                                 if(rx_gain == 0xff){//restore rx gain
3946                                         ODM_Write_DIG(podmpriv,pDigTable->BackupIGValue);
3947                                 }
3948                                 else{
3949                                         pDigTable->BackupIGValue = pDigTable->CurIGValue;
3950                                         ODM_Write_DIG(podmpriv,rx_gain);
3951                                 }
3952                         }
3953                         break;
3954                 case HW_VAR_TRIGGER_GPIO_0:
3955                         rtl8192cu_trigger_gpio_0(Adapter);
3956                         break;
3957 #ifdef CONFIG_BT_COEXIST
3958                 case HW_VAR_BT_SET_COEXIST:
3959                         {
3960                                 u8      bStart = (*(u8 *)val);
3961                                 rtl8192c_set_dm_bt_coexist(Adapter, bStart);
3962                         }
3963                         break;
3964                 case HW_VAR_BT_ISSUE_DELBA:
3965                         {
3966                                 u8      dir = (*(u8 *)val);
3967                                 rtl8192c_issue_delete_ba(Adapter, dir);
3968                         }
3969                         break;
3970 #endif
3971 #if (RATE_ADAPTIVE_SUPPORT==1)
3972                 case HW_VAR_RPT_TIMER_SETTING:
3973                         {
3974                                 u16     min_rpt_time = (*(u16 *)val);
3975                                 ODM_RA_Set_TxRPT_Time(podmpriv,min_rpt_time);
3976                         }
3977                         break;
3978 #endif
3979 #ifdef CONFIG_SW_ANTENNA_DIVERSITY
3980
3981                 case HW_VAR_ANTENNA_DIVERSITY_LINK:
3982                         //odm_SwAntDivRestAfterLink8192C(Adapter);
3983                         ODM_SwAntDivRestAfterLink(podmpriv);
3984                         break;
3985 #endif
3986 #ifdef CONFIG_ANTENNA_DIVERSITY
3987                 case HW_VAR_ANTENNA_DIVERSITY_SELECT:
3988                         {
3989                                 u8      Optimum_antenna = (*(u8 *)val);
3990                                 u8      Ant ;
3991                                 //switch antenna to Optimum_antenna
3992                                 //DBG_8192C("==> HW_VAR_ANTENNA_DIVERSITY_SELECT , Ant_(%s)\n",(Optimum_antenna==2)?"A":"B");
3993                                 if(pHalData->CurAntenna !=  Optimum_antenna)
3994                                 {
3995                                         Ant = (Optimum_antenna==2)?MAIN_ANT:AUX_ANT;
3996                                         ODM_UpdateRxIdleAnt(&pHalData->odmpriv, Ant);
3997
3998                                         pHalData->CurAntenna = Optimum_antenna ;
3999                                         //DBG_8192C("==> HW_VAR_ANTENNA_DIVERSITY_SELECT , Ant_(%s)\n",(Optimum_antenna==2)?"A":"B");
4000                                 }
4001                         }
4002                         break;
4003 #endif
4004                 case HW_VAR_EFUSE_BYTES: // To set EFUE total used bytes, added by Roger, 2008.12.22.
4005                         pHalData->EfuseUsedBytes = *((u16 *)val);
4006                         break;
4007                 case HW_VAR_FIFO_CLEARN_UP:
4008                         {
4009                                 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter);
4010                                 u8 trycnt = 100;
4011
4012                                 //pause tx
4013                                 rtw_write8(Adapter,REG_TXPAUSE,0xff);
4014
4015                                 //keep sn
4016                                 Adapter->xmitpriv.nqos_ssn = rtw_read16(Adapter,REG_NQOS_SEQ);
4017
4018                                 if(pwrpriv->bkeepfwalive != _TRUE)
4019                                 {
4020                                         //RX DMA stop
4021                                         rtw_write32(Adapter,REG_RXPKT_NUM,(rtw_read32(Adapter,REG_RXPKT_NUM)|RW_RELEASE_EN));
4022                                         do{
4023                                                 if(!(rtw_read32(Adapter,REG_RXPKT_NUM)&RXDMA_IDLE))
4024                                                         break;
4025                                         }while(trycnt--);
4026                                         if(trycnt ==0)
4027                                                 DBG_8192C("Stop RX DMA failed...... \n");
4028
4029                                         //RQPN Load 0
4030                                         rtw_write16(Adapter,REG_RQPN_NPQ,0x0);
4031                                         rtw_write32(Adapter,REG_RQPN,0x80000000);
4032                                         rtw_mdelay_os(10);
4033                                 }
4034                         }
4035                         break;
4036         case HW_VAR_APFM_ON_MAC:
4037                         pHalData->bMacPwrCtrlOn = *val;
4038                         DBG_871X("%s: bMacPwrCtrlOn=%d\n", __func__, pHalData->bMacPwrCtrlOn);
4039                         break;
4040
4041 #ifdef CONFIG_WOWLAN
4042                 case HW_VAR_WOWLAN:
4043                 {
4044                         struct wowlan_ioctl_param *poidparam;
4045                         struct recv_buf *precvbuf;
4046                         struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(Adapter);
4047                         struct security_priv *psecuritypriv = &Adapter->securitypriv;
4048                         int res, i;
4049                         u32 tmp;
4050                         u64 iv_low = 0, iv_high = 0;
4051                         u16 len = 0;
4052                         u8 mstatus = (*(u8 *)val);
4053                         u8 trycnt = 100;
4054                         u8 data[4], val8;
4055
4056                         poidparam = (struct wowlan_ioctl_param *)val;
4057                         switch (poidparam->subcode){
4058                                 case WOWLAN_ENABLE:
4059                                         DBG_871X_LEVEL(_drv_always_, "WOWLAN_ENABLE\n");
4060
4061                                         #ifndef DYNAMIC_CAMID_ALLOC
4062                                         val8 = (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)? 0xcc: 0xcf;
4063                                         rtw_write8(Adapter, REG_SECCFG, val8);
4064                                         DBG_871X_LEVEL(_drv_always_, "REG_SECCFG: %02x\n", rtw_read8(Adapter, REG_SECCFG));
4065                                         #endif
4066
4067                                         SetFwRelatedForWoWLAN8188ES(Adapter, _TRUE);
4068
4069                                         rtl8188e_set_FwJoinBssReport_cmd(Adapter, 1);
4070                                         rtw_msleep_os(2);
4071
4072                                         //Set Pattern
4073                                         //if(pwrctl->wowlan_pattern==_TRUE)
4074                                         //      rtw_wowlan_reload_pattern(Adapter);
4075
4076                                         //RX DMA stop
4077                                         DBG_871X_LEVEL(_drv_always_, "Pause DMA\n");
4078                                         rtw_write32(Adapter,REG_RXPKT_NUM,(rtw_read32(Adapter,REG_RXPKT_NUM)|RW_RELEASE_EN));
4079                                         do{
4080                                                 if((rtw_read32(Adapter, REG_RXPKT_NUM)&RXDMA_IDLE)) {
4081                                                         DBG_871X_LEVEL(_drv_always_, "RX_DMA_IDLE is true\n");
4082                                                         if (Adapter->intf_stop)
4083                                                                 Adapter->intf_stop(Adapter);
4084                                                         break;
4085                                                 } else {
4086                                                         // If RX_DMA is not idle, receive one pkt from DMA
4087                                                         DBG_871X_LEVEL(_drv_always_, "RX_DMA_IDLE is not true\n");
4088                                                 }
4089                                         }while(trycnt--);
4090
4091                                         if(trycnt ==0)
4092                                                 DBG_871X_LEVEL(_drv_always_, "Stop RX DMA failed...... \n");
4093
4094                                         //Set WOWLAN H2C command.
4095                                         DBG_871X_LEVEL(_drv_always_, "Set WOWLan cmd\n");
4096                                         rtl8188es_set_wowlan_cmd(Adapter, 1);
4097
4098                                         mstatus = rtw_read8(Adapter, REG_WOW_CTRL);
4099                                         trycnt = 10;
4100
4101                                         while(!(mstatus&BIT1) && trycnt>1) {
4102                                                 mstatus = rtw_read8(Adapter, REG_WOW_CTRL);
4103                                                 DBG_871X_LEVEL(_drv_always_, "Loop index: %d :0x%02x\n", trycnt, mstatus);
4104                                                 trycnt --;
4105                                                 rtw_msleep_os(2);
4106                                         }
4107
4108                                         pwrctl->wowlan_wake_reason = rtw_read8(Adapter, REG_WOWLAN_WAKE_REASON);
4109                                         DBG_871X_LEVEL(_drv_always_, "wowlan_wake_reason: 0x%02x\n",
4110                                                                                 pwrctl->wowlan_wake_reason);
4111
4112                                         /* Invoid SE0 reset signal during suspending*/
4113                                         rtw_write8(Adapter, REG_RSV_CTRL, 0x20);
4114                                         rtw_write8(Adapter, REG_RSV_CTRL, 0x60);
4115
4116                                         //rtw_msleep_os(10);
4117                                         break;
4118                                 case WOWLAN_DISABLE:
4119                                         trycnt = 10;
4120
4121                                         DBG_871X_LEVEL(_drv_always_, "WOWLAN_DISABLE\n");
4122
4123                                         rtl8188e_set_FwJoinBssReport_cmd(Adapter, 0);
4124
4125                                         #ifndef DYNAMIC_CAMID_ALLOC
4126                                         rtw_write8(Adapter, REG_SECCFG, 0x0c|BIT(5));// enable tx enc and rx dec engine, and no key search for MC/BC
4127                                         DBG_871X_LEVEL(_drv_always_, "REG_SECCFG: %02x\n", rtw_read8(Adapter, REG_SECCFG));
4128                                         #endif
4129
4130                                         pwrctl->wowlan_wake_reason =
4131                                                 rtw_read8(Adapter, REG_WOWLAN_WAKE_REASON);
4132                                         DBG_871X_LEVEL(_drv_always_,
4133                                                         "wakeup_reason: 0x%02x\n", pwrctl->wowlan_wake_reason);
4134
4135                                         rtl8188es_set_wowlan_cmd(Adapter, 0);
4136                                         mstatus = rtw_read8(Adapter, REG_WOW_CTRL);
4137                                         DBG_871X_LEVEL(_drv_info_, "%s mstatus:0x%02x\n", __func__, mstatus);
4138
4139                                         while(mstatus&BIT1 && trycnt>1) {
4140                                                 mstatus = rtw_read8(Adapter, REG_WOW_CTRL);
4141                                                 DBG_871X_LEVEL(_drv_always_, "Loop index: %d :0x%02x\n", trycnt, mstatus);
4142                                                 trycnt --;
4143                                                 rtw_msleep_os(2);
4144                                         }
4145
4146                                         if (mstatus & BIT1) {
4147                                                 DBG_871X_LEVEL(_drv_always_, "Disable WOW mode fail!!\n");
4148                                                 DBG_871X("Set 0x690=0x00\n");
4149                                                 rtw_write8(Adapter, REG_WOW_CTRL, (rtw_read8(Adapter, REG_WOW_CTRL)&0xf0));
4150                                                 DBG_871X_LEVEL(_drv_always_, "Release RXDMA\n");
4151                                                 rtw_write32(Adapter, REG_RXPKT_NUM,(rtw_read32(Adapter,REG_RXPKT_NUM)&(~RW_RELEASE_EN)));
4152                                         }
4153
4154                                         // 3.1 read fw iv
4155                                         iv_low = rtw_read32(Adapter, REG_TXPKTBUF_IV_LOW);
4156                                         //only low two bytes is PN, check AES_IV macro for detail
4157                                         iv_low &= 0xffff;
4158                                         iv_high = rtw_read32(Adapter, REG_TXPKTBUF_IV_HIGH);
4159                                         //get the real packet number
4160                                         pwrctl->wowlan_fw_iv = iv_high << 16 | iv_low;
4161                                         DBG_871X_LEVEL(_drv_always_, "fw_iv: 0x%016llx\n", pwrctl->wowlan_fw_iv);
4162                                         //Update TX iv data.
4163                                         rtw_set_sec_pn(Adapter);
4164
4165                                         SetFwRelatedForWoWLAN8188ES(Adapter, _FALSE);
4166
4167                                         if((pwrctl->wowlan_wake_reason != FWDecisionDisconnect) &&
4168                                                 (pwrctl->wowlan_wake_reason != Rx_Pairwisekey) &&
4169                                                 (pwrctl->wowlan_wake_reason != Rx_DisAssoc) &&
4170                                                 (pwrctl->wowlan_wake_reason != Rx_DeAuth))
4171                                                 rtl8188e_set_FwJoinBssReport_cmd(Adapter, 1);
4172
4173                                         rtw_msleep_os(5);
4174                                         break;
4175                                 default:
4176                                         break;
4177                         }
4178                 }
4179                 break;
4180 #endif //CONFIG_WOWLAN
4181
4182
4183         #if (RATE_ADAPTIVE_SUPPORT == 1)
4184                 case HW_VAR_TX_RPT_MAX_MACID:
4185                         {
4186                                 u8 maxMacid = *val;
4187                                 DBG_871X("### MacID(%d),Set Max Tx RPT MID(%d)\n",maxMacid,maxMacid+1);
4188                                 rtw_write8(Adapter, REG_TX_RPT_CTRL+1, maxMacid+1);
4189                         }
4190                         break;
4191         #endif
4192                 case HW_VAR_H2C_MEDIA_STATUS_RPT:
4193                         {
4194                                 rtl8188e_set_FwMediaStatus_cmd(Adapter , (*(u16 *)val));
4195                         }
4196                         break;
4197                 case HW_VAR_BCN_VALID:
4198                         //BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2, write 1 to clear, Clear by sw
4199                         rtw_write8(Adapter, REG_TDECTRL+2, rtw_read8(Adapter, REG_TDECTRL+2) | BIT0);
4200                         break;
4201
4202                 default:
4203                         SetHwReg8188E(Adapter, variable, val);
4204                         break;
4205         }
4206
4207 _func_exit_;
4208 }
4209
4210 void GetHwReg8188EU(PADAPTER Adapter, u8 variable, u8* val)
4211 {
4212         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
4213         DM_ODM_T                *podmpriv = &pHalData->odmpriv;
4214 _func_enter_;
4215
4216         switch(variable)
4217         {
4218                 case HW_VAR_TXPAUSE:
4219                         val[0] = rtw_read8(Adapter, REG_TXPAUSE);
4220                         break;
4221                 case HW_VAR_BCN_VALID:
4222                         //BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2
4223                         val[0] = (BIT0 & rtw_read8(Adapter, REG_TDECTRL+2))?_TRUE:_FALSE;
4224                         break;
4225                 case HW_VAR_FWLPS_RF_ON:
4226                         {
4227                                 //When we halt NIC, we should check if FW LPS is leave.
4228                                 if(adapter_to_pwrctl(Adapter)->rf_pwrstate == rf_off)
4229                                 {
4230                                         // If it is in HW/SW Radio OFF or IPS state, we do not check Fw LPS Leave,
4231                                         // because Fw is unload.
4232                                         val[0] = _TRUE;
4233                                 }
4234                                 else
4235                                 {
4236                                         u32 valRCR;
4237                                         valRCR = rtw_read32(Adapter, REG_RCR);
4238                                         valRCR &= 0x00070000;
4239                                         if(valRCR)
4240                                                 val[0] = _FALSE;
4241                                         else
4242                                                 val[0] = _TRUE;
4243                                 }
4244                         }
4245                         break;
4246 #ifdef CONFIG_ANTENNA_DIVERSITY
4247                 case HW_VAR_CURRENT_ANTENNA:
4248                         val[0] = pHalData->CurAntenna;
4249                         break;
4250 #endif
4251                 case HW_VAR_EFUSE_BYTES: // To get EFUE total used bytes, added by Roger, 2008.12.22.
4252                         *((u16 *)(val)) = pHalData->EfuseUsedBytes;
4253                         break;
4254                 case HW_VAR_APFM_ON_MAC:
4255                         *val = pHalData->bMacPwrCtrlOn;
4256                         break;
4257                 case HW_VAR_CHK_HI_QUEUE_EMPTY:
4258                         *val = ((rtw_read32(Adapter, REG_HGQ_INFO)&0x0000ff00)==0) ? _TRUE:_FALSE;
4259                         break;
4260                 default:
4261                         GetHwReg8188E(Adapter, variable, val);
4262                         break;
4263         }
4264
4265 _func_exit_;
4266 }
4267
4268 //
4269 //      Description:
4270 //              Query setting of specified variable.
4271 //
4272 u8
4273 GetHalDefVar8188EUsb(
4274         IN      PADAPTER                                Adapter,
4275         IN      HAL_DEF_VARIABLE                eVariable,
4276         IN      PVOID                                   pValue
4277         )
4278 {
4279         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
4280         u8                      bResult = _SUCCESS;
4281
4282         switch(eVariable)
4283         {
4284                 case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
4285 #if 1 //trunk
4286                         {
4287                                 struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
4288                                 struct sta_priv * pstapriv = &Adapter->stapriv;
4289                                 struct sta_info * psta;
4290                                 psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress);
4291                                 if(psta)
4292                                 {
4293                                         *((int *)pValue) = psta->rssi_stat.UndecoratedSmoothedPWDB;
4294                                 }
4295                         }
4296 #else //V4 branch
4297                                 if(check_fwstate(&Adapter->mlmepriv, WIFI_STATION_STATE) == _TRUE){
4298                                                 *((int *)pValue) = pHalData->dmpriv.UndecoratedSmoothedPWDB;
4299                                 }
4300                                 else{
4301
4302                                 }
4303 #endif
4304                         break;
4305                 case HAL_DEF_IS_SUPPORT_ANT_DIV:
4306 #ifdef CONFIG_ANTENNA_DIVERSITY
4307                         *((u8 *)pValue) = (pHalData->AntDivCfg==0)?_FALSE:_TRUE;
4308 #endif
4309                         break;
4310                 case HAL_DEF_CURRENT_ANTENNA:
4311 #ifdef CONFIG_ANTENNA_DIVERSITY
4312                         *(( u8*)pValue) = pHalData->CurAntenna;
4313 #endif
4314                         break;
4315                 case HAL_DEF_DRVINFO_SZ:
4316                         *(( u32*)pValue) = DRVINFO_SZ;
4317                         break;
4318                 case HAL_DEF_MAX_RECVBUF_SZ:
4319                         *(( u32*)pValue) = MAX_RECVBUF_SZ;
4320                         break;
4321                 case HAL_DEF_RX_PACKET_OFFSET:
4322                         *(( u32*)pValue) = RXDESC_SIZE + DRVINFO_SZ;
4323                         break;
4324 #if (RATE_ADAPTIVE_SUPPORT == 1)
4325                 case HAL_DEF_RA_DECISION_RATE:
4326                         {
4327                                 u8 MacID = *((u8*)pValue);
4328                                 *((u8*)pValue) = ODM_RA_GetDecisionRate_8188E(&(pHalData->odmpriv), MacID);
4329                         }
4330                         break;
4331
4332                 case HAL_DEF_RA_SGI:
4333                         {
4334                                 u8 MacID = *((u8*)pValue);
4335                                 *((u8*)pValue) = ODM_RA_GetShortGI_8188E(&(pHalData->odmpriv), MacID);
4336                         }
4337                         break;
4338 #endif
4339
4340
4341                 case HAL_DEF_PT_PWR_STATUS:
4342 #if(POWER_TRAINING_ACTIVE==1)
4343                         {
4344                                 u8 MacID = *((u8*)pValue);
4345                                 *((u8*)pValue) = ODM_RA_GetHwPwrStatus_8188E(&(pHalData->odmpriv), MacID);
4346                         }
4347 #endif//(POWER_TRAINING_ACTIVE==1)
4348                         break;
4349
4350                 case HW_VAR_MAX_RX_AMPDU_FACTOR:
4351                         *(( u32*)pValue) = MAX_AMPDU_FACTOR_64K;
4352                         break;
4353
4354                 case HAL_DEF_TX_LDPC:
4355                 case HAL_DEF_RX_LDPC:
4356                         *((u8 *)pValue) = _FALSE;
4357                         break;
4358                 case HAL_DEF_TX_STBC:
4359                         *((u8 *)pValue) = 0;
4360                         break;
4361                 case HAL_DEF_RX_STBC:
4362                         *((u8 *)pValue) = 1;
4363                         break;
4364                 case HAL_DEF_EXPLICIT_BEAMFORMEE:
4365                 case HAL_DEF_EXPLICIT_BEAMFORMER:
4366                         *((u8 *)pValue) = _FALSE;
4367                         break;
4368
4369                 case HW_DEF_RA_INFO_DUMP:
4370 #if (RATE_ADAPTIVE_SUPPORT == 1)
4371                         {
4372                                 u8 mac_id = *((u8*)pValue);
4373                                 u8                      bLinked = _FALSE;
4374 #ifdef CONFIG_CONCURRENT_MODE
4375                                 PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter;
4376 #endif //CONFIG_CONCURRENT_MODE
4377
4378                                 if(rtw_linked_check(Adapter))
4379                                         bLinked = _TRUE;
4380
4381 #ifdef CONFIG_CONCURRENT_MODE
4382                                 if(pbuddy_adapter && rtw_linked_check(pbuddy_adapter))
4383                                         bLinked = _TRUE;
4384 #endif
4385
4386                                 if(bLinked){
4387                                         DBG_871X("============ RA status - Mac_id:%d ===================\n",mac_id);
4388
4389                                         DBG_8192C("Mac_id:%d ,RSSI:%d(%%),PTStage = %d\n",
4390                                                 mac_id,pHalData->odmpriv.RAInfo[mac_id].RssiStaRA,pHalData->odmpriv.RAInfo[mac_id].PTStage);
4391
4392                                         DBG_8192C("RateID = %d,RAUseRate = 0x%08x,RateSGI = %d, DecisionRate = %s\n",
4393                                                 pHalData->odmpriv.RAInfo[mac_id].RateID,
4394                                                 pHalData->odmpriv.RAInfo[mac_id].RAUseRate,
4395                                                 pHalData->odmpriv.RAInfo[mac_id].RateSGI,
4396                                                 HDATA_RATE(pHalData->odmpriv.RAInfo[mac_id].DecisionRate));
4397
4398                                 }
4399                         }
4400 #endif  //(RATE_ADAPTIVE_SUPPORT == 1)
4401                         break;
4402                 default:
4403                         bResult = GetHalDefVar8188E(Adapter, eVariable, pValue);
4404                         break;
4405         }
4406
4407         return bResult;
4408 }
4409
4410
4411
4412
4413 //
4414 //      Description:
4415 //              Change default setting of specified variable.
4416 //
4417 u8
4418 SetHalDefVar8188EUsb(
4419         IN      PADAPTER                                Adapter,
4420         IN      HAL_DEF_VARIABLE                eVariable,
4421         IN      PVOID                                   pValue
4422         )
4423 {
4424         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
4425         u8                      bResult = _SUCCESS;
4426
4427         switch(eVariable)
4428         {
4429                 default:
4430                         bResult = SetHalDefVar(Adapter, eVariable, pValue);
4431                         break;
4432         }
4433
4434         return bResult;
4435 }
4436 /*
4437 u32  _update_92cu_basic_rate(_adapter *padapter, unsigned int mask)
4438 {
4439         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(padapter);
4440 #ifdef CONFIG_BT_COEXIST
4441         struct btcoexist_priv   *pbtpriv = &(pHalData->bt_coexist);
4442 #endif
4443         unsigned int BrateCfg = 0;
4444
4445 #ifdef CONFIG_BT_COEXIST
4446         if(     (pbtpriv->BT_Coexist) &&        (pbtpriv->BT_CoexistType == BT_CSR_BC4) )
4447         {
4448                 BrateCfg = mask  & 0x151;
4449                 //DBG_8192C("BT temp disable cck 2/5.5/11M, (0x%x = 0x%x)\n", REG_RRSR, BrateCfg & 0x151);
4450         }
4451         else
4452 #endif
4453         {
4454                 //if(pHalData->VersionID != VERSION_TEST_CHIP_88C)
4455                         BrateCfg = mask  & 0x15F;
4456                 //else  //for 88CU 46PING setting, Disable CCK 2M, 5.5M, Others must tuning
4457                 //      BrateCfg = mask  & 0x159;
4458         }
4459
4460         BrateCfg |= 0x01; // default enable 1M ACK rate
4461
4462         return BrateCfg;
4463 }
4464 */
4465 void _update_response_rate(_adapter *padapter,unsigned int mask)
4466 {
4467         u8      RateIndex = 0;
4468         // Set RRSR rate table.
4469         rtw_write8(padapter, REG_RRSR, mask&0xff);
4470         rtw_write8(padapter,REG_RRSR+1, (mask>>8)&0xff);
4471
4472         // Set RTS initial rate
4473         while(mask > 0x1)
4474         {
4475                 mask = (mask>> 1);
4476                 RateIndex++;
4477         }
4478         rtw_write8(padapter, REG_INIRTS_RATE_SEL, RateIndex);
4479 }
4480
4481 void SetBeaconRelatedRegisters8188EUsb(PADAPTER padapter)
4482 {
4483         u32     value32;
4484         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
4485         struct mlme_ext_priv    *pmlmeext = &(padapter->mlmeextpriv);
4486         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
4487         u32 bcn_ctrl_reg                        = REG_BCN_CTRL;
4488         //reset TSF, enable update TSF, correcting TSF On Beacon
4489
4490         //REG_BCN_INTERVAL
4491         //REG_BCNDMATIM
4492         //REG_ATIMWND
4493         //REG_TBTT_PROHIBIT
4494         //REG_DRVERLYINT
4495         //REG_BCN_MAX_ERR
4496         //REG_BCNTCFG //(0x510)
4497         //REG_DUAL_TSF_RST
4498         //REG_BCN_CTRL //(0x550)
4499
4500         //BCN interval
4501 #ifdef CONFIG_CONCURRENT_MODE
4502                 if (padapter->iface_type == IFACE_PORT1){
4503                 bcn_ctrl_reg = REG_BCN_CTRL_1;
4504                 }
4505 #endif
4506         rtw_write16(padapter, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval);
4507         rtw_write8(padapter, REG_ATIMWND, 0x02);// 2ms
4508
4509         _InitBeaconParameters(padapter);
4510
4511         rtw_write8(padapter, REG_SLOT, 0x09);
4512
4513         value32 =rtw_read32(padapter, REG_TCR);
4514         value32 &= ~TSFRST;
4515         rtw_write32(padapter,  REG_TCR, value32);
4516
4517         value32 |= TSFRST;
4518         rtw_write32(padapter, REG_TCR, value32);
4519
4520         // NOTE: Fix test chip's bug (about contention windows's randomness)
4521         rtw_write8(padapter,  REG_RXTSF_OFFSET_CCK, 0x50);
4522         rtw_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50);
4523
4524         _BeaconFunctionEnable(padapter, _TRUE, _TRUE);
4525
4526         ResumeTxBeacon(padapter);
4527
4528         //rtw_write8(padapter, 0x422, rtw_read8(padapter, 0x422)|BIT(6));
4529
4530         //rtw_write8(padapter, 0x541, 0xff);
4531
4532         //rtw_write8(padapter, 0x542, rtw_read8(padapter, 0x541)|BIT(0));
4533
4534         rtw_write8(padapter, bcn_ctrl_reg, rtw_read8(padapter, bcn_ctrl_reg)|BIT(1));
4535
4536 }
4537
4538 static void rtl8188eu_init_default_value(_adapter * padapter)
4539 {
4540         PHAL_DATA_TYPE pHalData;
4541         struct pwrctrl_priv *pwrctrlpriv;
4542         struct dm_priv *pdmpriv;
4543         u8 i;
4544
4545         pHalData = GET_HAL_DATA(padapter);
4546         pwrctrlpriv = adapter_to_pwrctl(padapter);
4547         pdmpriv = &pHalData->dmpriv;
4548
4549         padapter->registrypriv.wireless_mode = WIRELESS_11BG_24N;
4550         //init default value
4551         pHalData->fw_ractrl = _FALSE;
4552         if(!pwrctrlpriv->bkeepfwalive)
4553                 pHalData->LastHMEBoxNum = 0;
4554
4555         //init dm default value
4556         pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = _FALSE;
4557         pHalData->odmpriv.RFCalibrateInfo.TM_Trigger = 0;//for IQK
4558         //pdmpriv->binitialized = _FALSE;
4559 //      pdmpriv->prv_traffic_idx = 3;
4560 //      pdmpriv->initialize = 0;
4561         pHalData->pwrGroupCnt = 0;
4562         pHalData->PGMaxGroup= 13;
4563         pHalData->odmpriv.RFCalibrateInfo.ThermalValue_HP_index = 0;
4564         for(i = 0; i < HP_THERMAL_NUM; i++)
4565                 pHalData->odmpriv.RFCalibrateInfo.ThermalValue_HP[i] = 0;
4566
4567         pHalData->EfuseHal.fakeEfuseBank = 0;
4568         pHalData->EfuseHal.fakeEfuseUsedBytes = 0;
4569         _rtw_memset(pHalData->EfuseHal.fakeEfuseContent, 0xFF, EFUSE_MAX_HW_SIZE);
4570         _rtw_memset(pHalData->EfuseHal.fakeEfuseInitMap, 0xFF, EFUSE_MAX_MAP_LEN);
4571         _rtw_memset(pHalData->EfuseHal.fakeEfuseModifiedMap, 0xFF, EFUSE_MAX_MAP_LEN);
4572 }
4573
4574 static u8 rtl8188eu_ps_func(PADAPTER Adapter,HAL_INTF_PS_FUNC efunc_id, u8 *val)
4575 {
4576         u8 bResult = _TRUE;
4577         switch(efunc_id){
4578
4579                 #if defined(CONFIG_AUTOSUSPEND) && defined(SUPPORT_HW_RFOFF_DETECTED)
4580                 case HAL_USB_SELECT_SUSPEND:
4581                         {
4582                                 u8 bfwpoll = *(( u8*)val);
4583                                 //rtl8188e_set_FwSelectSuspend_cmd(Adapter,bfwpoll ,500);//note fw to support hw power down ping detect
4584                         }
4585                         break;
4586                 #endif //CONFIG_AUTOSUSPEND && SUPPORT_HW_RFOFF_DETECTED
4587
4588                 default:
4589                         break;
4590         }
4591         return bResult;
4592 }
4593
4594 void rtl8188eu_set_hal_ops(_adapter * padapter)
4595 {
4596         struct hal_ops  *pHalFunc = &padapter->HalFunc;
4597
4598 _func_enter_;
4599
4600 #ifdef CONFIG_CONCURRENT_MODE
4601         if(padapter->isprimary)
4602 #endif //CONFIG_CONCURRENT_MODE
4603         {
4604                 padapter->HalData = rtw_zvmalloc(sizeof(HAL_DATA_TYPE));
4605                 if(padapter->HalData == NULL){
4606                         DBG_8192C("cant not alloc memory for HAL DATA \n");
4607                 }
4608         }
4609
4610         //_rtw_memset(padapter->HalData, 0, sizeof(HAL_DATA_TYPE));
4611         padapter->hal_data_sz = sizeof(HAL_DATA_TYPE);
4612
4613         pHalFunc->hal_power_on = _InitPowerOn_8188EU;
4614         pHalFunc->hal_power_off = hal_poweroff_8188eu;
4615
4616         pHalFunc->hal_init = &rtl8188eu_hal_init;
4617         pHalFunc->hal_deinit = &rtl8188eu_hal_deinit;
4618
4619         //pHalFunc->free_hal_data = &rtl8192c_free_hal_data;
4620
4621         pHalFunc->inirp_init = &rtl8188eu_inirp_init;
4622         pHalFunc->inirp_deinit = &rtl8188eu_inirp_deinit;
4623
4624         pHalFunc->init_xmit_priv = &rtl8188eu_init_xmit_priv;
4625         pHalFunc->free_xmit_priv = &rtl8188eu_free_xmit_priv;
4626
4627         pHalFunc->init_recv_priv = &rtl8188eu_init_recv_priv;
4628         pHalFunc->free_recv_priv = &rtl8188eu_free_recv_priv;
4629 #ifdef CONFIG_SW_LED
4630         pHalFunc->InitSwLeds = &rtl8188eu_InitSwLeds;
4631         pHalFunc->DeInitSwLeds = &rtl8188eu_DeInitSwLeds;
4632 #else //case of hw led or no led
4633         pHalFunc->InitSwLeds = NULL;
4634         pHalFunc->DeInitSwLeds = NULL;
4635 #endif//CONFIG_SW_LED
4636
4637         pHalFunc->init_default_value = &rtl8188eu_init_default_value;
4638         pHalFunc->intf_chip_configure = &rtl8188eu_interface_configure;
4639         pHalFunc->read_adapter_info = &ReadAdapterInfo8188EU;
4640
4641         //pHalFunc->set_bwmode_handler = &PHY_SetBWMode8192C;
4642         //pHalFunc->set_channel_handler = &PHY_SwChnl8192C;
4643
4644         //pHalFunc->hal_dm_watchdog = &rtl8192c_HalDmWatchDog;
4645
4646
4647         pHalFunc->SetHwRegHandler = &SetHwReg8188EU;
4648         pHalFunc->GetHwRegHandler = &GetHwReg8188EU;
4649         pHalFunc->GetHalDefVarHandler = &GetHalDefVar8188EUsb;
4650         pHalFunc->SetHalDefVarHandler = &SetHalDefVar8188EUsb;
4651
4652         pHalFunc->SetBeaconRelatedRegistersHandler = &SetBeaconRelatedRegisters8188EUsb;
4653
4654         //pHalFunc->Add_RateATid = &rtl8192c_Add_RateATid;
4655
4656         pHalFunc->hal_xmit = &rtl8188eu_hal_xmit;
4657         pHalFunc->mgnt_xmit = &rtl8188eu_mgnt_xmit;
4658         pHalFunc->hal_xmitframe_enqueue = &rtl8188eu_hal_xmitframe_enqueue;
4659
4660
4661 #ifdef CONFIG_HOSTAPD_MLME
4662         pHalFunc->hostap_mgnt_xmit_entry = &rtl8188eu_hostap_mgnt_xmit_entry;
4663 #endif
4664         pHalFunc->interface_ps_func = &rtl8188eu_ps_func;
4665
4666 #ifdef CONFIG_XMIT_THREAD_MODE
4667         pHalFunc->xmit_thread_handler = &rtl8188eu_xmit_buf_handler;
4668 #endif
4669         rtl8188e_set_hal_ops(pHalFunc);
4670 _func_exit_;
4671
4672 }
4673