drivers/net/wireless/rockchip_wlan/rtl8188eu/hal/rtl8188e/usb/usb_halinit.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #define _HCI_HAL_INIT_C_
  21
  22 #include <drv_types.h>
  23 #include <rtl8188e_hal.h>
  24 #include "hal_com_h2c.h"
  25
  26 #ifndef CONFIG_USB_HCI
  27
  28 #error "CONFIG_USB_HCI shall be on!\n"
  29
  30 #endif
  31
  32
  33 static VOID
  34 _ConfigNormalChipOutEP_8188E(
  35         IN      PADAPTER        pAdapter,
  36         IN      u8              NumOutPipe
  37         )
  38 {
  39         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(pAdapter);
  40
  41         switch(NumOutPipe){
  42                 case    3:
  43                                 pHalData->OutEpQueueSel=TX_SELE_HQ| TX_SELE_LQ|TX_SELE_NQ;
  44                                 pHalData->OutEpNumber=3;
  45                                 break;
  46                 case    2:
  47                                 pHalData->OutEpQueueSel=TX_SELE_HQ| TX_SELE_NQ;
  48                                 pHalData->OutEpNumber=2;
  49                                 break;
  50                 case    1:
  51                                 pHalData->OutEpQueueSel=TX_SELE_HQ;
  52                                 pHalData->OutEpNumber=1;
  53                                 break;
  54                 default:
  55                                 break;
  56
  57         }
  58         DBG_871X("%s OutEpQueueSel(0x%02x), OutEpNumber(%d) \n",__FUNCTION__,pHalData->OutEpQueueSel,pHalData->OutEpNumber );
  59
  60 }
  61
  62 static BOOLEAN HalUsbSetQueuePipeMapping8188EUsb(
  63         IN      PADAPTER        pAdapter,
  64         IN      u8              NumInPipe,
  65         IN      u8              NumOutPipe
  66         )
  67 {
  68         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(pAdapter);
  69         BOOLEAN                 result          = _FALSE;
  70
  71         _ConfigNormalChipOutEP_8188E(pAdapter, NumOutPipe);
  72
  73         // Normal chip with one IN and one OUT doesn't have interrupt IN EP.
  74         if(1 == pHalData->OutEpNumber){
  75                 if(1 != NumInPipe){
  76                         return result;
  77                 }
  78         }
  79
  80         // All config other than above support one Bulk IN and one Interrupt IN.
  81         //if(2 != NumInPipe){
  82         //      return result;
  83         //}
  84
  85         result = Hal_MappingOutPipe(pAdapter, NumOutPipe);
  86
  87         return result;
  88
  89 }
  90
  91 void rtl8188eu_interface_configure(_adapter *padapter)
  92 {
  93         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(padapter);
  94         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
  95
  96         if (IS_HIGH_SPEED_USB(padapter))
  97         {
  98                 pHalData->UsbBulkOutSize = USB_HIGH_SPEED_BULK_SIZE;//512 bytes
  99         }
 100         else
 101         {
 102                 pHalData->UsbBulkOutSize = USB_FULL_SPEED_BULK_SIZE;//64 bytes
 103         }
 104
 105         pHalData->interfaceIndex = pdvobjpriv->InterfaceNumber;
 106
 107 #ifdef CONFIG_USB_TX_AGGREGATION
 108         pHalData->UsbTxAggMode          = 1;
 109         pHalData->UsbTxAggDescNum       = 0x1;  // only 4 bits
 110 #endif
 111
 112 #ifdef CONFIG_USB_RX_AGGREGATION
 113         pHalData->UsbRxAggMode          = USB_RX_AGG_DMA;// USB_RX_AGG_DMA;
 114         pHalData->UsbRxAggBlockCount    = 8; //unit : 512b
 115         pHalData->UsbRxAggBlockTimeout  = 0x6;
 116         pHalData->UsbRxAggPageCount     = 48; //uint :128 b //0x0A;     // 10 = MAX_RX_DMA_BUFFER_SIZE/2/pHalData->UsbBulkOutSize
 117         pHalData->UsbRxAggPageTimeout   = 0x4; //6, absolute time = 34ms/(2^6)
 118 #endif
 119
 120         HalUsbSetQueuePipeMapping8188EUsb(padapter,
 121                                 pdvobjpriv->RtNumInPipes, pdvobjpriv->RtNumOutPipes);
 122
 123 }
 124
 125 static u32 _InitPowerOn_8188EU(_adapter *padapter)
 126 {
 127         u16 value16;
 128         // HW Power on sequence
 129         u8 bMacPwrCtrlOn=_FALSE;
 130
 131
 132         rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
 133         if(bMacPwrCtrlOn == _TRUE)
 134                 return _SUCCESS;
 135
 136         if(!HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_PWR_ON_FLOW))
 137         {
 138                 DBG_871X(KERN_ERR "%s: run power on flow fail\n", __func__);
 139                 return _FAIL;
 140         }
 141
 142         // Enable MAC DMA/WMAC/SCHEDULE/SEC block
 143         // Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31.
 144         rtw_write16(padapter, REG_CR, 0x00);  //suggseted by zhouzhou, by page, 20111230
 145
 146
 147                 // Enable MAC DMA/WMAC/SCHEDULE/SEC block
 148         value16 = rtw_read16(padapter, REG_CR);
 149         value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
 150                                 | PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN);
 151         // for SDIO - Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31.
 152
 153         rtw_write16(padapter, REG_CR, value16);
 154
 155         bMacPwrCtrlOn = _TRUE;
 156         rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
 157
 158
 159         return _SUCCESS;
 160
 161 }
 162
 163
 164 static void _dbg_dump_macreg(_adapter *padapter)
 165 {
 166         u32 offset = 0;
 167         u32 val32 = 0;
 168         u32 index =0 ;
 169         for(index=0;index<64;index++)
 170         {
 171                 offset = index*4;
 172                 val32 = rtw_read32(padapter,offset);
 173                 DBG_8192C("offset : 0x%02x ,val:0x%08x\n",offset,val32);
 174         }
 175 }
 176
 177
 178 static void _InitPABias(_adapter *padapter)
 179 {
 180         HAL_DATA_TYPE           *pHalData       = GET_HAL_DATA(padapter);
 181         u8                      pa_setting;
 182         BOOLEAN         is92C = IS_92C_SERIAL(pHalData->VersionID);
 183
 184         //FIXED PA current issue
 185         //efuse_one_byte_read(padapter, 0x1FA, &pa_setting);
 186         pa_setting = EFUSE_Read1Byte(padapter, 0x1FA);
 187
 188         //RT_TRACE(COMP_INIT, DBG_LOUD, ("_InitPABias 0x1FA 0x%x \n",pa_setting));
 189
 190         if(!(pa_setting & BIT0))
 191         {
 192                 PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
 193                 PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
 194                 PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
 195                 PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
 196                 //RT_TRACE(COMP_INIT, DBG_LOUD, ("PA BIAS path A\n"));
 197         }
 198
 199         if(!(pa_setting & BIT1) && is92C)
 200         {
 201                 PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0x0F406);
 202                 PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0x4F406);
 203                 PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0x8F406);
 204                 PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0xCF406);
 205                 //RT_TRACE(COMP_INIT, DBG_LOUD, ("PA BIAS path B\n"));
 206         }
 207
 208         if(!(pa_setting & BIT4))
 209         {
 210                 pa_setting = rtw_read8(padapter, 0x16);
 211                 pa_setting &= 0x0F;
 212                 rtw_write8(padapter, 0x16, pa_setting | 0x80);
 213                 rtw_write8(padapter, 0x16, pa_setting | 0x90);
 214         }
 215 }
 216 #ifdef CONFIG_BT_COEXIST
 217 static void _InitBTCoexist(_adapter *padapter)
 218 {
 219         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(padapter);
 220         struct btcoexist_priv   *pbtpriv = &(pHalData->bt_coexist);
 221         u8 u1Tmp;
 222
 223         if(pbtpriv->BT_Coexist && pbtpriv->BT_CoexistType == BT_CSR_BC4)
 224         {
 225
 226 //#if MP_DRIVER != 1
 227         if (padapter->registrypriv.mp_mode == 0)
 228         {
 229                 if(pbtpriv->BT_Ant_isolation)
 230                 {
 231                         rtw_write8( padapter,REG_GPIO_MUXCFG, 0xa0);
 232                         DBG_8192C("BT write 0x%x = 0x%x\n", REG_GPIO_MUXCFG, 0xa0);
 233                 }
 234         }
 235 //#endif
 236
 237                 u1Tmp = rtw_read8(padapter, 0x4fd) & BIT0;
 238                 u1Tmp = u1Tmp |
 239                                 ((pbtpriv->BT_Ant_isolation==1)?0:BIT1) |
 240                                 ((pbtpriv->BT_Service==BT_SCO)?0:BIT2);
 241                 rtw_write8( padapter, 0x4fd, u1Tmp);
 242                 DBG_8192C("BT write 0x%x = 0x%x for non-isolation\n", 0x4fd, u1Tmp);
 243
 244
 245                 rtw_write32(padapter, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
 246                 DBG_8192C("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
 247
 248                 rtw_write32(padapter, REG_BT_COEX_TABLE+8, 0xffbd0040);
 249                 DBG_8192C("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE+8, 0xffbd0040);
 250
 251                 rtw_write32(padapter,  REG_BT_COEX_TABLE+0xc, 0x40000010);
 252                 DBG_8192C("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE+0xc, 0x40000010);
 253
 254                 //Config to 1T1R
 255                 u1Tmp =  rtw_read8(padapter,rOFDM0_TRxPathEnable);
 256                 u1Tmp &= ~(BIT1);
 257                 rtw_write8( padapter, rOFDM0_TRxPathEnable, u1Tmp);
 258                 DBG_8192C("BT write 0xC04 = 0x%x\n", u1Tmp);
 259
 260                 u1Tmp = rtw_read8(padapter, rOFDM1_TRxPathEnable);
 261                 u1Tmp &= ~(BIT1);
 262                 rtw_write8( padapter, rOFDM1_TRxPathEnable, u1Tmp);
 263                 DBG_8192C("BT write 0xD04 = 0x%x\n", u1Tmp);
 264
 265         }
 266 }
 267 #endif
 268
 269
 270
 271 //---------------------------------------------------------------
 272 //
 273 //      MAC init functions
 274 //
 275 //---------------------------------------------------------------
 276 static VOID
 277 _SetMacID(
 278         IN  PADAPTER Adapter, u8* MacID
 279         )
 280 {
 281         u32 i;
 282         for(i=0 ; i< MAC_ADDR_LEN ; i++){
 283 #ifdef  CONFIG_CONCURRENT_MODE
 284                 if(Adapter->iface_type == IFACE_PORT1)
 285                         rtw_write32(Adapter, REG_MACID1+i, MacID[i]);
 286                 else
 287 #endif
 288                 rtw_write32(Adapter, REG_MACID+i, MacID[i]);
 289         }
 290 }
 291
 292 static VOID
 293 _SetBSSID(
 294         IN  PADAPTER Adapter, u8* BSSID
 295         )
 296 {
 297         u32 i;
 298         for(i=0 ; i< MAC_ADDR_LEN ; i++){
 299 #ifdef  CONFIG_CONCURRENT_MODE
 300                 if(Adapter->iface_type == IFACE_PORT1)
 301                         rtw_write32(Adapter, REG_BSSID1+i, BSSID[i]);
 302                 else
 303 #endif
 304                 rtw_write32(Adapter, REG_BSSID+i, BSSID[i]);
 305         }
 306 }
 307
 308
 309 // Shall USB interface init this?
 310 static VOID
 311 _InitInterrupt(
 312         IN  PADAPTER Adapter
 313         )
 314 {
 315         u32     imr,imr_ex;
 316         u8  usb_opt;
 317         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 318
 319         //HISR write one to clear
 320         rtw_write32(Adapter, REG_HISR_88E, 0xFFFFFFFF);
 321         // HIMR -
 322         imr = IMR_PSTIMEOUT_88E | IMR_TBDER_88E | IMR_CPWM_88E | IMR_CPWM2_88E ;
 323         rtw_write32(Adapter, REG_HIMR_88E, imr);
 324         pHalData->IntrMask[0]=imr;
 325
 326         imr_ex = IMR_TXERR_88E | IMR_RXERR_88E | IMR_TXFOVW_88E |IMR_RXFOVW_88E;
 327         rtw_write32(Adapter, REG_HIMRE_88E, imr_ex);
 328         pHalData->IntrMask[1]=imr_ex;
 329
 330 #ifdef CONFIG_SUPPORT_USB_INT
 331         // REG_USB_SPECIAL_OPTION - BIT(4)
 332         // 0; Use interrupt endpoint to upload interrupt pkt
 333         // 1; Use bulk endpoint to upload interrupt pkt,
 334         usb_opt = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION);
 335
 336         if((IS_FULL_SPEED_USB(Adapter))
 337                 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
 338                 || pHalData->RtIntInPipe == 0x05
 339                 #endif
 340         )
 341                 usb_opt = usb_opt & (~INT_BULK_SEL);
 342         else
 343                 usb_opt = usb_opt | (INT_BULK_SEL);
 344
 345         rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, usb_opt );
 346
 347 #endif//CONFIG_SUPPORT_USB_INT
 348
 349 }
 350
 351
 352 static VOID
 353 _InitQueueReservedPage(
 354         IN  PADAPTER Adapter
 355         )
 356 {
 357         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
 358         struct registry_priv    *pregistrypriv = &Adapter->registrypriv;
 359         u32                     outEPNum        = (u32)pHalData->OutEpNumber;
 360         u32                     numHQ           = 0;
 361         u32                     numLQ           = 0;
 362         u32                     numNQ           = 0;
 363         u32                     numPubQ = 0x00;
 364         u32                     value32;
 365         u8                      value8;
 366         BOOLEAN                 bWiFiConfig     = pregistrypriv->wifi_spec;
 367
 368         if(bWiFiConfig || pregistrypriv->qos_opt_enable)
 369         {
 370                 if (pHalData->OutEpQueueSel & TX_SELE_HQ)
 371                         numHQ =  WMM_NORMAL_PAGE_NUM_HPQ_88E;
 372
 373                 if (pHalData->OutEpQueueSel & TX_SELE_LQ)
 374                         numLQ = WMM_NORMAL_PAGE_NUM_LPQ_88E;
 375
 376                 // NOTE: This step shall be proceed before writting REG_RQPN.
 377                 if (pHalData->OutEpQueueSel & TX_SELE_NQ)
 378                         numNQ = WMM_NORMAL_PAGE_NUM_NPQ_88E;
 379         }
 380         else
 381         {
 382                 if(pHalData->OutEpQueueSel & TX_SELE_HQ)
 383                         numHQ = NORMAL_PAGE_NUM_HPQ_88E;
 384
 385                 if(pHalData->OutEpQueueSel & TX_SELE_LQ)
 386                         numLQ = NORMAL_PAGE_NUM_LPQ_88E;
 387
 388                 // NOTE: This step shall be proceed before writting REG_RQPN.
 389                 if(pHalData->OutEpQueueSel & TX_SELE_NQ)
 390                         numNQ = NORMAL_PAGE_NUM_NPQ_88E;
 391         }
 392
 393         value8 = (u8)_NPQ(numNQ);
 394         rtw_write8(Adapter, REG_RQPN_NPQ, value8);
 395
 396         numPubQ = TX_TOTAL_PAGE_NUMBER_88E - numHQ - numLQ - numNQ;
 397
 398         // TX DMA
 399         value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
 400         rtw_write32(Adapter, REG_RQPN, value32);
 401 }
 402
 403 static VOID
 404 _InitTxBufferBoundary(
 405         IN PADAPTER Adapter,
 406         IN u8 txpktbuf_bndy
 407         )
 408 {
 409         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 410         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
 411
 412         //u16   txdmactrl;
 413
 414         rtw_write8(Adapter, REG_BCNQ_BDNY, txpktbuf_bndy);
 415         rtw_write8(Adapter, REG_MGQ_BDNY, txpktbuf_bndy);
 416         rtw_write8(Adapter, REG_WMAC_LBK_BF_HD, txpktbuf_bndy);
 417         rtw_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy);
 418         rtw_write8(Adapter, REG_TDECTRL+1, txpktbuf_bndy);
 419
 420 }
 421
 422 static VOID
 423 _InitPageBoundary(
 424         IN  PADAPTER Adapter
 425         )
 426 {
 427         // RX Page Boundary
 428         //
 429         u16 rxff_bndy = MAX_RX_DMA_BUFFER_SIZE_88E-1;
 430
 431         #if 0
 432
 433         // RX Page Boundary
 434         //srand(static_cast<unsigned int>(time(NULL)) );
 435         if(bSupportRemoteWakeUp)
 436         {
 437                 Offset = MAX_RX_DMA_BUFFER_SIZE_88E+MAX_TX_REPORT_BUFFER_SIZE-MAX_SUPPORT_WOL_PATTERN_NUM(Adapter)*WKFMCAM_SIZE;
 438                 Offset = Offset / 128; // RX page size = 128 byte
 439                 rxff_bndy= (Offset*128) -1;
 440         }
 441         else
 442
 443         #endif
 444         rtw_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
 445 }
 446
 447
 448 static VOID
 449 _InitNormalChipRegPriority(
 450         IN      PADAPTER        Adapter,
 451         IN      u16             beQ,
 452         IN      u16             bkQ,
 453         IN      u16             viQ,
 454         IN      u16             voQ,
 455         IN      u16             mgtQ,
 456         IN      u16             hiQ
 457         )
 458 {
 459         u16 value16     = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
 460
 461         value16 |=      _TXDMA_BEQ_MAP(beQ)     | _TXDMA_BKQ_MAP(bkQ) |
 462                                 _TXDMA_VIQ_MAP(viQ)     | _TXDMA_VOQ_MAP(voQ) |
 463                                 _TXDMA_MGQ_MAP(mgtQ)| _TXDMA_HIQ_MAP(hiQ);
 464
 465         rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
 466 }
 467
 468 static VOID
 469 _InitNormalChipOneOutEpPriority(
 470         IN      PADAPTER Adapter
 471         )
 472 {
 473         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 474
 475         u16     value = 0;
 476         switch(pHalData->OutEpQueueSel)
 477         {
 478                 case TX_SELE_HQ:
 479                         value = QUEUE_HIGH;
 480                         break;
 481                 case TX_SELE_LQ:
 482                         value = QUEUE_LOW;
 483                         break;
 484                 case TX_SELE_NQ:
 485                         value = QUEUE_NORMAL;
 486                         break;
 487                 default:
 488                         //RT_ASSERT(FALSE,("Shall not reach here!\n"));
 489                         break;
 490         }
 491
 492         _InitNormalChipRegPriority(Adapter,
 493                                                                 value,
 494                                                                 value,
 495                                                                 value,
 496                                                                 value,
 497                                                                 value,
 498                                                                 value
 499                                                                 );
 500
 501 }
 502
 503 static VOID
 504 _InitNormalChipTwoOutEpPriority(
 505         IN      PADAPTER Adapter
 506         )
 507 {
 508         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 509         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 510         u16                     beQ,bkQ,viQ,voQ,mgtQ,hiQ;
 511
 512
 513         u16     valueHi = 0;
 514         u16     valueLow = 0;
 515
 516         switch(pHalData->OutEpQueueSel)
 517         {
 518                 case (TX_SELE_HQ | TX_SELE_LQ):
 519                         valueHi = QUEUE_HIGH;
 520                         valueLow = QUEUE_LOW;
 521                         break;
 522                 case (TX_SELE_NQ | TX_SELE_LQ):
 523                         valueHi = QUEUE_NORMAL;
 524                         valueLow = QUEUE_LOW;
 525                         break;
 526                 case (TX_SELE_HQ | TX_SELE_NQ):
 527                         valueHi = QUEUE_HIGH;
 528                         valueLow = QUEUE_NORMAL;
 529                         break;
 530                 default:
 531                         //RT_ASSERT(FALSE,("Shall not reach here!\n"));
 532                         break;
 533         }
 534
 535         if(!pregistrypriv->wifi_spec ){
 536                 beQ             = valueLow;
 537                 bkQ             = valueLow;
 538                 viQ             = valueHi;
 539                 voQ             = valueHi;
 540                 mgtQ    = valueHi;
 541                 hiQ             = valueHi;
 542         }
 543         else{//for WMM ,CONFIG_OUT_EP_WIFI_MODE
 544                 beQ             = valueLow;
 545                 bkQ             = valueHi;
 546                 viQ             = valueHi;
 547                 voQ             = valueLow;
 548                 mgtQ    = valueHi;
 549                 hiQ             = valueHi;
 550         }
 551
 552         _InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
 553
 554 }
 555
 556 static VOID
 557 _InitNormalChipThreeOutEpPriority(
 558         IN      PADAPTER Adapter
 559         )
 560 {
 561         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 562         u16                     beQ,bkQ,viQ,voQ,mgtQ,hiQ;
 563
 564         if(!pregistrypriv->wifi_spec ){// typical setting
 565                 beQ             = QUEUE_LOW;
 566                 bkQ             = QUEUE_LOW;
 567                 viQ             = QUEUE_NORMAL;
 568                 voQ             = QUEUE_HIGH;
 569                 mgtQ    = QUEUE_HIGH;
 570                 hiQ             = QUEUE_HIGH;
 571         }
 572         else{// for WMM
 573                 beQ             = QUEUE_LOW;
 574                 bkQ             = QUEUE_NORMAL;
 575                 viQ             = QUEUE_NORMAL;
 576                 voQ             = QUEUE_HIGH;
 577                 mgtQ    = QUEUE_HIGH;
 578                 hiQ             = QUEUE_HIGH;
 579         }
 580         _InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
 581 }
 582
 583 static VOID
 584 _InitQueuePriority(
 585         IN      PADAPTER Adapter
 586         )
 587 {
 588         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
 589
 590         switch(pHalData->OutEpNumber)
 591         {
 592                 case 1:
 593                         _InitNormalChipOneOutEpPriority(Adapter);
 594                         break;
 595                 case 2:
 596                         _InitNormalChipTwoOutEpPriority(Adapter);
 597                         break;
 598                 case 3:
 599                         _InitNormalChipThreeOutEpPriority(Adapter);
 600                         break;
 601                 default:
 602                         //RT_ASSERT(FALSE,("Shall not reach here!\n"));
 603                         break;
 604         }
 605
 606
 607 }
 608
 609
 610
 611 static VOID
 612 _InitHardwareDropIncorrectBulkOut(
 613         IN  PADAPTER Adapter
 614         )
 615 {
 616 #ifdef ENABLE_USB_DROP_INCORRECT_OUT
 617         u32     value32 = rtw_read32(Adapter, REG_TXDMA_OFFSET_CHK);
 618         value32 |= DROP_DATA_EN;
 619         rtw_write32(Adapter, REG_TXDMA_OFFSET_CHK, value32);
 620 #endif
 621 }
 622
 623 static VOID
 624 _InitNetworkType(
 625         IN  PADAPTER Adapter
 626         )
 627 {
 628         u32     value32;
 629
 630         value32 = rtw_read32(Adapter, REG_CR);
 631         // TODO: use the other function to set network type
 632         value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
 633
 634         rtw_write32(Adapter, REG_CR, value32);
 635 //      RASSERT(pIoBase->rtw_read8(REG_CR + 2) == 0x2);
 636 }
 637
 638
 639 static VOID
 640 _InitDriverInfoSize(
 641         IN  PADAPTER    Adapter,
 642         IN      u8              drvInfoSize
 643         )
 644 {
 645         rtw_write8(Adapter,REG_RX_DRVINFO_SZ, drvInfoSize);
 646 }
 647
 648 static VOID
 649 _InitWMACSetting(
 650         IN  PADAPTER Adapter
 651         )
 652 {
 653         //u4Byte                        value32;
 654         //u16                   value16;
 655         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 656
 657         //pHalData->ReceiveConfig = AAP | APM | AM | AB | APP_ICV | ADF | AMF | APP_FCS | HTC_LOC_CTRL | APP_MIC | APP_PHYSTS;
 658         //pHalData->ReceiveConfig =
 659         //RCR_AAP | RCR_APM | RCR_AM | RCR_AB |RCR_CBSSID_DATA| RCR_CBSSID_BCN| RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | RCR_APP_PHYSTS;
 660          // don't turn on AAP, it will allow all packets to driver
 661         pHalData->ReceiveConfig = RCR_APM | RCR_AM | RCR_AB |RCR_CBSSID_DATA| RCR_CBSSID_BCN| RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | RCR_APP_PHYST_RXFF;
 662
 663 #if (1 == RTL8188E_RX_PACKET_INCLUDE_CRC)
 664         pHalData->ReceiveConfig |= ACRC32;
 665 #endif
 666
 667         // some REG_RCR will be modified later by phy_ConfigMACWithHeaderFile()
 668         rtw_write32(Adapter, REG_RCR, pHalData->ReceiveConfig);
 669
 670         // Accept all multicast address
 671         rtw_write32(Adapter, REG_MAR, 0xFFFFFFFF);
 672         rtw_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF);
 673
 674
 675         // Accept all data frames
 676         //value16 = 0xFFFF;
 677         //rtw_write16(Adapter, REG_RXFLTMAP2, value16);
 678
 679         // 2010.09.08 hpfan
 680         // Since ADF is removed from RCR, ps-poll will not be indicate to driver,
 681         // RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll.
 682         //value16 = 0x400;
 683         //rtw_write16(Adapter, REG_RXFLTMAP1, value16);
 684
 685         // Accept all management frames
 686         //value16 = 0xFFFF;
 687         //rtw_write16(Adapter, REG_RXFLTMAP0, value16);
 688
 689         //enable RX_SHIFT bits
 690         //rtw_write8(Adapter, REG_TRXDMA_CTRL, rtw_read8(Adapter, REG_TRXDMA_CTRL)|BIT(1));
 691
 692 }
 693
 694 static VOID
 695 _InitAdaptiveCtrl(
 696         IN  PADAPTER Adapter
 697         )
 698 {
 699         u16     value16;
 700         u32     value32;
 701
 702         // Response Rate Set
 703         value32 = rtw_read32(Adapter, REG_RRSR);
 704         value32 &= ~RATE_BITMAP_ALL;
 705         value32 |= RATE_RRSR_CCK_ONLY_1M;
 706         rtw_write32(Adapter, REG_RRSR, value32);
 707
 708         // CF-END Threshold
 709         //m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1);
 710
 711         // SIFS (used in NAV)
 712         value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
 713         rtw_write16(Adapter, REG_SPEC_SIFS, value16);
 714
 715         // Retry Limit
 716         value16 = _LRL(0x30) | _SRL(0x30);
 717         rtw_write16(Adapter, REG_RL, value16);
 718
 719 }
 720
 721 static VOID
 722 _InitRateFallback(
 723         IN  PADAPTER Adapter
 724         )
 725 {
 726         // Set Data Auto Rate Fallback Retry Count register.
 727         rtw_write32(Adapter, REG_DARFRC, 0x00000000);
 728         rtw_write32(Adapter, REG_DARFRC+4, 0x10080404);
 729         rtw_write32(Adapter, REG_RARFRC, 0x04030201);
 730         rtw_write32(Adapter, REG_RARFRC+4, 0x08070605);
 731
 732 }
 733
 734
 735 static VOID
 736 _InitEDCA(
 737         IN  PADAPTER Adapter
 738         )
 739 {
 740         // Set Spec SIFS (used in NAV)
 741         rtw_write16(Adapter,REG_SPEC_SIFS, 0x100a);
 742         rtw_write16(Adapter,REG_MAC_SPEC_SIFS, 0x100a);
 743
 744         // Set SIFS for CCK
 745         rtw_write16(Adapter,REG_SIFS_CTX, 0x100a);
 746
 747         // Set SIFS for OFDM
 748         rtw_write16(Adapter,REG_SIFS_TRX, 0x100a);
 749
 750         // TXOP
 751         rtw_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B);
 752         rtw_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F);
 753         rtw_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324);
 754         rtw_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226);
 755 }
 756
 757
 758 static VOID
 759 _InitBeaconMaxError(
 760         IN  PADAPTER    Adapter,
 761         IN      BOOLEAN         InfraMode
 762         )
 763 {
 764
 765 }
 766
 767
 768 #ifdef CONFIG_LED
 769 static void _InitHWLed(PADAPTER Adapter)
 770 {
 771         struct led_priv *pledpriv = &(Adapter->ledpriv);
 772
 773         if( pledpriv->LedStrategy != HW_LED)
 774                 return;
 775
 776 // HW led control
 777 // to do ....
 778 //must consider cases of antenna diversity/ commbo card/solo card/mini card
 779
 780 }
 781 #endif //CONFIG_LED
 782
 783 static VOID
 784 _InitRDGSetting(
 785         IN      PADAPTER Adapter
 786         )
 787 {
 788         rtw_write8(Adapter,REG_RD_CTRL,0xFF);
 789         rtw_write16(Adapter, REG_RD_NAV_NXT, 0x200);
 790         rtw_write8(Adapter,REG_RD_RESP_PKT_TH,0x05);
 791 }
 792
 793 static VOID
 794 _InitRxSetting(
 795         IN      PADAPTER Adapter
 796         )
 797 {
 798         rtw_write32(Adapter, REG_MACID, 0x87654321);
 799         rtw_write32(Adapter, 0x0700, 0x87654321);
 800 }
 801
 802 static VOID
 803 _InitRetryFunction(
 804         IN  PADAPTER Adapter
 805         )
 806 {
 807         u8      value8;
 808
 809         value8 = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL);
 810         value8 |= EN_AMPDU_RTY_NEW;
 811         rtw_write8(Adapter, REG_FWHW_TXQ_CTRL, value8);
 812
 813         // Set ACK timeout
 814         rtw_write8(Adapter, REG_ACKTO, 0x40);
 815 }
 816
 817 /*-----------------------------------------------------------------------------
 818  * Function:    usb_AggSettingTxUpdate()
 819  *
 820  * Overview:    Seperate TX/RX parameters update independent for TP detection and
 821  *                      dynamic TX/RX aggreagtion parameters update.
 822  *
 823  * Input:                       PADAPTER
 824  *
 825  * Output/Return:       NONE
 826  *
 827  * Revised History:
 828  *      When            Who             Remark
 829  *      12/10/2010      MHC             Seperate to smaller function.
 830  *
 831  *---------------------------------------------------------------------------*/
 832 static VOID
 833 usb_AggSettingTxUpdate(
 834         IN      PADAPTER                        Adapter
 835         )
 836 {
 837 #ifdef CONFIG_USB_TX_AGGREGATION
 838         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 839         //PMGNT_INFO            pMgntInfo = &(Adapter->MgntInfo);
 840         u32                     value32;
 841
 842         if(Adapter->registrypriv.wifi_spec)
 843                 pHalData->UsbTxAggMode = _FALSE;
 844
 845         if(pHalData->UsbTxAggMode){
 846                 value32 = rtw_read32(Adapter, REG_TDECTRL);
 847                 value32 = value32 & ~(BLK_DESC_NUM_MASK << BLK_DESC_NUM_SHIFT);
 848                 value32 |= ((pHalData->UsbTxAggDescNum & BLK_DESC_NUM_MASK) << BLK_DESC_NUM_SHIFT);
 849
 850                 rtw_write32(Adapter, REG_TDECTRL, value32);
 851         }
 852
 853 #endif
 854 }       // usb_AggSettingTxUpdate
 855
 856
 857 /*-----------------------------------------------------------------------------
 858  * Function:    usb_AggSettingRxUpdate()
 859  *
 860  * Overview:    Seperate TX/RX parameters update independent for TP detection and
 861  *                      dynamic TX/RX aggreagtion parameters update.
 862  *
 863  * Input:                       PADAPTER
 864  *
 865  * Output/Return:       NONE
 866  *
 867  * Revised History:
 868  *      When            Who             Remark
 869  *      12/10/2010      MHC             Seperate to smaller function.
 870  *
 871  *---------------------------------------------------------------------------*/
 872 static VOID
 873 usb_AggSettingRxUpdate(
 874         IN      PADAPTER                        Adapter
 875         )
 876 {
 877 #ifdef CONFIG_USB_RX_AGGREGATION
 878         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 879         //PMGNT_INFO            pMgntInfo = &(Adapter->MgntInfo);
 880         u8                      valueDMA;
 881         u8                      valueUSB;
 882
 883         valueDMA = rtw_read8(Adapter, REG_TRXDMA_CTRL);
 884         valueUSB = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION);
 885
 886         switch(pHalData->UsbRxAggMode)
 887         {
 888                 case USB_RX_AGG_DMA:
 889                         valueDMA |= RXDMA_AGG_EN;
 890                         valueUSB &= ~USB_AGG_EN;
 891                         break;
 892                 case USB_RX_AGG_USB:
 893                         valueDMA &= ~RXDMA_AGG_EN;
 894                         valueUSB |= USB_AGG_EN;
 895                         break;
 896                 case USB_RX_AGG_MIX:
 897                         valueDMA |= RXDMA_AGG_EN;
 898                         valueUSB |= USB_AGG_EN;
 899                         break;
 900                 case USB_RX_AGG_DISABLE:
 901                 default:
 902                         valueDMA &= ~RXDMA_AGG_EN;
 903                         valueUSB &= ~USB_AGG_EN;
 904                         break;
 905         }
 906
 907         rtw_write8(Adapter, REG_TRXDMA_CTRL, valueDMA);
 908         rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, valueUSB);
 909
 910         switch(pHalData->UsbRxAggMode)
 911         {
 912                 case USB_RX_AGG_DMA:
 913                         rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, pHalData->UsbRxAggPageCount);
 914                         rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH+1, pHalData->UsbRxAggPageTimeout);
 915                         break;
 916                 case USB_RX_AGG_USB:
 917                         rtw_write8(Adapter, REG_USB_AGG_TH, pHalData->UsbRxAggBlockCount);
 918                         rtw_write8(Adapter, REG_USB_AGG_TO, pHalData->UsbRxAggBlockTimeout);
 919                         break;
 920                 case USB_RX_AGG_MIX:
 921                         rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, pHalData->UsbRxAggPageCount);
 922                         rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH+1, (pHalData->UsbRxAggPageTimeout& 0x1F));//0x280[12:8]
 923
 924                         rtw_write8(Adapter, REG_USB_AGG_TH, pHalData->UsbRxAggBlockCount);
 925                         rtw_write8(Adapter, REG_USB_AGG_TO, pHalData->UsbRxAggBlockTimeout);
 926
 927                         break;
 928                 case USB_RX_AGG_DISABLE:
 929                 default:
 930                         // TODO:
 931                         break;
 932         }
 933
 934         switch(PBP_128)
 935         {
 936                 case PBP_128:
 937                         pHalData->HwRxPageSize = 128;
 938                         break;
 939                 case PBP_64:
 940                         pHalData->HwRxPageSize = 64;
 941                         break;
 942                 case PBP_256:
 943                         pHalData->HwRxPageSize = 256;
 944                         break;
 945                 case PBP_512:
 946                         pHalData->HwRxPageSize = 512;
 947                         break;
 948                 case PBP_1024:
 949                         pHalData->HwRxPageSize = 1024;
 950                         break;
 951                 default:
 952                         //RT_ASSERT(FALSE, ("RX_PAGE_SIZE_REG_VALUE definition is incorrect!\n"));
 953                         break;
 954         }
 955 #endif
 956 }       // usb_AggSettingRxUpdate
 957
 958 static VOID
 959 InitUsbAggregationSetting(
 960         IN  PADAPTER Adapter
 961         )
 962 {
 963         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 964
 965         // Tx aggregation setting
 966         usb_AggSettingTxUpdate(Adapter);
 967
 968         // Rx aggregation setting
 969         usb_AggSettingRxUpdate(Adapter);
 970
 971         // 201/12/10 MH Add for USB agg mode dynamic switch.
 972         pHalData->UsbRxHighSpeedMode = _FALSE;
 973 }
 974 VOID
 975 HalRxAggr8188EUsb(
 976         IN  PADAPTER Adapter,
 977         IN BOOLEAN      Value
 978         )
 979 {
 980 #if 0//USB_RX_AGGREGATION_92C
 981
 982         PMGNT_INFO              pMgntInfo = &Adapter->MgntInfo;
 983         u1Byte                  valueDMATimeout;
 984         u1Byte                  valueDMAPageCount;
 985         u1Byte                  valueUSBTimeout;
 986         u1Byte                  valueUSBBlockCount;
 987
 988         // selection to prevent bad TP.
 989         if( IS_WIRELESS_MODE_B(Adapter) || IS_WIRELESS_MODE_G(Adapter) || IS_WIRELESS_MODE_A(Adapter)|| pMgntInfo->bWiFiConfg)
 990         {
 991                 // 2010.04.27 hpfan
 992                 // Adjust RxAggrTimeout to close to zero disable RxAggr, suggested by designer
 993                 // Timeout value is calculated by 34 / (2^n)
 994                 valueDMATimeout = 0x0f;
 995                 valueDMAPageCount = 0x01;
 996                 valueUSBTimeout = 0x0f;
 997                 valueUSBBlockCount = 0x01;
 998                 rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_PGTO, (pu1Byte)&valueDMATimeout);
 999                 rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_PGTH, (pu1Byte)&valueDMAPageCount);
1000                 rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTO, (pu1Byte)&valueUSBTimeout);
1001                 rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTH, (pu1Byte)&valueUSBBlockCount);
1002         }
1003         else
1004         {
1005                 rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTO, (pu1Byte)&pMgntInfo->RegRxAggBlockTimeout);
1006                 rtw_hal_set_hwreg(Adapter, HW_VAR_RX_AGGR_USBTH, (pu1Byte)&pMgntInfo->RegRxAggBlockCount);
1007         }
1008
1009 #endif
1010 }
1011
1012 /*-----------------------------------------------------------------------------
1013  * Function:    USB_AggModeSwitch()
1014  *
1015  * Overview:    When RX traffic is more than 40M, we need to adjust some parameters to increase
1016  *                      RX speed by increasing batch indication size. This will decrease TCP ACK speed, we
1017  *                      need to monitor the influence of FTP/network share.
1018  *                      For TX mode, we are still ubder investigation.
1019  *
1020  * Input:               PADAPTER
1021  *
1022  * Output:              NONE
1023  *
1024  * Return:              NONE
1025  *
1026  * Revised History:
1027  *      When            Who             Remark
1028  *      12/10/2010      MHC             Create Version 0.
1029  *
1030  *---------------------------------------------------------------------------*/
1031 VOID
1032 USB_AggModeSwitch(
1033         IN      PADAPTER                        Adapter
1034         )
1035 {
1036 #if 0
1037         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1038         PMGNT_INFO              pMgntInfo = &(Adapter->MgntInfo);
1039
1040         //pHalData->UsbRxHighSpeedMode = FALSE;
1041         // How to measure the RX speed? We assume that when traffic is more than
1042         if (pMgntInfo->bRegAggDMEnable == FALSE)
1043         {
1044                 return; // Inf not support.
1045         }
1046
1047
1048         if (pMgntInfo->LinkDetectInfo.bHigherBusyRxTraffic == TRUE &&
1049                 pHalData->UsbRxHighSpeedMode == FALSE)
1050         {
1051                 pHalData->UsbRxHighSpeedMode = TRUE;
1052                 RT_TRACE(COMP_INIT, DBG_LOUD, ("UsbAggModeSwitchCheck to HIGH\n"));
1053         }
1054         else if (pMgntInfo->LinkDetectInfo.bHigherBusyRxTraffic == FALSE &&
1055                 pHalData->UsbRxHighSpeedMode == TRUE)
1056         {
1057                 pHalData->UsbRxHighSpeedMode = FALSE;
1058                 RT_TRACE(COMP_INIT, DBG_LOUD, ("UsbAggModeSwitchCheck to LOW\n"));
1059         }
1060         else
1061         {
1062                 return;
1063         }
1064
1065
1066 #if USB_RX_AGGREGATION_92C
1067         if (pHalData->UsbRxHighSpeedMode == TRUE)
1068         {
1069                 // 2010/12/10 MH The parameter is tested by SD1 engineer and SD3 channel emulator.
1070                 // USB mode
1071 #if (RT_PLATFORM == PLATFORM_LINUX)
1072                 if (pMgntInfo->LinkDetectInfo.bTxBusyTraffic)
1073                 {
1074                         pHalData->RxAggBlockCount       = 16;
1075                         pHalData->RxAggBlockTimeout     = 7;
1076                 }
1077                 else
1078 #endif
1079                 {
1080                         pHalData->RxAggBlockCount       = 40;
1081                         pHalData->RxAggBlockTimeout     = 5;
1082                 }
1083                 // Mix mode
1084                 pHalData->RxAggPageCount        = 72;
1085                 pHalData->RxAggPageTimeout      = 6;
1086         }
1087         else
1088         {
1089                 // USB mode
1090                 pHalData->RxAggBlockCount       = pMgntInfo->RegRxAggBlockCount;
1091                 pHalData->RxAggBlockTimeout     = pMgntInfo->RegRxAggBlockTimeout;
1092                 // Mix mode
1093                 pHalData->RxAggPageCount                = pMgntInfo->RegRxAggPageCount;
1094                 pHalData->RxAggPageTimeout      = pMgntInfo->RegRxAggPageTimeout;
1095         }
1096
1097         if (pHalData->RxAggBlockCount > MAX_RX_AGG_BLKCNT)
1098                 pHalData->RxAggBlockCount = MAX_RX_AGG_BLKCNT;
1099 #if (OS_WIN_FROM_VISTA(OS_VERSION)) || (RT_PLATFORM == PLATFORM_LINUX)  // do not support WINXP to prevent usbehci.sys BSOD
1100         if (IS_WIRELESS_MODE_N_24G(Adapter) || IS_WIRELESS_MODE_N_5G(Adapter))
1101         {
1102                 //
1103                 // 2010/12/24 MH According to V1012 QC IOT test, XP BSOD happen when running chariot test
1104                 // with the aggregation dynamic change!! We need to disable the function to prevent it is broken
1105                 // in usbehci.sys.
1106                 //
1107                 usb_AggSettingRxUpdate_8188E(Adapter);
1108
1109                 // 2010/12/27 MH According to designer's suggstion, we can only modify Timeout value. Otheriwse
1110                 // there might many HW incorrect behavior, the XP BSOD at usbehci.sys may be relative to the
1111                 // issue. Base on the newest test, we can not enable block cnt > 30, otherwise XP usbehci.sys may
1112                 // BSOD.
1113         }
1114 #endif
1115
1116 #endif
1117 #endif
1118 }       // USB_AggModeSwitch
1119
1120 static VOID
1121 _InitOperationMode(
1122         IN      PADAPTER                        Adapter
1123         )
1124 {
1125 #if 0//gtest
1126         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(Adapter);
1127         u1Byte                          regBwOpMode = 0;
1128         u4Byte                          regRATR = 0, regRRSR = 0;
1129
1130
1131         //1 This part need to modified according to the rate set we filtered!!
1132         //
1133         // Set RRSR, RATR, and REG_BWOPMODE registers
1134         //
1135         switch(Adapter->RegWirelessMode)
1136         {
1137                 case WIRELESS_MODE_B:
1138                         regBwOpMode = BW_OPMODE_20MHZ;
1139                         regRATR = RATE_ALL_CCK;
1140                         regRRSR = RATE_ALL_CCK;
1141                         break;
1142                 case WIRELESS_MODE_A:
1143                         regBwOpMode = BW_OPMODE_5G |BW_OPMODE_20MHZ;
1144                         regRATR = RATE_ALL_OFDM_AG;
1145                         regRRSR = RATE_ALL_OFDM_AG;
1146                         break;
1147                 case WIRELESS_MODE_G:
1148                         regBwOpMode = BW_OPMODE_20MHZ;
1149                         regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1150                         regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1151                         break;
1152                 case WIRELESS_MODE_AUTO:
1153                         if (Adapter->bInHctTest)
1154                         {
1155                             regBwOpMode = BW_OPMODE_20MHZ;
1156                             regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1157                             regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1158                         }
1159                         else
1160                         {
1161                             regBwOpMode = BW_OPMODE_20MHZ;
1162                             regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
1163                             regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1164                         }
1165                         break;
1166                 case WIRELESS_MODE_N_24G:
1167                         // It support CCK rate by default.
1168                         // CCK rate will be filtered out only when associated AP does not support it.
1169                         regBwOpMode = BW_OPMODE_20MHZ;
1170                                 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
1171                                 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1172                         break;
1173                 case WIRELESS_MODE_N_5G:
1174                         regBwOpMode = BW_OPMODE_5G;
1175                         regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
1176                         regRRSR = RATE_ALL_OFDM_AG;
1177                         break;
1178
1179                 default: //for MacOSX compiler warning.
1180                         break;
1181         }
1182
1183         // Ziv ????????
1184         //PlatformEFIOWrite4Byte(Adapter, REG_INIRTS_RATE_SEL, regRRSR);
1185         PlatformEFIOWrite1Byte(Adapter, REG_BWOPMODE, regBwOpMode);
1186 #endif
1187 }
1188
1189
1190  static VOID
1191 _InitBeaconParameters(
1192         IN  PADAPTER Adapter
1193         )
1194 {
1195         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1196
1197         rtw_write16(Adapter, REG_BCN_CTRL, 0x1010);
1198
1199         // TODO: Remove these magic number
1200         rtw_write16(Adapter, REG_TBTT_PROHIBIT,0x6404);// ms
1201         rtw_write8(Adapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME_8188E);// 5ms
1202         rtw_write8(Adapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME_8188E); // 2ms
1203
1204         // Suggested by designer timchen. Change beacon AIFS to the largest number
1205         // beacause test chip does not contension before sending beacon. by tynli. 2009.11.03
1206         rtw_write16(Adapter, REG_BCNTCFG, 0x660F);
1207
1208         pHalData->RegBcnCtrlVal = rtw_read8(Adapter, REG_BCN_CTRL);
1209         pHalData->RegTxPause = rtw_read8(Adapter, REG_TXPAUSE);
1210         pHalData->RegFwHwTxQCtrl = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL+2);
1211         pHalData->RegReg542 = rtw_read8(Adapter, REG_TBTT_PROHIBIT+2);
1212         pHalData->RegCR_1 = rtw_read8(Adapter, REG_CR+1);
1213 }
1214
1215 static VOID
1216 _InitRFType(
1217         IN      PADAPTER Adapter
1218         )
1219 {
1220         struct registry_priv     *pregpriv = &Adapter->registrypriv;
1221         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
1222         BOOLEAN                 is92CU          = IS_92C_SERIAL(pHalData->VersionID);
1223
1224 #if     DISABLE_BB_RF
1225         pHalData->rf_chip       = RF_PSEUDO_11N;
1226         return;
1227 #endif
1228
1229         pHalData->rf_chip       = RF_6052;
1230
1231         if(_FALSE == is92CU){
1232                 pHalData->rf_type = RF_1T1R;
1233                 DBG_8192C("Set RF Chip ID to RF_6052 and RF type to 1T1R.\n");
1234                 return;
1235         }
1236
1237         // TODO: Consider that EEPROM set 92CU to 1T1R later.
1238         // Force to overwrite setting according to chip version. Ignore EEPROM setting.
1239         //pHalData->RF_Type = is92CU ? RF_2T2R : RF_1T1R;
1240         MSG_8192C("Set RF Chip ID to RF_6052 and RF type to %d.\n", pHalData->rf_type);
1241
1242 }
1243
1244
1245 static VOID
1246 _BeaconFunctionEnable(
1247         IN      PADAPTER                Adapter,
1248         IN      BOOLEAN                 Enable,
1249         IN      BOOLEAN                 Linked
1250         )
1251 {
1252         rtw_write8(Adapter, REG_BCN_CTRL, (BIT4 | BIT3 | BIT1));
1253         //SetBcnCtrlReg(Adapter, (BIT4 | BIT3 | BIT1), 0x00);
1254         //RT_TRACE(COMP_BEACON, DBG_LOUD, ("_BeaconFunctionEnable 0x550 0x%x\n", PlatformEFIORead1Byte(Adapter, 0x550)));
1255
1256         rtw_write8(Adapter, REG_RD_CTRL+1, 0x6F);
1257 }
1258
1259
1260 // Set CCK and OFDM Block "ON"
1261 static VOID _BBTurnOnBlock(
1262         IN      PADAPTER                Adapter
1263         )
1264 {
1265 #if (DISABLE_BB_RF)
1266         return;
1267 #endif
1268
1269         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
1270         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
1271 }
1272
1273 static VOID _RfPowerSave(
1274         IN      PADAPTER                Adapter
1275         )
1276 {
1277 #if 0
1278         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
1279         PMGNT_INFO              pMgntInfo       = &(Adapter->MgntInfo);
1280         u1Byte                  eRFPath;
1281
1282 #if (DISABLE_BB_RF)
1283         return;
1284 #endif
1285
1286         if(pMgntInfo->RegRfOff == TRUE){ // User disable RF via registry.
1287                 RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter8192CUsb(): Turn off RF for RegRfOff.\n"));
1288                 MgntActSet_RF_State(Adapter, eRfOff, RF_CHANGE_BY_SW);
1289                 // Those action will be discard in MgntActSet_RF_State because off the same state
1290                 for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
1291                         PHY_SetRFReg(Adapter, eRFPath, 0x4, 0xC00, 0x0);
1292         }
1293         else if(pMgntInfo->RfOffReason > RF_CHANGE_BY_PS){ // H/W or S/W RF OFF before sleep.
1294                 RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter8192CUsb(): Turn off RF for RfOffReason(%ld).\n", pMgntInfo->RfOffReason));
1295                 MgntActSet_RF_State(Adapter, eRfOff, pMgntInfo->RfOffReason);
1296         }
1297         else{
1298                 pHalData->eRFPowerState = eRfOn;
1299                 pMgntInfo->RfOffReason = 0;
1300                 if(Adapter->bInSetPower || Adapter->bResetInProgress)
1301                         PlatformUsbEnableInPipes(Adapter);
1302                 RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter8192CUsb(): RF is on.\n"));
1303         }
1304 #endif
1305 }
1306
1307 enum {
1308         Antenna_Lfet = 1,
1309         Antenna_Right = 2,
1310 };
1311
1312 static VOID
1313 _InitAntenna_Selection(IN       PADAPTER Adapter)
1314 {
1315
1316         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(Adapter);
1317
1318         if(pHalData->AntDivCfg==0)
1319                 return;
1320         DBG_8192C("==>  %s ....\n",__FUNCTION__);
1321
1322         rtw_write32(Adapter, REG_LEDCFG0, rtw_read32(Adapter, REG_LEDCFG0)|BIT23);
1323         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);
1324
1325         if(PHY_QueryBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300) == MAIN_ANT)
1326                 pHalData->CurAntenna = MAIN_ANT;
1327         else
1328                 pHalData->CurAntenna = AUX_ANT;
1329         DBG_8192C("%s,Cur_ant:(%x)%s\n",__FUNCTION__,pHalData->CurAntenna,(pHalData->CurAntenna == MAIN_ANT)?"MAIN_ANT":"AUX_ANT");
1330
1331
1332 }
1333
1334 //
1335 // 2010/08/26 MH Add for selective suspend mode check.
1336 // If Efuse 0x0e bit1 is not enabled, we can not support selective suspend for Minicard and
1337 // slim card.
1338 //
1339 static VOID
1340 HalDetectSelectiveSuspendMode(
1341         IN PADAPTER                             Adapter
1342         )
1343 {
1344 #if 0
1345         u8      tmpvalue;
1346         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1347         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(Adapter);
1348
1349         // If support HW radio detect, we need to enable WOL ability, otherwise, we
1350         // can not use FW to notify host the power state switch.
1351
1352         EFUSE_ShadowRead(Adapter, 1, EEPROM_USB_OPTIONAL1, (u32 *)&tmpvalue);
1353
1354         DBG_8192C("HalDetectSelectiveSuspendMode(): SS ");
1355         if(tmpvalue & BIT1)
1356         {
1357                 DBG_8192C("Enable\n");
1358         }
1359         else
1360         {
1361                 DBG_8192C("Disable\n");
1362                 pdvobjpriv->RegUsbSS = _FALSE;
1363         }
1364
1365         // 2010/09/01 MH According to Dongle Selective Suspend INF. We can switch SS mode.
1366         if (pdvobjpriv->RegUsbSS && !SUPPORT_HW_RADIO_DETECT(pHalData))
1367         {
1368                 //PMGNT_INFO                            pMgntInfo = &(Adapter->MgntInfo);
1369
1370                 //if (!pMgntInfo->bRegDongleSS)
1371                 //{
1372                 //      RT_TRACE(COMP_INIT, DBG_LOUD, ("Dongle disable SS\n"));
1373                         pdvobjpriv->RegUsbSS = _FALSE;
1374                 //}
1375         }
1376 #endif
1377 }       // HalDetectSelectiveSuspendMode
1378 /*-----------------------------------------------------------------------------
1379  * Function:    HwSuspendModeEnable92Cu()
1380  *
1381  * Overview:    HW suspend mode switch.
1382  *
1383  * Input:               NONE
1384  *
1385  * Output:      NONE
1386  *
1387  * Return:      NONE
1388  *
1389  * Revised History:
1390  *      When            Who             Remark
1391  *      08/23/2010      MHC             HW suspend mode switch test..
1392  *---------------------------------------------------------------------------*/
1393 static VOID
1394 HwSuspendModeEnable_88eu(
1395         IN      PADAPTER        pAdapter,
1396         IN      u8                      Type
1397         )
1398 {
1399         //PRT_USB_DEVICE                pDevice = GET_RT_USB_DEVICE(pAdapter);
1400         u16     reg = rtw_read16(pAdapter, REG_GPIO_MUXCFG);
1401
1402         //if (!pDevice->RegUsbSS)
1403         {
1404                 return;
1405         }
1406
1407         //
1408         // 2010/08/23 MH According to Alfred's suggestion, we need to to prevent HW
1409         // to enter suspend mode automatically. Otherwise, it will shut down major power
1410         // domain and 8051 will stop. When we try to enter selective suspend mode, we
1411         // need to prevent HW to enter D2 mode aumotmatically. Another way, Host will
1412         // issue a S10 signal to power domain. Then it will cleat SIC setting(from Yngli).
1413         // We need to enable HW suspend mode when enter S3/S4 or disable. We need
1414         // to disable HW suspend mode for IPS/radio_off.
1415         //
1416         //RT_TRACE(COMP_RF, DBG_LOUD, ("HwSuspendModeEnable92Cu = %d\n", Type));
1417         if (Type == _FALSE)
1418         {
1419                 reg |= BIT14;
1420                 //RT_TRACE(COMP_RF, DBG_LOUD, ("REG_GPIO_MUXCFG = %x\n", reg));
1421                 rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
1422                 reg |= BIT12;
1423                 //RT_TRACE(COMP_RF, DBG_LOUD, ("REG_GPIO_MUXCFG = %x\n", reg));
1424                 rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
1425         }
1426         else
1427         {
1428                 reg &= (~BIT12);
1429                 rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
1430                 reg &= (~BIT14);
1431                 rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
1432         }
1433
1434 }       // HwSuspendModeEnable92Cu
1435 rt_rf_power_state RfOnOffDetect(IN      PADAPTER pAdapter )
1436 {
1437         struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(pAdapter);
1438         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(pAdapter);
1439         u8      val8;
1440         rt_rf_power_state rfpowerstate = rf_off;
1441
1442         if(pwrctl->bHWPowerdown)
1443         {
1444                 val8 = rtw_read8(pAdapter, REG_HSISR);
1445                 DBG_8192C("pwrdown, 0x5c(BIT7)=%02x\n", val8);
1446                 rfpowerstate = (val8 & BIT7) ? rf_off: rf_on;
1447         }
1448         else // rf on/off
1449         {
1450                 rtw_write8(     pAdapter, REG_MAC_PINMUX_CFG,rtw_read8(pAdapter, REG_MAC_PINMUX_CFG)&~(BIT3));
1451                 val8 = rtw_read8(pAdapter, REG_GPIO_IO_SEL);
1452                 DBG_8192C("GPIO_IN=%02x\n", val8);
1453                 rfpowerstate = (val8 & BIT3) ? rf_on : rf_off;
1454         }
1455         return rfpowerstate;
1456 }       // HalDetectPwrDownMode
1457
1458 void _ps_open_RF(_adapter *padapter);
1459
1460 u32 rtl8188eu_hal_init(PADAPTER Adapter)
1461 {
1462         u8      value8 = 0;
1463         u16  value16;
1464         u8      txpktbuf_bndy;
1465         u32     status = _SUCCESS;
1466         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
1467         struct pwrctrl_priv             *pwrctrlpriv = adapter_to_pwrctl(Adapter);
1468         struct registry_priv    *pregistrypriv = &Adapter->registrypriv;
1469
1470         rt_rf_power_state               eRfPowerStateToSet;
1471 #ifdef CONFIG_BT_COEXIST
1472         struct btcoexist_priv   *pbtpriv = &(pHalData->bt_coexist);
1473 #endif
1474
1475         u32 init_start_time = rtw_get_current_time();
1476
1477
1478 #ifdef DBG_HAL_INIT_PROFILING
1479
1480         enum HAL_INIT_STAGES {
1481                 HAL_INIT_STAGES_BEGIN = 0,
1482                 HAL_INIT_STAGES_INIT_PW_ON,
1483                 HAL_INIT_STAGES_MISC01,
1484                 HAL_INIT_STAGES_DOWNLOAD_FW,
1485                 HAL_INIT_STAGES_MAC,
1486                 HAL_INIT_STAGES_BB,
1487                 HAL_INIT_STAGES_RF,
1488                 HAL_INIT_STAGES_EFUSE_PATCH,
1489                 HAL_INIT_STAGES_INIT_LLTT,
1490
1491                 HAL_INIT_STAGES_MISC02,
1492                 HAL_INIT_STAGES_TURN_ON_BLOCK,
1493                 HAL_INIT_STAGES_INIT_SECURITY,
1494                 HAL_INIT_STAGES_MISC11,
1495                 HAL_INIT_STAGES_INIT_HAL_DM,
1496                 //HAL_INIT_STAGES_RF_PS,
1497                 HAL_INIT_STAGES_IQK,
1498                 HAL_INIT_STAGES_PW_TRACK,
1499                 HAL_INIT_STAGES_LCK,
1500                 //HAL_INIT_STAGES_MISC21,
1501                 //HAL_INIT_STAGES_INIT_PABIAS,
1502                 #ifdef CONFIG_BT_COEXIST
1503                 HAL_INIT_STAGES_BT_COEXIST,
1504                 #endif
1505                 //HAL_INIT_STAGES_ANTENNA_SEL,
1506                 //HAL_INIT_STAGES_MISC31,
1507                 HAL_INIT_STAGES_END,
1508                 HAL_INIT_STAGES_NUM
1509         };
1510
1511         char * hal_init_stages_str[] = {
1512                 "HAL_INIT_STAGES_BEGIN",
1513                 "HAL_INIT_STAGES_INIT_PW_ON",
1514                 "HAL_INIT_STAGES_MISC01",
1515                 "HAL_INIT_STAGES_DOWNLOAD_FW",
1516                 "HAL_INIT_STAGES_MAC",
1517                 "HAL_INIT_STAGES_BB",
1518                 "HAL_INIT_STAGES_RF",
1519                 "HAL_INIT_STAGES_EFUSE_PATCH",
1520                 "HAL_INIT_STAGES_INIT_LLTT",
1521                 "HAL_INIT_STAGES_MISC02",
1522                 "HAL_INIT_STAGES_TURN_ON_BLOCK",
1523                 "HAL_INIT_STAGES_INIT_SECURITY",
1524                 "HAL_INIT_STAGES_MISC11",
1525                 "HAL_INIT_STAGES_INIT_HAL_DM",
1526                 //"HAL_INIT_STAGES_RF_PS",
1527                 "HAL_INIT_STAGES_IQK",
1528                 "HAL_INIT_STAGES_PW_TRACK",
1529                 "HAL_INIT_STAGES_LCK",
1530                 //"HAL_INIT_STAGES_MISC21",
1531                 #ifdef CONFIG_BT_COEXIST
1532                 "HAL_INIT_STAGES_BT_COEXIST",
1533                 #endif
1534                 //"HAL_INIT_STAGES_ANTENNA_SEL",
1535                 //"HAL_INIT_STAGES_MISC31",
1536                 "HAL_INIT_STAGES_END",
1537         };
1538
1539         int hal_init_profiling_i;
1540         u32 hal_init_stages_timestamp[HAL_INIT_STAGES_NUM]; //used to record the time of each stage's starting point
1541
1542         for(hal_init_profiling_i=0;hal_init_profiling_i<HAL_INIT_STAGES_NUM;hal_init_profiling_i++)
1543                 hal_init_stages_timestamp[hal_init_profiling_i]=0;
1544
1545         #define HAL_INIT_PROFILE_TAG(stage) hal_init_stages_timestamp[(stage)]=rtw_get_current_time();
1546 #else
1547         #define HAL_INIT_PROFILE_TAG(stage) do {} while(0)
1548 #endif //DBG_HAL_INIT_PROFILING
1549
1550
1551
1552 _func_enter_;
1553
1554 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN);
1555
1556 #ifdef CONFIG_WOWLAN
1557
1558         pwrctrlpriv->wowlan_wake_reason = rtw_read8(Adapter, REG_WOWLAN_WAKE_REASON);
1559         DBG_8192C("%s wowlan_wake_reason: 0x%02x\n",
1560                                 __func__, pwrctrlpriv->wowlan_wake_reason);
1561
1562         if(rtw_read8(Adapter, REG_MCUFWDL)&BIT7){ /*&&
1563                 (pwrctrlpriv->wowlan_wake_reason & FWDecisionDisconnect)) {*/
1564                 u8 reg_val=0;
1565                 DBG_8192C("+Reset Entry+\n");
1566                 rtw_write8(Adapter, REG_MCUFWDL, 0x00);
1567                 _8051Reset88E(Adapter);
1568                 //reset BB
1569                 reg_val = rtw_read8(Adapter, REG_SYS_FUNC_EN);
1570                 reg_val &= ~(BIT(0) | BIT(1));
1571                 rtw_write8(Adapter, REG_SYS_FUNC_EN, reg_val);
1572                 //reset RF
1573                 rtw_write8(Adapter, REG_RF_CTRL, 0);
1574                 //reset TRX path
1575                 rtw_write16(Adapter, REG_CR, 0);
1576                 //reset MAC, Digital Core
1577                 reg_val = rtw_read8(Adapter, REG_SYS_FUNC_EN+1);
1578                 reg_val &= ~(BIT(4) | BIT(7));
1579                 rtw_write8(Adapter, REG_SYS_FUNC_EN+1, reg_val);
1580                 reg_val = rtw_read8(Adapter, REG_SYS_FUNC_EN+1);
1581                 reg_val |= BIT(4) | BIT(7);
1582                 rtw_write8(Adapter, REG_SYS_FUNC_EN+1, reg_val);
1583                 DBG_8192C("-Reset Entry-\n");
1584         }
1585 #endif //CONFIG_WOWLAN
1586
1587         if(pwrctrlpriv->bkeepfwalive)
1588         {
1589                 _ps_open_RF(Adapter);
1590
1591                 if(pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized){
1592 //                      PHY_IQCalibrate(padapter, _TRUE);
1593                         PHY_IQCalibrate_8188E(Adapter,_TRUE);
1594                 }
1595                 else
1596                 {
1597 //                      PHY_IQCalibrate(padapter, _FALSE);
1598                         PHY_IQCalibrate_8188E(Adapter,_FALSE);
1599                         pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = _TRUE;
1600                 }
1601
1602 //              dm_CheckTXPowerTracking(padapter);
1603 //              PHY_LCCalibrate(padapter);
1604                 ODM_TXPowerTrackingCheck(&pHalData->odmpriv );
1605                 PHY_LCCalibrate_8188E(&pHalData->odmpriv );
1606
1607                 goto exit;
1608         }
1609
1610
1611 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
1612         status = _InitPowerOn_8188EU(Adapter);
1613         if(status == _FAIL){
1614                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init power on!\n"));
1615                 goto exit;
1616         }
1617
1618         // Set RF type for BB/RF configuration
1619         _InitRFType(Adapter);//->_ReadRFType()
1620
1621         // Save target channel
1622         // <Roger_Notes> Current Channel will be updated again later.
1623         pHalData->CurrentChannel = 6;//default set to 6
1624         if(pwrctrlpriv->reg_rfoff == _TRUE){
1625                 pwrctrlpriv->rf_pwrstate = rf_off;
1626         }
1627
1628         // 2010/08/09 MH We need to check if we need to turnon or off RF after detecting
1629         // HW GPIO pin. Before PHY_RFConfig8192C.
1630         //HalDetectPwrDownMode(Adapter);
1631         // 2010/08/26 MH If Efuse does not support sective suspend then disable the function.
1632         //HalDetectSelectiveSuspendMode(Adapter);
1633
1634         if (!pregistrypriv->wifi_spec) {
1635                 txpktbuf_bndy = TX_PAGE_BOUNDARY_88E;
1636         } else {
1637                 // for WMM
1638                 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_88E;
1639         }
1640
1641 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01);
1642         _InitQueueReservedPage(Adapter);
1643         _InitQueuePriority(Adapter);
1644         _InitPageBoundary(Adapter);
1645         _InitTransferPageSize(Adapter);
1646
1647 #ifdef CONFIG_IOL_IOREG_CFG
1648         _InitTxBufferBoundary(Adapter, 0);
1649 #endif
1650
1651
1652
1653 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
1654 #if (MP_DRIVER == 1)
1655         if (Adapter->registrypriv.mp_mode == 1)
1656         {
1657                 _InitRxSetting(Adapter);
1658         }
1659 #endif  //MP_DRIVER == 1
1660         {
1661         #if 0
1662                 Adapter->bFWReady = _FALSE; //because no fw for test chip
1663                 pHalData->fw_ractrl = _FALSE;
1664         #else
1665
1666
1667                 status = rtl8188e_FirmwareDownload(Adapter, _FALSE);
1668
1669                 if (status != _SUCCESS) {
1670                         DBG_871X("%s: Download Firmware failed!!\n", __FUNCTION__);
1671                         Adapter->bFWReady = _FALSE;
1672                         pHalData->fw_ractrl = _FALSE;
1673                         return status;
1674                 } else {
1675                         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter8192CSdio(): Download Firmware Success!!\n"));
1676                         Adapter->bFWReady = _TRUE;
1677                         pHalData->fw_ractrl = _FALSE;
1678                 }
1679         #endif
1680         }
1681
1682
1683         rtl8188e_InitializeFirmwareVars(Adapter);
1684
1685
1686 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC);
1687 #if (HAL_MAC_ENABLE == 1)
1688         status = PHY_MACConfig8188E(Adapter);
1689         if(status == _FAIL)
1690         {
1691                 DBG_871X(" ### Failed to init MAC ...... \n ");
1692                 goto exit;
1693         }
1694 #endif
1695
1696         //
1697         //d. Initialize BB related configurations.
1698         //
1699 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB);
1700 #if (HAL_BB_ENABLE == 1)
1701         status = PHY_BBConfig8188E(Adapter);
1702         if(status == _FAIL)
1703         {
1704                 DBG_871X(" ### Failed to init BB ...... \n ");
1705                 goto exit;
1706         }
1707 #endif
1708
1709
1710 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF);
1711 #if (HAL_RF_ENABLE == 1)
1712         status = PHY_RFConfig8188E(Adapter);
1713         if(status == _FAIL)
1714         {
1715                 DBG_871X(" ### Failed to init RF ...... \n ");
1716                 goto exit;
1717         }
1718 #endif
1719
1720 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_EFUSE_PATCH);
1721 #if defined(CONFIG_IOL_EFUSE_PATCH)
1722         status = rtl8188e_iol_efuse_patch(Adapter);
1723         if(status == _FAIL){
1724                 DBG_871X("%s  rtl8188e_iol_efuse_patch failed \n",__FUNCTION__);
1725                 goto exit;
1726         }
1727 #endif
1728
1729         _InitTxBufferBoundary(Adapter, txpktbuf_bndy);
1730
1731 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT);
1732         status =  InitLLTTable(Adapter, txpktbuf_bndy);
1733         if(status == _FAIL){
1734                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init LLT table\n"));
1735                 goto exit;
1736         }
1737
1738 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
1739         // Get Rx PHY status in order to report RSSI and others.
1740         _InitDriverInfoSize(Adapter, DRVINFO_SZ);
1741
1742         _InitInterrupt(Adapter);
1743         hal_init_macaddr(Adapter);//set mac_address
1744         _InitNetworkType(Adapter);//set msr
1745         _InitWMACSetting(Adapter);
1746         _InitAdaptiveCtrl(Adapter);
1747         _InitEDCA(Adapter);
1748         //_InitRateFallback(Adapter);//just follow MP Team ???Georgia
1749         _InitRetryFunction(Adapter);
1750         InitUsbAggregationSetting(Adapter);
1751         _InitOperationMode(Adapter);//todo
1752         _InitBeaconParameters(Adapter);
1753         _InitBeaconMaxError(Adapter, _TRUE);
1754
1755         //
1756         // Init CR MACTXEN, MACRXEN after setting RxFF boundary REG_TRXFF_BNDY to patch
1757         // Hw bug which Hw initials RxFF boundry size to a value which is larger than the real Rx buffer size in 88E.
1758         //
1759         // Enable MACTXEN/MACRXEN block
1760         value16 = rtw_read16(Adapter, REG_CR);
1761         value16 |= (MACTXEN | MACRXEN);
1762         rtw_write8(Adapter, REG_CR, value16);
1763
1764         _InitHardwareDropIncorrectBulkOut(Adapter);
1765
1766
1767         if(pHalData->bRDGEnable){
1768                 _InitRDGSetting(Adapter);
1769         }
1770
1771 #if (RATE_ADAPTIVE_SUPPORT==1)
1772         {//Enable TX Report
1773                 //Enable Tx Report Timer
1774                 value8 = rtw_read8(Adapter, REG_TX_RPT_CTRL);
1775                 rtw_write8(Adapter,  REG_TX_RPT_CTRL, (value8|BIT1|BIT0));
1776                 //Set MAX RPT MACID
1777                 rtw_write8(Adapter,  REG_TX_RPT_CTRL+1, 2);//FOR sta mode ,0: bc/mc ,1:AP
1778                 //Tx RPT Timer. Unit: 32us
1779                 rtw_write16(Adapter, REG_TX_RPT_TIME, 0xCdf0);
1780         }
1781 #endif
1782
1783 #if 0
1784         if(pHTInfo->bRDGEnable){
1785                 _InitRDGSetting_8188E(Adapter);
1786         }
1787 #endif
1788
1789 #ifdef CONFIG_TX_EARLY_MODE
1790         if( pHalData->bEarlyModeEnable)
1791         {
1792                 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,("EarlyMode Enabled!!!\n"));
1793
1794                 value8 = rtw_read8(Adapter, REG_EARLY_MODE_CONTROL);
1795 #if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1
1796                 value8 = value8|0x1f;
1797 #else
1798                 value8 = value8|0xf;
1799 #endif
1800                 rtw_write8(Adapter, REG_EARLY_MODE_CONTROL, value8);
1801
1802                 rtw_write8(Adapter, REG_EARLY_MODE_CONTROL+3, 0x80);
1803
1804                 value8 = rtw_read8(Adapter, REG_TCR+1);
1805                 value8 = value8|0x40;
1806                 rtw_write8(Adapter,REG_TCR+1, value8);
1807         }
1808         else
1809 #endif
1810         {
1811                 rtw_write8(Adapter, REG_EARLY_MODE_CONTROL, 0);
1812         }
1813
1814         rtw_write32(Adapter,REG_MACID_NO_LINK_0,0xFFFFFFFF);
1815         rtw_write32(Adapter,REG_MACID_NO_LINK_1,0xFFFFFFFF);
1816
1817 #if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_TX_MCAST2UNI)
1818
1819 #ifdef CONFIG_CHECK_AC_LIFETIME
1820         // Enable lifetime check for the four ACs
1821         rtw_write8(Adapter, REG_LIFETIME_CTRL, 0x0F);
1822 #endif  // CONFIG_CHECK_AC_LIFETIME
1823
1824 #ifdef CONFIG_TX_MCAST2UNI
1825         rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400);  // unit: 256us. 256ms
1826         rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400);  // unit: 256us. 256ms
1827 #else   // CONFIG_TX_MCAST2UNI
1828         rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x3000);  // unit: 256us. 3s
1829         rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x3000);  // unit: 256us. 3s
1830 #endif  // CONFIG_TX_MCAST2UNI
1831 #endif  // CONFIG_CONCURRENT_MODE || CONFIG_TX_MCAST2UNI
1832
1833
1834 #ifdef CONFIG_LED
1835         _InitHWLed(Adapter);
1836 #endif //CONFIG_LED
1837
1838
1839         //
1840         // Joseph Note: Keep RfRegChnlVal for later use.
1841         //
1842         pHalData->RfRegChnlVal[0] = PHY_QueryRFReg(Adapter, 0, RF_CHNLBW, bRFRegOffsetMask);
1843         pHalData->RfRegChnlVal[1] = PHY_QueryRFReg(Adapter, 1, RF_CHNLBW, bRFRegOffsetMask);
1844
1845 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK);
1846         _BBTurnOnBlock(Adapter);
1847         //NicIFSetMacAddress(padapter, padapter->PermanentAddress);
1848
1849 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY);
1850         invalidate_cam_all(Adapter);
1851
1852 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11);
1853         // 2010/12/17 MH We need to set TX power according to EFUSE content at first.
1854         PHY_SetTxPowerLevel8188E(Adapter, pHalData->CurrentChannel);
1855
1856 // Move by Neo for USB SS to below setp
1857 //_RfPowerSave(Adapter);
1858
1859         _InitAntenna_Selection(Adapter);
1860
1861         //
1862         // Disable BAR, suggested by Scott
1863         // 2010.04.09 add by hpfan
1864         //
1865         rtw_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff);
1866
1867         // HW SEQ CTRL
1868         //set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM.
1869         rtw_write8(Adapter,REG_HWSEQ_CTRL, 0xFF);
1870
1871         if(pregistrypriv->wifi_spec)
1872                 rtw_write16(Adapter,REG_FAST_EDCA_CTRL ,0);
1873
1874         //Nav limit , suggest by scott
1875         rtw_write8(Adapter, 0x652, 0x0);
1876
1877 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
1878         rtl8188e_InitHalDm(Adapter);
1879
1880 #if (MP_DRIVER == 1)
1881         if (Adapter->registrypriv.mp_mode == 1)
1882         {
1883                 Adapter->mppriv.channel = pHalData->CurrentChannel;
1884                 MPT_InitializeAdapter(Adapter, Adapter->mppriv.channel);
1885         }
1886         else
1887 #endif  //#if (MP_DRIVER == 1)
1888         {
1889         //
1890         // 2010/08/11 MH Merge from 8192SE for Minicard init. We need to confirm current radio status
1891         // and then decide to enable RF or not.!!!??? For Selective suspend mode. We may not
1892         // call init_adapter. May cause some problem??
1893         //
1894         // Fix the bug that Hw/Sw radio off before S3/S4, the RF off action will not be executed
1895         // in MgntActSet_RF_State() after wake up, because the value of pHalData->eRFPowerState
1896         // is the same as eRfOff, we should change it to eRfOn after we config RF parameters.
1897         // Added by tynli. 2010.03.30.
1898         pwrctrlpriv->rf_pwrstate = rf_on;
1899
1900 #if 0  //to do
1901         RT_CLEAR_PS_LEVEL(pwrctrlpriv, RT_RF_OFF_LEVL_HALT_NIC);
1902 #if 1 //Todo
1903         // 20100326 Joseph: Copy from GPIOChangeRFWorkItemCallBack() function to check HW radio on/off.
1904         // 20100329 Joseph: Revise and integrate the HW/SW radio off code in initialization.
1905
1906         eRfPowerStateToSet = (rt_rf_power_state) RfOnOffDetect(Adapter);
1907         pwrctrlpriv->rfoff_reason |= eRfPowerStateToSet==rf_on ? RF_CHANGE_BY_INIT : RF_CHANGE_BY_HW;
1908         pwrctrlpriv->rfoff_reason |= (pwrctrlpriv->reg_rfoff) ? RF_CHANGE_BY_SW : 0;
1909
1910         if(pwrctrlpriv->rfoff_reason&RF_CHANGE_BY_HW)
1911                 pwrctrlpriv->b_hw_radio_off = _TRUE;
1912
1913         DBG_8192C("eRfPowerStateToSet=%d\n", eRfPowerStateToSet);
1914
1915         if(pwrctrlpriv->reg_rfoff == _TRUE)
1916         {       // User disable RF via registry.
1917                 DBG_8192C("InitializeAdapter8192CU(): Turn off RF for RegRfOff.\n");
1918                 //MgntActSet_RF_State(Adapter, rf_off, RF_CHANGE_BY_SW, _TRUE);
1919
1920                 // Those action will be discard in MgntActSet_RF_State because off the same state
1921                 //for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
1922                         //PHY_SetRFReg(Adapter, eRFPath, 0x4, 0xC00, 0x0);
1923         }
1924         else if(pwrctrlpriv->rfoff_reason > RF_CHANGE_BY_PS)
1925         {       // H/W or S/W RF OFF before sleep.
1926                 DBG_8192C(" Turn off RF for RfOffReason(%x) ----------\n", pwrctrlpriv->rfoff_reason);
1927                 //pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT;
1928                 pwrctrlpriv->rf_pwrstate = rf_on;
1929                 //MgntActSet_RF_State(Adapter, rf_off, pwrctrlpriv->rfoff_reason, _TRUE);
1930         }
1931         else
1932         {
1933                 // Perform GPIO polling to find out current RF state. added by Roger, 2010.04.09.
1934                 if(pHalData->BoardType == BOARD_MINICARD /*&& (Adapter->MgntInfo.PowerSaveControl.bGpioRfSw)*/)
1935                 {
1936                         DBG_8192C("InitializeAdapter8192CU(): RF=%d \n", eRfPowerStateToSet);
1937                         if (eRfPowerStateToSet == rf_off)
1938                         {
1939                                 //MgntActSet_RF_State(Adapter, rf_off, RF_CHANGE_BY_HW, _TRUE);
1940                                 pwrctrlpriv->b_hw_radio_off = _TRUE;
1941                         }
1942                         else
1943                         {
1944                                 pwrctrlpriv->rf_pwrstate = rf_off;
1945                                 pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT;
1946                                 pwrctrlpriv->b_hw_radio_off = _FALSE;
1947                                 //MgntActSet_RF_State(Adapter, rf_on, pwrctrlpriv->rfoff_reason, _TRUE);
1948                         }
1949                 }
1950                 else
1951                 {
1952                         pwrctrlpriv->rf_pwrstate = rf_off;
1953                         pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT;
1954                         //MgntActSet_RF_State(Adapter, rf_on, pwrctrlpriv->rfoff_reason, _TRUE);
1955                 }
1956
1957                 pwrctrlpriv->rfoff_reason = 0;
1958                 pwrctrlpriv->b_hw_radio_off = _FALSE;
1959                 pwrctrlpriv->rf_pwrstate = rf_on;
1960                 rtw_led_control(Adapter, LED_CTL_POWER_ON);
1961
1962         }
1963
1964         // 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c.
1965         // Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1.
1966         if(pHalData->pwrdown && eRfPowerStateToSet == rf_off)
1967         {
1968                 // Enable register area 0x0-0xc.
1969                 rtw_write8(Adapter, REG_RSV_CTRL, 0x0);
1970
1971                 //
1972                 // <Roger_Notes> We should configure HW PDn source for WiFi ONLY, and then
1973                 // our HW will be set in power-down mode if PDn source from all  functions are configured.
1974                 // 2010.10.06.
1975                 //
1976                 //if(IS_HARDWARE_TYPE_8723AU(Adapter))
1977                 //{
1978                 //      u1bTmp = rtw_read8(Adapter, REG_MULTI_FUNC_CTRL);
1979                 //      rtw_write8(Adapter, REG_MULTI_FUNC_CTRL, (u1bTmp|WL_HWPDN_EN));
1980                 //}
1981                 //else
1982                 //{
1983                         rtw_write16(Adapter, REG_APS_FSMCO, 0x8812);
1984                 //}
1985         }
1986         //DrvIFIndicateCurrentPhyStatus(Adapter); // 2010/08/17 MH Disable to prevent BSOD.
1987 #endif
1988 #endif
1989
1990
1991         // enable Tx report.
1992         rtw_write8(Adapter,  REG_FWHW_TXQ_CTRL+1, 0x0F);
1993
1994         // Suggested by SD1 pisa. Added by tynli. 2011.10.21.
1995         rtw_write8(Adapter, REG_EARLY_MODE_CONTROL+3, 0x01);//Pretx_en, for WEP/TKIP SEC
1996
1997         //tynli_test_tx_report.
1998         rtw_write16(Adapter, REG_TX_RPT_TIME, 0x3DF0);
1999         //RT_TRACE(COMP_INIT, DBG_TRACE, ("InitializeAdapter8188EUsb() <====\n"));
2000
2001         //enable tx DMA to drop the redundate data of packet
2002         rtw_write16(Adapter,REG_TXDMA_OFFSET_CHK, (rtw_read16(Adapter,REG_TXDMA_OFFSET_CHK) | DROP_DATA_EN));
2003
2004 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK);
2005         // 2010/08/26 MH Merge from 8192CE.
2006         if(pwrctrlpriv->rf_pwrstate == rf_on)
2007         {
2008                 if(pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized){
2009                         PHY_IQCalibrate_8188E(Adapter,_TRUE);
2010                 }
2011                 else
2012                 {
2013                         PHY_IQCalibrate_8188E(Adapter,_FALSE);
2014                         pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = _TRUE;
2015                 }
2016
2017 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK);
2018
2019                 ODM_TXPowerTrackingCheck(&pHalData->odmpriv );
2020
2021
2022 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK);
2023                 PHY_LCCalibrate_8188E(&pHalData->odmpriv );
2024         }
2025 }
2026
2027 //HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS);
2028 //      _InitPABias(Adapter);
2029         rtw_write8(Adapter, REG_USB_HRPWM, 0);
2030
2031 #ifdef CONFIG_XMIT_ACK
2032         //ack for xmit mgmt frames.
2033         rtw_write32(Adapter, REG_FWHW_TXQ_CTRL, rtw_read32(Adapter, REG_FWHW_TXQ_CTRL)|BIT(12));
2034 #endif //CONFIG_XMIT_ACK
2035
2036 exit:
2037 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END);
2038
2039         DBG_871X("%s in %dms\n", __FUNCTION__, rtw_get_passing_time_ms(init_start_time));
2040
2041         #ifdef DBG_HAL_INIT_PROFILING
2042         hal_init_stages_timestamp[HAL_INIT_STAGES_END]=rtw_get_current_time();
2043
2044         for(hal_init_profiling_i=0;hal_init_profiling_i<HAL_INIT_STAGES_NUM-1;hal_init_profiling_i++) {
2045                 DBG_871X("DBG_HAL_INIT_PROFILING: %35s, %u, %5u, %5u\n"
2046                         , hal_init_stages_str[hal_init_profiling_i]
2047                         , hal_init_stages_timestamp[hal_init_profiling_i]
2048                         , (hal_init_stages_timestamp[hal_init_profiling_i+1]-hal_init_stages_timestamp[hal_init_profiling_i])
2049                         , rtw_get_time_interval_ms(hal_init_stages_timestamp[hal_init_profiling_i], hal_init_stages_timestamp[hal_init_profiling_i+1])
2050                 );
2051         }
2052         #endif
2053
2054
2055 _func_exit_;
2056
2057         return status;
2058 }
2059
2060 void _ps_open_RF(_adapter *padapter) {
2061         //here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified
2062         //phy_SsPwrSwitch92CU(padapter, rf_on, 1);
2063 }
2064
2065 void _ps_close_RF(_adapter *padapter){
2066         //here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified
2067         //phy_SsPwrSwitch92CU(padapter, rf_off, 1);
2068 }
2069
2070
2071 VOID
2072 hal_poweroff_8188eu(
2073         IN      PADAPTER                        Adapter
2074 )
2075 {
2076
2077         u8      val8;
2078         u16     val16;
2079         u32     val32;
2080         u8 bMacPwrCtrlOn = _FALSE;
2081
2082         rtw_hal_get_hwreg(Adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
2083         if(bMacPwrCtrlOn == _FALSE)
2084                 return ;
2085
2086         RT_TRACE(COMP_INIT, DBG_LOUD, ("%s\n",__FUNCTION__));
2087
2088         //Stop Tx Report Timer. 0x4EC[Bit1]=b'0
2089         val8 = rtw_read8(Adapter, REG_TX_RPT_CTRL);
2090         rtw_write8(Adapter, REG_TX_RPT_CTRL, val8&(~BIT1));
2091
2092         // stop rx
2093         rtw_write8(Adapter, REG_CR, 0x0);
2094
2095         // Run LPS WL RFOFF flow
2096         HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_LPS_ENTER_FLOW);
2097
2098
2099         // 2. 0x1F[7:0] = 0             // turn off RF
2100         //rtw_write8(Adapter, REG_RF_CTRL, 0x00);
2101
2102         val8 = rtw_read8(Adapter, REG_MCUFWDL);
2103         if ((val8 & RAM_DL_SEL) && Adapter->bFWReady) //8051 RAM code
2104         {
2105                 //rtl8723a_FirmwareSelfReset(padapter);
2106                 //_8051Reset88E(padapter);
2107
2108                 // Reset MCU 0x2[10]=0.
2109                 val8 = rtw_read8(Adapter, REG_SYS_FUNC_EN+1);
2110                 val8 &= ~BIT(2);        // 0x2[10], FEN_CPUEN
2111                 rtw_write8(Adapter, REG_SYS_FUNC_EN+1, val8);
2112         }
2113
2114         //val8 = rtw_read8(Adapter, REG_SYS_FUNC_EN+1);
2115         //val8 &= ~BIT(2);      // 0x2[10], FEN_CPUEN
2116         //rtw_write8(Adapter, REG_SYS_FUNC_EN+1, val8);
2117
2118         // MCUFWDL 0x80[1:0]=0
2119         // reset MCU ready status
2120         rtw_write8(Adapter, REG_MCUFWDL, 0);
2121
2122         //YJ,add,111212
2123         //Disable 32k
2124         val8 = rtw_read8(Adapter, REG_32K_CTRL);
2125         rtw_write8(Adapter, REG_32K_CTRL, val8&(~BIT0));
2126
2127         // Card disable power action flow
2128         HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, Rtl8188E_NIC_DISABLE_FLOW);
2129
2130         // Reset MCU IO Wrapper
2131         val8 = rtw_read8(Adapter, REG_RSV_CTRL+1);
2132         rtw_write8(Adapter, REG_RSV_CTRL+1, (val8&(~BIT3)));
2133         val8 = rtw_read8(Adapter, REG_RSV_CTRL+1);
2134         rtw_write8(Adapter, REG_RSV_CTRL+1, val8|BIT3);
2135
2136 #if 0
2137         // 7. RSV_CTRL 0x1C[7:0] = 0x0E                 // lock ISO/CLK/Power control register
2138         rtw_write8(Adapter, REG_RSV_CTRL, 0x0e);
2139 #endif
2140 #if 1
2141         //YJ,test add, 111207. For Power Consumption.
2142         val8 = rtw_read8(Adapter, GPIO_IN);
2143         rtw_write8(Adapter, GPIO_OUT, val8);
2144         rtw_write8(Adapter, GPIO_IO_SEL, 0xFF);//Reg0x46
2145
2146         val8 = rtw_read8(Adapter, REG_GPIO_IO_SEL);
2147         //rtw_write8(Adapter, REG_GPIO_IO_SEL, (val8<<4)|val8);
2148         rtw_write8(Adapter, REG_GPIO_IO_SEL, (val8<<4));
2149         val8 = rtw_read8(Adapter, REG_GPIO_IO_SEL+1);
2150         rtw_write8(Adapter, REG_GPIO_IO_SEL+1, val8|0x0F);//Reg0x43
2151         rtw_write32(Adapter, REG_BB_PAD_CTRL, 0x00080808);//set LNA ,TRSW,EX_PA Pin to output mode
2152 #endif
2153
2154         Adapter->bFWReady = _FALSE;
2155
2156         bMacPwrCtrlOn = _FALSE;
2157         rtw_hal_set_hwreg(Adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
2158 }
2159 static void rtl8192cu_hw_power_down(_adapter *padapter)
2160 {
2161         // 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c.
2162         // Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1.
2163
2164         // Enable register area 0x0-0xc.
2165         rtw_write8(padapter,REG_RSV_CTRL, 0x0);
2166         rtw_write16(padapter, REG_APS_FSMCO, 0x8812);
2167 }
2168
2169 u32 rtl8188eu_hal_deinit(PADAPTER Adapter)
2170  {
2171         struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(Adapter);
2172         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2173         DBG_8192C("==> %s \n",__FUNCTION__);
2174
2175 #ifdef CONFIG_SUPPORT_USB_INT
2176         rtw_write32(Adapter, REG_HIMR_88E, IMR_DISABLED_88E);
2177         rtw_write32(Adapter, REG_HIMRE_88E, IMR_DISABLED_88E);
2178 #endif
2179
2180  #ifdef SUPPORT_HW_RFOFF_DETECTED
2181         DBG_8192C("bkeepfwalive(%x)\n", pwrctl->bkeepfwalive);
2182         if(pwrctl->bkeepfwalive)
2183         {
2184                 _ps_close_RF(Adapter);
2185                 if((pwrctl->bHWPwrPindetect) && (pwrctl->bHWPowerdown))
2186                         rtl8192cu_hw_power_down(Adapter);
2187         }
2188         else
2189 #endif
2190         {
2191                 if(Adapter->hw_init_completed == _TRUE){
2192                         hal_poweroff_8188eu(Adapter);
2193
2194                         if((pwrctl->bHWPwrPindetect ) && (pwrctl->bHWPowerdown))
2195                                 rtl8192cu_hw_power_down(Adapter);
2196
2197                 }
2198         }
2199         return _SUCCESS;
2200  }
2201
2202
2203 unsigned int rtl8188eu_inirp_init(PADAPTER Adapter)
2204 {
2205         u8 i;
2206         struct recv_buf *precvbuf;
2207         uint    status;
2208         struct dvobj_priv *pdev= adapter_to_dvobj(Adapter);
2209         struct intf_hdl * pintfhdl=&Adapter->iopriv.intf;
2210         struct recv_priv *precvpriv = &(Adapter->recvpriv);
2211         u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
2212 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
2213         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2214         u32 (*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr);
2215 #endif
2216
2217 _func_enter_;
2218
2219         _read_port = pintfhdl->io_ops._read_port;
2220
2221         status = _SUCCESS;
2222
2223         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("===> usb_inirp_init \n"));
2224
2225         precvpriv->ff_hwaddr = RECV_BULK_IN_ADDR;
2226
2227         //issue Rx irp to receive data
2228         precvbuf = (struct recv_buf *)precvpriv->precv_buf;
2229         for(i=0; i<NR_RECVBUFF; i++)
2230         {
2231                 if(_read_port(pintfhdl, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf) == _FALSE )
2232                 {
2233                         RT_TRACE(_module_hci_hal_init_c_,_drv_err_,("usb_rx_init: usb_read_port error \n"));
2234                         status = _FAIL;
2235                         goto exit;
2236                 }
2237
2238                 precvbuf++;
2239                 precvpriv->free_recv_buf_queue_cnt--;
2240         }
2241
2242 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
2243         if(pHalData->RtIntInPipe != 0x05)
2244         {
2245                 status = _FAIL;
2246                 DBG_871X("%s =>Warning !! Have not USB Int-IN pipe,  pHalData->RtIntInPipe(%d)!!!\n",__FUNCTION__,pHalData->RtIntInPipe);
2247                 goto exit;
2248         }
2249         _read_interrupt = pintfhdl->io_ops._read_interrupt;
2250         if(_read_interrupt(pintfhdl, RECV_INT_IN_ADDR) == _FALSE )
2251         {
2252                 RT_TRACE(_module_hci_hal_init_c_,_drv_err_,("usb_rx_init: usb_read_interrupt error \n"));
2253                 status = _FAIL;
2254         }
2255 #endif
2256
2257 exit:
2258
2259         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("<=== usb_inirp_init \n"));
2260
2261 _func_exit_;
2262
2263         return status;
2264
2265 }
2266
2267 unsigned int rtl8188eu_inirp_deinit(PADAPTER Adapter)
2268 {
2269         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("\n ===> usb_rx_deinit \n"));
2270
2271         rtw_read_port_cancel(Adapter);
2272
2273         RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("\n <=== usb_rx_deinit \n"));
2274
2275         return _SUCCESS;
2276 }
2277
2278
2279
2280 //-------------------------------------------------------------------------
2281 //
2282 //      EEPROM Power index mapping
2283 //
2284 //-------------------------------------------------------------------------
2285
2286
2287 //-------------------------------------------------------------------
2288 //
2289 //      EEPROM/EFUSE Content Parsing
2290 //
2291 //-------------------------------------------------------------------
2292 static VOID
2293 _ReadBoardType(
2294         IN      PADAPTER        Adapter,
2295         IN      u8*             PROMContent,
2296         IN      BOOLEAN         AutoloadFail
2297         )
2298 {
2299
2300 }
2301
2302
2303 static VOID
2304 _ReadLEDSetting(
2305         IN      PADAPTER        Adapter,
2306         IN      u8*             PROMContent,
2307         IN      BOOLEAN         AutoloadFail
2308         )
2309 {
2310         struct led_priv *pledpriv = &(Adapter->ledpriv);
2311         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2312         EEPROM_EFUSE_PRIV       *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
2313 #ifdef CONFIG_SW_LED
2314         pledpriv->bRegUseLed = _TRUE;
2315
2316         switch(pEEPROM->CustomerID)
2317         {
2318                 default:
2319                         pledpriv->LedStrategy = SW_LED_MODE1;
2320                         break;
2321         }
2322         pHalData->bLedOpenDrain = _TRUE;// Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16.
2323 #else // HW LED
2324         pledpriv->LedStrategy = HW_LED;
2325 #endif //CONFIG_SW_LED
2326 }
2327
2328 static VOID
2329 _ReadRFSetting(
2330         IN      PADAPTER        Adapter,
2331         IN      u8*     PROMContent,
2332         IN      BOOLEAN         AutoloadFail
2333         )
2334 {
2335 }
2336
2337 static VOID
2338 hal_InitPGData(
2339         IN      PADAPTER        pAdapter,
2340         IN      OUT     u8              *PROMContent
2341         )
2342 {
2343 #if 0
2344         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter);
2345         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
2346         u32     i;
2347         u16     value16;
2348
2349         if(_FALSE == pEEPROM->bautoload_fail_flag)
2350         { // autoload OK.
2351                 if (_TRUE == pEEPROM->EepromOrEfuse)
2352                 {
2353                         // Read all Content from EEPROM or EFUSE.
2354                         for(i = 0; i < HWSET_MAX_SIZE_88E; i += 2)
2355                         {
2356                                 //value16 = EF2Byte(ReadEEprom(pAdapter, (u2Byte) (i>>1)));
2357                                 //*((u16 *)(&PROMContent[i])) = value16;
2358                         }
2359                 }
2360                 else
2361                 {
2362                         // Read EFUSE real map to shadow.
2363                         EFUSE_ShadowMapUpdate(pAdapter, EFUSE_WIFI, _FALSE);
2364                         _rtw_memcpy((void*)PROMContent, (void*)pEEPROM->efuse_eeprom_data, HWSET_MAX_SIZE_88E);
2365                 }
2366         }
2367         else
2368         {//autoload fail
2369                 //RT_TRACE(COMP_INIT, DBG_LOUD, ("AutoLoad Fail reported from CR9346!!\n"));
2370                 pEEPROM->bautoload_fail_flag = _TRUE;
2371                 //update to default value 0xFF
2372                 if (_FALSE == pEEPROM->EepromOrEfuse)
2373                 EFUSE_ShadowMapUpdate(pAdapter, EFUSE_WIFI, _FALSE);
2374         }
2375 #endif
2376 }
2377 static void
2378 Hal_EfuseParsePIDVID_8188EU(
2379         IN      PADAPTER                pAdapter,
2380         IN      u8*                             hwinfo,
2381         IN      BOOLEAN                 AutoLoadFail
2382         )
2383 {
2384
2385         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
2386
2387         if( !AutoLoadFail )
2388         {
2389                 // VID, PID
2390                 pHalData->EEPROMVID = EF2Byte( *(u16 *)&hwinfo[EEPROM_VID_88EU] );
2391                 pHalData->EEPROMPID = EF2Byte( *(u16 *)&hwinfo[EEPROM_PID_88EU] );
2392
2393                 // Customer ID, 0x00 and 0xff are reserved for Realtek.
2394                 pHalData->EEPROMCustomerID = *(u8 *)&hwinfo[EEPROM_CustomID_88E];
2395                 pHalData->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID;
2396
2397         }
2398         else
2399         {
2400                 pHalData->EEPROMVID                     = EEPROM_Default_VID;
2401                 pHalData->EEPROMPID                     = EEPROM_Default_PID;
2402
2403                 // Customer ID, 0x00 and 0xff are reserved for Realtek.
2404                 pHalData->EEPROMCustomerID              = EEPROM_Default_CustomerID;
2405                 pHalData->EEPROMSubCustomerID   = EEPROM_Default_SubCustomerID;
2406
2407         }
2408
2409         DBG_871X("VID = 0x%04X, PID = 0x%04X\n", pHalData->EEPROMVID, pHalData->EEPROMPID);
2410         DBG_871X("Customer ID: 0x%02X, SubCustomer ID: 0x%02X\n", pHalData->EEPROMCustomerID, pHalData->EEPROMSubCustomerID);
2411 }
2412
2413 static void
2414 Hal_EfuseParseMACAddr_8188EU(
2415         IN      PADAPTER                padapter,
2416         IN      u8*                     hwinfo,
2417         IN      BOOLEAN                 AutoLoadFail
2418         )
2419 {
2420         u16                     i, usValue;
2421         u8                      sMacAddr[6] = {0x00, 0xE0, 0x4C, 0x81, 0x88, 0x02};
2422         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
2423
2424         if (AutoLoadFail)
2425         {
2426 //              sMacAddr[5] = (u1Byte)GetRandomNumber(1, 254);
2427                 for (i=0; i<6; i++)
2428                         pEEPROM->mac_addr[i] = sMacAddr[i];
2429         }
2430         else
2431         {
2432                 //Read Permanent MAC address
2433                 _rtw_memcpy(pEEPROM->mac_addr, &hwinfo[EEPROM_MAC_ADDR_88EU], ETH_ALEN);
2434
2435         }
2436 //      NicIFSetMacAddress(pAdapter, pAdapter->PermanentAddress);
2437
2438         RT_TRACE(_module_hci_hal_init_c_, _drv_notice_,
2439                  ("Hal_EfuseParseMACAddr_8188ES: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
2440                   pEEPROM->mac_addr[0], pEEPROM->mac_addr[1],
2441                   pEEPROM->mac_addr[2], pEEPROM->mac_addr[3],
2442                   pEEPROM->mac_addr[4], pEEPROM->mac_addr[5]));
2443 }
2444
2445
2446 static void
2447 Hal_CustomizeByCustomerID_8188EU(
2448         IN      PADAPTER                padapter
2449         )
2450 {
2451 #if 0
2452         EEPROM_EFUSE_PRIV       *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
2453         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);
2454
2455         // For customized behavior.
2456         if((pHalData->EEPROMVID == 0x103C) && (pHalData->EEPROMVID == 0x1629))// HP Lite-On for RTL8188CUS Slim Combo.
2457                 pEEPROM->CustomerID = RT_CID_819x_HP;
2458
2459         // Decide CustomerID according to VID/DID or EEPROM
2460         switch(pHalData->EEPROMCustomerID)
2461         {
2462                 case EEPROM_CID_DEFAULT:
2463                         if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3308))
2464                                 pEEPROM->CustomerID = RT_CID_DLINK;
2465                         else if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3309))
2466                                 pEEPROM->CustomerID = RT_CID_DLINK;
2467                         else if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x330a))
2468                                 pEEPROM->CustomerID = RT_CID_DLINK;
2469                         break;
2470                 case EEPROM_CID_WHQL:
2471                         padapter->bInHctTest = TRUE;
2472
2473                         pMgntInfo->bSupportTurboMode = FALSE;
2474                         pMgntInfo->bAutoTurboBy8186 = FALSE;
2475
2476                         pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
2477                         pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
2478                         pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
2479                         pMgntInfo->PowerSaveControl.bLeisurePsModeBackup =FALSE;
2480                         pMgntInfo->keepAliveLevel = 0;
2481
2482                         padapter->bUnloadDriverwhenS3S4 = FALSE;
2483                         break;
2484                 default:
2485                         pEEPROM->CustomerID = RT_CID_DEFAULT;
2486                         break;
2487
2488         }
2489
2490         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Mgnt Customer ID: 0x%02x\n", pEEPROM->CustomerID));
2491
2492         hal_CustomizedBehavior_8723U(padapter);
2493 #endif
2494 }
2495
2496 #ifdef CONFIG_EFUSE_CONFIG_FILE
2497 static u32 Hal_readPGDataFromConfigFile(
2498         PADAPTER        padapter)
2499 {
2500         u32 i;
2501         struct file *fp;
2502         mm_segment_t fs;
2503         u8 temp[3];
2504         loff_t pos = 0;
2505         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
2506         u8      *PROMContent = pEEPROM->efuse_eeprom_data;
2507
2508
2509         temp[2] = 0; // add end of string '\0'
2510
2511         fp = filp_open("/system/etc/wifi/wifi_efuse.map", O_RDWR,  0644);
2512         if (IS_ERR(fp)) {
2513                 pEEPROM->bloadfile_fail_flag = _TRUE;
2514                 DBG_871X("Error, Efuse configure file doesn't exist.\n");
2515                 return _FAIL;
2516         }
2517
2518         fs = get_fs();
2519         set_fs(KERNEL_DS);
2520
2521         DBG_871X("Efuse configure file:\n");
2522         for (i=0; i<HWSET_MAX_SIZE_88E; i++) {
2523                 vfs_read(fp, temp, 2, &pos);
2524                 PROMContent[i] = simple_strtoul(temp, NULL, 16 );
2525                 pos += 1; // Filter the space character
2526                 DBG_871X("%02X \n", PROMContent[i]);
2527         }
2528         DBG_871X("\n");
2529         set_fs(fs);
2530
2531         filp_close(fp, NULL);
2532
2533         pEEPROM->bloadfile_fail_flag = _FALSE;
2534
2535         return _SUCCESS;
2536 }
2537
2538 static void
2539 Hal_ReadMACAddrFromFile_8188EU(
2540         PADAPTER                padapter
2541         )
2542 {
2543         u32 i;
2544         struct file *fp;
2545         mm_segment_t fs;
2546         u8 source_addr[18];
2547         loff_t pos = 0;
2548         u32 curtime = rtw_get_current_time();
2549         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
2550         u8 *head, *end;
2551
2552         u8 null_mac_addr[ETH_ALEN] = {0, 0, 0,0, 0, 0};
2553         u8 multi_mac_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
2554
2555         _rtw_memset(source_addr, 0, 18);
2556         _rtw_memset(pEEPROM->mac_addr, 0, ETH_ALEN);
2557
2558         fp = filp_open("/data/wifimac.txt", O_RDWR,  0644);
2559         if (IS_ERR(fp)) {
2560                 pEEPROM->bloadmac_fail_flag = _TRUE;
2561                 DBG_871X("Error, wifi mac address file doesn't exist.\n");
2562         } else {
2563                 fs = get_fs();
2564                 set_fs(KERNEL_DS);
2565
2566                 DBG_871X("wifi mac address:\n");
2567                 vfs_read(fp, source_addr, 18, &pos);
2568                 source_addr[17] = ':';
2569
2570                 head = end = source_addr;
2571                 for (i=0; i<ETH_ALEN; i++) {
2572                         while (end && (*end != ':') )
2573                                 end++;
2574
2575                         if (end && (*end == ':') )
2576                                 *end = '\0';
2577
2578                         pEEPROM->mac_addr[i] = simple_strtoul(head, NULL, 16 );
2579
2580                         if (end) {
2581                                 end++;
2582                                 head = end;
2583                         }
2584                         DBG_871X("%02x \n", pEEPROM->mac_addr[i]);
2585                 }
2586                 DBG_871X("\n");
2587                 set_fs(fs);
2588                 pEEPROM->bloadmac_fail_flag = _FALSE;
2589                 filp_close(fp, NULL);
2590         }
2591
2592         if ( (_rtw_memcmp(pEEPROM->mac_addr, null_mac_addr, ETH_ALEN)) ||
2593                 (_rtw_memcmp(pEEPROM->mac_addr, multi_mac_addr, ETH_ALEN)) ) {
2594                 pEEPROM->mac_addr[0] = 0x00;
2595                 pEEPROM->mac_addr[1] = 0xe0;
2596                 pEEPROM->mac_addr[2] = 0x4c;
2597                 pEEPROM->mac_addr[3] = (u8)(curtime & 0xff) ;
2598                 pEEPROM->mac_addr[4] = (u8)((curtime>>8) & 0xff) ;
2599                 pEEPROM->mac_addr[5] = (u8)((curtime>>16) & 0xff) ;
2600         }
2601
2602         DBG_871X("Hal_ReadMACAddrFromFile_8188ES: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
2603                   pEEPROM->mac_addr[0], pEEPROM->mac_addr[1],
2604                   pEEPROM->mac_addr[2], pEEPROM->mac_addr[3],
2605                   pEEPROM->mac_addr[4], pEEPROM->mac_addr[5]);
2606 }
2607 #endif //CONFIG_EFUSE_CONFIG_FILE
2608
2609
2610 static VOID
2611 readAdapterInfo_8188EU(
2612         IN      PADAPTER        padapter
2613         )
2614 {
2615 #if 1
2616         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
2617
2618         /* parse the eeprom/efuse content */
2619         Hal_EfuseParseIDCode88E(padapter, pEEPROM->efuse_eeprom_data);
2620         Hal_EfuseParsePIDVID_8188EU(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
2621 #ifdef CONFIG_EFUSE_CONFIG_FILE
2622         Hal_ReadMACAddrFromFile_8188EU(padapter);
2623 #else //CONFIG_EFUSE_CONFIG_FILE
2624         Hal_EfuseParseMACAddr_8188EU(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
2625 #endif //CONFIG_EFUSE_CONFIG_FILE
2626
2627         Hal_ReadPowerSavingMode88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
2628         Hal_ReadTxPowerInfo88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
2629         Hal_EfuseParseEEPROMVer88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
2630         rtl8188e_EfuseParseChnlPlan(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
2631         Hal_EfuseParseXtal_8188E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
2632         Hal_EfuseParseCustomerID88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
2633         Hal_ReadAntennaDiversity88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
2634         Hal_EfuseParseBoardType88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
2635         Hal_ReadThermalMeter_88E(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
2636
2637         //
2638         // The following part initialize some vars by PG info.
2639         //
2640         Hal_InitChannelPlan(padapter);
2641 #if defined(CONFIG_WOWLAN) && defined(CONFIG_SDIO_HCI)
2642         Hal_DetectWoWMode(padapter);
2643 #endif //CONFIG_WOWLAN && CONFIG_SDIO_HCI
2644         Hal_CustomizeByCustomerID_8188EU(padapter);
2645
2646         _ReadLEDSetting(padapter, pEEPROM->efuse_eeprom_data, pEEPROM->bautoload_fail_flag);
2647
2648 #else
2649
2650 #ifdef CONFIG_INTEL_PROXIM
2651                 /* for intel proximity */
2652         if (pHalData->rf_type== RF_1T1R) {
2653                 Adapter->proximity.proxim_support = _TRUE;
2654         } else if (pHalData->rf_type== RF_2T2R) {
2655                 if ((pHalData->EEPROMPID == 0x8186) &&
2656                         (pHalData->EEPROMVID== 0x0bda))
2657                 Adapter->proximity.proxim_support = _TRUE;
2658         } else {
2659                 Adapter->proximity.proxim_support = _FALSE;
2660         }
2661 #endif //CONFIG_INTEL_PROXIM
2662 #endif
2663 }
2664
2665 static void _ReadPROMContent(
2666         IN PADAPTER             Adapter
2667         )
2668 {
2669         EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
2670         u8                      eeValue;
2671
2672         /* check system boot selection */
2673         eeValue = rtw_read8(Adapter, REG_9346CR);
2674         pEEPROM->EepromOrEfuse          = (eeValue & BOOT_FROM_EEPROM) ? _TRUE : _FALSE;
2675         pEEPROM->bautoload_fail_flag    = (eeValue & EEPROM_EN) ? _FALSE : _TRUE;
2676
2677
2678         DBG_8192C("Boot from %s, Autoload %s !\n", (pEEPROM->EepromOrEfuse ? "EEPROM" : "EFUSE"),
2679                                 (pEEPROM->bautoload_fail_flag ? "Fail" : "OK") );
2680
2681         //pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE;
2682 #ifdef CONFIG_EFUSE_CONFIG_FILE
2683         Hal_readPGDataFromConfigFile(Adapter);
2684 #else //CONFIG_EFUSE_CONFIG_FILE
2685         Hal_InitPGData88E(Adapter);
2686 #endif  //CONFIG_EFUSE_CONFIG_FILE
2687         readAdapterInfo_8188EU(Adapter);
2688 }
2689
2690
2691
2692 static VOID
2693 _ReadRFType(
2694         IN      PADAPTER        Adapter
2695         )
2696 {
2697         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2698
2699 #if DISABLE_BB_RF
2700         pHalData->rf_chip = RF_PSEUDO_11N;
2701 #else
2702         pHalData->rf_chip = RF_6052;
2703 #endif
2704 }
2705
2706 static int _ReadAdapterInfo8188EU(PADAPTER      Adapter)
2707 {
2708         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2709         u32 start=rtw_get_current_time();
2710
2711         MSG_8192C("====> %s\n", __FUNCTION__);
2712
2713         //Efuse_InitSomeVar(Adapter);
2714
2715         //if(IS_HARDWARE_TYPE_8723A(Adapter))
2716         //      _EfuseCellSel(Adapter);
2717
2718         _ReadRFType(Adapter);//rf_chip -> _InitRFType()
2719         _ReadPROMContent(Adapter);
2720
2721         //MSG_8192C("%s()(done), rf_chip=0x%x, rf_type=0x%x\n",  __FUNCTION__, pHalData->rf_chip, pHalData->rf_type);
2722
2723         MSG_8192C("<==== %s in %d ms\n", __FUNCTION__, rtw_get_passing_time_ms(start));
2724
2725         return _SUCCESS;
2726 }
2727
2728
2729 static void ReadAdapterInfo8188EU(PADAPTER Adapter)
2730 {
2731         // Read EEPROM size before call any EEPROM function
2732         Adapter->EepromAddressSize = GetEEPROMSize8188E(Adapter);
2733
2734         _ReadAdapterInfo8188EU(Adapter);
2735 }
2736
2737
2738 #define GPIO_DEBUG_PORT_NUM 0
2739 static void rtl8192cu_trigger_gpio_0(_adapter *padapter)
2740 {
2741 #ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ
2742         u32 gpioctrl;
2743         DBG_8192C("==> trigger_gpio_0...\n");
2744         rtw_write16_async(padapter,REG_GPIO_PIN_CTRL,0);
2745         rtw_write8_async(padapter,REG_GPIO_PIN_CTRL+2,0xFF);
2746         gpioctrl = (BIT(GPIO_DEBUG_PORT_NUM)<<24 )|(BIT(GPIO_DEBUG_PORT_NUM)<<16);
2747         rtw_write32_async(padapter,REG_GPIO_PIN_CTRL,gpioctrl);
2748         gpioctrl |= (BIT(GPIO_DEBUG_PORT_NUM)<<8);
2749         rtw_write32_async(padapter,REG_GPIO_PIN_CTRL,gpioctrl);
2750         DBG_8192C("<=== trigger_gpio_0...\n");
2751 #endif
2752 }
2753
2754 void UpdateInterruptMask8188EU(PADAPTER padapter,u8 bHIMR0 ,u32 AddMSR, u32 RemoveMSR)
2755 {
2756         HAL_DATA_TYPE *pHalData;
2757
2758         u32 *himr;
2759         pHalData = GET_HAL_DATA(padapter);
2760
2761         if(bHIMR0)
2762                 himr = &(pHalData->IntrMask[0]);
2763         else
2764                 himr = &(pHalData->IntrMask[1]);
2765
2766         if (AddMSR)
2767                 *himr |= AddMSR;
2768
2769         if (RemoveMSR)
2770                 *himr &= (~RemoveMSR);
2771
2772         if(bHIMR0)
2773                 rtw_write32(padapter, REG_HIMR_88E, *himr);
2774         else
2775                 rtw_write32(padapter, REG_HIMRE_88E, *himr);
2776
2777 }
2778
2779 static void hw_var_set_macaddr(PADAPTER Adapter, u8 variable, u8* val)
2780 {
2781         u8 idx = 0;
2782         u32 reg_macid;
2783
2784 #ifdef CONFIG_CONCURRENT_MODE
2785         if(Adapter->iface_type == IFACE_PORT1)
2786         {
2787                 reg_macid = REG_MACID1;
2788         }
2789         else
2790 #endif
2791         {
2792                 reg_macid = REG_MACID;
2793         }
2794
2795         for(idx = 0 ; idx < 6; idx++)
2796         {
2797                 rtw_write8(Adapter, (reg_macid+idx), val[idx]);
2798         }
2799
2800 }
2801
2802 static void hw_var_set_bssid(PADAPTER Adapter, u8 variable, u8* val)
2803 {
2804         u8      idx = 0;
2805         u32 reg_bssid;
2806
2807 #ifdef CONFIG_CONCURRENT_MODE
2808         if(Adapter->iface_type == IFACE_PORT1)
2809         {
2810                 reg_bssid = REG_BSSID1;
2811         }
2812         else
2813 #endif
2814         {
2815                 reg_bssid = REG_BSSID;
2816         }
2817
2818         for(idx = 0 ; idx < 6; idx++)
2819         {
2820                 rtw_write8(Adapter, (reg_bssid+idx), val[idx]);
2821         }
2822
2823 }
2824
2825 static void hw_var_set_bcn_func(PADAPTER Adapter, u8 variable, u8* val)
2826 {
2827         u32 bcn_ctrl_reg;
2828
2829 #ifdef CONFIG_CONCURRENT_MODE
2830         if(Adapter->iface_type == IFACE_PORT1)
2831         {
2832                 bcn_ctrl_reg = REG_BCN_CTRL_1;
2833         }
2834         else
2835 #endif
2836         {
2837                 bcn_ctrl_reg = REG_BCN_CTRL;
2838         }
2839
2840         if(*((u8 *)val))
2841         {
2842                 rtw_write8(Adapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT));
2843         }
2844         else
2845         {
2846                 rtw_write8(Adapter, bcn_ctrl_reg, rtw_read8(Adapter, bcn_ctrl_reg)&(~(EN_BCN_FUNCTION | EN_TXBCN_RPT)));
2847         }
2848
2849
2850 }
2851
2852 static void hw_var_set_mlme_disconnect(PADAPTER Adapter, u8 variable, u8* val)
2853 {
2854 #ifdef CONFIG_CONCURRENT_MODE
2855         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2856         PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter;
2857
2858
2859         if(check_buddy_mlmeinfo_state(Adapter, _HW_STATE_NOLINK_))
2860                 rtw_write16(Adapter, REG_RXFLTMAP2, 0x00);
2861
2862
2863         if(Adapter->iface_type == IFACE_PORT1)
2864         {
2865                 //reset TSF1
2866                 rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1));
2867
2868                 //disable update TSF1
2869                 rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(4));
2870
2871                 // disable Port1's beacon function
2872                 rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(3)));
2873         }
2874         else
2875         {
2876                 //reset TSF
2877                 rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(0));
2878
2879                 //disable update TSF
2880                 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
2881         }
2882 #endif
2883 }
2884
2885 void SetHwReg8188EU(PADAPTER Adapter, u8 variable, u8* val)
2886 {
2887         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2888         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
2889         DM_ODM_T                *podmpriv = &pHalData->odmpriv;
2890 _func_enter_;
2891
2892         switch(variable)
2893         {
2894                 case HW_VAR_MEDIA_STATUS:
2895                         {
2896                                 u8 val8;
2897
2898                                 val8 = rtw_read8(Adapter, MSR)&0x0c;
2899                                 val8 |= *((u8 *)val);
2900                                 rtw_write8(Adapter, MSR, val8);
2901                         }
2902                         break;
2903                 case HW_VAR_MEDIA_STATUS1:
2904                         {
2905                                 u8 val8;
2906
2907                                 val8 = rtw_read8(Adapter, MSR)&0x03;
2908                                 val8 |= *((u8 *)val) <<2;
2909                                 rtw_write8(Adapter, MSR, val8);
2910                         }
2911                         break;
2912                 case HW_VAR_MAC_ADDR:
2913                         hw_var_set_macaddr(Adapter, variable, val);
2914                         break;
2915                 case HW_VAR_BSSID:
2916                         hw_var_set_bssid(Adapter, variable, val);
2917                         break;
2918                 case HW_VAR_TXPAUSE:
2919                         rtw_write8(Adapter, REG_TXPAUSE, *((u8 *)val));
2920                         break;
2921                 case HW_VAR_BCN_FUNC:
2922                         hw_var_set_bcn_func(Adapter, variable, val);
2923                         break;
2924                 case HW_VAR_CHECK_BSSID:
2925                         if(*((u8 *)val))
2926                         {
2927                                 rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
2928                         }
2929                         else
2930                         {
2931                                 u32     val32;
2932
2933                                 val32 = rtw_read32(Adapter, REG_RCR);
2934
2935                                 val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
2936
2937                                 rtw_write32(Adapter, REG_RCR, val32);
2938                         }
2939                         break;
2940                 case HW_VAR_MLME_DISCONNECT:
2941 #ifdef CONFIG_CONCURRENT_MODE
2942                         hw_var_set_mlme_disconnect(Adapter, variable, val);
2943 #else
2944                         {
2945                                 //Set RCR to not to receive data frame when NO LINK state
2946                                 //rtw_write32(Adapter, REG_RCR, rtw_read32(padapter, REG_RCR) & ~RCR_ADF);
2947                                 //reject all data frames
2948                                 rtw_write16(Adapter, REG_RXFLTMAP2,0x00);
2949
2950                                 //reset TSF
2951                                 rtw_write8(Adapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1)));
2952
2953                                 //disable update TSF
2954                                 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
2955                         }
2956 #endif
2957                         break;
2958                 case HW_VAR_ON_RCR_AM:
2959                         rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_AM);
2960                         DBG_871X("%s, %d, RCR= %x \n", __FUNCTION__,__LINE__, rtw_read32(Adapter, REG_RCR));
2961                         break;
2962               case HW_VAR_OFF_RCR_AM:
2963                         rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)& (~RCR_AM));
2964                         DBG_871X("%s, %d, RCR= %x \n", __FUNCTION__,__LINE__, rtw_read32(Adapter, REG_RCR));
2965                         break;
2966                 case HW_VAR_BEACON_INTERVAL:
2967                         rtw_write16(Adapter, REG_BCN_INTERVAL, *((u16 *)val));
2968 #ifdef  CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
2969                         {
2970                                 struct mlme_ext_priv    *pmlmeext = &Adapter->mlmeextpriv;
2971                                 struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
2972                                 u16 bcn_interval =      *((u16 *)val);
2973                                 if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE){
2974                                         DBG_8192C("%s==> bcn_interval:%d, eraly_int:%d \n",__FUNCTION__,bcn_interval,bcn_interval>>1);
2975                                         rtw_write8(Adapter, REG_DRVERLYINT, bcn_interval>>1);// 50ms for sdio
2976                                 }
2977                         }
2978 #endif//CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
2979
2980                         break;
2981                 case HW_VAR_SLOT_TIME:
2982                         {
2983                                 rtw_write8(Adapter, REG_SLOT, val[0]);
2984                         }
2985                         break;
2986                 case HW_VAR_ACK_PREAMBLE:
2987                         {
2988                                 u8      regTmp;
2989                                 u8      bShortPreamble = *( (PBOOLEAN)val );
2990                                 // Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily)
2991                                 regTmp = (pHalData->nCur40MhzPrimeSC)<<5;
2992                                 rtw_write8(Adapter, REG_RRSR+2, regTmp);
2993
2994                                 regTmp = rtw_read8(Adapter,REG_WMAC_TRXPTCL_CTL+2);
2995                                 if(bShortPreamble)
2996                                         regTmp |= BIT1;
2997                                 else
2998                                         regTmp &= (~BIT1);
2999                                 rtw_write8(Adapter,REG_WMAC_TRXPTCL_CTL+2,regTmp);
3000                         }
3001                         break;
3002                 case HW_VAR_CAM_EMPTY_ENTRY:
3003                         {
3004                                 u8      ucIndex = *((u8 *)val);
3005                                 u8      i;
3006                                 u32     ulCommand=0;
3007                                 u32     ulContent=0;
3008                                 u32     ulEncAlgo=CAM_AES;
3009
3010                                 for(i=0;i<CAM_CONTENT_COUNT;i++)
3011                                 {
3012                                         // filled id in CAM config 2 byte
3013                                         if( i == 0)
3014                                         {
3015                                                 ulContent |=(ucIndex & 0x03) | ((u16)(ulEncAlgo)<<2);
3016                                                 //ulContent |= CAM_VALID;
3017                                         }
3018                                         else
3019                                         {
3020                                                 ulContent = 0;
3021                                         }
3022                                         // polling bit, and No Write enable, and address
3023                                         ulCommand= CAM_CONTENT_COUNT*ucIndex+i;
3024                                         ulCommand= ulCommand | CAM_POLLINIG|CAM_WRITE;
3025                                         // write content 0 is equall to mark invalid
3026                                         rtw_write32(Adapter, WCAMI, ulContent);  //delay_ms(40);
3027                                         //RT_TRACE(COMP_SEC, DBG_LOUD, ("CAM_empty_entry(): WRITE A4: %lx \n",ulContent));
3028                                         rtw_write32(Adapter, RWCAM, ulCommand);  //delay_ms(40);
3029                                         //RT_TRACE(COMP_SEC, DBG_LOUD, ("CAM_empty_entry(): WRITE A0: %lx \n",ulCommand));
3030                                 }
3031                         }
3032                         break;
3033                 case HW_VAR_CAM_INVALID_ALL:
3034                         rtw_write32(Adapter, RWCAM, BIT(31)|BIT(30));
3035                         break;
3036                 case HW_VAR_CAM_WRITE:
3037                         {
3038                                 u32     cmd;
3039                                 u32     *cam_val = (u32 *)val;
3040                                 rtw_write32(Adapter, WCAMI, cam_val[0]);
3041
3042                                 cmd = CAM_POLLINIG | CAM_WRITE | cam_val[1];
3043                                 rtw_write32(Adapter, RWCAM, cmd);
3044                         }
3045                         break;
3046                 case HW_VAR_AC_PARAM_VO:
3047                         rtw_write32(Adapter, REG_EDCA_VO_PARAM, ((u32 *)(val))[0]);
3048                         break;
3049                 case HW_VAR_AC_PARAM_VI:
3050                         rtw_write32(Adapter, REG_EDCA_VI_PARAM, ((u32 *)(val))[0]);
3051                         break;
3052                 case HW_VAR_AC_PARAM_BE:
3053                         pHalData->AcParam_BE = ((u32 *)(val))[0];
3054                         rtw_write32(Adapter, REG_EDCA_BE_PARAM, ((u32 *)(val))[0]);
3055                         break;
3056                 case HW_VAR_AC_PARAM_BK:
3057                         rtw_write32(Adapter, REG_EDCA_BK_PARAM, ((u32 *)(val))[0]);
3058                         break;
3059                 case HW_VAR_ACM_CTRL:
3060                         {
3061                                 u8      acm_ctrl = *((u8 *)val);
3062                                 u8      AcmCtrl = rtw_read8( Adapter, REG_ACMHWCTRL);
3063
3064                                 if(acm_ctrl > 1)
3065                                         AcmCtrl = AcmCtrl | 0x1;
3066
3067                                 if(acm_ctrl & BIT(3))
3068                                         AcmCtrl |= AcmHw_VoqEn;
3069                                 else
3070                                         AcmCtrl &= (~AcmHw_VoqEn);
3071
3072                                 if(acm_ctrl & BIT(2))
3073                                         AcmCtrl |= AcmHw_ViqEn;
3074                                 else
3075                                         AcmCtrl &= (~AcmHw_ViqEn);
3076
3077                                 if(acm_ctrl & BIT(1))
3078                                         AcmCtrl |= AcmHw_BeqEn;
3079                                 else
3080                                         AcmCtrl &= (~AcmHw_BeqEn);
3081
3082                                 DBG_871X("[HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl );
3083                                 rtw_write8(Adapter, REG_ACMHWCTRL, AcmCtrl );
3084                         }
3085                         break;
3086                 case HW_VAR_AMPDU_MIN_SPACE:
3087                         {
3088                                 u8      MinSpacingToSet;
3089                                 u8      SecMinSpace;
3090
3091                                 MinSpacingToSet = *((u8 *)val);
3092                                 if(MinSpacingToSet <= 7)
3093                                 {
3094                                         switch(Adapter->securitypriv.dot11PrivacyAlgrthm)
3095                                         {
3096                                                 case _NO_PRIVACY_:
3097                                                 case _AES_:
3098                                                         SecMinSpace = 0;
3099                                                         break;
3100
3101                                                 case _WEP40_:
3102                                                 case _WEP104_:
3103                                                 case _TKIP_:
3104                                                 case _TKIP_WTMIC_:
3105                                                         SecMinSpace = 6;
3106                                                         break;
3107                                                 default:
3108                                                         SecMinSpace = 7;
3109                                                         break;
3110                                         }
3111
3112                                         if(MinSpacingToSet < SecMinSpace){
3113                                                 MinSpacingToSet = SecMinSpace;
3114                                         }
3115
3116                                         //RT_TRACE(COMP_MLME, DBG_LOUD, ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", Adapter->MgntInfo.MinSpaceCfg));
3117                                         rtw_write8(Adapter, REG_AMPDU_MIN_SPACE, (rtw_read8(Adapter, REG_AMPDU_MIN_SPACE) & 0xf8) | MinSpacingToSet);
3118                                 }
3119                         }
3120                         break;
3121                 case HW_VAR_AMPDU_FACTOR:
3122                         {
3123                                 u8      RegToSet_Normal[4]={0x41,0xa8,0x72, 0xb9};
3124                                 u8      RegToSet_BT[4]={0x31,0x74,0x42, 0x97};
3125                                 u8      FactorToSet;
3126                                 u8      *pRegToSet;
3127                                 u8      index = 0;
3128
3129 #ifdef CONFIG_BT_COEXIST
3130                                 if(     (pHalData->bt_coexist.BT_Coexist) &&
3131                                         (pHalData->bt_coexist.BT_CoexistType == BT_CSR_BC4) )
3132                                         pRegToSet = RegToSet_BT; // 0x97427431;
3133                                 else
3134 #endif
3135                                         pRegToSet = RegToSet_Normal; // 0xb972a841;
3136
3137                                 FactorToSet = *((u8 *)val);
3138                                 if(FactorToSet <= 3)
3139                                 {
3140                                         FactorToSet = (1<<(FactorToSet + 2));
3141                                         if(FactorToSet>0xf)
3142                                                 FactorToSet = 0xf;
3143
3144                                         for(index=0; index<4; index++)
3145                                         {
3146                                                 if((pRegToSet[index] & 0xf0) > (FactorToSet<<4))
3147                                                         pRegToSet[index] = (pRegToSet[index] & 0x0f) | (FactorToSet<<4);
3148
3149                                                 if((pRegToSet[index] & 0x0f) > FactorToSet)
3150                                                         pRegToSet[index] = (pRegToSet[index] & 0xf0) | (FactorToSet);
3151
3152                                                 rtw_write8(Adapter, (REG_AGGLEN_LMT+index), pRegToSet[index]);
3153                                         }
3154
3155                                         //RT_TRACE(COMP_MLME, DBG_LOUD, ("Set HW_VAR_AMPDU_FACTOR: %#x\n", FactorToSet));
3156                                 }
3157                         }
3158                         break;
3159                 case HW_VAR_RXDMA_AGG_PG_TH:
3160                         #ifdef CONFIG_USB_RX_AGGREGATION
3161                         {
3162                                 u8      threshold = *((u8 *)val);
3163                                 if( threshold == 0)
3164                                 {
3165                                         threshold = pHalData->UsbRxAggPageCount;
3166                                 }
3167                                 rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, threshold);
3168                         }
3169                         #endif
3170                         break;
3171                 case HW_VAR_SET_RPWM:
3172 #ifdef CONFIG_LPS_LCLK
3173                         {
3174                                 u8      ps_state = *((u8 *)val);
3175                                 //rpwm value only use BIT0(clock bit) ,BIT6(Ack bit), and BIT7(Toggle bit) for 88e.
3176                                 //BIT0 value - 1: 32k, 0:40MHz.
3177                                 //BIT6 value - 1: report cpwm value after success set, 0:do not report.
3178                                 //BIT7 value - Toggle bit change.
3179                                 //modify by Thomas. 2012/4/2.
3180                                 ps_state = ps_state & 0xC1;
3181                                 //DBG_871X("##### Change RPWM value to = %x for switch clk #####\n",ps_state);
3182                                 rtw_write8(Adapter, REG_USB_HRPWM, ps_state);
3183                         }
3184 #endif
3185                         break;
3186                 case HW_VAR_H2C_FW_PWRMODE:
3187                         {
3188                                 u8      psmode = (*(u8 *)val);
3189
3190                                 // Forece leave RF low power mode for 1T1R to prevent conficting setting in Fw power
3191                                 // saving sequence. 2010.06.07. Added by tynli. Suggested by SD3 yschang.
3192                                 if( (psmode != PS_MODE_ACTIVE) && (!IS_92C_SERIAL(pHalData->VersionID)))
3193                                 {
3194                                         ODM_RF_Saving(podmpriv, _TRUE);
3195                                 }
3196                                 rtl8188e_set_FwPwrMode_cmd(Adapter, psmode);
3197                         }
3198                         break;
3199                 case HW_VAR_H2C_FW_JOINBSSRPT:
3200                     {
3201                                 u8      mstatus = (*(u8 *)val);
3202                                 rtl8188e_set_FwJoinBssReport_cmd(Adapter, mstatus);
3203                         }
3204                         break;
3205 #ifdef CONFIG_P2P_PS
3206                 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
3207                         {
3208                                 u8      p2p_ps_state = (*(u8 *)val);
3209                                 rtl8188e_set_p2p_ps_offload_cmd(Adapter, p2p_ps_state);
3210                         }
3211                         break;
3212 #endif //CONFIG_P2P_PS
3213 #ifdef CONFIG_TDLS
3214                 case HW_VAR_TDLS_WRCR:
3215                         rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)&(~RCR_CBSSID_DATA ));
3216                         break;
3217                 case HW_VAR_TDLS_INIT_CH_SEN:
3218                         {
3219                                 rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)&(~ RCR_CBSSID_DATA )&(~RCR_CBSSID_BCN ));
3220                                 rtw_write16(Adapter, REG_RXFLTMAP2,0xffff);
3221
3222                                 //disable update TSF
3223                                 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
3224                         }
3225                         break;
3226                 case HW_VAR_TDLS_DONE_CH_SEN:
3227                         {
3228                                 //enable update TSF
3229                                 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~ BIT(4)));
3230                                 rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|(RCR_CBSSID_BCN ));
3231                         }
3232                         break;
3233                 case HW_VAR_TDLS_RS_RCR:
3234                         rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|(RCR_CBSSID_DATA));
3235                         break;
3236 #endif //CONFIG_TDLS
3237                 case HW_VAR_INITIAL_GAIN:
3238                         {
3239                                 DIG_T   *pDigTable = &podmpriv->DM_DigTable;
3240                                 u32             rx_gain = ((u32 *)(val))[0];
3241
3242                                 if(rx_gain == 0xff){//restore rx gain
3243                                         ODM_Write_DIG(podmpriv,pDigTable->BackupIGValue);
3244                                 }
3245                                 else{
3246                                         pDigTable->BackupIGValue = pDigTable->CurIGValue;
3247                                         ODM_Write_DIG(podmpriv,rx_gain);
3248                                 }
3249                         }
3250                         break;
3251                 case HW_VAR_TRIGGER_GPIO_0:
3252                         rtl8192cu_trigger_gpio_0(Adapter);
3253                         break;
3254 #ifdef CONFIG_BT_COEXIST
3255                 case HW_VAR_BT_SET_COEXIST:
3256                         {
3257                                 u8      bStart = (*(u8 *)val);
3258                                 rtl8192c_set_dm_bt_coexist(Adapter, bStart);
3259                         }
3260                         break;
3261                 case HW_VAR_BT_ISSUE_DELBA:
3262                         {
3263                                 u8      dir = (*(u8 *)val);
3264                                 rtl8192c_issue_delete_ba(Adapter, dir);
3265                         }
3266                         break;
3267 #endif
3268 #if (RATE_ADAPTIVE_SUPPORT==1)
3269                 case HW_VAR_RPT_TIMER_SETTING:
3270                         {
3271                                 u16     min_rpt_time = (*(u16 *)val);
3272                                 ODM_RA_Set_TxRPT_Time(podmpriv,min_rpt_time);
3273                         }
3274                         break;
3275 #endif
3276 #ifdef CONFIG_SW_ANTENNA_DIVERSITY
3277
3278                 case HW_VAR_ANTENNA_DIVERSITY_LINK:
3279                         //odm_SwAntDivRestAfterLink8192C(Adapter);
3280                         ODM_SwAntDivRestAfterLink(podmpriv);
3281                         break;
3282 #endif
3283 #ifdef CONFIG_ANTENNA_DIVERSITY
3284                 case HW_VAR_ANTENNA_DIVERSITY_SELECT:
3285                         {
3286                                 u8      Optimum_antenna = (*(u8 *)val);
3287                                 u8      Ant ;
3288                                 //switch antenna to Optimum_antenna
3289                                 //DBG_8192C("==> HW_VAR_ANTENNA_DIVERSITY_SELECT , Ant_(%s)\n",(Optimum_antenna==2)?"A":"B");
3290                                 if(pHalData->CurAntenna !=  Optimum_antenna)
3291                                 {
3292                                         Ant = (Optimum_antenna==2)?MAIN_ANT:AUX_ANT;
3293                                         ODM_UpdateRxIdleAnt(&pHalData->odmpriv, Ant);
3294
3295                                         pHalData->CurAntenna = Optimum_antenna ;
3296                                         //DBG_8192C("==> HW_VAR_ANTENNA_DIVERSITY_SELECT , Ant_(%s)\n",(Optimum_antenna==2)?"A":"B");
3297                                 }
3298                         }
3299                         break;
3300 #endif
3301                 case HW_VAR_EFUSE_BYTES: // To set EFUE total used bytes, added by Roger, 2008.12.22.
3302                         pHalData->EfuseUsedBytes = *((u16 *)val);
3303                         break;
3304                 case HW_VAR_FIFO_CLEARN_UP:
3305                         {
3306                                 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter);
3307                                 u8 trycnt = 100;
3308
3309                                 //pause tx
3310                                 rtw_write8(Adapter,REG_TXPAUSE,0xff);
3311
3312                                 //keep sn
3313                                 Adapter->xmitpriv.nqos_ssn = rtw_read16(Adapter,REG_NQOS_SEQ);
3314
3315                                 if(pwrpriv->bkeepfwalive != _TRUE)
3316                                 {
3317                                         //RX DMA stop
3318                                         rtw_write32(Adapter,REG_RXPKT_NUM,(rtw_read32(Adapter,REG_RXPKT_NUM)|RW_RELEASE_EN));
3319                                         do{
3320                                                 if(!(rtw_read32(Adapter,REG_RXPKT_NUM)&RXDMA_IDLE))
3321                                                         break;
3322                                         }while(trycnt--);
3323                                         if(trycnt ==0)
3324                                                 DBG_8192C("Stop RX DMA failed...... \n");
3325
3326                                         //RQPN Load 0
3327                                         rtw_write16(Adapter,REG_RQPN_NPQ,0x0);
3328                                         rtw_write32(Adapter,REG_RQPN,0x80000000);
3329                                         rtw_mdelay_os(10);
3330                                 }
3331                         }
3332                         break;
3333         case HW_VAR_APFM_ON_MAC:
3334                         pHalData->bMacPwrCtrlOn = *val;
3335                         DBG_871X("%s: bMacPwrCtrlOn=%d\n", __func__, pHalData->bMacPwrCtrlOn);
3336                         break;
3337
3338 #ifdef CONFIG_WOWLAN
3339                 case HW_VAR_WOWLAN:
3340                 {
3341                         struct wowlan_ioctl_param *poidparam;
3342                         struct recv_buf *precvbuf;
3343                         struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(Adapter);
3344                         struct security_priv *psecuritypriv = &Adapter->securitypriv;
3345                         int res, i;
3346                         u32 tmp;
3347                         u64 iv_low = 0, iv_high = 0;
3348                         u16 len = 0;
3349                         u8 mstatus = (*(u8 *)val);
3350                         u8 trycnt = 100;
3351                         u8 data[4], val8;
3352
3353                         poidparam = (struct wowlan_ioctl_param *)val;
3354                         switch (poidparam->subcode){
3355                                 case WOWLAN_ENABLE:
3356                                         DBG_871X_LEVEL(_drv_always_, "WOWLAN_ENABLE\n");
3357
3358                                         #ifndef DYNAMIC_CAMID_ALLOC
3359                                         val8 = (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)? 0xcc: 0xcf;
3360                                         rtw_write8(Adapter, REG_SECCFG, val8);
3361                                         DBG_871X_LEVEL(_drv_always_, "REG_SECCFG: %02x\n", rtw_read8(Adapter, REG_SECCFG));
3362                                         #endif
3363
3364                                         SetFwRelatedForWoWLAN8188ES(Adapter, _TRUE);
3365
3366                                         rtl8188e_set_FwJoinBssReport_cmd(Adapter, 1);
3367                                         rtw_msleep_os(2);
3368
3369                                         //Set Pattern
3370                                         //if(pwrctl->wowlan_pattern==_TRUE)
3371                                         //      rtw_wowlan_reload_pattern(Adapter);
3372
3373                                         //RX DMA stop
3374                                         DBG_871X_LEVEL(_drv_always_, "Pause DMA\n");
3375                                         rtw_write32(Adapter,REG_RXPKT_NUM,(rtw_read32(Adapter,REG_RXPKT_NUM)|RW_RELEASE_EN));
3376                                         do{
3377                                                 if((rtw_read32(Adapter, REG_RXPKT_NUM)&RXDMA_IDLE)) {
3378                                                         DBG_871X_LEVEL(_drv_always_, "RX_DMA_IDLE is true\n");
3379                                                         if (Adapter->intf_stop)
3380                                                                 Adapter->intf_stop(Adapter);
3381                                                         break;
3382                                                 } else {
3383                                                         // If RX_DMA is not idle, receive one pkt from DMA
3384                                                         DBG_871X_LEVEL(_drv_always_, "RX_DMA_IDLE is not true\n");
3385                                                 }
3386                                         }while(trycnt--);
3387
3388                                         if(trycnt ==0)
3389                                                 DBG_871X_LEVEL(_drv_always_, "Stop RX DMA failed...... \n");
3390
3391                                         //Set WOWLAN H2C command.
3392                                         DBG_871X_LEVEL(_drv_always_, "Set WOWLan cmd\n");
3393                                         rtl8188es_set_wowlan_cmd(Adapter, 1);
3394
3395                                         mstatus = rtw_read8(Adapter, REG_WOW_CTRL);
3396                                         trycnt = 10;
3397
3398                                         while(!(mstatus&BIT1) && trycnt>1) {
3399                                                 mstatus = rtw_read8(Adapter, REG_WOW_CTRL);
3400                                                 DBG_871X_LEVEL(_drv_always_, "Loop index: %d :0x%02x\n", trycnt, mstatus);
3401                                                 trycnt --;
3402                                                 rtw_msleep_os(2);
3403                                         }
3404
3405                                         pwrctl->wowlan_wake_reason = rtw_read8(Adapter, REG_WOWLAN_WAKE_REASON);
3406                                         DBG_871X_LEVEL(_drv_always_, "wowlan_wake_reason: 0x%02x\n",
3407                                                                                 pwrctl->wowlan_wake_reason);
3408
3409                                         /* Invoid SE0 reset signal during suspending*/
3410                                         rtw_write8(Adapter, REG_RSV_CTRL, 0x20);
3411                                         rtw_write8(Adapter, REG_RSV_CTRL, 0x60);
3412
3413                                         //rtw_msleep_os(10);
3414                                         break;
3415                                 case WOWLAN_DISABLE:
3416                                         trycnt = 10;
3417
3418                                         DBG_871X_LEVEL(_drv_always_, "WOWLAN_DISABLE\n");
3419
3420                                         rtl8188e_set_FwJoinBssReport_cmd(Adapter, 0);
3421
3422                                         #ifndef DYNAMIC_CAMID_ALLOC
3423                                         rtw_write8(Adapter, REG_SECCFG, 0x0c|BIT(5));// enable tx enc and rx dec engine, and no key search for MC/BC
3424                                         DBG_871X_LEVEL(_drv_always_, "REG_SECCFG: %02x\n", rtw_read8(Adapter, REG_SECCFG));
3425                                         #endif
3426
3427                                         pwrctl->wowlan_wake_reason =
3428                                                 rtw_read8(Adapter, REG_WOWLAN_WAKE_REASON);
3429                                         DBG_871X_LEVEL(_drv_always_,
3430                                                         "wakeup_reason: 0x%02x\n", pwrctl->wowlan_wake_reason);
3431
3432                                         rtl8188es_set_wowlan_cmd(Adapter, 0);
3433                                         mstatus = rtw_read8(Adapter, REG_WOW_CTRL);
3434                                         DBG_871X_LEVEL(_drv_info_, "%s mstatus:0x%02x\n", __func__, mstatus);
3435
3436                                         while(mstatus&BIT1 && trycnt>1) {
3437                                                 mstatus = rtw_read8(Adapter, REG_WOW_CTRL);
3438                                                 DBG_871X_LEVEL(_drv_always_, "Loop index: %d :0x%02x\n", trycnt, mstatus);
3439                                                 trycnt --;
3440                                                 rtw_msleep_os(2);
3441                                         }
3442
3443                                         if (mstatus & BIT1) {
3444                                                 DBG_871X_LEVEL(_drv_always_, "Disable WOW mode fail!!\n");
3445                                                 DBG_871X("Set 0x690=0x00\n");
3446                                                 rtw_write8(Adapter, REG_WOW_CTRL, (rtw_read8(Adapter, REG_WOW_CTRL)&0xf0));
3447                                                 DBG_871X_LEVEL(_drv_always_, "Release RXDMA\n");
3448                                                 rtw_write32(Adapter, REG_RXPKT_NUM,(rtw_read32(Adapter,REG_RXPKT_NUM)&(~RW_RELEASE_EN)));
3449                                         }
3450
3451                                         // 3.1 read fw iv
3452                                         iv_low = rtw_read32(Adapter, REG_TXPKTBUF_IV_LOW);
3453                                         //only low two bytes is PN, check AES_IV macro for detail
3454                                         iv_low &= 0xffff;
3455                                         iv_high = rtw_read32(Adapter, REG_TXPKTBUF_IV_HIGH);
3456                                         //get the real packet number
3457                                         pwrctl->wowlan_fw_iv = iv_high << 16 | iv_low;
3458                                         DBG_871X_LEVEL(_drv_always_, "fw_iv: 0x%016llx\n", pwrctl->wowlan_fw_iv);
3459                                         //Update TX iv data.
3460                                         rtw_set_sec_pn(Adapter);
3461
3462                                         SetFwRelatedForWoWLAN8188ES(Adapter, _FALSE);
3463
3464                                         if((pwrctl->wowlan_wake_reason != FWDecisionDisconnect) &&
3465                                                 (pwrctl->wowlan_wake_reason != Rx_Pairwisekey) &&
3466                                                 (pwrctl->wowlan_wake_reason != Rx_DisAssoc) &&
3467                                                 (pwrctl->wowlan_wake_reason != Rx_DeAuth))
3468                                                 rtl8188e_set_FwJoinBssReport_cmd(Adapter, 1);
3469
3470                                         rtw_msleep_os(5);
3471                                         break;
3472                                 default:
3473                                         break;
3474                         }
3475                 }
3476                 break;
3477 #endif //CONFIG_WOWLAN
3478
3479
3480         #if (RATE_ADAPTIVE_SUPPORT == 1)
3481                 case HW_VAR_TX_RPT_MAX_MACID:
3482                         {
3483                                 u8 maxMacid = *val;
3484                                 DBG_871X("### MacID(%d),Set Max Tx RPT MID(%d)\n",maxMacid,maxMacid+1);
3485                                 rtw_write8(Adapter, REG_TX_RPT_CTRL+1, maxMacid+1);
3486                         }
3487                         break;
3488         #endif
3489                 case HW_VAR_H2C_MEDIA_STATUS_RPT:
3490                         {
3491                                 rtl8188e_set_FwMediaStatus_cmd(Adapter , (*(u16 *)val));
3492                         }
3493                         break;
3494                 case HW_VAR_BCN_VALID:
3495                         //BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2, write 1 to clear, Clear by sw
3496                         rtw_write8(Adapter, REG_TDECTRL+2, rtw_read8(Adapter, REG_TDECTRL+2) | BIT0);
3497                         break;
3498
3499                 default:
3500                         SetHwReg8188E(Adapter, variable, val);
3501                         break;
3502         }
3503
3504 _func_exit_;
3505 }
3506
3507 void GetHwReg8188EU(PADAPTER Adapter, u8 variable, u8* val)
3508 {
3509         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3510         DM_ODM_T                *podmpriv = &pHalData->odmpriv;
3511 _func_enter_;
3512
3513         switch(variable)
3514         {
3515                 case HW_VAR_TXPAUSE:
3516                         val[0] = rtw_read8(Adapter, REG_TXPAUSE);
3517                         break;
3518                 case HW_VAR_BCN_VALID:
3519                         //BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2
3520                         val[0] = (BIT0 & rtw_read8(Adapter, REG_TDECTRL+2))?_TRUE:_FALSE;
3521                         break;
3522                 case HW_VAR_FWLPS_RF_ON:
3523                         {
3524                                 //When we halt NIC, we should check if FW LPS is leave.
3525                                 if(adapter_to_pwrctl(Adapter)->rf_pwrstate == rf_off)
3526                                 {
3527                                         // If it is in HW/SW Radio OFF or IPS state, we do not check Fw LPS Leave,
3528                                         // because Fw is unload.
3529                                         val[0] = _TRUE;
3530                                 }
3531                                 else
3532                                 {
3533                                         u32 valRCR;
3534                                         valRCR = rtw_read32(Adapter, REG_RCR);
3535                                         valRCR &= 0x00070000;
3536                                         if(valRCR)
3537                                                 val[0] = _FALSE;
3538                                         else
3539                                                 val[0] = _TRUE;
3540                                 }
3541                         }
3542                         break;
3543 #ifdef CONFIG_ANTENNA_DIVERSITY
3544                 case HW_VAR_CURRENT_ANTENNA:
3545                         val[0] = pHalData->CurAntenna;
3546                         break;
3547 #endif
3548                 case HW_VAR_EFUSE_BYTES: // To get EFUE total used bytes, added by Roger, 2008.12.22.
3549                         *((u16 *)(val)) = pHalData->EfuseUsedBytes;
3550                         break;
3551                 case HW_VAR_APFM_ON_MAC:
3552                         *val = pHalData->bMacPwrCtrlOn;
3553                         break;
3554                 case HW_VAR_CHK_HI_QUEUE_EMPTY:
3555                         *val = ((rtw_read32(Adapter, REG_HGQ_INFO)&0x0000ff00)==0) ? _TRUE:_FALSE;
3556                         break;
3557                 default:
3558                         GetHwReg8188E(Adapter, variable, val);
3559                         break;
3560         }
3561
3562 _func_exit_;
3563 }
3564
3565 //
3566 //      Description:
3567 //              Query setting of specified variable.
3568 //
3569 u8
3570 GetHalDefVar8188EUsb(
3571         IN      PADAPTER                                Adapter,
3572         IN      HAL_DEF_VARIABLE                eVariable,
3573         IN      PVOID                                   pValue
3574         )
3575 {
3576         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3577         u8                      bResult = _SUCCESS;
3578
3579         switch(eVariable)
3580         {
3581                 case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
3582 #if 1 //trunk
3583                         {
3584                                 struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
3585                                 struct sta_priv * pstapriv = &Adapter->stapriv;
3586                                 struct sta_info * psta;
3587                                 psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress);
3588                                 if(psta)
3589                                 {
3590                                         *((int *)pValue) = psta->rssi_stat.UndecoratedSmoothedPWDB;
3591                                 }
3592                         }
3593 #else //V4 branch
3594                                 if(check_fwstate(&Adapter->mlmepriv, WIFI_STATION_STATE) == _TRUE){
3595                                                 *((int *)pValue) = pHalData->dmpriv.UndecoratedSmoothedPWDB;
3596                                 }
3597                                 else{
3598
3599                                 }
3600 #endif
3601                         break;
3602                 case HAL_DEF_IS_SUPPORT_ANT_DIV:
3603 #ifdef CONFIG_ANTENNA_DIVERSITY
3604                         *((u8 *)pValue) = (pHalData->AntDivCfg==0)?_FALSE:_TRUE;
3605 #endif
3606                         break;
3607                 case HAL_DEF_CURRENT_ANTENNA:
3608 #ifdef CONFIG_ANTENNA_DIVERSITY
3609                         *(( u8*)pValue) = pHalData->CurAntenna;
3610 #endif
3611                         break;
3612                 case HAL_DEF_DRVINFO_SZ:
3613                         *(( u32*)pValue) = DRVINFO_SZ;
3614                         break;
3615                 case HAL_DEF_MAX_RECVBUF_SZ:
3616                         *(( u32*)pValue) = MAX_RECVBUF_SZ;
3617                         break;
3618                 case HAL_DEF_RX_PACKET_OFFSET:
3619                         *(( u32*)pValue) = RXDESC_SIZE + DRVINFO_SZ;
3620                         break;
3621 #if (RATE_ADAPTIVE_SUPPORT == 1)
3622                 case HAL_DEF_RA_DECISION_RATE:
3623                         {
3624                                 u8 MacID = *((u8*)pValue);
3625                                 *((u8*)pValue) = ODM_RA_GetDecisionRate_8188E(&(pHalData->odmpriv), MacID);
3626                         }
3627                         break;
3628
3629                 case HAL_DEF_RA_SGI:
3630                         {
3631                                 u8 MacID = *((u8*)pValue);
3632                                 *((u8*)pValue) = ODM_RA_GetShortGI_8188E(&(pHalData->odmpriv), MacID);
3633                         }
3634                         break;
3635 #endif
3636
3637
3638                 case HAL_DEF_PT_PWR_STATUS:
3639 #if(POWER_TRAINING_ACTIVE==1)
3640                         {
3641                                 u8 MacID = *((u8*)pValue);
3642                                 *((u8*)pValue) = ODM_RA_GetHwPwrStatus_8188E(&(pHalData->odmpriv), MacID);
3643                         }
3644 #endif//(POWER_TRAINING_ACTIVE==1)
3645                         break;
3646
3647                 case HW_VAR_MAX_RX_AMPDU_FACTOR:
3648                         *(( u32*)pValue) = MAX_AMPDU_FACTOR_64K;
3649                         break;
3650
3651                 case HAL_DEF_TX_LDPC:
3652                 case HAL_DEF_RX_LDPC:
3653                         *((u8 *)pValue) = _FALSE;
3654                         break;
3655                 case HAL_DEF_TX_STBC:
3656                         *((u8 *)pValue) = 0;
3657                         break;
3658                 case HAL_DEF_RX_STBC:
3659                         *((u8 *)pValue) = 1;
3660                         break;
3661                 case HAL_DEF_EXPLICIT_BEAMFORMEE:
3662                 case HAL_DEF_EXPLICIT_BEAMFORMER:
3663                         *((u8 *)pValue) = _FALSE;
3664                         break;
3665
3666                 case HW_DEF_RA_INFO_DUMP:
3667 #if (RATE_ADAPTIVE_SUPPORT == 1)
3668                         {
3669                                 u8 mac_id = *((u8*)pValue);
3670                                 u8                      bLinked = _FALSE;
3671 #ifdef CONFIG_CONCURRENT_MODE
3672                                 PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter;
3673 #endif //CONFIG_CONCURRENT_MODE
3674
3675                                 if(rtw_linked_check(Adapter))
3676                                         bLinked = _TRUE;
3677
3678 #ifdef CONFIG_CONCURRENT_MODE
3679                                 if(pbuddy_adapter && rtw_linked_check(pbuddy_adapter))
3680                                         bLinked = _TRUE;
3681 #endif
3682
3683                                 if(bLinked){
3684                                         DBG_871X("============ RA status - Mac_id:%d ===================\n",mac_id);
3685
3686                                         DBG_8192C("Mac_id:%d ,RSSI:%d(%%),PTStage = %d\n",
3687                                                 mac_id,pHalData->odmpriv.RAInfo[mac_id].RssiStaRA,pHalData->odmpriv.RAInfo[mac_id].PTStage);
3688
3689                                         DBG_8192C("RateID = %d,RAUseRate = 0x%08x,RateSGI = %d, DecisionRate = %s\n",
3690                                                 pHalData->odmpriv.RAInfo[mac_id].RateID,
3691                                                 pHalData->odmpriv.RAInfo[mac_id].RAUseRate,
3692                                                 pHalData->odmpriv.RAInfo[mac_id].RateSGI,
3693                                                 HDATA_RATE(pHalData->odmpriv.RAInfo[mac_id].DecisionRate));
3694
3695                                 }
3696                         }
3697 #endif  //(RATE_ADAPTIVE_SUPPORT == 1)
3698                         break;
3699                 default:
3700                         bResult = GetHalDefVar8188E(Adapter, eVariable, pValue);
3701                         break;
3702         }
3703
3704         return bResult;
3705 }
3706
3707
3708
3709
3710 //
3711 //      Description:
3712 //              Change default setting of specified variable.
3713 //
3714 u8
3715 SetHalDefVar8188EUsb(
3716         IN      PADAPTER                                Adapter,
3717         IN      HAL_DEF_VARIABLE                eVariable,
3718         IN      PVOID                                   pValue
3719         )
3720 {
3721         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3722         u8                      bResult = _SUCCESS;
3723
3724         switch(eVariable)
3725         {
3726                 default:
3727                         bResult = SetHalDefVar(Adapter, eVariable, pValue);
3728                         break;
3729         }
3730
3731         return bResult;
3732 }
3733 /*
3734 u32  _update_92cu_basic_rate(_adapter *padapter, unsigned int mask)
3735 {
3736         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(padapter);
3737 #ifdef CONFIG_BT_COEXIST
3738         struct btcoexist_priv   *pbtpriv = &(pHalData->bt_coexist);
3739 #endif
3740         unsigned int BrateCfg = 0;
3741
3742 #ifdef CONFIG_BT_COEXIST
3743         if(     (pbtpriv->BT_Coexist) &&        (pbtpriv->BT_CoexistType == BT_CSR_BC4) )
3744         {
3745                 BrateCfg = mask  & 0x151;
3746                 //DBG_8192C("BT temp disable cck 2/5.5/11M, (0x%x = 0x%x)\n", REG_RRSR, BrateCfg & 0x151);
3747         }
3748         else
3749 #endif
3750         {
3751                 //if(pHalData->VersionID != VERSION_TEST_CHIP_88C)
3752                         BrateCfg = mask  & 0x15F;
3753                 //else  //for 88CU 46PING setting, Disable CCK 2M, 5.5M, Others must tuning
3754                 //      BrateCfg = mask  & 0x159;
3755         }
3756
3757         BrateCfg |= 0x01; // default enable 1M ACK rate
3758
3759         return BrateCfg;
3760 }
3761 */
3762 void _update_response_rate(_adapter *padapter,unsigned int mask)
3763 {
3764         u8      RateIndex = 0;
3765         // Set RRSR rate table.
3766         rtw_write8(padapter, REG_RRSR, mask&0xff);
3767         rtw_write8(padapter,REG_RRSR+1, (mask>>8)&0xff);
3768
3769         // Set RTS initial rate
3770         while(mask > 0x1)
3771         {
3772                 mask = (mask>> 1);
3773                 RateIndex++;
3774         }
3775         rtw_write8(padapter, REG_INIRTS_RATE_SEL, RateIndex);
3776 }
3777
3778 void SetBeaconRelatedRegisters8188EUsb(PADAPTER padapter)
3779 {
3780         u32     value32;
3781         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3782         struct mlme_ext_priv    *pmlmeext = &(padapter->mlmeextpriv);
3783         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
3784         u32 bcn_ctrl_reg                        = REG_BCN_CTRL;
3785         //reset TSF, enable update TSF, correcting TSF On Beacon
3786
3787         //REG_BCN_INTERVAL
3788         //REG_BCNDMATIM
3789         //REG_ATIMWND
3790         //REG_TBTT_PROHIBIT
3791         //REG_DRVERLYINT
3792         //REG_BCN_MAX_ERR
3793         //REG_BCNTCFG //(0x510)
3794         //REG_DUAL_TSF_RST
3795         //REG_BCN_CTRL //(0x550)
3796
3797         //BCN interval
3798 #ifdef CONFIG_CONCURRENT_MODE
3799                 if (padapter->iface_type == IFACE_PORT1){
3800                 bcn_ctrl_reg = REG_BCN_CTRL_1;
3801                 }
3802 #endif
3803         rtw_write16(padapter, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval);
3804         rtw_write8(padapter, REG_ATIMWND, 0x02);// 2ms
3805
3806         _InitBeaconParameters(padapter);
3807
3808         rtw_write8(padapter, REG_SLOT, 0x09);
3809
3810         value32 =rtw_read32(padapter, REG_TCR);
3811         value32 &= ~TSFRST;
3812         rtw_write32(padapter,  REG_TCR, value32);
3813
3814         value32 |= TSFRST;
3815         rtw_write32(padapter, REG_TCR, value32);
3816
3817         // NOTE: Fix test chip's bug (about contention windows's randomness)
3818         rtw_write8(padapter,  REG_RXTSF_OFFSET_CCK, 0x50);
3819         rtw_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50);
3820
3821         _BeaconFunctionEnable(padapter, _TRUE, _TRUE);
3822
3823         ResumeTxBeacon(padapter);
3824
3825         //rtw_write8(padapter, 0x422, rtw_read8(padapter, 0x422)|BIT(6));
3826
3827         //rtw_write8(padapter, 0x541, 0xff);
3828
3829         //rtw_write8(padapter, 0x542, rtw_read8(padapter, 0x541)|BIT(0));
3830
3831         rtw_write8(padapter, bcn_ctrl_reg, rtw_read8(padapter, bcn_ctrl_reg)|BIT(1));
3832
3833 }
3834
3835 static void rtl8188eu_init_default_value(_adapter * padapter)
3836 {
3837         PHAL_DATA_TYPE pHalData;
3838         struct pwrctrl_priv *pwrctrlpriv;
3839         struct dm_priv *pdmpriv;
3840         u8 i;
3841
3842         pHalData = GET_HAL_DATA(padapter);
3843         pwrctrlpriv = adapter_to_pwrctl(padapter);
3844         pdmpriv = &pHalData->dmpriv;
3845
3846         padapter->registrypriv.wireless_mode = WIRELESS_11BG_24N;
3847         //init default value
3848         pHalData->fw_ractrl = _FALSE;
3849         if(!pwrctrlpriv->bkeepfwalive)
3850                 pHalData->LastHMEBoxNum = 0;
3851
3852         //init dm default value
3853         pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = _FALSE;
3854         pHalData->odmpriv.RFCalibrateInfo.TM_Trigger = 0;//for IQK
3855         //pdmpriv->binitialized = _FALSE;
3856 //      pdmpriv->prv_traffic_idx = 3;
3857 //      pdmpriv->initialize = 0;
3858         pHalData->pwrGroupCnt = 0;
3859         pHalData->PGMaxGroup= 13;
3860         pHalData->odmpriv.RFCalibrateInfo.ThermalValue_HP_index = 0;
3861         for(i = 0; i < HP_THERMAL_NUM; i++)
3862                 pHalData->odmpriv.RFCalibrateInfo.ThermalValue_HP[i] = 0;
3863
3864         pHalData->EfuseHal.fakeEfuseBank = 0;
3865         pHalData->EfuseHal.fakeEfuseUsedBytes = 0;
3866         _rtw_memset(pHalData->EfuseHal.fakeEfuseContent, 0xFF, EFUSE_MAX_HW_SIZE);
3867         _rtw_memset(pHalData->EfuseHal.fakeEfuseInitMap, 0xFF, EFUSE_MAX_MAP_LEN);
3868         _rtw_memset(pHalData->EfuseHal.fakeEfuseModifiedMap, 0xFF, EFUSE_MAX_MAP_LEN);
3869 }
3870
3871 static u8 rtl8188eu_ps_func(PADAPTER Adapter,HAL_INTF_PS_FUNC efunc_id, u8 *val)
3872 {
3873         u8 bResult = _TRUE;
3874         switch(efunc_id){
3875
3876                 #if defined(CONFIG_AUTOSUSPEND) && defined(SUPPORT_HW_RFOFF_DETECTED)
3877                 case HAL_USB_SELECT_SUSPEND:
3878                         {
3879                                 u8 bfwpoll = *(( u8*)val);
3880                                 //rtl8188e_set_FwSelectSuspend_cmd(Adapter,bfwpoll ,500);//note fw to support hw power down ping detect
3881                         }
3882                         break;
3883                 #endif //CONFIG_AUTOSUSPEND && SUPPORT_HW_RFOFF_DETECTED
3884
3885                 default:
3886                         break;
3887         }
3888         return bResult;
3889 }
3890
3891 void rtl8188eu_set_hal_ops(_adapter * padapter)
3892 {
3893         struct hal_ops  *pHalFunc = &padapter->HalFunc;
3894
3895 _func_enter_;
3896
3897 #ifdef CONFIG_CONCURRENT_MODE
3898         if(padapter->isprimary)
3899 #endif //CONFIG_CONCURRENT_MODE
3900         {
3901                 padapter->HalData = rtw_zvmalloc(sizeof(HAL_DATA_TYPE));
3902                 if(padapter->HalData == NULL){
3903                         DBG_8192C("cant not alloc memory for HAL DATA \n");
3904                 }
3905         }
3906
3907         //_rtw_memset(padapter->HalData, 0, sizeof(HAL_DATA_TYPE));
3908         padapter->hal_data_sz = sizeof(HAL_DATA_TYPE);
3909
3910         pHalFunc->hal_power_on = _InitPowerOn_8188EU;
3911         pHalFunc->hal_power_off = hal_poweroff_8188eu;
3912
3913         pHalFunc->hal_init = &rtl8188eu_hal_init;
3914         pHalFunc->hal_deinit = &rtl8188eu_hal_deinit;
3915
3916         //pHalFunc->free_hal_data = &rtl8192c_free_hal_data;
3917
3918         pHalFunc->inirp_init = &rtl8188eu_inirp_init;
3919         pHalFunc->inirp_deinit = &rtl8188eu_inirp_deinit;
3920
3921         pHalFunc->init_xmit_priv = &rtl8188eu_init_xmit_priv;
3922         pHalFunc->free_xmit_priv = &rtl8188eu_free_xmit_priv;
3923
3924         pHalFunc->init_recv_priv = &rtl8188eu_init_recv_priv;
3925         pHalFunc->free_recv_priv = &rtl8188eu_free_recv_priv;
3926 #ifdef CONFIG_SW_LED
3927         pHalFunc->InitSwLeds = &rtl8188eu_InitSwLeds;
3928         pHalFunc->DeInitSwLeds = &rtl8188eu_DeInitSwLeds;
3929 #else //case of hw led or no led
3930         pHalFunc->InitSwLeds = NULL;
3931         pHalFunc->DeInitSwLeds = NULL;
3932 #endif//CONFIG_SW_LED
3933
3934         pHalFunc->init_default_value = &rtl8188eu_init_default_value;
3935         pHalFunc->intf_chip_configure = &rtl8188eu_interface_configure;
3936         pHalFunc->read_adapter_info = &ReadAdapterInfo8188EU;
3937
3938         //pHalFunc->set_bwmode_handler = &PHY_SetBWMode8192C;
3939         //pHalFunc->set_channel_handler = &PHY_SwChnl8192C;
3940
3941         //pHalFunc->hal_dm_watchdog = &rtl8192c_HalDmWatchDog;
3942
3943
3944         pHalFunc->SetHwRegHandler = &SetHwReg8188EU;
3945         pHalFunc->GetHwRegHandler = &GetHwReg8188EU;
3946         pHalFunc->GetHalDefVarHandler = &GetHalDefVar8188EUsb;
3947         pHalFunc->SetHalDefVarHandler = &SetHalDefVar8188EUsb;
3948
3949         pHalFunc->SetBeaconRelatedRegistersHandler = &SetBeaconRelatedRegisters8188EUsb;
3950
3951         //pHalFunc->Add_RateATid = &rtl8192c_Add_RateATid;
3952
3953         pHalFunc->hal_xmit = &rtl8188eu_hal_xmit;
3954         pHalFunc->mgnt_xmit = &rtl8188eu_mgnt_xmit;
3955         pHalFunc->hal_xmitframe_enqueue = &rtl8188eu_hal_xmitframe_enqueue;
3956
3957
3958 #ifdef CONFIG_HOSTAPD_MLME
3959         pHalFunc->hostap_mgnt_xmit_entry = &rtl8188eu_hostap_mgnt_xmit_entry;
3960 #endif
3961         pHalFunc->interface_ps_func = &rtl8188eu_ps_func;
3962
3963 #ifdef CONFIG_XMIT_THREAD_MODE
3964         pHalFunc->xmit_thread_handler = &rtl8188eu_xmit_buf_handler;
3965 #endif
3966         rtl8188e_set_hal_ops(pHalFunc);
3967 _func_exit_;
3968
3969 }
3970