drivers/net/wireless/rockchip_wlan/rtl8188eu/hal/rtl8188e/rtl8188e_phycfg.c

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *\r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *\r
  19  ******************************************************************************/\r
  20 #define _RTL8188E_PHYCFG_C_\r
  21 \r
  22 #include <drv_types.h>\r
  23 #include <rtl8188e_hal.h>\r
  24 \r
  25 \r
  26 /*---------------------------Define Local Constant---------------------------*/\r
  27 /* Channel switch:The size of command tables for switch channel*/\r
  28 #define MAX_PRECMD_CNT 16\r
  29 #define MAX_RFDEPENDCMD_CNT 16\r
  30 #define MAX_POSTCMD_CNT 16\r
  31 \r
  32 #define MAX_DOZE_WAITING_TIMES_9x 64\r
  33 \r
  34 /*---------------------------Define Local Constant---------------------------*/\r
  35 \r
  36 \r
  37 /*------------------------Define global variable-----------------------------*/\r
  38 \r
  39 /*------------------------Define local variable------------------------------*/\r
  40 \r
  41 \r
  42 /*--------------------Define export function prototype-----------------------*/\r
  43 // Please refer to header file\r
  44 /*--------------------Define export function prototype-----------------------*/\r
  45 \r
  46 /*----------------------------Function Body----------------------------------*/\r
  47 //\r
  48 // 1. BB register R/W API\r
  49 //\r
  50 \r
  51 #if(SIC_ENABLE == 1)\r
  52 static BOOLEAN\r
  53 sic_IsSICReady(\r
  54         IN      PADAPTER        Adapter\r
  55         )\r
  56 {\r
  57         BOOLEAN         bRet=_FALSE;\r
  58         u32             retryCnt=0;\r
  59         u8              sic_cmd=0xff;\r
  60 \r
  61         while(1)\r
  62         {               \r
  63                 if(retryCnt++ >= SIC_MAX_POLL_CNT)\r
  64                 {\r
  65                         //RTPRINT(FPHY, (PHY_SICR|PHY_SICW), ("[SIC], sic_IsSICReady() return FALSE\n"));\r
  66                         return _FALSE;\r
  67                 }\r
  68 \r
  69                 //if(RT_SDIO_CANNOT_IO(Adapter))\r
  70                 //      return _FALSE;\r
  71 \r
  72                 sic_cmd = rtw_read8(Adapter, SIC_CMD_REG);\r
  73                 //sic_cmd = PlatformEFIORead1Byte(Adapter, SIC_CMD_REG);\r
  74 #if(SIC_HW_SUPPORT == 1)\r
  75                 sic_cmd &= 0xf0;        // [7:4]\r
  76 #endif\r
  77                 //RTPRINT(FPHY, (PHY_SICR|PHY_SICW), ("[SIC], sic_IsSICReady(), readback 0x%x=0x%x\n", SIC_CMD_REG, sic_cmd));\r
  78                 if(sic_cmd == SIC_CMD_READY)\r
  79                         return _TRUE;\r
  80                 else\r
  81                 {\r
  82                         rtw_msleep_os(1);\r
  83                         //delay_ms(1);\r
  84                 }\r
  85         }\r
  86 \r
  87         return bRet;\r
  88 }\r
  89 \r
  90 /*\r
  91 u32\r
  92 sic_CalculateBitShift(\r
  93         u32 BitMask\r
  94         )\r
  95 {\r
  96         u32 i;\r
  97 \r
  98         for(i=0; i<=31; i++)\r
  99         {\r
 100                 if ( ((BitMask>>i) &  0x1 ) == 1)\r
 101                         break;\r
 102         }\r
 103 \r
 104         return (i);\r
 105 }\r
 106 */\r
 107 \r
 108 static u32\r
 109 sic_Read4Byte(\r
 110         PVOID           Adapter,\r
 111         u32             offset\r
 112         )\r
 113 {\r
 114         u32     u4ret=0xffffffff;\r
 115 #if RTL8188E_SUPPORT == 1\r
 116         u8      retry = 0;\r
 117 #endif\r
 118 \r
 119         //RTPRINT(FPHY, PHY_SICR, ("[SIC], sic_Read4Byte(): read offset(%#x)\n", offset));\r
 120         \r
 121         if(sic_IsSICReady(Adapter))\r
 122         {\r
 123 #if(SIC_HW_SUPPORT == 1)\r
 124                 rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_PREREAD);\r
 125                 //PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_PREREAD);\r
 126                 //RTPRINT(FPHY, PHY_SICR, ("write cmdreg 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_PREREAD));\r
 127 #endif\r
 128                 rtw_write8(Adapter, SIC_ADDR_REG, (u8)(offset&0xff));\r
 129                 //PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG, (u1Byte)(offset&0xff));\r
 130                 //RTPRINT(FPHY, PHY_SICR, ("write 0x%x = 0x%x\n", SIC_ADDR_REG, (u1Byte)(offset&0xff)));\r
 131                 rtw_write8(Adapter, SIC_ADDR_REG+1, (u8)((offset&0xff00)>>8));\r
 132                 //PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG+1, (u1Byte)((offset&0xff00)>>8));\r
 133                 //RTPRINT(FPHY, PHY_SICR, ("write 0x%x = 0x%x\n", SIC_ADDR_REG+1, (u1Byte)((offset&0xff00)>>8)));\r
 134                 rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_READ);\r
 135                 //PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_READ);\r
 136                 //RTPRINT(FPHY, PHY_SICR, ("write cmdreg 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_READ));\r
 137 \r
 138 #if RTL8188E_SUPPORT == 1\r
 139                 retry = 4;\r
 140                 while(retry--){                 \r
 141                         rtw_udelay_os(50);\r
 142                         //PlatformStallExecution(50);\r
 143                 }\r
 144 #else\r
 145                 rtw_udelay_os(200);\r
 146                 //PlatformStallExecution(200);\r
 147 #endif\r
 148 \r
 149                 if(sic_IsSICReady(Adapter))\r
 150                 {\r
 151                         u4ret = rtw_read32(Adapter, SIC_DATA_REG);\r
 152                         //u4ret = PlatformEFIORead4Byte(Adapter, SIC_DATA_REG);\r
 153                         //RTPRINT(FPHY, PHY_SICR, ("read 0x%x = 0x%x\n", SIC_DATA_REG, u4ret));\r
 154                         //DbgPrint("<===Read 0x%x = 0x%x\n", offset, u4ret);\r
 155                 }\r
 156         }\r
 157         \r
 158         return u4ret;\r
 159 }\r
 160 \r
 161 static VOID\r
 162 sic_Write4Byte(\r
 163         PVOID           Adapter,\r
 164         u32             offset,\r
 165         u32             data\r
 166         )\r
 167 {\r
 168 #if RTL8188E_SUPPORT == 1\r
 169         u8      retry = 6;\r
 170 #endif\r
 171         //DbgPrint("=>Write 0x%x = 0x%x\n", offset, data);\r
 172         //RTPRINT(FPHY, PHY_SICW, ("[SIC], sic_Write4Byte(): write offset(%#x)=0x%x\n", offset, data));\r
 173         if(sic_IsSICReady(Adapter))\r
 174         {\r
 175 #if(SIC_HW_SUPPORT == 1)\r
 176                 rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_PREWRITE);\r
 177                 //PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_PREWRITE);\r
 178                 //RTPRINT(FPHY, PHY_SICW, ("write data 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_PREWRITE));\r
 179 #endif\r
 180                 rtw_write8(Adapter, SIC_ADDR_REG, (u8)(offset&0xff));\r
 181                 //PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG, (u1Byte)(offset&0xff));\r
 182                 //RTPRINT(FPHY, PHY_SICW, ("write 0x%x=0x%x\n", SIC_ADDR_REG, (u1Byte)(offset&0xff)));\r
 183                 rtw_write8(Adapter, SIC_ADDR_REG+1, (u8)((offset&0xff00)>>8));\r
 184                 //PlatformEFIOWrite1Byte(Adapter, SIC_ADDR_REG+1, (u1Byte)((offset&0xff00)>>8));\r
 185                 //RTPRINT(FPHY, PHY_SICW, ("write 0x%x=0x%x\n", (SIC_ADDR_REG+1), (u1Byte)((offset&0xff00)>>8)));\r
 186                 rtw_write32(Adapter, SIC_DATA_REG, (u32)data);\r
 187                 //PlatformEFIOWrite4Byte(Adapter, SIC_DATA_REG, (u4Byte)data);\r
 188                 //RTPRINT(FPHY, PHY_SICW, ("write data 0x%x = 0x%x\n", SIC_DATA_REG, data));\r
 189                 rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_WRITE);\r
 190                 //PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_WRITE);\r
 191                 //RTPRINT(FPHY, PHY_SICW, ("write data 0x%x = 0x%x\n", SIC_CMD_REG, SIC_CMD_WRITE));\r
 192 #if RTL8188E_SUPPORT == 1\r
 193                 while(retry--){\r
 194                         rtw_udelay_os(50);\r
 195                         //PlatformStallExecution(50);\r
 196                 }\r
 197 #else\r
 198                 rtw_udelay_os(150);\r
 199                 //PlatformStallExecution(150);\r
 200 #endif\r
 201 \r
 202         }\r
 203 }\r
 204 //============================================================\r
 205 // extern function\r
 206 //============================================================\r
 207 static VOID\r
 208 SIC_SetBBReg(\r
 209         IN      PADAPTER        Adapter,\r
 210         IN      u32             RegAddr,\r
 211         IN      u32             BitMask,\r
 212         IN      u32             Data\r
 213         )\r
 214 {\r
 215         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
 216         u32                     OriginalValue, BitShift;\r
 217         u16                     BBWaitCounter = 0;\r
 218 \r
 219         //RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_SetBBReg() start\n"));\r
 220 /*\r
 221         while(PlatformAtomicExchange(&pHalData->bChangeBBInProgress, _TRUE) == _TRUE)\r
 222         {\r
 223                 BBWaitCounter ++;\r
 224                 delay_ms(10); // 1 ms\r
 225 \r
 226                 if((BBWaitCounter > 100) || RT_CANNOT_IO(Adapter))\r
 227                 {// Wait too long, return FALSE to avoid to be stuck here.\r
 228                         RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_SetBBReg(), Fail to set BB offset(%#x)!!, WaitCnt(%d)\n", RegAddr, BBWaitCounter));\r
 229                         return;\r
 230                 }               \r
 231         }\r
 232 */\r
 233         //\r
 234         // Critical section start\r
 235         // \r
 236         \r
 237         //RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_SetBBReg(), mask=0x%x, addr[0x%x]=0x%x\n", BitMask, RegAddr, Data));\r
 238 \r
 239         if(BitMask!= bMaskDWord){//if not "double word" write\r
 240                 OriginalValue = sic_Read4Byte(Adapter, RegAddr);\r
 241                 //BitShift = sic_CalculateBitShift(BitMask);\r
 242                 BitShift = PHY_CalculateBitShift(BitMask);              \r
 243                 Data = (((OriginalValue) & (~BitMask)) | (Data << BitShift));\r
 244         }\r
 245 \r
 246         sic_Write4Byte(Adapter, RegAddr, Data);\r
 247 \r
 248         //PlatformAtomicExchange(&pHalData->bChangeBBInProgress, _FALSE);\r
 249         //RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_SetBBReg() end\n"));\r
 250 }\r
 251 \r
 252 static u32\r
 253 SIC_QueryBBReg(\r
 254         IN      PADAPTER        Adapter,\r
 255         IN      u32             RegAddr,\r
 256         IN      u32             BitMask\r
 257         )\r
 258 {\r
 259         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
 260         u32                     ReturnValue = 0, OriginalValue, BitShift;\r
 261         u16                     BBWaitCounter = 0;\r
 262 \r
 263         //RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_QueryBBReg() start\n"));\r
 264 \r
 265 /*\r
 266         while(PlatformAtomicExchange(&pHalData->bChangeBBInProgress, _TRUE) == _TRUE)\r
 267         {\r
 268                 BBWaitCounter ++;\r
 269                 delay_ms(10); // 10 ms\r
 270 \r
 271                 if((BBWaitCounter > 100) || RT_CANNOT_IO(Adapter))\r
 272                 {// Wait too long, return FALSE to avoid to be stuck here.\r
 273                         RTPRINT(FPHY, PHY_SICW, ("[SIC], SIC_QueryBBReg(), Fail to query BB offset(%#x)!!, WaitCnt(%d)\n", RegAddr, BBWaitCounter));\r
 274                         return ReturnValue;\r
 275                 }               \r
 276         }\r
 277 */\r
 278         OriginalValue = sic_Read4Byte(Adapter, RegAddr);\r
 279         //BitShift = sic_CalculateBitShift(BitMask);\r
 280         BitShift = PHY_CalculateBitShift(BitMask);\r
 281         ReturnValue = (OriginalValue & BitMask) >> BitShift;\r
 282 \r
 283         //RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_QueryBBReg(), 0x%x=0x%x\n", RegAddr, OriginalValue));\r
 284         //RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_QueryBBReg() end\n"));\r
 285 \r
 286         //PlatformAtomicExchange(&pHalData->bChangeBBInProgress, _FALSE);       \r
 287         return (ReturnValue);\r
 288 }\r
 289 \r
 290 VOID\r
 291 SIC_Init(\r
 292         IN      PADAPTER        Adapter\r
 293         )\r
 294 {\r
 295         // Here we need to write 0x1b8~0x1bf = 0 after fw is downloaded\r
 296         // because for 8723E at beginning 0x1b8=0x1e, that will cause\r
 297         // sic always not be ready\r
 298 #if(SIC_HW_SUPPORT == 1)\r
 299         //RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_Init(), write 0x%x = 0x%x\n", \r
 300         //      SIC_INIT_REG, SIC_INIT_VAL));\r
 301         rtw_write8(Adapter, SIC_INIT_REG, SIC_INIT_VAL);\r
 302         //PlatformEFIOWrite1Byte(Adapter, SIC_INIT_REG, SIC_INIT_VAL);\r
 303         //RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_Init(), write 0x%x = 0x%x\n", \r
 304         //      SIC_CMD_REG, SIC_CMD_INIT));\r
 305         rtw_write8(Adapter, SIC_CMD_REG, SIC_CMD_INIT);\r
 306         //PlatformEFIOWrite1Byte(Adapter, SIC_CMD_REG, SIC_CMD_INIT);\r
 307 #else\r
 308         //RTPRINT(FPHY, PHY_SICR, ("[SIC], SIC_Init(), write 0x1b8~0x1bf = 0x0\n"));\r
 309         rtw_write32(Adapter, SIC_CMD_REG, 0);\r
 310         //PlatformEFIOWrite4Byte(Adapter, SIC_CMD_REG, 0);\r
 311         rtw_write32(Adapter, SIC_CMD_REG+4, 0);\r
 312         //PlatformEFIOWrite4Byte(Adapter, SIC_CMD_REG+4, 0);\r
 313 #endif\r
 314 }\r
 315 \r
 316 static BOOLEAN\r
 317 SIC_LedOff(\r
 318         IN      PADAPTER        Adapter\r
 319         )\r
 320 {\r
 321         // When SIC is enabled, led pin will be used as debug pin,\r
 322         // so don't execute led function when SIC is enabled.\r
 323         return _TRUE;\r
 324 }\r
 325 #endif\r
 326 \r
 327 /**\r
 328 * Function:     PHY_QueryBBReg\r
 329 *\r
 330 * OverView:     Read "sepcific bits" from BB register\r
 331 *\r
 332 * Input:\r
 333 *                       PADAPTER                Adapter,\r
 334 *                       u4Byte                  RegAddr,                //The target address to be readback\r
 335 *                       u4Byte                  BitMask         //The target bit position in the target address\r
 336 *                                                                               //to be readback\r
 337 * Output:       None\r
 338 * Return:               u4Byte                  Data                    //The readback register value\r
 339 * Note:         This function is equal to "GetRegSetting" in PHY programming guide\r
 340 */\r
 341 u32\r
 342 PHY_QueryBBReg8188E(\r
 343         IN      PADAPTER        Adapter,\r
 344         IN      u32             RegAddr,\r
 345         IN      u32             BitMask\r
 346         )\r
 347 {\r
 348         u32     ReturnValue = 0, OriginalValue, BitShift;\r
 349         u16     BBWaitCounter = 0;\r
 350 \r
 351 #if (DISABLE_BB_RF == 1)\r
 352         return 0;\r
 353 #endif\r
 354 \r
 355 #if(SIC_ENABLE == 1)\r
 356         return SIC_QueryBBReg(Adapter, RegAddr, BitMask);\r
 357 #endif\r
 358 \r
 359         //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx)\n", RegAddr, BitMask));\r
 360 \r
 361         OriginalValue = rtw_read32(Adapter, RegAddr);\r
 362         BitShift = PHY_CalculateBitShift(BitMask);\r
 363         ReturnValue = (OriginalValue & BitMask) >> BitShift;\r
 364 \r
 365         //RTPRINT(FPHY, PHY_BBR, ("BBR MASK=0x%lx Addr[0x%lx]=0x%lx\n", BitMask, RegAddr, OriginalValue));\r
 366         //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx), OriginalValue(%#lx)\n", RegAddr, BitMask, OriginalValue));\r
 367 \r
 368         return (ReturnValue);\r
 369 \r
 370 }\r
 371 \r
 372 \r
 373 /**\r
 374 * Function:     PHY_SetBBReg\r
 375 *\r
 376 * OverView:     Write "Specific bits" to BB register (page 8~)\r
 377 *\r
 378 * Input:\r
 379 *                       PADAPTER                Adapter,\r
 380 *                       u4Byte                  RegAddr,                //The target address to be modified\r
 381 *                       u4Byte                  BitMask         //The target bit position in the target address\r
 382 *                                                                               //to be modified\r
 383 *                       u4Byte                  Data                    //The new register value in the target bit position\r
 384 *                                                                               //of the target address\r
 385 *\r
 386 * Output:       None\r
 387 * Return:               None\r
 388 * Note:         This function is equal to "PutRegSetting" in PHY programming guide\r
 389 */\r
 390 \r
 391 VOID\r
 392 PHY_SetBBReg8188E(\r
 393         IN      PADAPTER        Adapter,\r
 394         IN      u32             RegAddr,\r
 395         IN      u32             BitMask,\r
 396         IN      u32             Data\r
 397         )\r
 398 {\r
 399         HAL_DATA_TYPE   *pHalData               = GET_HAL_DATA(Adapter);\r
 400         //u16                   BBWaitCounter   = 0;\r
 401         u32                     OriginalValue, BitShift;\r
 402 \r
 403 #if (DISABLE_BB_RF == 1)\r
 404         return;\r
 405 #endif\r
 406 \r
 407 #if(SIC_ENABLE == 1)\r
 408         SIC_SetBBReg(Adapter, RegAddr, BitMask, Data);\r
 409         return; \r
 410 #endif\r
 411 \r
 412         //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data));\r
 413 \r
 414         if(BitMask!= bMaskDWord){//if not "double word" write\r
 415                 OriginalValue = rtw_read32(Adapter, RegAddr);\r
 416                 BitShift = PHY_CalculateBitShift(BitMask);\r
 417                 Data = ((OriginalValue & (~BitMask)) | ((Data << BitShift) & BitMask));\r
 418         }\r
 419 \r
 420         rtw_write32(Adapter, RegAddr, Data);\r
 421 \r
 422         //RTPRINT(FPHY, PHY_BBW, ("BBW MASK=0x%lx Addr[0x%lx]=0x%lx\n", BitMask, RegAddr, Data));\r
 423         //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data));\r
 424 \r
 425 }\r
 426 \r
 427 \r
 428 //\r
 429 // 2. RF register R/W API\r
 430 //\r
 431 /**\r
 432 * Function:     phy_RFSerialRead\r
 433 *\r
 434 * OverView:     Read regster from RF chips\r
 435 *\r
 436 * Input:\r
 437 *                       PADAPTER                Adapter,\r
 438 *                       u8                              eRFPath,        //Radio path of A/B/C/D\r
 439 *                       u4Byte                  Offset,         //The target address to be read\r
 440 *\r
 441 * Output:       None\r
 442 * Return:               u4Byte                  reback value\r
 443 * Note:         Threre are three types of serial operations:\r
 444 *                       1. Software serial write\r
 445 *                       2. Hardware LSSI-Low Speed Serial Interface\r
 446 *                       3. Hardware HSSI-High speed\r
 447 *                       serial write. Driver need to implement (1) and (2).\r
 448 *                       This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()\r
 449 */\r
 450 static  u32\r
 451 phy_RFSerialRead(\r
 452         IN      PADAPTER                Adapter,\r
 453         IN      u8                              eRFPath,\r
 454         IN      u32                             Offset\r
 455         )\r
 456 {\r
 457         u32                                             retValue = 0;\r
 458         HAL_DATA_TYPE                           *pHalData = GET_HAL_DATA(Adapter);\r
 459         BB_REGISTER_DEFINITION_T        *pPhyReg = &pHalData->PHYRegDef[eRFPath];\r
 460         u32                                             NewOffset;\r
 461         u32                                             tmplong,tmplong2;\r
 462         u8                                      RfPiEnable=0;\r
 463 #if 0\r
 464         if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs\r
 465                 return  retValue;\r
 466         if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs\r
 467                 return  retValue;\r
 468 #endif\r
 469         //\r
 470         // Make sure RF register offset is correct\r
 471         //\r
 472         Offset &= 0xff;\r
 473 \r
 474         //\r
 475         // Switch page for 8256 RF IC\r
 476         //\r
 477         NewOffset = Offset;\r
 478 \r
 479         // 2009/06/17 MH We can not execute IO for power save or other accident mode.\r
 480         //if(RT_CANNOT_IO(Adapter))\r
 481         //{\r
 482         //      RTPRINT(FPHY, PHY_RFR, ("phy_RFSerialRead return all one\n"));\r
 483         //      return  0xFFFFFFFF;\r
 484         //}\r
 485 \r
 486         // For 92S LSSI Read RFLSSIRead\r
 487         // For RF A/B write 0x824/82c(does not work in the future)\r
 488         // We must use 0x824 for RF A and B to execute read trigger\r
 489         tmplong = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord);\r
 490         if(eRFPath == RF_PATH_A)\r
 491                 tmplong2 = tmplong;\r
 492         else\r
 493                 tmplong2 = PHY_QueryBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord);\r
 494 \r
 495         tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge;  //T65 RF\r
 496 \r
 497         PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong&(~bLSSIReadEdge));\r
 498         rtw_udelay_os(10);// PlatformStallExecution(10);\r
 499 \r
 500         PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2);\r
 501         rtw_udelay_os(100);//PlatformStallExecution(100);\r
 502 \r
 503         //PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong|bLSSIReadEdge);\r
 504         rtw_udelay_os(10);//PlatformStallExecution(10);\r
 505 \r
 506         if(eRFPath == RF_PATH_A)\r
 507                 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1, BIT8);\r
 508         else if(eRFPath == RF_PATH_B)\r
 509                 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1, BIT8);\r
 510 \r
 511         if(RfPiEnable)\r
 512         {       // Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF\r
 513                 retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData);\r
 514                 //DBG_8192C("Readback from RF-PI : 0x%x\n", retValue);\r
 515         }\r
 516         else\r
 517         {       //Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF\r
 518                 retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);\r
 519                 //DBG_8192C("Readback from RF-SI : 0x%x\n", retValue);\r
 520         }\r
 521         //DBG_8192C("RFR-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rfLSSIReadBack, retValue);\r
 522 \r
 523         return retValue;\r
 524 \r
 525 }\r
 526 \r
 527 \r
 528 \r
 529 /**\r
 530 * Function:     phy_RFSerialWrite\r
 531 *\r
 532 * OverView:     Write data to RF register (page 8~)\r
 533 *\r
 534 * Input:\r
 535 *                       PADAPTER                Adapter,\r
 536 *                       u8                              eRFPath,        //Radio path of A/B/C/D\r
 537 *                       u4Byte                  Offset,         //The target address to be read\r
 538 *                       u4Byte                  Data                    //The new register Data in the target bit position\r
 539 *                                                                               //of the target to be read\r
 540 *\r
 541 * Output:       None\r
 542 * Return:               None\r
 543 * Note:         Threre are three types of serial operations:\r
 544 *                       1. Software serial write\r
 545 *                       2. Hardware LSSI-Low Speed Serial Interface\r
 546 *                       3. Hardware HSSI-High speed\r
 547 *                       serial write. Driver need to implement (1) and (2).\r
 548 *                       This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()\r
 549  *\r
 550  * Note:                  For RF8256 only\r
 551  *                       The total count of RTL8256(Zebra4) register is around 36 bit it only employs\r
 552  *                       4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])\r
 553  *                       to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration\r
 554  *                       programming guide" for more details.\r
 555  *                       Thus, we define a sub-finction for RTL8526 register address conversion\r
 556  *                     ===========================================================\r
 557  *                       Register Mode          RegCTL[1]               RegCTL[0]               Note\r
 558  *                                                              (Reg00[12])             (Reg00[10])\r
 559  *                     ===========================================================\r
 560  *                       Reg_Mode0                              0                               x                       Reg 0 ~15(0x0 ~ 0xf)\r
 561  *                     ------------------------------------------------------------------\r
 562  *                       Reg_Mode1                              1                               0                       Reg 16 ~30(0x1 ~ 0xf)\r
 563  *                     ------------------------------------------------------------------\r
 564  *                       Reg_Mode2                              1                               1                       Reg 31 ~ 45(0x1 ~ 0xf)\r
 565  *                     ------------------------------------------------------------------\r
 566  *\r
 567  *      2008/09/02      MH      Add 92S RF definition\r
 568  *\r
 569  *\r
 570  *\r
 571 */\r
 572 static  VOID\r
 573 phy_RFSerialWrite(\r
 574         IN      PADAPTER                Adapter,\r
 575         IN      u8                              eRFPath,\r
 576         IN      u32                             Offset,\r
 577         IN      u32                             Data\r
 578         )\r
 579 {\r
 580         u32                                             DataAndAddr = 0;\r
 581         HAL_DATA_TYPE                           *pHalData = GET_HAL_DATA(Adapter);\r
 582         BB_REGISTER_DEFINITION_T        *pPhyReg = &pHalData->PHYRegDef[eRFPath];\r
 583         u32                                             NewOffset;\r
 584 \r
 585 #if 0\r
 586         //<Roger_TODO> We should check valid regs for RF_6052 case.\r
 587         if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs\r
 588                 return;\r
 589         if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs\r
 590                 return;\r
 591 #endif\r
 592 \r
 593         // 2009/06/17 MH We can not execute IO for power save or other accident mode.\r
 594         //if(RT_CANNOT_IO(Adapter))\r
 595         //{\r
 596         //      RTPRINT(FPHY, PHY_RFW, ("phy_RFSerialWrite stop\n"));\r
 597         //      return;\r
 598         //}\r
 599 \r
 600         Offset &= 0xff;\r
 601 \r
 602         //\r
 603         // Shadow Update\r
 604         //\r
 605         //PHY_RFShadowWrite(Adapter, eRFPath, Offset, Data);\r
 606 \r
 607         //\r
 608         // Switch page for 8256 RF IC\r
 609         //\r
 610         NewOffset = Offset;\r
 611 \r
 612         //\r
 613         // Put write addr in [5:0]  and write data in [31:16]\r
 614         //\r
 615         //DataAndAddr = (Data<<16) | (NewOffset&0x3f);\r
 616         DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff;       // T65 RF\r
 617 \r
 618         //\r
 619         // Write Operation\r
 620         //\r
 621         PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);\r
 622         //RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]=0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr));\r
 623 \r
 624 }\r
 625 \r
 626 \r
 627 /**\r
 628 * Function:     PHY_QueryRFReg\r
 629 *\r
 630 * OverView:     Query "Specific bits" to RF register (page 8~)\r
 631 *\r
 632 * Input:\r
 633 *                       PADAPTER                Adapter,\r
 634 *                       u8                              eRFPath,        //Radio path of A/B/C/D\r
 635 *                       u4Byte                  RegAddr,                //The target address to be read\r
 636 *                       u4Byte                  BitMask         //The target bit position in the target address\r
 637 *                                                                               //to be read\r
 638 *\r
 639 * Output:       None\r
 640 * Return:               u4Byte                  Readback value\r
 641 * Note:         This function is equal to "GetRFRegSetting" in PHY programming guide\r
 642 */\r
 643 u32\r
 644 PHY_QueryRFReg8188E(\r
 645         IN      PADAPTER                Adapter,\r
 646         IN      u8                              eRFPath,\r
 647         IN      u32                             RegAddr,\r
 648         IN      u32                             BitMask\r
 649         )\r
 650 {\r
 651         u32 Original_Value, Readback_Value, BitShift;\r
 652         //HAL_DATA_TYPE         *pHalData = GET_HAL_DATA(Adapter);\r
 653         //u8    RFWaitCounter = 0;\r
 654         //_irqL irqL;\r
 655 \r
 656 #if (DISABLE_BB_RF == 1)\r
 657         return 0;\r
 658 #endif\r
 659 \r
 660         //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryRFReg(): RegAddr(%#lx), eRFPath(%#x), BitMask(%#lx)\n", RegAddr, eRFPath,BitMask));\r
 661 \r
 662 #ifdef CONFIG_USB_HCI\r
 663         //PlatformAcquireMutex(&pHalData->mxRFOperate);\r
 664 #else\r
 665         //_enter_critical(&pHalData->rf_lock, &irqL);\r
 666 #endif\r
 667 \r
 668 \r
 669         Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr);\r
 670 \r
 671         BitShift =  PHY_CalculateBitShift(BitMask);\r
 672         Readback_Value = (Original_Value & BitMask) >> BitShift;\r
 673 \r
 674 #ifdef CONFIG_USB_HCI\r
 675         //PlatformReleaseMutex(&pHalData->mxRFOperate);\r
 676 #else\r
 677         //_exit_critical(&pHalData->rf_lock, &irqL);\r
 678 #endif\r
 679 \r
 680 \r
 681         //RTPRINT(FPHY, PHY_RFR, ("RFR-%d MASK=0x%lx Addr[0x%lx]=0x%lx\n", eRFPath, BitMask, RegAddr, Original_Value));//BitMask(%#lx),BitMask,\r
 682         //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_QueryRFReg(): RegAddr(%#lx), eRFPath(%#x),  Original_Value(%#lx)\n",\r
 683         //                              RegAddr, eRFPath, Original_Value));\r
 684 \r
 685         return (Readback_Value);\r
 686 }\r
 687 \r
 688 /**\r
 689 * Function:     PHY_SetRFReg\r
 690 *\r
 691 * OverView:     Write "Specific bits" to RF register (page 8~)\r
 692 *\r
 693 * Input:\r
 694 *                       PADAPTER                Adapter,\r
 695 *                       u8                              eRFPath,        //Radio path of A/B/C/D\r
 696 *                       u4Byte                  RegAddr,                //The target address to be modified\r
 697 *                       u4Byte                  BitMask         //The target bit position in the target address\r
 698 *                                                                               //to be modified\r
 699 *                       u4Byte                  Data                    //The new register Data in the target bit position\r
 700 *                                                                               //of the target address\r
 701 *\r
 702 * Output:       None\r
 703 * Return:               None\r
 704 * Note:         This function is equal to "PutRFRegSetting" in PHY programming guide\r
 705 */\r
 706 VOID\r
 707 PHY_SetRFReg8188E(\r
 708         IN      PADAPTER                Adapter,\r
 709         IN      u8                              eRFPath,\r
 710         IN      u32                             RegAddr,\r
 711         IN      u32                             BitMask,\r
 712         IN      u32                             Data\r
 713         )\r
 714 {\r
 715 \r
 716         //HAL_DATA_TYPE *pHalData               = GET_HAL_DATA(Adapter);\r
 717         //u1Byte                        RFWaitCounter   = 0;\r
 718         u32             Original_Value, BitShift;\r
 719         //_irqL irqL;\r
 720 \r
 721 #if (DISABLE_BB_RF == 1)\r
 722         return;\r
 723 #endif\r
 724 \r
 725         //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n",\r
 726         //      RegAddr, BitMask, Data, eRFPath));\r
 727         //RTPRINT(FINIT, INIT_RF, ("PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n",\r
 728         //      RegAddr, BitMask, Data, eRFPath));\r
 729 \r
 730 \r
 731 #ifdef CONFIG_USB_HCI\r
 732         //PlatformAcquireMutex(&pHalData->mxRFOperate);\r
 733 #else\r
 734         //_enter_critical(&pHalData->rf_lock, &irqL);\r
 735 #endif\r
 736 \r
 737 \r
 738         // RF data is 12 bits only\r
 739         if (BitMask != bRFRegOffsetMask)\r
 740         {\r
 741                 Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr);\r
 742                 BitShift =  PHY_CalculateBitShift(BitMask);\r
 743                 Data = ((Original_Value & (~BitMask)) | (Data<< BitShift));\r
 744         }\r
 745 \r
 746         phy_RFSerialWrite(Adapter, eRFPath, RegAddr, Data);\r
 747 \r
 748 \r
 749 #ifdef CONFIG_USB_HCI\r
 750         //PlatformReleaseMutex(&pHalData->mxRFOperate);\r
 751 #else\r
 752         //_exit_critical(&pHalData->rf_lock, &irqL);\r
 753 #endif\r
 754 \r
 755         //PHY_QueryRFReg(Adapter,eRFPath,RegAddr,BitMask);\r
 756         //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n",\r
 757         //              RegAddr, BitMask, Data, eRFPath));\r
 758 \r
 759 }\r
 760 \r
 761 \r
 762 //\r
 763 // 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt.\r
 764 //\r
 765 \r
 766 /*-----------------------------------------------------------------------------\r
 767  * Function:    PHY_MACConfig8192C\r
 768  *\r
 769  * Overview:    Condig MAC by header file or parameter file.\r
 770  *\r
 771  * Input:       NONE\r
 772  *\r
 773  * Output:      NONE\r
 774  *\r
 775  * Return:      NONE\r
 776  *\r
 777  * Revised History:\r
 778  *  When                Who             Remark\r
 779  *  08/12/2008  MHC             Create Version 0.\r
 780  *\r
 781  *---------------------------------------------------------------------------*/\r
 782 s32 PHY_MACConfig8188E(PADAPTER Adapter)\r
 783 {\r
 784         int             rtStatus = _SUCCESS;\r
 785         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
 786         s8                      *pszMACRegFile;\r
 787         s8                      sz8188EMACRegFile[] = RTL8188E_PHY_MACREG;\r
 788 \r
 789         pszMACRegFile = sz8188EMACRegFile;\r
 790 \r
 791         //\r
 792         // Config MAC\r
 793         //\r
 794 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\r
 795         rtStatus = phy_ConfigMACWithParaFile(Adapter, pszMACRegFile);\r
 796         if (rtStatus == _FAIL)\r
 797 #endif\r
 798         {\r
 799 #ifdef CONFIG_EMBEDDED_FWIMG\r
 800                 if(HAL_STATUS_FAILURE == ODM_ConfigMACWithHeaderFile(&pHalData->odmpriv))\r
 801                         rtStatus = _FAIL;\r
 802                 else\r
 803                         rtStatus = _SUCCESS;\r
 804 #endif//CONFIG_EMBEDDED_FWIMG\r
 805         }\r
 806 \r
 807         // 2010.07.13 AMPDU aggregation number B\r
 808         rtw_write8(Adapter, REG_MAX_AGGR_NUM, MAX_AGGR_NUM);\r
 809         //rtw_write8(Adapter, REG_MAX_AGGR_NUM, 0x0B); \r
 810 \r
 811         return rtStatus;\r
 812 \r
 813 }\r
 814 \r
 815 /*-----------------------------------------------------------------------------\r
 816 * Function:     phy_InitBBRFRegisterDefinition\r
 817 *\r
 818 * OverView:     Initialize Register definition offset for Radio Path A/B/C/D\r
 819 *\r
 820 * Input:\r
 821 *                       PADAPTER                Adapter,\r
 822 *\r
 823 * Output:       None\r
 824 * Return:               None\r
 825 * Note:         The initialization value is constant and it should never be changes\r
 826 -----------------------------------------------------------------------------*/\r
 827 static  VOID\r
 828 phy_InitBBRFRegisterDefinition(\r
 829         IN      PADAPTER                Adapter\r
 830 )\r
 831 {\r
 832         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);\r
 833 \r
 834         // RF Interface Sowrtware Control\r
 835         pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870\r
 836         pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)\r
 837         pHalData->PHYRegDef[RF_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874\r
 838         pHalData->PHYRegDef[RF_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)\r
 839 \r
 840         // RF Interface Output (and Enable)\r
 841         pHalData->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860\r
 842         pHalData->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864\r
 843 \r
 844         // RF Interface (Output and)  Enable\r
 845         pHalData->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)\r
 846         pHalData->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)\r
 847 \r
 848         //Addr of LSSI. Wirte RF register by driver\r
 849         pHalData->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter\r
 850         pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;\r
 851 \r
 852         // Tranceiver A~D HSSI Parameter-2\r
 853         pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;  //wire control parameter2\r
 854         pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;  //wire control parameter2\r
 855 \r
 856         // Tranceiver LSSI Readback SI mode\r
 857         pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;\r
 858         pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;\r
 859         pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;\r
 860         pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; \r
 861 \r
 862         // Tranceiver LSSI Readback PI mode\r
 863         pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;\r
 864         pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;\r
 865         //pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBackPi = rFPGA0_XC_LSSIReadBack;\r
 866         //pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBackPi = rFPGA0_XD_LSSIReadBack;     \r
 867 \r
 868 }\r
 869 \r
 870 //****************************************\r
 871 // The following is for High Power PA\r
 872 //****************************************\r
 873 VOID\r
 874 phy_ConfigBBExternalPA(\r
 875         IN      PADAPTER                        Adapter\r
 876 )\r
 877 {\r
 878 #ifdef CONFIG_USB_HCI\r
 879         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
 880         u16 i=0;\r
 881         u32 temp=0;\r
 882 \r
 883         if(!pHalData->ExternalPA)\r
 884         {\r
 885                 return;\r
 886         }\r
 887 \r
 888         // 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the\r
 889         // same code as SU. It is already updated in PHY_REG_1T_HP.txt.\r
 890 #if 0\r
 891         PHY_SetBBReg(Adapter, 0xee8, BIT28, 1);\r
 892         temp = PHY_QueryBBReg(Adapter, 0x860, bMaskDWord);\r
 893         temp |= (BIT26|BIT21|BIT10|BIT5);\r
 894         PHY_SetBBReg(Adapter, 0x860, bMaskDWord, temp);\r
 895         PHY_SetBBReg(Adapter, 0x870, BIT10, 0);\r
 896         PHY_SetBBReg(Adapter, 0xc80, bMaskDWord, 0x20000080);\r
 897         PHY_SetBBReg(Adapter, 0xc88, bMaskDWord, 0x40000100);\r
 898 #endif\r
 899 \r
 900 #endif\r
 901 }\r
 902 \r
 903 \r
 904 VOID\r
 905 storePwrIndexDiffRateOffset(\r
 906         IN      PADAPTER        Adapter,\r
 907         IN      u32             RegAddr,\r
 908         IN      u32             BitMask,\r
 909         IN      u32             Data\r
 910         )\r
 911 {\r
 912         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
 913         \r
 914         if(RegAddr == rTxAGC_A_Rate18_06)\r
 915         {\r
 916                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0] = Data;\r
 917                 //printk("MCSTxPowerLevelOriginalOffset[%d][0]-TxAGC_A_Rate18_06 = 0x%x\n", pHalData->pwrGroupCnt,\r
 918                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0]);\r
 919         }\r
 920         if(RegAddr == rTxAGC_A_Rate54_24)\r
 921         {\r
 922                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1] = Data;\r
 923                 //printk("MCSTxPowerLevelOriginalOffset[%d][1]-TxAGC_A_Rate54_24 = 0x%x\n", pHalData->pwrGroupCnt,\r
 924                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1]);\r
 925         }\r
 926         if(RegAddr == rTxAGC_A_CCK1_Mcs32)\r
 927         {\r
 928                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6] = Data;\r
 929                 //printk("MCSTxPowerLevelOriginalOffset[%d][6]-TxAGC_A_CCK1_Mcs32 = 0x%x\n", pHalData->pwrGroupCnt,\r
 930                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6]);\r
 931         }\r
 932         if(RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0xffffff00)\r
 933         {\r
 934                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7] = Data;\r
 935                 //printk("MCSTxPowerLevelOriginalOffset[%d][7]-TxAGC_B_CCK11_A_CCK2_11 = 0x%x\n", pHalData->pwrGroupCnt,\r
 936                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7]);\r
 937         }\r
 938         if(RegAddr == rTxAGC_A_Mcs03_Mcs00)\r
 939         {\r
 940                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2] = Data;\r
 941                 //printk("MCSTxPowerLevelOriginalOffset[%d][2]-TxAGC_A_Mcs03_Mcs00 = 0x%x\n", pHalData->pwrGroupCnt,\r
 942                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2]);\r
 943         }\r
 944         if(RegAddr == rTxAGC_A_Mcs07_Mcs04)\r
 945         {\r
 946                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3] = Data;\r
 947                 //printk("MCSTxPowerLevelOriginalOffset[%d][3]-TxAGC_A_Mcs07_Mcs04 = 0x%x\n", pHalData->pwrGroupCnt,\r
 948                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3]);\r
 949         }\r
 950         if(RegAddr == rTxAGC_A_Mcs11_Mcs08)\r
 951         {\r
 952                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4] = Data;\r
 953                 //printk("MCSTxPowerLevelOriginalOffset[%d][4]-TxAGC_A_Mcs11_Mcs08 = 0x%x\n", pHalData->pwrGroupCnt,\r
 954                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4]);\r
 955         }\r
 956         if(RegAddr == rTxAGC_A_Mcs15_Mcs12)\r
 957         {\r
 958                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5] = Data;\r
 959                 //printk("MCSTxPowerLevelOriginalOffset[%d][5]-TxAGC_A_Mcs15_Mcs12 = 0x%x\n", pHalData->pwrGroupCnt,pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5]);\r
 960                 if(pHalData->rf_type== RF_1T1R)\r
 961                 {\r
 962                         //printk("pwrGroupCnt = %d\n", pHalData->pwrGroupCnt);\r
 963                         pHalData->pwrGroupCnt++;                        \r
 964                 }\r
 965         }\r
 966         if(RegAddr == rTxAGC_B_Rate18_06)\r
 967         {\r
 968                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8] = Data;\r
 969                 //printk("MCSTxPowerLevelOriginalOffset[%d][8]-TxAGC_B_Rate18_06 = 0x%x\n", pHalData->pwrGroupCnt,\r
 970                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8]);\r
 971         }\r
 972         if(RegAddr == rTxAGC_B_Rate54_24)\r
 973         {\r
 974                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9] = Data;\r
 975                 //printk("MCSTxPowerLevelOriginalOffset[%d][9]-TxAGC_B_Rate54_24 = 0x%x\n", pHalData->pwrGroupCnt,\r
 976                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9]);\r
 977         }\r
 978         if(RegAddr == rTxAGC_B_CCK1_55_Mcs32)\r
 979         {\r
 980                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14] = Data;\r
 981                 //printk("MCSTxPowerLevelOriginalOffset[%d][14]-TxAGC_B_CCK1_55_Mcs32 = 0x%x\n", pHalData->pwrGroupCnt,\r
 982                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14]);\r
 983         }\r
 984         if(RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0x000000ff)\r
 985         {\r
 986                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15] = Data;\r
 987                 //printk("MCSTxPowerLevelOriginalOffset[%d][15]-TxAGC_B_CCK11_A_CCK2_11 = 0x%x\n", pHalData->pwrGroupCnt,\r
 988                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15]);\r
 989         }\r
 990         if(RegAddr == rTxAGC_B_Mcs03_Mcs00)\r
 991         {\r
 992                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10] = Data;\r
 993                 //printk("MCSTxPowerLevelOriginalOffset[%d][10]-TxAGC_B_Mcs03_Mcs00 = 0x%x\n", pHalData->pwrGroupCnt,\r
 994                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10]);\r
 995         }\r
 996         if(RegAddr == rTxAGC_B_Mcs07_Mcs04)\r
 997         {\r
 998                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11] = Data;\r
 999                 //printk("MCSTxPowerLevelOriginalOffset[%d][11]-TxAGC_B_Mcs07_Mcs04 = 0x%x\n", pHalData->pwrGroupCnt,\r
1000                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11]);\r
1001         }\r
1002         if(RegAddr == rTxAGC_B_Mcs11_Mcs08)\r
1003         {\r
1004                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12] = Data;\r
1005                 //printk("MCSTxPowerLevelOriginalOffset[%d][12]-TxAGC_B_Mcs11_Mcs08 = 0x%x\n", pHalData->pwrGroupCnt,\r
1006                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12]);\r
1007         }\r
1008         if(RegAddr == rTxAGC_B_Mcs15_Mcs12)\r
1009         {\r
1010                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13] = Data;\r
1011                 //printk("MCSTxPowerLevelOriginalOffset[%d][13]-TxAGC_B_Mcs15_Mcs12 = 0x%x\n", pHalData->pwrGroupCnt,\r
1012                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13]);\r
1013                 \r
1014                 if(pHalData->rf_type != RF_1T1R)\r
1015                 {\r
1016                         //printk("pwrGroupCnt = %d\n", pHalData->pwrGroupCnt);  \r
1017                         pHalData->pwrGroupCnt++;\r
1018                 }\r
1019         }\r
1020 }\r
1021 \r
1022 \r
1023 static VOID\r
1024 phy_BB8192C_Config_1T(\r
1025         IN PADAPTER Adapter\r
1026         )\r
1027 {\r
1028 #if 0\r
1029         //for path - A\r
1030         PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x1);\r
1031         PHY_SetBBReg(Adapter, rFPGA1_TxInfo, 0x0303, 0x0101);\r
1032         PHY_SetBBReg(Adapter, 0xe74, 0x0c000000, 0x1);\r
1033         PHY_SetBBReg(Adapter, 0xe78, 0x0c000000, 0x1);\r
1034         PHY_SetBBReg(Adapter, 0xe7c, 0x0c000000, 0x1);\r
1035         PHY_SetBBReg(Adapter, 0xe80, 0x0c000000, 0x1);\r
1036         PHY_SetBBReg(Adapter, 0xe88, 0x0c000000, 0x1);\r
1037 #endif\r
1038         //for path - B\r
1039         PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x2);\r
1040         PHY_SetBBReg(Adapter, rFPGA1_TxInfo, 0x300033, 0x200022);\r
1041 \r
1042         // 20100519 Joseph: Add for 1T2R config. Suggested by Kevin, Jenyu and Yunan.\r
1043         PHY_SetBBReg(Adapter, rCCK0_AFESetting, bMaskByte3, 0x45);\r
1044         PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskByte0, 0x23);\r
1045         PHY_SetBBReg(Adapter, rOFDM0_AGCParameter1, 0x30, 0x1); // B path first AGC\r
1046 \r
1047         PHY_SetBBReg(Adapter, 0xe74, 0x0c000000, 0x2);\r
1048         PHY_SetBBReg(Adapter, 0xe78, 0x0c000000, 0x2);\r
1049         PHY_SetBBReg(Adapter, 0xe7c, 0x0c000000, 0x2);\r
1050         PHY_SetBBReg(Adapter, 0xe80, 0x0c000000, 0x2);\r
1051         PHY_SetBBReg(Adapter, 0xe88, 0x0c000000, 0x2);\r
1052 \r
1053 \r
1054 }\r
1055 \r
1056 // Joseph test: new initialize order!!\r
1057 // Test only!! This part need to be re-organized.\r
1058 // Now it is just for 8256.\r
1059 static  int\r
1060 phy_BB8190_Config_HardCode(\r
1061         IN      PADAPTER        Adapter\r
1062         )\r
1063 {\r
1064         //RT_ASSERT(FALSE, ("This function is not implement yet!! \n"));\r
1065         return _SUCCESS;\r
1066 }\r
1067 \r
1068 static  int\r
1069 phy_BB8188E_Config_ParaFile(\r
1070         IN      PADAPTER        Adapter\r
1071         )\r
1072 {\r
1073         EEPROM_EFUSE_PRIV       *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);\r
1074         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);\r
1075         int                     rtStatus = _SUCCESS;\r
1076 \r
1077         u8      sz8188EBBRegFile[] = RTL8188E_PHY_REG;\r
1078         u8      sz8188EAGCTableFile[] = RTL8188E_AGC_TAB;\r
1079         u8      sz8188EBBRegPgFile[] = RTL8188E_PHY_REG_PG;\r
1080         u8      sz8188EBBRegMpFile[] = RTL8188E_PHY_REG_MP;\r
1081         u8      sz8188EBBRegLimitFile[] = RTL8188E_TXPWR_LMT;\r
1082 \r
1083         u8      *pszBBRegFile = NULL, *pszAGCTableFile = NULL, *pszBBRegPgFile = NULL, *pszBBRegMpFile=NULL,\r
1084                 *pszRFTxPwrLmtFile = NULL;\r
1085 \r
1086 \r
1087         //RT_TRACE(COMP_INIT, DBG_TRACE, ("==>phy_BB8192S_Config_ParaFile\n"));\r
1088 \r
1089         pszBBRegFile = sz8188EBBRegFile ;\r
1090         pszAGCTableFile = sz8188EAGCTableFile;\r
1091         pszBBRegPgFile = sz8188EBBRegPgFile;\r
1092         pszBBRegMpFile = sz8188EBBRegMpFile;\r
1093         pszRFTxPwrLmtFile = sz8188EBBRegLimitFile;\r
1094 \r
1095         PHY_InitTxPowerLimit( Adapter );\r
1096 \r
1097         if ( Adapter->registrypriv.RegEnableTxPowerLimit == 1 || \r
1098              ( Adapter->registrypriv.RegEnableTxPowerLimit == 2 && pHalData->EEPROMRegulatory == 1 ) )\r
1099         {\r
1100 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\r
1101                 if (PHY_ConfigRFWithPowerLimitTableParaFile( Adapter, pszRFTxPwrLmtFile )== _FAIL)\r
1102 #endif\r
1103                 {\r
1104 #ifdef CONFIG_EMBEDDED_FWIMG\r
1105                         if (HAL_STATUS_SUCCESS != ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, CONFIG_RF_TXPWR_LMT, (ODM_RF_RADIO_PATH_E)0))\r
1106                                 rtStatus = _FAIL;\r
1107 #endif\r
1108                 }\r
1109 \r
1110                 if(rtStatus != _SUCCESS){\r
1111                         DBG_871X("phy_BB8188E_Config_ParaFile():Read Tx power limit fail!!\n");\r
1112                         goto phy_BB8190_Config_ParaFile_Fail;\r
1113                 }\r
1114         }\r
1115 \r
1116         //\r
1117         // 1. Read PHY_REG.TXT BB INIT!!\r
1118         //\r
1119 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\r
1120         if (phy_ConfigBBWithParaFile(Adapter, pszBBRegFile, CONFIG_BB_PHY_REG) == _FAIL)\r
1121 #endif\r
1122         {\r
1123 #ifdef CONFIG_EMBEDDED_FWIMG            \r
1124                 if(HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG))\r
1125                         rtStatus = _FAIL;\r
1126 #endif\r
1127         }\r
1128 \r
1129         if(rtStatus != _SUCCESS){\r
1130                 //RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():Write BB Reg Fail!!"));\r
1131                 goto phy_BB8190_Config_ParaFile_Fail;\r
1132         }\r
1133 \r
1134 #if (MP_DRIVER == 1)\r
1135         //\r
1136         // 1.1 Read PHY_REG_MP.TXT BB INIT!!\r
1137         //\r
1138         if (Adapter->registrypriv.mp_mode == 1) {\r
1139                 //3 Read PHY_REG.TXT BB INIT!!\r
1140 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\r
1141                 if (phy_ConfigBBWithMpParaFile(Adapter, pszBBRegMpFile) == _FAIL)\r
1142 #endif\r
1143                 {\r
1144 #ifdef CONFIG_EMBEDDED_FWIMG\r
1145                         if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG_MP))\r
1146                                 rtStatus = _FAIL;\r
1147 #endif\r
1148                 }\r
1149 \r
1150                 if(rtStatus != _SUCCESS){\r
1151                         DBG_871X("phy_BB8188E_Config_ParaFile():Write BB Reg MP Fail!!");\r
1152                         goto phy_BB8190_Config_ParaFile_Fail;\r
1153                 }\r
1154         }\r
1155 #endif  // #if (MP_DRIVER == 1)\r
1156 \r
1157         //\r
1158         // 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt\r
1159         //\r
1160         PHY_InitTxPowerByRate( Adapter );\r
1161         if ( ( Adapter->registrypriv.RegEnableTxPowerByRate == 1 || \r
1162              ( Adapter->registrypriv.RegEnableTxPowerByRate == 2 && pHalData->EEPROMRegulatory != 2 )  ) )\r
1163         {\r
1164                 pHalData->pwrGroupCnt = 0;\r
1165 \r
1166 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\r
1167                 if (phy_ConfigBBWithPgParaFile(Adapter, pszBBRegPgFile) == _FAIL)\r
1168 #endif\r
1169                 {\r
1170 #ifdef CONFIG_EMBEDDED_FWIMG                    \r
1171                         if(HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG_PG))\r
1172                                 rtStatus = _FAIL;                       \r
1173 #endif\r
1174                 }\r
1175 \r
1176                 if ( pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_EXACT_VALUE )\r
1177                         PHY_TxPowerByRateConfiguration(Adapter);\r
1178 \r
1179                 if ( Adapter->registrypriv.RegEnableTxPowerLimit == 1 || \r
1180                  ( Adapter->registrypriv.RegEnableTxPowerLimit == 2 && pHalData->EEPROMRegulatory == 1 ) )\r
1181                         PHY_ConvertTxPowerLimitToPowerIndex( Adapter );\r
1182 \r
1183                 if(rtStatus != _SUCCESS){\r
1184                         DBG_871X("%s(): CONFIG_BB_PHY_REG_PG Fail!!\n",__FUNCTION__     );\r
1185                         goto phy_BB8190_Config_ParaFile_Fail;\r
1186                 }\r
1187         }\r
1188 \r
1189         //\r
1190         // 3. BB AGC table Initialization\r
1191         //\r
1192 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE\r
1193         if (phy_ConfigBBWithParaFile(Adapter, pszAGCTableFile, CONFIG_BB_AGC_TAB) == _FAIL)\r
1194 #endif\r
1195         {\r
1196 #ifdef CONFIG_EMBEDDED_FWIMG\r
1197                 if(HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv,  CONFIG_BB_AGC_TAB))\r
1198                         rtStatus = _FAIL;               \r
1199 #endif\r
1200         }\r
1201 \r
1202         if(rtStatus != _SUCCESS){\r
1203                 //RT_TRACE(COMP_FPGA, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():AGC Table Fail\n"));\r
1204                 goto phy_BB8190_Config_ParaFile_Fail;\r
1205         }\r
1206 \r
1207 \r
1208 phy_BB8190_Config_ParaFile_Fail:\r
1209 \r
1210         return rtStatus;\r
1211 }\r
1212 \r
1213 \r
1214 int\r
1215 PHY_BBConfig8188E(\r
1216         IN      PADAPTER        Adapter\r
1217         )\r
1218 {\r
1219         int     rtStatus = _SUCCESS;\r
1220         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
1221         u32     RegVal;\r
1222         u8      TmpU1B=0;\r
1223         u8      value8,CrystalCap;\r
1224 \r
1225         phy_InitBBRFRegisterDefinition(Adapter);\r
1226 \r
1227 \r
1228         // Enable BB and RF\r
1229         RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);\r
1230         rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1));\r
1231 \r
1232         // 20090923 Joseph: Advised by Steven and Jenyu. Power sequence before init RF.\r
1233         //rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x83);\r
1234         //rtw_write8(Adapter, REG_AFE_PLL_CTRL+1, 0xdb);\r
1235 \r
1236         rtw_write8(Adapter, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB);\r
1237 \r
1238 #ifdef CONFIG_USB_HCI\r
1239         rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);\r
1240 #else\r
1241         rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL|FEN_PCIEA|FEN_DIO_PCIE|FEN_BB_GLB_RSTn|FEN_BBRSTB);\r
1242 #endif\r
1243 \r
1244 #if 0\r
1245 #ifdef CONFIG_USB_HCI\r
1246         //To Fix MAC loopback mode fail. Suggested by SD4 Johnny. 2010.03.23.\r
1247         rtw_write8(Adapter, REG_LDOHCI12_CTRL, 0x0f);\r
1248         rtw_write8(Adapter, 0x15, 0xe9);\r
1249 #endif\r
1250 \r
1251         rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, 0x80);\r
1252 #endif\r
1253 \r
1254 #ifdef CONFIG_USB_HCI\r
1255                 //rtw_write8(Adapter, 0x15, 0xe9);\r
1256 #endif\r
1257 \r
1258 \r
1259 #ifdef CONFIG_PCI_HCI\r
1260         // Force use left antenna by default for 88C.\r
1261         //      if(!IS_92C_SERIAL(pHalData->VersionID) || IS_92C_1T2R(pHalData->VersionID))\r
1262         if(Adapter->ledpriv.LedStrategy != SW_LED_MODE10)\r
1263         {\r
1264                 RegVal = rtw_read32(Adapter, REG_LEDCFG0);\r
1265                 rtw_write32(Adapter, REG_LEDCFG0, RegVal|BIT23);\r
1266         }\r
1267 #endif\r
1268 \r
1269         //\r
1270         // Config BB and AGC\r
1271         //\r
1272         rtStatus = phy_BB8188E_Config_ParaFile(Adapter);\r
1273 \r
1274         // write 0x24[16:11] = 0x24[22:17] = CrystalCap\r
1275         CrystalCap = pHalData->CrystalCap & 0x3F;\r
1276         PHY_SetBBReg(Adapter, REG_AFE_XTAL_CTRL, 0x7ff800, (CrystalCap | (CrystalCap << 6)));\r
1277         \r
1278         return rtStatus;\r
1279         \r
1280 }\r
1281 \r
1282 \r
1283 int\r
1284 PHY_RFConfig8188E(\r
1285         IN      PADAPTER        Adapter\r
1286         )\r
1287 {\r
1288         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
1289         int             rtStatus = _SUCCESS;\r
1290 \r
1291         //\r
1292         // RF config\r
1293         //\r
1294         rtStatus = PHY_RF6052_Config8188E(Adapter);\r
1295 #if 0\r
1296         switch(pHalData->rf_chip)\r
1297         {\r
1298                 case RF_6052:\r
1299                         rtStatus = PHY_RF6052_Config(Adapter);\r
1300                         break;\r
1301                 case RF_8225:\r
1302                         rtStatus = PHY_RF8225_Config(Adapter);\r
1303                         break;\r
1304                 case RF_8256:\r
1305                         rtStatus = PHY_RF8256_Config(Adapter);\r
1306                         break;\r
1307                 case RF_8258:\r
1308                         break;\r
1309                 case RF_PSEUDO_11N:\r
1310                         rtStatus = PHY_RF8225_Config(Adapter);\r
1311                         break;\r
1312                 default: //for MacOs Warning: "RF_TYPE_MIN" not handled in switch\r
1313                         break;\r
1314         }\r
1315 #endif\r
1316         return rtStatus;\r
1317 }\r
1318 \r
1319 \r
1320 /*-----------------------------------------------------------------------------\r
1321  * Function:    PHY_ConfigRFWithParaFile()\r
1322  *\r
1323  * Overview:    This function read RF parameters from general file format, and do RF 3-wire\r
1324  *\r
1325  * Input:       PADAPTER                        Adapter\r
1326  *                      ps1Byte                                 pFileName\r
1327  *                      u8                                      eRFPath\r
1328  *\r
1329  * Output:      NONE\r
1330  *\r
1331  * Return:      RT_STATUS_SUCCESS: configuration file exist\r
1332  *\r
1333  * Note:                Delay may be required for RF configuration\r
1334  *---------------------------------------------------------------------------*/\r
1335 int\r
1336 rtl8188e_PHY_ConfigRFWithParaFile(\r
1337         IN      PADAPTER                Adapter,\r
1338         IN      u8*                             pFileName,\r
1339         IN      u8                              eRFPath\r
1340 )\r
1341 {\r
1342         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
1343 \r
1344         int     rtStatus = _SUCCESS;\r
1345 \r
1346 \r
1347         return rtStatus;\r
1348 \r
1349 }\r
1350 \r
1351 //****************************************\r
1352 // The following is for High Power PA\r
1353 //****************************************\r
1354 #define HighPowerRadioAArrayLen 22\r
1355 //This is for High power PA\r
1356 u32 Rtl8192S_HighPower_RadioA_Array[HighPowerRadioAArrayLen] = {\r
1357 0x013,0x00029ea4,\r
1358 0x013,0x00025e74,\r
1359 0x013,0x00020ea4,\r
1360 0x013,0x0001ced0,\r
1361 0x013,0x00019f40,\r
1362 0x013,0x00014e70,\r
1363 0x013,0x000106a0,\r
1364 0x013,0x0000c670,\r
1365 0x013,0x000082a0,\r
1366 0x013,0x00004270,\r
1367 0x013,0x00000240,\r
1368 };\r
1369 \r
1370 int\r
1371 PHY_ConfigRFExternalPA(\r
1372         IN      PADAPTER                Adapter,\r
1373         IN      u8                              eRFPath\r
1374 )\r
1375 {\r
1376         int     rtStatus = _SUCCESS;\r
1377 #ifdef CONFIG_USB_HCI\r
1378         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
1379         u16 i=0;\r
1380 \r
1381         if(!pHalData->ExternalPA)\r
1382         {\r
1383                 return rtStatus;\r
1384         }\r
1385 \r
1386         // 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the\r
1387         // same code as SU. It is already updated in radio_a_1T_HP.txt.\r
1388 #if 0\r
1389         //add for SU High Power PA\r
1390         for(i = 0;i<HighPowerRadioAArrayLen; i=i+2)\r
1391         {\r
1392                 RT_TRACE(COMP_INIT, DBG_LOUD, ("External PA, write RF 0x%lx=0x%lx\n", Rtl8192S_HighPower_RadioA_Array[i], Rtl8192S_HighPower_RadioA_Array[i+1]));\r
1393                 PHY_SetRFReg(Adapter, eRFPath, Rtl8192S_HighPower_RadioA_Array[i], bRFRegOffsetMask, Rtl8192S_HighPower_RadioA_Array[i+1]);\r
1394         }\r
1395 #endif\r
1396 \r
1397 #endif\r
1398         return rtStatus;\r
1399 }\r
1400 //****************************************\r
1401 /*-----------------------------------------------------------------------------\r
1402  * Function:    GetTxPowerLevel8190()\r
1403  *\r
1404  * Overview:    This function is export to "common" moudule\r
1405  *\r
1406  * Input:       PADAPTER                Adapter\r
1407  *                      psByte                  Power Level\r
1408  *\r
1409  * Output:      NONE\r
1410  *\r
1411  * Return:      NONE\r
1412  *\r
1413  *---------------------------------------------------------------------------*/\r
1414 VOID\r
1415 PHY_GetTxPowerLevel8188E(\r
1416         IN      PADAPTER        Adapter,\r
1417         OUT s32*                        powerlevel\r
1418         )\r
1419 {\r
1420 #if 0\r
1421         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
1422         PMGNT_INFO              pMgntInfo = &(Adapter->MgntInfo);\r
1423         s4Byte                  TxPwrDbm = 13;\r
1424         RT_TRACE(COMP_TXAGC, DBG_LOUD, ("PHY_GetTxPowerLevel8188E(): TxPowerLevel: %#x\n", TxPwrDbm));\r
1425 \r
1426         if ( pMgntInfo->ClientConfigPwrInDbm != UNSPECIFIED_PWR_DBM )\r
1427                 *powerlevel = pMgntInfo->ClientConfigPwrInDbm;\r
1428         else\r
1429                 *powerlevel = TxPwrDbm;\r
1430 #endif\r
1431 }\r
1432 \r
1433 /*-----------------------------------------------------------------------------\r
1434  * Function:    SetTxPowerLevel8190()\r
1435  *\r
1436  * Overview:    This function is export to "HalCommon" moudule\r
1437  *                      We must consider RF path later!!!!!!!\r
1438  *\r
1439  * Input:       PADAPTER                Adapter\r
1440  *                      u1Byte          channel\r
1441  *\r
1442  * Output:      NONE\r
1443  *\r
1444  * Return:      NONE\r
1445  *      2008/11/04      MHC             We remove EEPROM_93C56.\r
1446  *                                              We need to move CCX relative code to independet file.\r
1447  *      2009/01/21      MHC             Support new EEPROM format from SD3 requirement.\r
1448  *\r
1449  *---------------------------------------------------------------------------*/\r
1450 VOID\r
1451 PHY_SetTxPowerLevel8188E(\r
1452         IN      PADAPTER        Adapter,\r
1453         IN      u8                      Channel\r
1454         )\r
1455 {               \r
1456         //DBG_871X("==>PHY_SetTxPowerLevel8188E()\n");\r
1457 \r
1458         PHY_SetTxPowerLevelByPath(Adapter, Channel, ODM_RF_PATH_A);\r
1459         \r
1460         //DBG_871X("<==PHY_SetTxPowerLevel8188E()\n");\r
1461 }\r
1462 \r
1463 VOID\r
1464 PHY_SetTxPowerIndex_8188E(\r
1465         IN      PADAPTER                        Adapter,\r
1466         IN      u32                                     PowerIndex,\r
1467         IN      u8                                      RFPath, \r
1468         IN      u8                                      Rate\r
1469         )\r
1470 {\r
1471         if (RFPath == ODM_RF_PATH_A)\r
1472         {\r
1473                 switch (Rate)\r
1474                 {\r
1475                         case MGN_1M:    PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32,      bMaskByte1, PowerIndex); break;\r
1476                         case MGN_2M:    PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte1, PowerIndex); break;\r
1477                         case MGN_5_5M:  PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte2, PowerIndex); break;\r
1478                         case MGN_11M:   PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte3, PowerIndex); break;\r
1479 \r
1480                         case MGN_6M:    PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte0, PowerIndex); break;\r
1481                         case MGN_9M:    PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte1, PowerIndex); break;\r
1482                         case MGN_12M:   PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte2, PowerIndex); break;\r
1483                         case MGN_18M:   PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte3, PowerIndex); break;\r
1484 \r
1485                         case MGN_24M:   PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte0, PowerIndex); break;\r
1486                         case MGN_36M:   PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte1, PowerIndex); break;\r
1487                         case MGN_48M:   PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte2, PowerIndex); break;\r
1488                         case MGN_54M:   PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte3, PowerIndex); break;\r
1489 \r
1490                         case MGN_MCS0:  PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte0, PowerIndex); break;\r
1491                         case MGN_MCS1:  PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte1, PowerIndex); break;\r
1492                         case MGN_MCS2:  PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte2, PowerIndex); break;\r
1493                         case MGN_MCS3:  PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte3, PowerIndex); break;\r
1494 \r
1495                         case MGN_MCS4:  PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte0, PowerIndex); break;\r
1496                         case MGN_MCS5:  PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte1, PowerIndex); break;\r
1497                         case MGN_MCS6:  PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte2, PowerIndex); break;\r
1498                         case MGN_MCS7:  PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte3, PowerIndex); break;\r
1499 \r
1500                         case MGN_MCS8:  PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskByte0, PowerIndex); break;\r
1501                         case MGN_MCS9:  PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskByte1, PowerIndex); break;\r
1502                         case MGN_MCS10: PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskByte2, PowerIndex); break;\r
1503                         case MGN_MCS11: PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskByte3, PowerIndex); break;\r
1504 \r
1505                         case MGN_MCS12: PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskByte0, PowerIndex); break;\r
1506                         case MGN_MCS13: PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskByte1, PowerIndex); break;\r
1507                         case MGN_MCS14: PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskByte2, PowerIndex); break;\r
1508                         case MGN_MCS15: PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskByte3, PowerIndex); break;\r
1509 \r
1510                         default:\r
1511                          DBG_871X("Invalid Rate!!\n");\r
1512                          break;                         \r
1513                 }\r
1514         }\r
1515         else if (RFPath == ODM_RF_PATH_B)\r
1516         {\r
1517                 switch (Rate)\r
1518                 {\r
1519                         case MGN_1M:    PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, bMaskByte1, PowerIndex); break;\r
1520                         case MGN_2M:    PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, bMaskByte2, PowerIndex); break;\r
1521                         case MGN_5_5M:  PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, bMaskByte3, PowerIndex); break;\r
1522                         case MGN_11M:   PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, PowerIndex); break;\r
1523                                                                      \r
1524                         case MGN_6M:    PHY_SetBBReg(Adapter, rTxAGC_B_Rate18_06, bMaskByte0, PowerIndex); break;\r
1525                         case MGN_9M:    PHY_SetBBReg(Adapter, rTxAGC_B_Rate18_06, bMaskByte1, PowerIndex); break;\r
1526                         case MGN_12M:   PHY_SetBBReg(Adapter, rTxAGC_B_Rate18_06, bMaskByte2, PowerIndex); break;\r
1527                         case MGN_18M:   PHY_SetBBReg(Adapter, rTxAGC_B_Rate18_06, bMaskByte3, PowerIndex); break;\r
1528                                                                      \r
1529                         case MGN_24M:   PHY_SetBBReg(Adapter, rTxAGC_B_Rate54_24, bMaskByte0, PowerIndex); break;\r
1530                         case MGN_36M:   PHY_SetBBReg(Adapter, rTxAGC_B_Rate54_24, bMaskByte1, PowerIndex); break;\r
1531                         case MGN_48M:   PHY_SetBBReg(Adapter, rTxAGC_B_Rate54_24, bMaskByte2, PowerIndex); break;\r
1532                         case MGN_54M:   PHY_SetBBReg(Adapter, rTxAGC_B_Rate54_24, bMaskByte3, PowerIndex); break;\r
1533                                                                      \r
1534                         case MGN_MCS0:  PHY_SetBBReg(Adapter, rTxAGC_B_Mcs03_Mcs00, bMaskByte0, PowerIndex); break;\r
1535                         case MGN_MCS1:  PHY_SetBBReg(Adapter, rTxAGC_B_Mcs03_Mcs00, bMaskByte1, PowerIndex); break;\r
1536                         case MGN_MCS2:  PHY_SetBBReg(Adapter, rTxAGC_B_Mcs03_Mcs00, bMaskByte2, PowerIndex); break;\r
1537                         case MGN_MCS3:  PHY_SetBBReg(Adapter, rTxAGC_B_Mcs03_Mcs00, bMaskByte3, PowerIndex); break;\r
1538                                                                      \r
1539                         case MGN_MCS4:  PHY_SetBBReg(Adapter, rTxAGC_B_Mcs07_Mcs04, bMaskByte0, PowerIndex); break;\r
1540                         case MGN_MCS5:  PHY_SetBBReg(Adapter, rTxAGC_B_Mcs07_Mcs04, bMaskByte1, PowerIndex); break;\r
1541                         case MGN_MCS6:  PHY_SetBBReg(Adapter, rTxAGC_B_Mcs07_Mcs04, bMaskByte2, PowerIndex); break;\r
1542                         case MGN_MCS7:  PHY_SetBBReg(Adapter, rTxAGC_B_Mcs07_Mcs04, bMaskByte3, PowerIndex); break;\r
1543                                                                      \r
1544                         case MGN_MCS8:  PHY_SetBBReg(Adapter, rTxAGC_B_Mcs11_Mcs08, bMaskByte0, PowerIndex); break;\r
1545                         case MGN_MCS9:  PHY_SetBBReg(Adapter, rTxAGC_B_Mcs11_Mcs08, bMaskByte1, PowerIndex); break;\r
1546                         case MGN_MCS10: PHY_SetBBReg(Adapter, rTxAGC_B_Mcs11_Mcs08, bMaskByte2, PowerIndex); break;\r
1547                         case MGN_MCS11: PHY_SetBBReg(Adapter, rTxAGC_B_Mcs11_Mcs08, bMaskByte3, PowerIndex); break;\r
1548                                                                      \r
1549                         case MGN_MCS12: PHY_SetBBReg(Adapter, rTxAGC_B_Mcs15_Mcs12, bMaskByte0, PowerIndex); break;\r
1550                         case MGN_MCS13: PHY_SetBBReg(Adapter, rTxAGC_B_Mcs15_Mcs12, bMaskByte1, PowerIndex); break;\r
1551                         case MGN_MCS14: PHY_SetBBReg(Adapter, rTxAGC_B_Mcs15_Mcs12, bMaskByte2, PowerIndex); break;\r
1552                         case MGN_MCS15: PHY_SetBBReg(Adapter, rTxAGC_B_Mcs15_Mcs12, bMaskByte3, PowerIndex); break;\r
1553 \r
1554                         default:\r
1555                              DBG_871X("Invalid Rate!!\n");\r
1556                              break;                     \r
1557                 }\r
1558         }\r
1559         else\r
1560         {\r
1561                 DBG_871X("Invalid RFPath!!\n");\r
1562         }\r
1563 }\r
1564 \r
1565 u8\r
1566 phy_GetCurrentTxNum_8188E(\r
1567         IN      PADAPTER        pAdapter,\r
1568         IN      u8                      Rate\r
1569         )\r
1570 {\r
1571         u8      tmpByte = 0;\r
1572         u32     tmpDWord = 0;\r
1573         u8      TxNum = RF_TX_NUM_NONIMPLEMENT;\r
1574 \r
1575         if ( ( Rate >= MGN_MCS8 && Rate <= MGN_MCS15 ) )\r
1576                 TxNum = RF_2TX;\r
1577         else\r
1578                 TxNum = RF_1TX;\r
1579 \r
1580         return TxNum;\r
1581 }\r
1582 \r
1583 s8 tx_power_extra_bias(\r
1584         IN      u8                              RFPath,\r
1585         IN      u8                              Rate,   \r
1586         IN      CHANNEL_WIDTH   BandWidth,      \r
1587         IN      u8                              Channel\r
1588         )\r
1589 {\r
1590         s8 bias = 0;\r
1591 \r
1592         if (Rate == MGN_2M)\r
1593                 bias = -9;\r
1594 \r
1595         return bias;\r
1596 }\r
1597 \r
1598 u8\r
1599 PHY_GetTxPowerIndex_8188E(\r
1600         IN      PADAPTER                pAdapter,\r
1601         IN      u8                              RFPath,\r
1602         IN      u8                              Rate,   \r
1603         IN      CHANNEL_WIDTH   BandWidth,      \r
1604         IN      u8                              Channel\r
1605         )\r
1606 {\r
1607         PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);\r
1608         u8 base_index = 0;\r
1609         s8 by_rate_diff = 0, txPower = 0, limit = 0, track_diff = 0, extra_bias = 0;\r
1610         u8 txNum = phy_GetCurrentTxNum_8188E(pAdapter, Rate);\r
1611         BOOLEAN bIn24G = _FALSE;\r
1612 \r
1613         base_index = PHY_GetTxPowerIndexBase(pAdapter,RFPath, Rate, BandWidth, Channel, &bIn24G);\r
1614 \r
1615         by_rate_diff = PHY_GetTxPowerByRate(pAdapter, BAND_ON_2_4G, RFPath, txNum, Rate);\r
1616         limit = PHY_GetTxPowerLimit(pAdapter, pAdapter->registrypriv.RegPwrTblSel, (u8)(!bIn24G), pHalData->CurrentChannelBW, RFPath, Rate, pHalData->CurrentChannel);\r
1617         by_rate_diff = by_rate_diff > limit ? limit : by_rate_diff;\r
1618 \r
1619         track_diff = PHY_GetTxPowerTrackingOffset(pAdapter, RFPath, Rate);\r
1620 \r
1621         extra_bias = tx_power_extra_bias(RFPath, Rate, BandWidth, Channel);\r
1622 \r
1623         txPower = base_index + by_rate_diff + track_diff + extra_bias;\r
1624 \r
1625         if(txPower > MAX_POWER_INDEX)\r
1626                 txPower = MAX_POWER_INDEX;\r
1627 \r
1628         if (0)\r
1629         DBG_871X("RF-%c ch%d TxPwrIdx = %d(0x%X) [%2u %2d %2d %2d]\n"\r
1630                 , ((RFPath==0)?'A':'B'), Channel, txPower, txPower, base_index, by_rate_diff, track_diff, extra_bias);\r
1631 \r
1632         return (u8)txPower;     \r
1633 }\r
1634 \r
1635 //\r
1636 //      Description:\r
1637 //              Update transmit power level of all channel supported.\r
1638 //\r
1639 //      TODO:\r
1640 //              A mode.\r
1641 //      By Bruce, 2008-02-04.\r
1642 //\r
1643 BOOLEAN\r
1644 PHY_UpdateTxPowerDbm8188E(\r
1645         IN      PADAPTER        Adapter,\r
1646         IN      int             powerInDbm\r
1647         )\r
1648 {\r
1649         return _TRUE;\r
1650 }\r
1651 \r
1652 VOID\r
1653 PHY_ScanOperationBackup8188E(\r
1654         IN      PADAPTER        Adapter,\r
1655         IN      u8              Operation\r
1656         )\r
1657 {\r
1658 #if 0\r
1659         IO_TYPE IoType;\r
1660 \r
1661         if(!Adapter->bDriverStopped)\r
1662         {\r
1663                 switch(Operation)\r
1664                 {\r
1665                         case SCAN_OPT_BACKUP:\r
1666                                 IoType = IO_CMD_PAUSE_DM_BY_SCAN;\r
1667                                 rtw_hal_set_hwreg(Adapter,HW_VAR_IO_CMD,  (pu1Byte)&IoType);\r
1668 \r
1669                                 break;\r
1670 \r
1671                         case SCAN_OPT_RESTORE:\r
1672                                 IoType = IO_CMD_RESUME_DM_BY_SCAN;\r
1673                                 rtw_hal_set_hwreg(Adapter,HW_VAR_IO_CMD,  (pu1Byte)&IoType);\r
1674                                 break;\r
1675 \r
1676                         default:\r
1677                                 RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown Scan Backup Operation. \n"));\r
1678                                 break;\r
1679                 }\r
1680         }\r
1681 #endif\r
1682 }\r
1683 void \r
1684 phy_SpurCalibration_8188E(\r
1685         IN      PADAPTER                        Adapter\r
1686         )\r
1687 {\r
1688         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
1689         \r
1690         if(pHalData->CurrentChannelBW == CHANNEL_WIDTH_20 && pHalData->CurrentChannel == 13){\r
1691                 PHY_SetBBReg(Adapter, rOFDM1_CFOTracking, BIT(28), 0x1); //enable CSI Mask\r
1692                 PHY_SetBBReg(Adapter, rOFDM1_csi_fix_mask1, BIT(26)|BIT(25), 0x3); //Fix CSI Mask Tone\r
1693                 PHY_SetBBReg(Adapter, rOFDM1_csi_fix_mask2, BIT(26)|BIT(25), 0x0); \r
1694         }\r
1695         else if(pHalData->CurrentChannelBW == CHANNEL_WIDTH_40 && pHalData->CurrentChannel == 11){\r
1696                 PHY_SetBBReg(Adapter, rOFDM1_CFOTracking, BIT(28), 0x1); //enable CSI Mask\r
1697                 PHY_SetBBReg(Adapter, rOFDM1_csi_fix_mask1, BIT(26)|BIT(25), 0x0); \r
1698                 PHY_SetBBReg(Adapter, rOFDM1_csi_fix_mask2, BIT(26)|BIT(25), 0x3); //Fix CSI Mask Tone\r
1699         }\r
1700         else{\r
1701                 PHY_SetBBReg(Adapter, rOFDM1_CFOTracking, BIT(28), 0x0); //disable CSI Mask\r
1702                 PHY_SetBBReg(Adapter, rOFDM1_csi_fix_mask1, BIT(26)|BIT(25), 0x0); \r
1703                 PHY_SetBBReg(Adapter, rOFDM1_csi_fix_mask2, BIT(26)|BIT(25), 0x0); \r
1704         }\r
1705 \r
1706 }\r
1707 \r
1708 /*-----------------------------------------------------------------------------\r
1709  * Function:    PHY_SetBWModeCallback8192C()\r
1710  *\r
1711  * Overview:    Timer callback function for SetSetBWMode\r
1712  *\r
1713  * Input:               PRT_TIMER               pTimer\r
1714  *\r
1715  * Output:      NONE\r
1716  *\r
1717  * Return:      NONE\r
1718  *\r
1719  * Note:                (1) We do not take j mode into consideration now\r
1720  *                      (2) Will two workitem of "switch channel" and "switch channel bandwidth" run\r
1721  *                           concurrently?\r
1722  *---------------------------------------------------------------------------*/\r
1723 static VOID\r
1724 _PHY_SetBWMode88E(\r
1725         IN      PADAPTER        Adapter\r
1726 )\r
1727 {\r
1728 //      PADAPTER                        Adapter = (PADAPTER)pTimer->Adapter;\r
1729         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);\r
1730         u8                              regBwOpMode;\r
1731         u8                              regRRSR_RSC;\r
1732 \r
1733         //return;\r
1734 \r
1735         // Added it for 20/40 mhz switch time evaluation by guangan 070531\r
1736         //u4Byte                                NowL, NowH;\r
1737         //u8Byte                                BeginTime, EndTime;\r
1738 \r
1739         /*RT_TRACE(COMP_SCAN, DBG_LOUD, ("==>PHY_SetBWModeCallback8192C()  Switch to %s bandwidth\n", \\r
1740                                         pHalData->CurrentChannelBW == CHANNEL_WIDTH_20?"20MHz":"40MHz"))*/\r
1741 \r
1742         if(pHalData->rf_chip == RF_PSEUDO_11N)\r
1743         {\r
1744                 //pHalData->SetBWModeInProgress= _FALSE;\r
1745                 return;\r
1746         }\r
1747 \r
1748         // There is no 40MHz mode in RF_8225.\r
1749         if(pHalData->rf_chip==RF_8225)\r
1750                 return;\r
1751 \r
1752         if(Adapter->bDriverStopped)\r
1753                 return;\r
1754 \r
1755         // Added it for 20/40 mhz switch time evaluation by guangan 070531\r
1756         //NowL = PlatformEFIORead4Byte(Adapter, TSFR);\r
1757         //NowH = PlatformEFIORead4Byte(Adapter, TSFR+4);\r
1758         //BeginTime = ((u8Byte)NowH << 32) + NowL;\r
1759 \r
1760         //3//\r
1761         //3//<1>Set MAC register\r
1762         //3//\r
1763         //Adapter->HalFunc.SetBWModeHandler();\r
1764 \r
1765         regBwOpMode = rtw_read8(Adapter, REG_BWOPMODE);\r
1766         regRRSR_RSC = rtw_read8(Adapter, REG_RRSR+2);\r
1767         //regBwOpMode = rtw_hal_get_hwreg(Adapter,HW_VAR_BWMODE,(pu1Byte)&regBwOpMode);\r
1768 \r
1769         switch(pHalData->CurrentChannelBW)\r
1770         {\r
1771                 case CHANNEL_WIDTH_20:\r
1772                         regBwOpMode |= BW_OPMODE_20MHZ;\r
1773                            // 2007/02/07 Mark by Emily becasue we have not verify whether this register works\r
1774                         rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);\r
1775                         break;\r
1776 \r
1777                 case CHANNEL_WIDTH_40:\r
1778                         regBwOpMode &= ~BW_OPMODE_20MHZ;\r
1779                                 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works\r
1780                         rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);\r
1781 \r
1782                         regRRSR_RSC = (regRRSR_RSC&0x90) |(pHalData->nCur40MhzPrimeSC<<5);\r
1783                         rtw_write8(Adapter, REG_RRSR+2, regRRSR_RSC);\r
1784                         break;\r
1785 \r
1786                 default:\r
1787                         /*RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetBWModeCallback8192C():\r
1788                                                 unknown Bandwidth: %#X\n",pHalData->CurrentChannelBW));*/\r
1789                         break;\r
1790         }\r
1791 \r
1792         //3//\r
1793         //3//<2>Set PHY related register\r
1794         //3//\r
1795         switch(pHalData->CurrentChannelBW)\r
1796         {\r
1797                 /* 20 MHz channel*/\r
1798                 case CHANNEL_WIDTH_20:\r
1799                         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0);\r
1800                         PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0);\r
1801                         //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 1);\r
1802 \r
1803                         break;\r
1804 \r
1805 \r
1806                 /* 40 MHz channel*/\r
1807                 case CHANNEL_WIDTH_40:\r
1808                         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1);\r
1809                         PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1);\r
1810 \r
1811                         // Set Control channel to upper or lower. These settings are required only for 40MHz\r
1812                         PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1));\r
1813                         PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC);\r
1814                         //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 0);\r
1815 \r
1816                         PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC==HAL_PRIME_CHNL_OFFSET_LOWER)?2:1);\r
1817 \r
1818                         break;\r
1819 \r
1820 \r
1821 \r
1822                 default:\r
1823                         /*RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetBWModeCallback8192C(): unknown Bandwidth: %#X\n"\\r
1824                                                 ,pHalData->CurrentChannelBW));*/\r
1825                         break;\r
1826 \r
1827         }\r
1828         //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315\r
1829 \r
1830         // Added it for 20/40 mhz switch time evaluation by guangan 070531\r
1831         //NowL = PlatformEFIORead4Byte(Adapter, TSFR);\r
1832         //NowH = PlatformEFIORead4Byte(Adapter, TSFR+4);\r
1833         //EndTime = ((u8Byte)NowH << 32) + NowL;\r
1834         //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime)));\r
1835 \r
1836         //3<3>Set RF related register\r
1837         switch(pHalData->rf_chip)\r
1838         {\r
1839                 case RF_8225:\r
1840                         //PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);\r
1841                         break;\r
1842 \r
1843                 case RF_8256:\r
1844                         // Please implement this function in Hal8190PciPhy8256.c\r
1845                         //PHY_SetRF8256Bandwidth(Adapter, pHalData->CurrentChannelBW);\r
1846                         break;\r
1847 \r
1848                 case RF_8258:\r
1849                         // Please implement this function in Hal8190PciPhy8258.c\r
1850                         // PHY_SetRF8258Bandwidth();\r
1851                         break;\r
1852 \r
1853                 case RF_PSEUDO_11N:\r
1854                         // Do Nothing\r
1855                         break;\r
1856 \r
1857                 case RF_6052:\r
1858                         rtl8188e_PHY_RF6052SetBandwidth(Adapter, pHalData->CurrentChannelBW);\r
1859                         break;\r
1860 \r
1861                 default:\r
1862                         //RT_ASSERT(FALSE, ("Unknown RFChipID: %d\n", pHalData->RFChipID));\r
1863                         break;\r
1864         }\r
1865 \r
1866         //pHalData->SetBWModeInProgress= FALSE;\r
1867 \r
1868         //RT_TRACE(COMP_SCAN, DBG_LOUD, ("<==PHY_SetBWModeCallback8192C() \n" ));\r
1869 }\r
1870 \r
1871 \r
1872  /*-----------------------------------------------------------------------------\r
1873  * Function:   SetBWMode8190Pci()\r
1874  *\r
1875  * Overview:  This function is export to "HalCommon" moudule\r
1876  *\r
1877  * Input:               PADAPTER                        Adapter\r
1878  *                      CHANNEL_WIDTH   Bandwidth       //20M or 40M\r
1879  *\r
1880  * Output:      NONE\r
1881  *\r
1882  * Return:      NONE\r
1883  *\r
1884  * Note:                We do not take j mode into consideration now\r
1885  *---------------------------------------------------------------------------*/\r
1886 VOID\r
1887 PHY_SetBWMode8188E(\r
1888         IN      PADAPTER                                        Adapter,\r
1889         IN      CHANNEL_WIDTH   Bandwidth,      // 20M or 40M\r
1890         IN      unsigned char   Offset          // Upper, Lower, or Don't care\r
1891 )\r
1892 {\r
1893         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
1894         CHANNEL_WIDTH   tmpBW= pHalData->CurrentChannelBW;\r
1895         // Modified it for 20/40 mhz switch by guangan 070531\r
1896         //PMGNT_INFO    pMgntInfo=&Adapter->MgntInfo;\r
1897 \r
1898         //return;\r
1899 \r
1900         //if(pHalData->SwChnlInProgress)\r
1901 //      if(pMgntInfo->bScanInProgress)\r
1902 //      {\r
1903 //              RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() %s Exit because bScanInProgress!\n",\r
1904 //                                      Bandwidth == CHANNEL_WIDTH_20?"20MHz":"40MHz"));\r
1905 //              return;\r
1906 //      }\r
1907 \r
1908 //      if(pHalData->SetBWModeInProgress)\r
1909 //      {\r
1910 //              // Modified it for 20/40 mhz switch by guangan 070531\r
1911 //              RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() %s cancel last timer because SetBWModeInProgress!\n",\r
1912 //                                      Bandwidth == CHANNEL_WIDTH_20?"20MHz":"40MHz"));\r
1913 //              PlatformCancelTimer(Adapter, &pHalData->SetBWModeTimer);\r
1914 //              //return;\r
1915 //      }\r
1916 \r
1917         //if(pHalData->SetBWModeInProgress)\r
1918         //      return;\r
1919 \r
1920         //pHalData->SetBWModeInProgress= TRUE;\r
1921 \r
1922         pHalData->CurrentChannelBW = Bandwidth;\r
1923 \r
1924 #if 0\r
1925         if(Offset==EXTCHNL_OFFSET_LOWER)\r
1926                 pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;\r
1927         else if(Offset==EXTCHNL_OFFSET_UPPER)\r
1928                 pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;\r
1929         else\r
1930                 pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;\r
1931 #else\r
1932         pHalData->nCur40MhzPrimeSC = Offset;\r
1933 #endif\r
1934 \r
1935         if((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))\r
1936         {\r
1937         #if 0\r
1938                 //PlatformSetTimer(Adapter, &(pHalData->SetBWModeTimer), 0);\r
1939         #else\r
1940                 _PHY_SetBWMode88E(Adapter);\r
1941         #endif\r
1942                 if (IS_VENDOR_8188E_I_CUT_SERIES(Adapter)&& IS_HARDWARE_TYPE_8188ES(Adapter))\r
1943                         phy_SpurCalibration_8188E( Adapter);\r
1944         }\r
1945         else\r
1946         {\r
1947                 //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() SetBWModeInProgress FALSE driver sleep or unload\n"));\r
1948                 //pHalData->SetBWModeInProgress= FALSE;\r
1949                 pHalData->CurrentChannelBW = tmpBW;\r
1950         }\r
1951         \r
1952 }\r
1953 \r
1954 \r
1955 static void _PHY_SwChnl8188E(PADAPTER Adapter, u8 channel)\r
1956 {\r
1957         u8 eRFPath;\r
1958         u32 param1, param2;\r
1959         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
1960 \r
1961         if ( Adapter->bNotifyChannelChange )\r
1962         {\r
1963                 DBG_871X( "[%s] ch = %d\n", __FUNCTION__, channel );\r
1964         }\r
1965 \r
1966         //s1. pre common command - CmdID_SetTxPowerLevel\r
1967         PHY_SetTxPowerLevel8188E(Adapter, channel);\r
1968 \r
1969         //s2. RF dependent command - CmdID_RF_WriteReg, param1=RF_CHNLBW, param2=channel\r
1970         param1 = RF_CHNLBW;\r
1971         param2 = channel;\r
1972         for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)\r
1973         {\r
1974                 pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | param2);\r
1975                 PHY_SetRFReg(Adapter, eRFPath, param1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);\r
1976         }\r
1977 \r
1978 \r
1979         //s3. post common command - CmdID_End, None\r
1980 \r
1981 }\r
1982 VOID\r
1983 PHY_SwChnl8188E(        // Call after initialization\r
1984         IN      PADAPTER        Adapter,\r
1985         IN      u8              channel\r
1986         )\r
1987 {\r
1988         //PADAPTER Adapter =  ADJUST_TO_ADAPTIVE_ADAPTER(pAdapter, _TRUE);\r
1989         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
1990         u8      tmpchannel = pHalData->CurrentChannel;\r
1991         BOOLEAN  bResult = _TRUE;\r
1992 \r
1993         if(pHalData->rf_chip == RF_PSEUDO_11N)\r
1994         {\r
1995                 //pHalData->SwChnlInProgress=FALSE;\r
1996                 return;                                                                 //return immediately if it is peudo-phy\r
1997         }\r
1998 \r
1999         //if(pHalData->SwChnlInProgress)\r
2000         //      return;\r
2001 \r
2002         //if(pHalData->SetBWModeInProgress)\r
2003         //      return;\r
2004 \r
2005         //--------------------------------------------\r
2006         switch(pHalData->CurrentWirelessMode)\r
2007         {\r
2008                 case WIRELESS_MODE_A:\r
2009                 case WIRELESS_MODE_N_5G:\r
2010                         //RT_ASSERT((channel>14), ("WIRELESS_MODE_A but channel<=14"));\r
2011                         break;\r
2012 \r
2013                 case WIRELESS_MODE_B:\r
2014                         //RT_ASSERT((channel<=14), ("WIRELESS_MODE_B but channel>14"));\r
2015                         break;\r
2016 \r
2017                 case WIRELESS_MODE_G:\r
2018                 case WIRELESS_MODE_N_24G:\r
2019                         //RT_ASSERT((channel<=14), ("WIRELESS_MODE_G but channel>14"));\r
2020                         break;\r
2021 \r
2022                 default:\r
2023                         //RT_ASSERT(FALSE, ("Invalid WirelessMode(%#x)!!\n", pHalData->CurrentWirelessMode));\r
2024                         break;\r
2025         }\r
2026         //--------------------------------------------\r
2027 \r
2028         //pHalData->SwChnlInProgress = TRUE;\r
2029         if(channel == 0)\r
2030                 channel = 1;\r
2031 \r
2032         pHalData->CurrentChannel=channel;\r
2033 \r
2034         //pHalData->SwChnlStage=0;\r
2035         //pHalData->SwChnlStep=0;\r
2036 \r
2037         if((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))\r
2038         {\r
2039                 #if 0\r
2040                 //PlatformSetTimer(Adapter, &(pHalData->SwChnlTimer), 0);\r
2041                 #else\r
2042                 _PHY_SwChnl8188E(Adapter, channel);\r
2043                 #endif\r
2044 \r
2045                 if (IS_VENDOR_8188E_I_CUT_SERIES(Adapter)&& IS_HARDWARE_TYPE_8188ES(Adapter))\r
2046                         phy_SpurCalibration_8188E( Adapter);\r
2047                 \r
2048 \r
2049                 if(bResult)\r
2050                 {\r
2051                         //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress TRUE schdule workitem done\n"));\r
2052                 }\r
2053                 else\r
2054                 {\r
2055                         //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress FALSE schdule workitem error\n"));\r
2056                         //if(IS_HARDWARE_TYPE_8192SU(Adapter))\r
2057                         //{\r
2058                         //      pHalData->SwChnlInProgress = FALSE;\r
2059                                 pHalData->CurrentChannel = tmpchannel;\r
2060                         //}\r
2061                 }\r
2062 \r
2063         }\r
2064         else\r
2065         {\r
2066                 //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress FALSE driver sleep or unload\n"));\r
2067                 //if(IS_HARDWARE_TYPE_8192SU(Adapter))\r
2068                 //{\r
2069                 //      pHalData->SwChnlInProgress = FALSE;\r
2070                         pHalData->CurrentChannel = tmpchannel;\r
2071                 //}\r
2072         }\r
2073 }\r
2074 \r
2075 VOID\r
2076 PHY_SetSwChnlBWMode8188E(\r
2077         IN      PADAPTER                        Adapter,\r
2078         IN      u8                                      channel,\r
2079         IN      CHANNEL_WIDTH   Bandwidth,\r
2080         IN      u8                                      Offset40,\r
2081         IN      u8                                      Offset80\r
2082 )\r
2083 {\r
2084         //DBG_871X("%s()===>\n",__FUNCTION__);\r
2085 \r
2086         PHY_SwChnl8188E(Adapter, channel);\r
2087         PHY_SetBWMode8188E(Adapter, Bandwidth, Offset40);\r
2088 \r
2089         //DBG_871X("<==%s()\n",__FUNCTION__);\r
2090 }\r
2091 \r
2092 \r
2093 //\r
2094 //      Description:\r
2095 //              Configure H/W functionality to enable/disable Monitor mode.\r
2096 //              Note, because we possibly need to configure BB and RF in this function,\r
2097 //              so caller should in PASSIVE_LEVEL. 080118, by rcnjko.\r
2098 //\r
2099 VOID\r
2100 PHY_SetMonitorMode8192C(\r
2101         IN      PADAPTER                        pAdapter,\r
2102         IN      BOOLEAN                         bEnableMonitorMode\r
2103         )\r
2104 {\r
2105 #if 0\r
2106         HAL_DATA_TYPE           *pHalData       = GET_HAL_DATA(pAdapter);\r
2107         BOOLEAN                         bFilterOutNonAssociatedBSSID = FALSE;\r
2108 \r
2109         //2 Note: we may need to stop antenna diversity.\r
2110         if(bEnableMonitorMode)\r
2111         {\r
2112                 bFilterOutNonAssociatedBSSID = FALSE;\r
2113                 RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): enable monitor mode\n"));\r
2114 \r
2115                 pHalData->bInMonitorMode = TRUE;\r
2116                 pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, TRUE, TRUE);\r
2117                 rtw_hal_set_hwreg(pAdapter, HW_VAR_CHECK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID);\r
2118         }\r
2119         else\r
2120         {\r
2121                 bFilterOutNonAssociatedBSSID = TRUE;\r
2122                 RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): disable monitor mode\n"));\r
2123 \r
2124                 pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, FALSE, TRUE);\r
2125                 pHalData->bInMonitorMode = FALSE;\r
2126                 rtw_hal_set_hwreg(pAdapter, HW_VAR_CHECK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID);\r
2127         }\r
2128 #endif\r
2129 }\r
2130 \r
2131 \r
2132 /*-----------------------------------------------------------------------------\r
2133  * Function:    PHYCheckIsLegalRfPath8190Pci()\r
2134  *\r
2135  * Overview:    Check different RF type to execute legal judgement. If RF Path is illegal\r
2136  *                      We will return false.\r
2137  *\r
2138  * Input:               NONE\r
2139  *\r
2140  * Output:              NONE\r
2141  *\r
2142  * Return:              NONE\r
2143  *\r
2144  * Revised History:\r
2145  *      When            Who             Remark\r
2146  *      11/15/2007      MHC             Create Version 0.\r
2147  *\r
2148  *---------------------------------------------------------------------------*/\r
2149 BOOLEAN\r
2150 PHY_CheckIsLegalRfPath8192C(\r
2151         IN      PADAPTER        pAdapter,\r
2152         IN      u32     eRFPath)\r
2153 {\r
2154 //      HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
2155         BOOLEAN                         rtValue = _TRUE;\r
2156 \r
2157         // NOt check RF Path now.!\r
2158 #if 0\r
2159         if (pHalData->RF_Type == RF_1T2R && eRFPath != RF_PATH_A)\r
2160         {\r
2161                 rtValue = FALSE;\r
2162         }\r
2163         if (pHalData->RF_Type == RF_1T2R && eRFPath != RF_PATH_A)\r
2164         {\r
2165 \r
2166         }\r
2167 #endif\r
2168         return  rtValue;\r
2169 \r
2170 }       /* PHY_CheckIsLegalRfPath8192C */\r
2171 \r
2172 static VOID _PHY_SetRFPathSwitch(\r
2173         IN      PADAPTER        pAdapter,\r
2174         IN      BOOLEAN         bMain,\r
2175         IN      BOOLEAN         is2T\r
2176         )\r
2177 {\r
2178         u8      u1bTmp;\r
2179 \r
2180         if(!pAdapter->hw_init_completed)\r
2181         {\r
2182                 u1bTmp = rtw_read8(pAdapter, REG_LEDCFG2) | BIT7;\r
2183                 rtw_write8(pAdapter, REG_LEDCFG2, u1bTmp);\r
2184                 //PHY_SetBBReg(pAdapter, REG_LEDCFG0, BIT23, 0x01);\r
2185                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);\r
2186         }\r
2187 \r
2188         if(is2T)\r
2189         {\r
2190                 if(bMain)\r
2191                         PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1);        //92C_Path_A\r
2192                 else\r
2193                         PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2);        //BT\r
2194         }\r
2195         else\r
2196         {\r
2197 \r
2198                 if(bMain)\r
2199                         PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0x2);    //Main\r
2200                 else\r
2201                         PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0x1);    //Aux\r
2202         }\r
2203 \r
2204 }\r
2205 \r
2206 //return value TRUE => Main; FALSE => Aux\r
2207 \r
2208 static BOOLEAN _PHY_QueryRFPathSwitch(\r
2209         IN      PADAPTER        pAdapter,\r
2210         IN      BOOLEAN         is2T\r
2211         )\r
2212 {\r
2213 //      if(is2T)\r
2214 //              return _TRUE;\r
2215 \r
2216         if(!pAdapter->hw_init_completed)\r
2217         {\r
2218                 PHY_SetBBReg(pAdapter, REG_LEDCFG0, BIT23, 0x01);\r
2219                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);\r
2220         }\r
2221 \r
2222         if(is2T)\r
2223         {\r
2224                 if(PHY_QueryBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01)\r
2225                         return _TRUE;\r
2226                 else\r
2227                         return _FALSE;\r
2228         }\r
2229         else\r
2230         {\r
2231                 if(PHY_QueryBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300) == 0x02)\r
2232                         return _TRUE;\r
2233                 else\r
2234                         return _FALSE;\r
2235         }\r
2236 }\r
2237 \r
2238 \r
2239 static VOID\r
2240 _PHY_DumpRFReg(IN       PADAPTER        pAdapter)\r
2241 {\r
2242         u32 rfRegValue,rfRegOffset;\r
2243 \r
2244         //RTPRINT(FINIT, INIT_RF, ("PHY_DumpRFReg()====>\n"));\r
2245 \r
2246         for(rfRegOffset = 0x00;rfRegOffset<=0x30;rfRegOffset++){\r
2247                 rfRegValue = PHY_QueryRFReg(pAdapter,RF_PATH_A, rfRegOffset, bMaskDWord);\r
2248                 //RTPRINT(FINIT, INIT_RF, (" 0x%02x = 0x%08x\n",rfRegOffset,rfRegValue));\r
2249         }\r
2250         //RTPRINT(FINIT, INIT_RF, ("<===== PHY_DumpRFReg()\n"));\r
2251 }\r
2252 \r
2253 \r
2254 //\r
2255 // Move from phycfg.c to gen.c to be code independent later\r
2256 //\r
2257 //-------------------------Move to other DIR later----------------------------*/\r
2258 #ifdef CONFIG_USB_HCI\r
2259 \r
2260 //\r
2261 //      Description:\r
2262 //              To dump all Tx FIFO LLT related link-list table.\r
2263 //              Added by Roger, 2009.03.10.\r
2264 //\r
2265 VOID\r
2266 DumpBBDbgPort_92CU(\r
2267         IN      PADAPTER                        Adapter\r
2268         )\r
2269 {\r
2270 \r
2271         //RT_TRACE(COMP_SEND, DBG_WARNING, ("\n>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"));\r
2272         //RT_TRACE(COMP_SEND, DBG_WARNING, ("BaseBand Debug Ports:\n"));\r
2273 \r
2274         PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0000);\r
2275         //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));\r
2276 \r
2277         PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0803);\r
2278         //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));\r
2279 \r
2280         PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0a06);\r
2281         //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));\r
2282 \r
2283         PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0007);\r
2284         //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));\r
2285 \r
2286         PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0100);\r
2287         PHY_SetBBReg(Adapter, 0x0a28, 0x00ff0000, 0x000f0000);\r
2288         //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));\r
2289 \r
2290         PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0100);\r
2291         PHY_SetBBReg(Adapter, 0x0a28, 0x00ff0000, 0x00150000);\r
2292         //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));\r
2293 \r
2294         //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0x800, PHY_QueryBBReg(Adapter, 0x0800, bMaskDWord)));\r
2295         //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0x900, PHY_QueryBBReg(Adapter, 0x0900, bMaskDWord)));\r
2296         //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa00, PHY_QueryBBReg(Adapter, 0x0a00, bMaskDWord)));\r
2297         //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa54, PHY_QueryBBReg(Adapter, 0x0a54, bMaskDWord)));\r
2298         //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa58, PHY_QueryBBReg(Adapter, 0x0a58, bMaskDWord)));\r
2299 \r
2300 }\r
2301 #endif\r
2302 \r