drivers/net/wireless/rockchip_wlan/rtl8188eu/hal/phydm/txbf/haltxbfjaguar.c

   1 //============================================================
   2 // Description:
   3 //
   4 // This file is for 8812/8821/8811 TXBF mechanism
   5 //
   6 //============================================================
   7 #include "mp_precomp.h"
   8 #include "../phydm_precomp.h"
   9
  10 #if (BEAMFORMING_SUPPORT == 1)
  11 #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
  12 VOID
  13 HalTxbf8812A_setNDPArate(
  14         IN PVOID                        pDM_VOID,
  15         IN u1Byte       BW,
  16         IN u1Byte       Rate
  17 )
  18 {
  19         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;
  20
  21         ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8812A,  (Rate << 2 | BW));
  22
  23 }
  24
  25 VOID
  26 halTxbfJaguar_RfMode(
  27         IN PVOID                        pDM_VOID,
  28         IN PRT_BEAMFORMING_INFO pBeamInfo
  29 )
  30 {
  31         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;
  32
  33         if (pDM_Odm->RFType == ODM_1T1R)
  34                 return;
  35
  36         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] set TxIQGen\n", __func__));
  37
  38         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WeLut_Jaguar, 0x80000, 0x1);    /*RF Mode table write enable*/
  39         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WeLut_Jaguar, 0x80000, 0x1);    /*RF Mode table write enable*/
  40
  41         if (pBeamInfo->beamformee_su_cnt > 0) {
  42                 // Paath_A
  43                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0x78000, 0x3);           /*Select RX mode*/
  44                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x3F7FF);      /*Set Table data*/
  45                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xE26BF);      /*Enable TXIQGEN in RX mode*/
  46                 // Path_B
  47                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0x78000, 0x3);           /*Select RX mode*/
  48                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x3F7FF);      /*Set Table data*/
  49                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0xE26BF);      /*Enable TXIQGEN in RX mode*/
  50         } else {
  51                 // Paath_A
  52                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0x78000, 0x3);           /*Select RX mode*/
  53                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x3F7FF);      /*Set Table data*/
  54                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xC26BF);      /*Disable TXIQGEN in RX mode*/
  55                 // Path_B
  56                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0x78000, 0x3);           /*Select RX mode*/
  57                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x3F7FF);      /*Set Table data*/
  58                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0xC26BF);      /*Disable TXIQGEN in RX mode*/
  59         }
  60
  61         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WeLut_Jaguar, 0x80000, 0x0);    /*RF Mode table write disable*/
  62         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WeLut_Jaguar, 0x80000, 0x0);    /*RF Mode table write disable*/
  63
  64         if (pBeamInfo->beamformee_su_cnt > 0)
  65                 ODM_SetBBReg(pDM_Odm, rTxPath_Jaguar, bMaskByte1, 0x33);
  66         else
  67                 ODM_SetBBReg(pDM_Odm, rTxPath_Jaguar, bMaskByte1, 0x11);
  68 }
  69
  70
  71 VOID
  72 halTxbfJaguar_DownloadNDPA(
  73         IN PVOID                        pDM_VOID,
  74         IN      u1Byte                          Idx
  75 )
  76 {
  77         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;
  78         u1Byte                  u1bTmp = 0, tmpReg422 = 0, Head_Page;
  79         u1Byte                  BcnValidReg = 0, count = 0, DLBcnCount = 0;
  80         BOOLEAN                 bSendBeacon = FALSE;
  81         u1Byte                  TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812;  /*default reseved 1 page for the IC type which is undefined.*/
  82         PRT_BEAMFORMING_INFO    pBeamInfo = &pDM_Odm->BeamformingInfo;
  83         PRT_BEAMFORMEE_ENTRY    pBeamEntry = pBeamInfo->BeamformeeEntry + Idx;
  84         PADAPTER                Adapter = pDM_Odm->Adapter;
  85 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
  86         *pDM_Odm->pbFwDwRsvdPageInProgress = TRUE;
  87 #endif
  88         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
  89
  90         if (Idx == 0)
  91                 Head_Page = 0xFE;
  92         else
  93                 Head_Page = 0xFE;
  94
  95         Adapter->HalFunc.GetHalDefVarHandler(Adapter, HAL_DEF_TX_PAGE_BOUNDARY, (pu1Byte)&TxPageBndy);
  96
  97         /*Set REG_CR bit 8. DMA beacon by SW.*/
  98         u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8812A + 1);
  99         ODM_Write1Byte(pDM_Odm,  REG_CR_8812A + 1, (u1bTmp | BIT0));
 100
 101
 102         /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
 103         tmpReg422 = ODM_Read1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8812A + 2);
 104         ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8812A + 2,  tmpReg422 & (~BIT6));
 105
 106         if (tmpReg422 & BIT6) {
 107                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("SetBeamformDownloadNDPA_8812(): There is an Adapter is sending beacon.\n"));
 108                 bSendBeacon = TRUE;
 109         }
 110
 111         /*TDECTRL[15:8] 0x209[7:0] = 0xF6       Beacon Head for TXDMA*/
 112         ODM_Write1Byte(pDM_Odm, REG_TDECTRL_8812A + 1, Head_Page);
 113
 114         do {
 115                 /*Clear beacon valid check bit.*/
 116                 BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_TDECTRL_8812A + 2);
 117                 ODM_Write1Byte(pDM_Odm, REG_TDECTRL_8812A + 2, (BcnValidReg | BIT0));
 118
 119                 /*download NDPA rsvd page.*/
 120                 if (pBeamEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU)
 121                         Beamforming_SendVHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->AID, pBeamEntry->SoundBW, BEACON_QUEUE);
 122                 else
 123                         Beamforming_SendHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->SoundBW, BEACON_QUEUE);
 124
 125                 /*check rsvd page download OK.*/
 126                 BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_TDECTRL_8812A + 2);
 127                 count = 0;
 128                 while (!(BcnValidReg & BIT0) && count < 20) {
 129                         count++;
 130                         ODM_delay_ms(10);
 131                         BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_TDECTRL_8812A + 2);
 132                 }
 133                 DLBcnCount++;
 134         } while (!(BcnValidReg & BIT0) && DLBcnCount < 5);
 135
 136         if (!(BcnValidReg & BIT0))
 137                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Download RSVD page failed!\n", __func__));
 138
 139         /*TDECTRL[15:8] 0x209[7:0] = 0xF6       Beacon Head for TXDMA*/
 140         ODM_Write1Byte(pDM_Odm, REG_TDECTRL_8812A + 1, TxPageBndy);
 141
 142         /*To make sure that if there exists an adapter which would like to send beacon.*/
 143         /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
 144         /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/
 145         /*the beacon cannot be sent by HW.*/
 146         /*2010.06.23. Added by tynli.*/
 147         if (bSendBeacon)
 148                 ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8812A + 2, tmpReg422);
 149
 150         /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
 151         /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
 152         u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8812A + 1);
 153         ODM_Write1Byte(pDM_Odm, REG_CR_8812A + 1, (u1bTmp & (~BIT0)));
 154
 155         pBeamEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED;
 156 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 157         *pDM_Odm->pbFwDwRsvdPageInProgress = FALSE;
 158 #endif
 159 }
 160
 161
 162 VOID
 163 halTxbfJaguar_FwTxBFCmd(
 164         IN PVOID                        pDM_VOID
 165 )
 166 {
 167         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;
 168         u1Byte  Idx, Period0 = 0, Period1 = 0;
 169         u1Byte  PageNum0 = 0xFF, PageNum1 = 0xFF;
 170         u1Byte  u1TxBFParm[3] = {0};
 171         PRT_BEAMFORMING_INFO    pBeamInfo = &pDM_Odm->BeamformingInfo;
 172
 173         for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) {
 174                 /*Modified by David*/
 175                 if (pBeamInfo->BeamformeeEntry[Idx].bUsed && pBeamInfo->BeamformeeEntry[Idx].BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
 176                         if (Idx == 0) {
 177                                 if (pBeamInfo->BeamformeeEntry[Idx].bSound)
 178                                         PageNum0 = 0xFE;
 179                                 else
 180                                         PageNum0 = 0xFF; /*stop sounding*/
 181                                 Period0 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod);
 182                         } else if (Idx == 1) {
 183                                 if (pBeamInfo->BeamformeeEntry[Idx].bSound)
 184                                         PageNum1 = 0xFE;
 185                                 else
 186                                         PageNum1 = 0xFF; /*stop sounding*/
 187                                 Period1 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod);
 188                         }
 189                 }
 190         }
 191
 192         u1TxBFParm[0] = PageNum0;
 193         u1TxBFParm[1] = PageNum1;
 194         u1TxBFParm[2] = (Period1 << 4) | Period0;
 195         ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_TXBF, 3, u1TxBFParm);
 196
 197         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD,
 198                 ("[%s] PageNum0 = %d Period0 = %d, PageNum1 = %d Period1 %d\n", __func__, PageNum0, Period0, PageNum1, Period1));
 199 }
 200
 201
 202 VOID
 203 HalTxbfJaguar_Enter(
 204         IN PVOID                        pDM_VOID,
 205         IN u1Byte                               BFerBFeeIdx
 206 )
 207 {
 208         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;
 209         u1Byte                                  i = 0;
 210         u1Byte                                  BFerIdx = (BFerBFeeIdx & 0xF0) >> 4;
 211         u1Byte                                  BFeeIdx = (BFerBFeeIdx & 0xF);
 212         u4Byte                                  CSI_Param;
 213         PRT_BEAMFORMING_INFO    pBeamformingInfo = &pDM_Odm->BeamformingInfo;
 214         RT_BEAMFORMEE_ENTRY     BeamformeeEntry;
 215         RT_BEAMFORMER_ENTRY     BeamformerEntry;
 216         u2Byte                                  STAid = 0;
 217
 218         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Start!\n", __func__));
 219
 220         halTxbfJaguar_RfMode(pDM_Odm, pBeamformingInfo);
 221
 222         if (pDM_Odm->RFType == ODM_2T2R)
 223                 ODM_SetBBReg(pDM_Odm, ODM_REG_CSI_CONTENT_VALUE, bMaskDWord, 0x00000000);       /*Nc =2*/
 224         else
 225                 ODM_SetBBReg(pDM_Odm, ODM_REG_CSI_CONTENT_VALUE, bMaskDWord, 0x01081008);       /*Nc =1*/
 226
 227         if ((pBeamformingInfo->beamformer_su_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) {
 228                 BeamformerEntry = pBeamformingInfo->BeamformerEntry[BFerIdx];
 229
 230                 /*Sounding protocol control*/
 231                 ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A, 0xCB);
 232
 233                 /*MAC address/Partial AID of Beamformer*/
 234                 if (BFerIdx == 0) {
 235                         for (i = 0; i < 6 ; i++)
 236                                 ODM_Write1Byte(pDM_Odm, (REG_BFMER0_INFO_8812A + i), BeamformerEntry.MacAddr[i]);
 237                         /*CSI report use legacy ofdm so don't need to fill P_AID. */
 238                         /*PlatformEFIOWrite2Byte(Adapter, REG_BFMER0_INFO_8812A+6, BeamformEntry.P_AID); */
 239                 } else {
 240                         for (i = 0; i < 6 ; i++)
 241                                 ODM_Write1Byte(pDM_Odm, (REG_BFMER1_INFO_8812A + i), BeamformerEntry.MacAddr[i]);
 242                         /*CSI report use legacy ofdm so don't need to fill P_AID.*/
 243                         /*PlatformEFIOWrite2Byte(Adapter, REG_BFMER1_INFO_8812A+6, BeamformEntry.P_AID);*/
 244                 }
 245
 246                 /*CSI report parameters of Beamformee*/
 247                 if (BeamformerEntry.BeamformEntryCap & BEAMFORMEE_CAP_VHT_SU) {
 248                         if (pDM_Odm->RFType == ODM_2T2R)
 249                                 CSI_Param = 0x01090109;
 250                         else
 251                                 CSI_Param = 0x01080108;
 252                 } else {
 253                         if (pDM_Odm->RFType == ODM_2T2R)
 254                                 CSI_Param = 0x03090309;
 255                         else
 256                                 CSI_Param = 0x03080308;
 257                 }
 258
 259                 ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8812A, CSI_Param);
 260                 ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8812A, CSI_Param);
 261                 ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8812A, CSI_Param);
 262
 263                 /*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us,  MP chip)*/
 264                 ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A + 3, 0x50);
 265         }
 266
 267
 268         if ((pBeamformingInfo->beamformee_su_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) {
 269                 BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[BFeeIdx];
 270
 271                 if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS))
 272                         STAid = BeamformeeEntry.MacId;
 273                 else
 274                         STAid = BeamformeeEntry.P_AID;
 275
 276                 /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
 277                 if (BFeeIdx == 0) {
 278                         ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8812A, STAid);
 279                         ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 3) | BIT4 | BIT6 | BIT7);
 280                 } else
 281                         ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 2, STAid | BIT12 | BIT14 | BIT15);
 282
 283                 /*CSI report parameters of Beamformee*/
 284                 if (BFeeIdx == 0) {
 285                         /*Get BIT24 & BIT25*/
 286                         u1Byte  tmp = ODM_Read1Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 3) & 0x3;
 287
 288                         ODM_Write1Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 3, tmp | 0x60);
 289                         ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A, STAid | BIT9);
 290                 } else {
 291                         /*Set BIT25*/
 292                         ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 2, STAid | 0xE200);
 293                 }
 294                         phydm_Beamforming_Notify(pDM_Odm);
 295         }
 296 }
 297
 298
 299 VOID
 300 HalTxbfJaguar_Leave(
 301         IN PVOID                        pDM_VOID,
 302         IN u1Byte                               Idx
 303 )
 304 {
 305         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;
 306         PRT_BEAMFORMING_INFO    pBeamformingInfo = &pDM_Odm->BeamformingInfo;
 307         RT_BEAMFORMER_ENTRY     BeamformerEntry;
 308         RT_BEAMFORMEE_ENTRY     BeamformeeEntry;
 309
 310         if (Idx < BEAMFORMER_ENTRY_NUM) {
 311                 BeamformerEntry = pBeamformingInfo->BeamformerEntry[Idx];
 312                 BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[Idx];
 313         } else
 314                 return;
 315
 316         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Start!, IDx = %d\n", __func__, Idx));
 317
 318         /*Clear P_AID of Beamformee*/
 319         /*Clear MAC address of Beamformer*/
 320         /*Clear Associated Bfmee Sel*/
 321
 322         if (BeamformerEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) {
 323                 ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A, 0xC8);
 324                 if (Idx == 0) {
 325                         ODM_Write4Byte(pDM_Odm, REG_BFMER0_INFO_8812A, 0);
 326                         ODM_Write2Byte(pDM_Odm, REG_BFMER0_INFO_8812A + 4, 0);
 327                         ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8812A, 0);
 328                         ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8812A, 0);
 329                         ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8812A, 0);
 330                 } else {
 331                         ODM_Write4Byte(pDM_Odm, REG_BFMER1_INFO_8812A, 0);
 332                         ODM_Write2Byte(pDM_Odm, REG_BFMER1_INFO_8812A + 4, 0);
 333                         ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8812A, 0);
 334                         ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8812A, 0);
 335                         ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8812A, 0);
 336                 }
 337         }
 338
 339         if (BeamformeeEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) {
 340                 halTxbfJaguar_RfMode(pDM_Odm, pBeamformingInfo);
 341                 if (Idx == 0) {
 342                         ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8812A, 0x0);
 343                         ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A, 0);
 344                 } else {
 345                         ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 2, ODM_Read2Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 2) & 0xF000);
 346                         ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 2, ODM_Read2Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 2) & 0x60);
 347                 }
 348         }
 349
 350 }
 351
 352
 353 VOID
 354 HalTxbfJaguar_Status(
 355         IN PVOID                        pDM_VOID,
 356         IN u1Byte                               Idx
 357 )
 358 {
 359         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;
 360         u2Byte                                  BeamCtrlVal;
 361         u4Byte                                  BeamCtrlReg;
 362         PRT_BEAMFORMING_INFO    pBeamInfo = &pDM_Odm->BeamformingInfo;
 363         RT_BEAMFORMEE_ENTRY     BeamformEntry = pBeamInfo->BeamformeeEntry[Idx];
 364
 365         if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS))
 366                 BeamCtrlVal = BeamformEntry.MacId;
 367         else
 368                 BeamCtrlVal = BeamformEntry.P_AID;
 369
 370         if (Idx == 0)
 371                 BeamCtrlReg = REG_TXBF_CTRL_8812A;
 372         else {
 373                 BeamCtrlReg = REG_TXBF_CTRL_8812A + 2;
 374                 BeamCtrlVal |= BIT12 | BIT14 | BIT15;
 375         }
 376
 377         if (BeamformEntry.BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
 378                 if (BeamformEntry.SoundBW == CHANNEL_WIDTH_20)
 379                         BeamCtrlVal |= BIT9;
 380                 else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_40)
 381                         BeamCtrlVal |= (BIT9 | BIT10);
 382                 else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_80)
 383                         BeamCtrlVal |= (BIT9 | BIT10 | BIT11);
 384         } else
 385                 BeamCtrlVal &= ~(BIT9 | BIT10 | BIT11);
 386
 387         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] BeamCtrlVal = 0x%x!\n", __func__, BeamCtrlVal));
 388
 389         ODM_Write2Byte(pDM_Odm, BeamCtrlReg, BeamCtrlVal);
 390 }
 391
 392
 393
 394 VOID
 395 HalTxbfJaguar_FwTxBF(
 396         IN PVOID                        pDM_VOID,
 397         IN      u1Byte                          Idx
 398 )
 399 {
 400         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;
 401         PRT_BEAMFORMING_INFO    pBeamInfo = &pDM_Odm->BeamformingInfo;
 402         PRT_BEAMFORMEE_ENTRY    pBeamEntry = pBeamInfo->BeamformeeEntry + Idx;
 403
 404         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
 405
 406         if (pBeamEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING)
 407                 halTxbfJaguar_DownloadNDPA(pDM_Odm, Idx);
 408
 409         halTxbfJaguar_FwTxBFCmd(pDM_Odm);
 410 }
 411
 412
 413 VOID
 414 HalTxbfJaguar_Patch(
 415         IN PVOID                        pDM_VOID,
 416         IN      u1Byte                          Operation
 417 )
 418 {
 419         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;
 420         PRT_BEAMFORMING_INFO    pBeamInfo = &pDM_Odm->BeamformingInfo;
 421
 422         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
 423
 424         if (pBeamInfo->BeamformCap == BEAMFORMING_CAP_NONE)
 425                 return;
 426 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 427         if (Operation == SCAN_OPT_BACKUP_BAND0)
 428                 ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A, 0xC8);
 429         else if (Operation == SCAN_OPT_RESTORE)
 430                 ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A, 0xCB);
 431 #endif
 432 }
 433
 434 VOID
 435 HalTxbfJaguar_Clk_8812A(
 436         IN PVOID                        pDM_VOID
 437 )
 438 {
 439         PDM_ODM_T       pDM_Odm = (PDM_ODM_T)pDM_VOID;
 440         u2Byte  u2btmp;
 441         u1Byte  Count = 0, u1btmp;
 442         PADAPTER        Adapter = pDM_Odm->Adapter;
 443
 444         ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__));
 445
 446         if (*(pDM_Odm->pbScanInProcess)) {
 447                 ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] return by Scan\n", __func__));
 448                 return;
 449         }
 450 #if DEV_BUS_TYPE == RT_PCI_INTERFACE
 451         /*Stop PCIe TxDMA*/
 452         ODM_Write1Byte(pDM_Odm, REG_PCIE_CTRL_REG_8812A + 1, 0xFE);
 453 #endif
 454
 455         /*Stop Usb TxDMA*/
 456 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 457         RT_DISABLE_FUNC(Adapter, DF_TX_BIT);
 458         PlatformReturnAllPendingTxPackets(Adapter);
 459 #else
 460         rtw_write_port_cancel(Adapter);
 461 #endif
 462
 463         /*Wait TXFF empty*/
 464         for (Count = 0; Count < 100; Count++) {
 465                 u2btmp = ODM_Read2Byte(pDM_Odm, REG_TXPKT_EMPTY_8812A);
 466                 u2btmp = u2btmp & 0xfff;
 467                 if (u2btmp != 0xfff) {
 468                         ODM_delay_ms(10);
 469                         continue;
 470                 } else
 471                         break;
 472         }
 473
 474         /*TX pause*/
 475         ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812A, 0xFF);
 476
 477         /*Wait TX State Machine OK*/
 478         for (Count = 0; Count < 100; Count++) {
 479                 if (ODM_Read4Byte(pDM_Odm, REG_SCH_TXCMD_8812A) != 0)
 480                         continue;
 481                 else
 482                         break;
 483         }
 484
 485
 486         /*Stop RX DMA path*/
 487         u1btmp = ODM_Read1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A);
 488         ODM_Write1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A, u1btmp | BIT2);
 489
 490         for (Count = 0; Count < 100; Count++) {
 491                 u1btmp = ODM_Read1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A);
 492                 if (u1btmp & BIT1)
 493                         break;
 494                 else
 495                         ODM_delay_ms(10);
 496         }
 497
 498         /*Disable clock*/
 499         ODM_Write1Byte(pDM_Odm, REG_SYS_CLKR_8812A + 1, 0xf0);
 500         /*Disable 320M*/
 501         ODM_Write1Byte(pDM_Odm, REG_AFE_PLL_CTRL_8812A + 3, 0x8);
 502         /*Enable 320M*/
 503         ODM_Write1Byte(pDM_Odm, REG_AFE_PLL_CTRL_8812A + 3, 0xa);
 504         /*Enable clock*/
 505         ODM_Write1Byte(pDM_Odm, REG_SYS_CLKR_8812A + 1, 0xfc);
 506
 507
 508         /*Release Tx pause*/
 509         ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812A, 0);
 510
 511         /*Enable RX DMA path*/
 512         u1btmp = ODM_Read1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A);
 513         ODM_Write1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A, u1btmp & (~BIT2));
 514 #if DEV_BUS_TYPE == RT_PCI_INTERFACE
 515         /*Enable PCIe TxDMA*/
 516         ODM_Write1Byte(pDM_Odm, REG_PCIE_CTRL_REG_8812A + 1, 0);
 517 #endif
 518         /*Start Usb TxDMA*/
 519         RT_ENABLE_FUNC(Adapter, DF_TX_BIT);
 520 }
 521
 522 #endif
 523
 524
 525
 526 #endif
 527