drivers/net/wireless/rockchip_wlan/rtl8188eu/hal/OUTSRC/rtl8188e/odm_RegConfig8188E.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20
  21
  22
  23 #include "../odm_precomp.h"
  24
  25 #if (RTL8188E_SUPPORT == 1)
  26
  27 void
  28 odm_ConfigRFReg_8188E(
  29         IN      PDM_ODM_T                               pDM_Odm,
  30         IN      u4Byte                                  Addr,
  31         IN      u4Byte                                  Data,
  32         IN  ODM_RF_RADIO_PATH_E     RF_PATH,
  33         IN      u4Byte                              RegAddr
  34         )
  35 {
  36     if(Addr == 0xffe)
  37         {
  38                 #ifdef CONFIG_LONG_DELAY_ISSUE
  39                 ODM_sleep_ms(50);
  40                 #else
  41                 ODM_delay_ms(50);
  42                 #endif
  43         }
  44         else if (Addr == 0xfd)
  45         {
  46                 ODM_delay_ms(5);
  47         }
  48         else if (Addr == 0xfc)
  49         {
  50                 ODM_delay_ms(1);
  51         }
  52         else if (Addr == 0xfb)
  53         {
  54                 ODM_delay_us(50);
  55         }
  56         else if (Addr == 0xfa)
  57         {
  58                 ODM_delay_us(5);
  59         }
  60         else if (Addr == 0xf9)
  61         {
  62                 ODM_delay_us(1);
  63         }
  64         else
  65         {
  66                 ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
  67                 // Add 1us delay between BB/RF register setting.
  68                 ODM_delay_us(1);
  69         }
  70 }
  71
  72
  73 void
  74 odm_ConfigRF_RadioA_8188E(
  75         IN      PDM_ODM_T                               pDM_Odm,
  76         IN      u4Byte                                  Addr,
  77         IN      u4Byte                                  Data
  78         )
  79 {
  80         u4Byte  content = 0x1000; // RF_Content: radioa_txt
  81         u4Byte  maskforPhySet= (u4Byte)(content&0xE000);
  82
  83     odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet);
  84
  85     ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data));
  86 }
  87
  88 void
  89 odm_ConfigRF_RadioB_8188E(
  90         IN      PDM_ODM_T                               pDM_Odm,
  91         IN      u4Byte                                  Addr,
  92         IN      u4Byte                                  Data
  93         )
  94 {
  95         u4Byte  content = 0x1001; // RF_Content: radiob_txt
  96         u4Byte  maskforPhySet= (u4Byte)(content&0xE000);
  97
  98     odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet);
  99
 100         ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data));
 101
 102 }
 103
 104 void
 105 odm_ConfigMAC_8188E(
 106         IN      PDM_ODM_T       pDM_Odm,
 107         IN      u4Byte          Addr,
 108         IN      u1Byte          Data
 109         )
 110 {
 111         ODM_Write1Byte(pDM_Odm, Addr, Data);
 112         ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data));
 113 }
 114
 115 void
 116 odm_ConfigBB_AGC_8188E(
 117     IN  PDM_ODM_T       pDM_Odm,
 118     IN  u4Byte          Addr,
 119     IN  u4Byte          Bitmask,
 120     IN  u4Byte          Data
 121     )
 122 {
 123         ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
 124         // Add 1us delay between BB/RF register setting.
 125         ODM_delay_us(1);
 126
 127     ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data));
 128 }
 129
 130 void
 131 odm_ConfigBB_PHY_REG_PG_8188E(
 132         IN      PDM_ODM_T       pDM_Odm,
 133         IN      u4Byte          Band,
 134         IN      u4Byte          RfPath,
 135         IN      u4Byte          TxNum,
 136     IN  u4Byte          Addr,
 137     IN  u4Byte          Bitmask,
 138     IN  u4Byte          Data
 139     )
 140 {
 141         if (Addr == 0xfe){
 142                 #ifdef CONFIG_LONG_DELAY_ISSUE
 143                 ODM_sleep_ms(50);
 144                 #else
 145                 ODM_delay_ms(50);
 146                 #endif
 147         }
 148         else if (Addr == 0xfd){
 149                 ODM_delay_ms(5);
 150         }
 151         else if (Addr == 0xfc){
 152                 ODM_delay_ms(1);
 153         }
 154         else if (Addr == 0xfb){
 155                 ODM_delay_us(50);
 156         }
 157         else if (Addr == 0xfa){
 158                 ODM_delay_us(5);
 159         }
 160         else if (Addr == 0xf9){
 161                 ODM_delay_us(1);
 162         }
 163         else {
 164                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data));
 165
 166         #if     !(DM_ODM_SUPPORT_TYPE&ODM_AP)
 167                 PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data);
 168         #endif
 169         }
 170 }
 171
 172 void
 173 odm_ConfigBB_TXPWR_LMT_8188E(
 174         IN      PDM_ODM_T       pDM_Odm,
 175         IN      pu1Byte         Regulation,
 176         IN      pu1Byte         Band,
 177         IN      pu1Byte         Bandwidth,
 178         IN      pu1Byte         RateSection,
 179         IN      pu1Byte         RfPath,
 180         IN      pu1Byte         Channel,
 181         IN      pu1Byte         PowerLimit
 182     )
 183 {
 184 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
 185         PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band,
 186                 Bandwidth, RateSection, RfPath, Channel, PowerLimit);
 187 #elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
 188         PHY_SetTxPowerLimit(pDM_Odm->Adapter, Regulation, Band,
 189                 Bandwidth, RateSection, RfPath, Channel, PowerLimit);
 190 #endif
 191 }
 192
 193 void
 194 odm_ConfigBB_PHY_8188E(
 195         IN      PDM_ODM_T       pDM_Odm,
 196     IN  u4Byte          Addr,
 197     IN  u4Byte          Bitmask,
 198     IN  u4Byte          Data
 199     )
 200 {
 201         if (Addr == 0xfe){
 202                 #ifdef CONFIG_LONG_DELAY_ISSUE
 203                 ODM_sleep_ms(50);
 204                 #else
 205                 ODM_delay_ms(50);
 206                 #endif
 207         }
 208         else if (Addr == 0xfd){
 209                 ODM_delay_ms(5);
 210         }
 211         else if (Addr == 0xfc){
 212                 ODM_delay_ms(1);
 213         }
 214         else if (Addr == 0xfb){
 215                 ODM_delay_us(50);
 216         }
 217         else if (Addr == 0xfa){
 218                 ODM_delay_us(5);
 219         }
 220         else if (Addr == 0xf9){
 221                 ODM_delay_us(1);
 222         }
 223         else {
 224                 if (Addr == 0xa24)
 225                         pDM_Odm->RFCalibrateInfo.RegA24 = Data;
 226                 ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
 227
 228                 // Add 1us delay between BB/RF register setting.
 229                 ODM_delay_us(1);
 230         ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data));
 231         }
 232 }
 233 #endif
 234