1 /******************************************************************************
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3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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5 * This program is free software; you can redistribute it and/or modify it
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6 * under the terms of version 2 of the GNU General Public License as
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7 * published by the Free Software Foundation.
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9 * This program is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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14 * You should have received a copy of the GNU General Public License along with
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15 * this program; if not, write to the Free Software Foundation, Inc.,
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16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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19 ******************************************************************************/
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22 #include "../odm_precomp.h"
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26 /*---------------------------Define Local Constant---------------------------*/
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27 // 2010/04/25 MH Define the max tx power tracking tx agc power.
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28 #define ODM_TXPWRTRACK_MAX_IDX_88E 6
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30 /*---------------------------Define Local Constant---------------------------*/
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33 //3============================================================
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34 //3 Tx Power Tracking
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35 //3============================================================
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38 void setIqkMatrix_8188E(
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46 s4Byte ele_A=0, ele_D, ele_C=0, value32;
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48 ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22;
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50 //new element A = element D x X
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51 if((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G))
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53 if ((IqkResult_X & 0x00000200) != 0) //consider minus
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54 IqkResult_X = IqkResult_X | 0xFFFFFC00;
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55 ele_A = ((IqkResult_X * ele_D)>>8)&0x000003FF;
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57 //new element C = element D x Y
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58 if ((IqkResult_Y & 0x00000200) != 0)
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59 IqkResult_Y = IqkResult_Y | 0xFFFFFC00;
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60 ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF;
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62 //if (RFPath == ODM_RF_PATH_A)
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66 //wirte new elements A, C, D to regC80 and regC94, element B is always 0
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67 value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A;
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68 ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32);
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70 value32 = (ele_C&0x000003C0)>>6;
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71 ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32);
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73 value32 = ((IqkResult_X * ele_D)>>7)&0x01;
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74 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32);
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77 //wirte new elements A, C, D to regC88 and regC9C, element B is always 0
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78 value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A;
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79 ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32);
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81 value32 = (ele_C&0x000003C0)>>6;
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82 ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32);
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84 value32 = ((IqkResult_X * ele_D)>>7)&0x01;
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85 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32);
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97 ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]);
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98 ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00);
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99 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00);
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102 case ODM_RF_PATH_B:
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103 ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]);
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104 ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00);
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105 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00);
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113 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n",
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114 (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y));
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119 u1Byte DeltaThermalIndex,
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120 u1Byte ThermalValue,
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124 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
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125 PADAPTER Adapter = pDM_Odm->Adapter;
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126 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
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129 ODM_ResetIQKResult(pDM_Odm);
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131 #if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
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132 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
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134 PlatformAcquireMutex(&pHalData->mxChnlBwControl);
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136 PlatformAcquireSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK);
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138 #elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
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139 PlatformAcquireMutex(&pHalData->mxChnlBwControl);
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144 pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue;
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145 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
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146 PHY_IQCalibrate_8188E(pDM_Odm, FALSE);
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148 PHY_IQCalibrate_8188E(Adapter, FALSE);
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151 #if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
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152 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
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154 PlatformReleaseMutex(&pHalData->mxChnlBwControl);
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156 PlatformReleaseSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK);
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158 #elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
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159 PlatformReleaseMutex(&pHalData->mxChnlBwControl);
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164 /*-----------------------------------------------------------------------------
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165 * Function: odm_TxPwrTrackSetPwr88E()
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167 * Overview: 88E change all channel tx power accordign to flag.
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168 * OFDM & CCK are all different.
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178 * 04/23/2012 MHC Create Version 0.
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180 *---------------------------------------------------------------------------*/
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182 ODM_TxPwrTrackSetPwr88E(
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184 PWRTRACK_METHOD Method,
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186 u1Byte ChannelMappedIndex
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189 PADAPTER Adapter = pDM_Odm->Adapter;
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190 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
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191 u1Byte PwrTrackingLimit_OFDM = 30; //+0dB
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192 u1Byte PwrTrackingLimit_CCK= 28; //-2dB
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193 u1Byte TxRate = 0xFF;
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194 u1Byte Final_OFDM_Swing_Index = 0;
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195 u1Byte Final_CCK_Swing_Index = 0;
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199 if ( *(pDM_Odm->mp_mode) == 1)
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201 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE ))
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202 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
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203 PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx);
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204 #elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
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205 PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx);
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207 TxRate = MptToMgntRate(pMptCtx->MptRateIndex);
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213 u2Byte rate = *(pDM_Odm->pForcedDataRate);
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215 if(!rate) //auto rate
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217 if(pDM_Odm->TxRate != 0xFF)
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218 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
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219 TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate);
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220 #elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
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221 TxRate = HwRateToMRate(pDM_Odm->TxRate);
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226 TxRate = (u1Byte)rate;
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230 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>ODM_TxPwrTrackSetPwr8723B\n"));
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235 if((TxRate >= MGN_1M)&&(TxRate <= MGN_11M))
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236 PwrTrackingLimit_CCK = 28; //-2dB
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238 else if((TxRate >= MGN_6M)&&(TxRate <= MGN_48M))
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239 PwrTrackingLimit_OFDM= 36; //+3dB
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240 else if(TxRate == MGN_54M)
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241 PwrTrackingLimit_OFDM= 34; //+2dB
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244 else if((TxRate >= MGN_MCS0)&&(TxRate <= MGN_MCS2)) //QPSK/BPSK
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245 PwrTrackingLimit_OFDM= 38; //+4dB
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246 else if((TxRate >= MGN_MCS3)&&(TxRate <= MGN_MCS4)) //16QAM
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247 PwrTrackingLimit_OFDM= 36; //+3dB
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248 else if((TxRate >= MGN_MCS5)&&(TxRate <= MGN_MCS7)) //64QAM
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249 PwrTrackingLimit_OFDM= 34; //+2dB
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252 PwrTrackingLimit_OFDM = pDM_Odm->DefaultOfdmIndex; //Default OFDM index = 30
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254 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("TxRate=0x%x, PwrTrackingLimit=%d\n", TxRate, PwrTrackingLimit_OFDM));
\r
256 if (Method == TXAGC)
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258 u4Byte pwr = 0, TxAGC = 0;
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259 PADAPTER Adapter = pDM_Odm->Adapter;
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261 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = pDM_Odm->Absolute_OFDMSwingIdx[RFPath]; //Remnant index equal to aboslute compensate value.
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263 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr88E CH=%d\n", *(pDM_Odm->pChannel)));
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265 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE ))
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267 #if (MP_DRIVER == 1)
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268 if ( *(pDM_Odm->mp_mode) == 1)
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270 pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF);
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271 pwr += pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_A];
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272 PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr);
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273 TxAGC = (pwr<<16)|(pwr<<8)|(pwr);
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274 PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC);
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275 //RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr88E: CCK Tx-rf(A) Power = 0x%x\n", TxAGC));
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277 pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF);
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278 pwr += (pDM_Odm->BbSwingIdxOfdm[ODM_RF_PATH_A] - pDM_Odm->BbSwingIdxOfdmBase[RF_PATH_A]);
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279 TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr);
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280 PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
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281 PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
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282 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
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283 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
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284 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
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285 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
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286 //RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr88E: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC));
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291 //PHY_SetTxPowerLevel8188E(pDM_Odm->Adapter, *pDM_Odm->pChannel);
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292 pDM_Odm->Modify_TxAGC_Flag_PathA = TRUE;
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293 pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = TRUE;
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295 if (RFPath == ODM_RF_PATH_A)
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297 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK );
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298 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM );
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299 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 );
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305 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
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306 //PHY_RF6052SetCCKTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel));
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307 //PHY_RF6052SetOFDMTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel));
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311 else if (Method == BBSWING)
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313 Final_OFDM_Swing_Index = pDM_Odm->DefaultOfdmIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];
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314 Final_CCK_Swing_Index = pDM_Odm->DefaultCckIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];
\r
316 if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM)
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317 Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM;
\r
318 else if (Final_OFDM_Swing_Index < 0)
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319 Final_OFDM_Swing_Index = 0;
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321 if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE)
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322 Final_CCK_Swing_Index = CCK_TABLE_SIZE-1;
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323 else if (pDM_Odm->BbSwingIdxCck < 0)
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324 Final_CCK_Swing_Index = 0;
\r
326 // Adjust BB swing by OFDM IQ matrix
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327 if (RFPath == ODM_RF_PATH_A)
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329 setIqkMatrix_8188E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A,
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330 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],
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331 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);
\r
332 // Adjust BB swing by CCK filter coefficient
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333 if(!pDM_Odm->RFCalibrateInfo.bCCKinCH14){
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334 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][0]);
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335 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][1]);
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336 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][2]);
\r
337 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][3]);
\r
338 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][4]);
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339 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][5]);
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340 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][6]);
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341 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][7]);
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345 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][0]);
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346 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][1]);
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347 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][2]);
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348 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][3]);
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349 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][4]);
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350 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][5]);
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351 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][6]);
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352 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][7]);
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356 else if (Method == MIX_MODE)
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358 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("pDM_Odm->DefaultOfdmIndex=%d, pDM_Odm->DefaultCCKIndex=%d, pDM_Odm->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n",
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359 pDM_Odm->DefaultOfdmIndex, pDM_Odm->DefaultCckIndex, pDM_Odm->Absolute_OFDMSwingIdx[RFPath],RFPath ));
\r
361 Final_CCK_Swing_Index = pDM_Odm->DefaultCckIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];
\r
362 Final_OFDM_Swing_Index = pDM_Odm->DefaultOfdmIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];
\r
364 if(Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM ) //BBSwing higher then Limit
\r
366 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM;
\r
368 setIqkMatrix_8188E(pDM_Odm, PwrTrackingLimit_OFDM, ODM_RF_PATH_A,
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369 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],
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370 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);
\r
372 pDM_Odm->Modify_TxAGC_Flag_PathA = TRUE;
\r
374 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM );
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375 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 );
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377 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d \n", PwrTrackingLimit_OFDM, pDM_Odm->Remnant_OFDMSwingIdx[RFPath]));
\r
379 else if (Final_OFDM_Swing_Index < 0)
\r
381 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index ;
\r
383 setIqkMatrix_8188E(pDM_Odm, 0, ODM_RF_PATH_A,
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384 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],
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385 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);
\r
387 pDM_Odm->Modify_TxAGC_Flag_PathA = TRUE;
\r
389 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM );
\r
390 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 );
\r
392 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d \n", pDM_Odm->Remnant_OFDMSwingIdx[RFPath]));
\r
396 setIqkMatrix_8188E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A,
\r
397 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],
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398 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);
\r
400 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index));
\r
402 if(pDM_Odm->Modify_TxAGC_Flag_PathA) //If TxAGC has changed, reset TxAGC again
\r
404 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = 0;
\r
406 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM );
\r
407 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 );
\r
409 pDM_Odm->Modify_TxAGC_Flag_PathA = FALSE;
\r
411 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE \n"));
\r
415 if(Final_CCK_Swing_Index > PwrTrackingLimit_CCK)
\r
417 pDM_Odm->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK;
\r
419 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A CCK Over Limit , PwrTrackingLimit_CCK = %d , pDM_Odm->Remnant_CCKSwingIdx = %d \n", PwrTrackingLimit_CCK, pDM_Odm->Remnant_CCKSwingIdx));
\r
421 // Adjust BB swing by CCK filter coefficient
\r
423 if(!pDM_Odm->RFCalibrateInfo.bCCKinCH14)
\r
425 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][0]);
\r
426 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][1]);
\r
427 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][2]);
\r
428 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][3]);
\r
429 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][4]);
\r
430 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][5]);
\r
431 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][6]);
\r
432 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][7]);
\r
436 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][0]);
\r
437 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][1]);
\r
438 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][2]);
\r
439 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][3]);
\r
440 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][4]);
\r
441 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][5]);
\r
442 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][6]);
\r
443 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][7]);
\r
446 pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = TRUE;
\r
448 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK );
\r
451 else if(Final_CCK_Swing_Index < 0) // Lowest CCK Index = 0
\r
453 pDM_Odm->Remnant_CCKSwingIdx = Final_CCK_Swing_Index;
\r
455 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A CCK Under Limit , PwrTrackingLimit_CCK = %d , pDM_Odm->Remnant_CCKSwingIdx = %d \n", 0, pDM_Odm->Remnant_CCKSwingIdx));
\r
457 if(!pDM_Odm->RFCalibrateInfo.bCCKinCH14)
\r
459 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[0][0]);
\r
460 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[0][1]);
\r
461 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[0][2]);
\r
462 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[0][3]);
\r
463 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[0][4]);
\r
464 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[0][5]);
\r
465 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[0][6]);
\r
466 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[0][7]);
\r
470 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[0][0]);
\r
471 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[0][1]);
\r
472 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[0][2]);
\r
473 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[0][3]);
\r
474 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[0][4]);
\r
475 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[0][5]);
\r
476 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[0][6]);
\r
477 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[0][7]);
\r
480 pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = TRUE;
\r
482 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK );
\r
487 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A CCK Compensate with BBSwing , Final_CCK_Swing_Index = %d \n", Final_CCK_Swing_Index));
\r
489 if(!pDM_Odm->RFCalibrateInfo.bCCKinCH14)
\r
491 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][0]);
\r
492 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][1]);
\r
493 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][2]);
\r
494 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][3]);
\r
495 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][4]);
\r
496 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][5]);
\r
497 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][6]);
\r
498 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][7]);
\r
502 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][0]);
\r
503 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][1]);
\r
504 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][2]);
\r
505 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][3]);
\r
506 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][4]);
\r
507 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][5]);
\r
508 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][6]);
\r
509 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][7]);
\r
512 if(pDM_Odm->Modify_TxAGC_Flag_PathA_CCK) //If TxAGC has changed, reset TxAGC again
\r
514 pDM_Odm->Remnant_CCKSwingIdx = 0;
\r
515 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK );
\r
516 pDM_Odm->Modify_TxAGC_Flag_PathA_CCK= FALSE;
\r
518 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A pDM_Odm->Modify_TxAGC_Flag_CCK = FALSE \n"));
\r
526 } // odm_TxPwrTrackSetPwr88E
\r
529 GetDeltaSwingTable_8188E(
\r
530 IN PDM_ODM_T pDM_Odm,
\r
531 OUT pu1Byte *TemperatureUP_A,
\r
532 OUT pu1Byte *TemperatureDOWN_A,
\r
533 OUT pu1Byte *TemperatureUP_B,
\r
534 OUT pu1Byte *TemperatureDOWN_B
\r
537 *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E;
\r
538 *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E;
\r
539 *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E;
\r
540 *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E;
\r
543 void ConfigureTxpowerTrack_8188E(
\r
544 PTXPWRTRACK_CFG pConfig
\r
547 pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE;
\r
548 pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE;
\r
549 pConfig->Threshold_IQK = IQK_THRESHOLD;
\r
550 pConfig->AverageThermalNum = AVG_THERMAL_NUM_88E;
\r
551 pConfig->RfPathCount = MAX_PATH_NUM_8188E;
\r
552 pConfig->ThermalRegAddr = RF_T_METER_88E;
\r
554 pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr88E;
\r
555 pConfig->DoIQK = DoIQK_8188E;
\r
556 pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8188E;
\r
557 pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8188E;
\r
561 #define MAX_TOLERANCE 5
\r
562 #define IQK_DELAY_TIME 1 //ms
\r
564 u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
\r
565 phy_PathA_IQK_8188E(
\r
566 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
567 IN PDM_ODM_T pDM_Odm,
\r
569 IN PADAPTER pAdapter,
\r
571 IN BOOLEAN configPathB
\r
574 u4Byte regEAC, regE94, regE9C, regEA4;
\r
575 u1Byte result = 0x00;
\r
576 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
577 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
578 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
579 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
\r
581 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
582 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
\r
585 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n"));
\r
588 //path-A IQK setting
\r
589 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n"));
\r
590 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c);
\r
591 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c);
\r
592 ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214032a);
\r
593 ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000);
\r
595 //LO calibration setting
\r
596 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));
\r
597 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);
\r
599 //One shot, path A LOK & IQK
\r
600 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));
\r
601 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
\r
602 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
\r
605 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E));
\r
606 //PlatformStallExecution(IQK_DELAY_TIME_88E*1000);
\r
607 ODM_delay_ms(IQK_DELAY_TIME_88E);
\r
610 regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);
\r
611 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));
\r
612 regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord);
\r
613 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94));
\r
614 regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord);
\r
615 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C));
\r
616 regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord);
\r
617 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4));
\r
619 if(!(regEAC & BIT28) &&
\r
620 (((regE94 & 0x03FF0000)>>16) != 0x142) &&
\r
621 (((regE9C & 0x03FF0000)>>16) != 0x42) )
\r
623 else //if Tx not OK, ignore Rx
\r
627 if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK
\r
628 (((regEA4 & 0x03FF0000)>>16) != 0x132) &&
\r
629 (((regEAC & 0x03FF0000)>>16) != 0x36))
\r
632 RT_DISP(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n"));
\r
640 u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
\r
642 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
643 IN PDM_ODM_T pDM_Odm,
\r
645 IN PADAPTER pAdapter,
\r
647 IN BOOLEAN configPathB
\r
650 u4Byte regEAC, regE94, regE9C, regEA4, u4tmp;
\r
651 u1Byte result = 0x00;
\r
652 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
653 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
654 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
655 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
\r
657 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
658 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
\r
661 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n"));
\r
663 //1 Get TXIMR setting
\r
664 //modify RXIQK mode table
\r
665 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n"));
\r
666 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
\r
667 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 );
\r
668 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 );
\r
669 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f );
\r
670 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf117B );
\r
671 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
\r
674 ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
\r
675 ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800);
\r
677 //path-A IQK setting
\r
678 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c);
\r
679 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c);
\r
680 ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160804);
\r
681 ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000);
\r
683 //LO calibration setting
\r
684 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));
\r
685 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
\r
687 //One shot, path A LOK & IQK
\r
688 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));
\r
689 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
\r
690 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
\r
693 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E));
\r
694 //PlatformStallExecution(IQK_DELAY_TIME_88E*1000);
\r
695 ODM_delay_ms(IQK_DELAY_TIME_88E);
\r
699 regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);
\r
700 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));
\r
701 regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord);
\r
702 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94));
\r
703 regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord);
\r
704 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C));
\r
706 if(!(regEAC & BIT28) &&
\r
707 (((regE94 & 0x03FF0000)>>16) != 0x142) &&
\r
708 (((regE9C & 0x03FF0000)>>16) != 0x42) )
\r
710 else //if Tx not OK, ignore Rx
\r
713 u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16);
\r
714 ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp);
\r
715 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp));
\r
719 //modify RXIQK mode table
\r
720 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n"));
\r
721 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
\r
722 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 );
\r
723 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 );
\r
724 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f );
\r
725 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ffa );
\r
726 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
\r
729 ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
\r
731 //path-A IQK setting
\r
732 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x30008c1c);
\r
733 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1c);
\r
734 ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c05);
\r
735 ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160c05);
\r
737 //LO calibration setting
\r
738 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));
\r
739 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);
\r
741 //One shot, path A LOK & IQK
\r
742 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));
\r
743 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
\r
744 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
\r
747 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E));
\r
748 //PlatformStallExecution(IQK_DELAY_TIME_88E*1000);
\r
749 ODM_delay_ms(IQK_DELAY_TIME_88E);
\r
752 regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);
\r
753 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));
\r
754 regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord);
\r
755 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94));
\r
756 regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord);
\r
757 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C));
\r
758 regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord);
\r
759 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4));
\r
762 if(!(regEAC & BIT28) &&
\r
763 (((regE94 & 0x03FF0000)>>16) != 0x142) &&
\r
764 (((regE9C & 0x03FF0000)>>16) != 0x42) )
\r
766 else //if Tx not OK, ignore Rx
\r
770 if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK
\r
771 (((regEA4 & 0x03FF0000)>>16) != 0x132) &&
\r
772 (((regEAC & 0x03FF0000)>>16) != 0x36))
\r
775 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK fail!!\n"));
\r
782 u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
\r
783 phy_PathB_IQK_8188E(
\r
784 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
785 IN PDM_ODM_T pDM_Odm
\r
787 IN PADAPTER pAdapter
\r
791 u4Byte regEAC, regEB4, regEBC, regEC4, regECC;
\r
792 u1Byte result = 0x00;
\r
793 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
794 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
795 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
796 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
\r
798 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
799 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
\r
802 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n"));
\r
804 //One shot, path B LOK & IQK
\r
805 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));
\r
806 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000002);
\r
807 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000000);
\r
810 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_88E));
\r
811 //PlatformStallExecution(IQK_DELAY_TIME_88E*1000);
\r
812 ODM_delay_ms(IQK_DELAY_TIME_88E);
\r
815 regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);
\r
816 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));
\r
817 regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord);
\r
818 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb4 = 0x%x\n", regEB4));
\r
819 regEBC= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord);
\r
820 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xebc = 0x%x\n", regEBC));
\r
821 regEC4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord);
\r
822 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xec4 = 0x%x\n", regEC4));
\r
823 regECC= ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord);
\r
824 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xecc = 0x%x\n", regECC));
\r
826 if(!(regEAC & BIT31) &&
\r
827 (((regEB4 & 0x03FF0000)>>16) != 0x142) &&
\r
828 (((regEBC & 0x03FF0000)>>16) != 0x42))
\r
833 if(!(regEAC & BIT30) &&
\r
834 (((regEC4 & 0x03FF0000)>>16) != 0x132) &&
\r
835 (((regECC & 0x03FF0000)>>16) != 0x36))
\r
838 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n"));
\r
846 _PHY_PathAFillIQKMatrix(
\r
847 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
848 IN PDM_ODM_T pDM_Odm,
\r
850 IN PADAPTER pAdapter,
\r
853 IN s4Byte result[][8],
\r
854 IN u1Byte final_candidate,
\r
858 u4Byte Oldval_0, X, TX0_A, reg;
\r
860 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
861 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
862 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
863 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
\r
865 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
866 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
\r
869 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed"));
\r
871 if(final_candidate == 0xFF)
\r
876 Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
\r
878 X = result[final_candidate][0];
\r
879 if ((X & 0x00000200) != 0)
\r
880 X = X | 0xFFFFFC00;
\r
881 TX0_A = (X * Oldval_0) >> 8;
\r
882 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0));
\r
883 ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A);
\r
885 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1));
\r
887 Y = result[final_candidate][1];
\r
888 if ((Y & 0x00000200) != 0)
\r
889 Y = Y | 0xFFFFFC00;
\r
892 TX0_C = (Y * Oldval_0) >> 8;
\r
893 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C));
\r
894 ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6));
\r
895 ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F));
\r
897 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1));
\r
901 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathAFillIQKMatrix only Tx OK\n"));
\r
905 reg = result[final_candidate][2];
\r
906 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
\r
907 if( RTL_ABS(reg ,0x100) >= 16)
\r
910 ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg);
\r
912 reg = result[final_candidate][3] & 0x3F;
\r
913 ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg);
\r
915 reg = (result[final_candidate][3] >> 6) & 0xF;
\r
916 ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg);
\r
921 _PHY_PathBFillIQKMatrix(
\r
922 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
923 IN PDM_ODM_T pDM_Odm,
\r
925 IN PADAPTER pAdapter,
\r
928 IN s4Byte result[][8],
\r
929 IN u1Byte final_candidate,
\r
930 IN BOOLEAN bTxOnly //do Tx only
\r
933 u4Byte Oldval_1, X, TX1_A, reg;
\r
935 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
936 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
937 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
938 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
\r
940 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
941 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
\r
944 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed"));
\r
946 if(final_candidate == 0xFF)
\r
951 Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
\r
953 X = result[final_candidate][4];
\r
954 if ((X & 0x00000200) != 0)
\r
955 X = X | 0xFFFFFC00;
\r
956 TX1_A = (X * Oldval_1) >> 8;
\r
957 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A));
\r
958 ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A);
\r
960 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1));
\r
962 Y = result[final_candidate][5];
\r
963 if ((Y & 0x00000200) != 0)
\r
964 Y = Y | 0xFFFFFC00;
\r
966 TX1_C = (Y * Oldval_1) >> 8;
\r
967 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C));
\r
968 ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6));
\r
969 ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F));
\r
971 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1));
\r
976 reg = result[final_candidate][6];
\r
977 ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg);
\r
979 reg = result[final_candidate][7] & 0x3F;
\r
980 ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg);
\r
982 reg = (result[final_candidate][7] >> 6) & 0xF;
\r
983 ODM_SetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, 0x0000F000, reg);
\r
988 // 2011/07/26 MH Add an API for testing IQK fail case.
\r
990 // MP Already declare in odm.c
\r
991 #if !(DM_ODM_SUPPORT_TYPE & ODM_WIN)
\r
993 ODM_CheckPowerStatus(
\r
994 IN PADAPTER Adapter)
\r
997 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
998 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
\r
999 RT_RF_POWER_STATE rtState;
\r
1000 PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
\r
1002 // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence.
\r
1003 if (pMgntInfo->init_adpt_in_progress == TRUE)
\r
1005 ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter"));
\r
1010 // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK.
\r
1012 Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState));
\r
1013 if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff)
\r
1015 ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n",
\r
1016 Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState));
\r
1025 _PHY_SaveADDARegisters(
\r
1026 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1027 IN PDM_ODM_T pDM_Odm,
\r
1029 IN PADAPTER pAdapter,
\r
1031 IN pu4Byte ADDAReg,
\r
1032 IN pu4Byte ADDABackup,
\r
1033 IN u4Byte RegisterNum
\r
1037 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1038 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
1039 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
1040 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
\r
1042 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
1043 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
\r
1046 if (ODM_CheckPowerStatus(pAdapter) == FALSE)
\r
1050 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n"));
\r
1051 for( i = 0 ; i < RegisterNum ; i++){
\r
1052 ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord);
\r
1058 _PHY_SaveMACRegisters(
\r
1059 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1060 IN PDM_ODM_T pDM_Odm,
\r
1062 IN PADAPTER pAdapter,
\r
1064 IN pu4Byte MACReg,
\r
1065 IN pu4Byte MACBackup
\r
1069 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1070 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
1071 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
1072 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
\r
1074 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
1075 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
\r
1078 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n"));
\r
1079 for( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){
\r
1080 MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]);
\r
1082 MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]);
\r
1088 _PHY_ReloadADDARegisters(
\r
1089 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1090 IN PDM_ODM_T pDM_Odm,
\r
1092 IN PADAPTER pAdapter,
\r
1094 IN pu4Byte ADDAReg,
\r
1095 IN pu4Byte ADDABackup,
\r
1096 IN u4Byte RegiesterNum
\r
1100 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1101 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
1102 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
1103 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
\r
1105 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
1106 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
\r
1110 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n"));
\r
1111 for(i = 0 ; i < RegiesterNum; i++)
\r
1113 ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]);
\r
1118 _PHY_ReloadMACRegisters(
\r
1119 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1120 IN PDM_ODM_T pDM_Odm,
\r
1122 IN PADAPTER pAdapter,
\r
1124 IN pu4Byte MACReg,
\r
1125 IN pu4Byte MACBackup
\r
1129 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1130 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
1131 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
1132 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
\r
1134 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
1135 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
\r
1138 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n"));
\r
1139 for(i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){
\r
1140 ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]);
\r
1142 ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]);
\r
1148 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1149 IN PDM_ODM_T pDM_Odm,
\r
1151 IN PADAPTER pAdapter,
\r
1153 IN pu4Byte ADDAReg,
\r
1154 IN BOOLEAN isPathAOn,
\r
1160 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1161 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
1162 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
1163 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
\r
1165 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
1166 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
\r
1169 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n"));
\r
1171 pathOn = isPathAOn ? 0x04db25a4 : 0x0b1b25a4;
\r
1172 if(FALSE == is2T){
\r
1173 pathOn = 0x0bdb25a0;
\r
1174 ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x0b1b25a0);
\r
1177 ODM_SetBBReg(pDM_Odm,ADDAReg[0], bMaskDWord, pathOn);
\r
1180 for( i = 1 ; i < IQK_ADDA_REG_NUM ; i++){
\r
1181 ODM_SetBBReg(pDM_Odm,ADDAReg[i], bMaskDWord, pathOn);
\r
1187 _PHY_MACSettingCalibration(
\r
1188 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1189 IN PDM_ODM_T pDM_Odm,
\r
1191 IN PADAPTER pAdapter,
\r
1193 IN pu4Byte MACReg,
\r
1194 IN pu4Byte MACBackup
\r
1198 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1199 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
1200 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
1201 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
\r
1203 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
1204 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
\r
1207 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n"));
\r
1209 ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F);
\r
1211 for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){
\r
1212 ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3)));
\r
1214 ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5)));
\r
1219 _PHY_PathAStandBy(
\r
1220 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1221 IN PDM_ODM_T pDM_Odm
\r
1223 IN PADAPTER pAdapter
\r
1227 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1228 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
1229 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
1230 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
\r
1232 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
1233 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
\r
1236 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n"));
\r
1238 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x0);
\r
1239 ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000);
\r
1240 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
\r
1244 _PHY_PIModeSwitch(
\r
1245 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1246 IN PDM_ODM_T pDM_Odm,
\r
1248 IN PADAPTER pAdapter,
\r
1254 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1255 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
1256 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
1257 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
\r
1259 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
1260 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
\r
1263 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI")));
\r
1265 mode = PIMode ? 0x01000100 : 0x01000000;
\r
1266 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode);
\r
1267 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode);
\r
1271 phy_SimularityCompare_8188E(
\r
1272 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1273 IN PDM_ODM_T pDM_Odm,
\r
1275 IN PADAPTER pAdapter,
\r
1277 IN s4Byte result[][8],
\r
1282 u4Byte i, j, diff, SimularityBitMap, bound = 0;
\r
1283 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1284 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
1285 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
1286 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
\r
1288 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
1289 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
\r
1292 u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B
\r
1293 BOOLEAN bResult = TRUE;
\r
1294 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1295 BOOLEAN is2T = IS_92C_SERIAL( pHalData->VersionID);
\r
1305 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8188E c1 %d c2 %d!!!\n", c1, c2));
\r
1308 SimularityBitMap = 0;
\r
1310 for( i = 0; i < bound; i++ )
\r
1312 diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]);
\r
1313 if (diff > MAX_TOLERANCE)
\r
1315 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8188E differnece overflow index %d compare1 0x%x compare2 0x%x!!!\n", i, result[c1][i], result[c2][i]));
\r
1317 if((i == 2 || i == 6) && !SimularityBitMap)
\r
1319 if(result[c1][i]+result[c1][i+1] == 0)
\r
1320 final_candidate[(i/4)] = c2;
\r
1321 else if (result[c2][i]+result[c2][i+1] == 0)
\r
1322 final_candidate[(i/4)] = c1;
\r
1324 SimularityBitMap = SimularityBitMap|(1<<i);
\r
1327 SimularityBitMap = SimularityBitMap|(1<<i);
\r
1331 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8188E SimularityBitMap %d !!!\n", SimularityBitMap));
\r
1333 if ( SimularityBitMap == 0)
\r
1335 for( i = 0; i < (bound/4); i++ )
\r
1337 if(final_candidate[i] != 0xFF)
\r
1339 for( j = i*4; j < (i+1)*4-2; j++)
\r
1340 result[3][j] = result[final_candidate[i]][j];
\r
1346 else if (!(SimularityBitMap & 0x0F)) //path A OK
\r
1348 for(i = 0; i < 4; i++)
\r
1349 result[3][i] = result[c1][i];
\r
1352 else if (!(SimularityBitMap & 0xF0) && is2T) //path B OK
\r
1354 for(i = 4; i < 8; i++)
\r
1355 result[3][i] = result[c1][i];
\r
1366 phy_IQCalibrate_8188E(
\r
1367 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1368 IN PDM_ODM_T pDM_Odm,
\r
1370 IN PADAPTER pAdapter,
\r
1372 IN s4Byte result[][8],
\r
1377 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1378 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
1379 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
1380 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
\r
1382 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
1383 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
\r
1387 u1Byte PathAOK=0, PathBOK=0;
\r
1388 u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = {
\r
1389 rFPGA0_XCD_SwitchControl, rBlue_Tooth,
\r
1390 rRx_Wait_CCA, rTx_CCK_RFON,
\r
1391 rTx_CCK_BBON, rTx_OFDM_RFON,
\r
1392 rTx_OFDM_BBON, rTx_To_Rx,
\r
1393 rTx_To_Tx, rRx_CCK,
\r
1394 rRx_OFDM, rRx_Wait_RIFS,
\r
1395 rRx_TO_Rx, rStandby,
\r
1396 rSleep, rPMPD_ANAEN };
\r
1397 u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = {
\r
1398 REG_TXPAUSE, REG_BCN_CTRL,
\r
1399 REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
\r
1401 //since 92C & 92D have the different define in IQK_BB_REG
\r
1402 u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
\r
1403 rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar,
\r
1404 rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB,
\r
1405 rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE,
\r
1406 rFPGA0_XB_RFInterfaceOE, rCCK0_AFESetting
\r
1409 u4Byte retryCount = 2;
\r
1411 if ( *(pDM_Odm->mp_mode) == 1)
\r
1414 // Note: IQ calibration must be performed after loading
\r
1415 // PHY_REG.txt , and radio_a, radio_b.txt
\r
1419 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
\r
1421 if(pDM_Odm->priv->pshare->rf_ft_var.mp_specific)
\r
1429 // bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord);
\r
1430 // RT_DISP(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue));
\r
1432 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));
\r
1434 // Save ADDA parameters, turn Path A ADDA on
\r
1435 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1436 _PHY_SaveADDARegisters(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
\r
1437 _PHY_SaveMACRegisters(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
\r
1438 _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
\r
1440 _PHY_SaveADDARegisters(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
\r
1441 _PHY_SaveMACRegisters(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
\r
1442 _PHY_SaveADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
\r
1445 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));
\r
1447 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1449 _PHY_PathADDAOn(pAdapter, ADDA_REG, TRUE, is2T);
\r
1451 _PHY_PathADDAOn(pDM_Odm, ADDA_REG, TRUE, is2T);
\r
1457 pDM_Odm->RFCalibrateInfo.bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8));
\r
1460 if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){
\r
1461 // Switch BB to PI mode to do IQ Calibration.
\r
1462 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1463 _PHY_PIModeSwitch(pAdapter, TRUE);
\r
1465 _PHY_PIModeSwitch(pDM_Odm, TRUE);
\r
1471 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1472 _PHY_MACSettingCalibration(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
\r
1474 _PHY_MACSettingCalibration(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
\r
1478 //ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00);
\r
1479 ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, 0x0f000000, 0xf);
\r
1480 ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600);
\r
1481 ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4);
\r
1482 ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);
\r
1485 ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01);
\r
1486 ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01);
\r
1487 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00);
\r
1488 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00);
\r
1493 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000);
\r
1494 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000);
\r
1499 ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000);
\r
1503 ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x0f600000);
\r
1506 // IQ calibration setting
\r
1507 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n"));
\r
1508 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
\r
1509 ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
\r
1510 ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800);
\r
1512 for(i = 0 ; i < retryCount ; i++){
\r
1513 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1514 PathAOK = phy_PathA_IQK_8188E(pAdapter, is2T);
\r
1516 PathAOK = phy_PathA_IQK_8188E(pDM_Odm, is2T);
\r
1518 // if(PathAOK == 0x03){
\r
1519 if(PathAOK == 0x01){
\r
1520 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n"));
\r
1521 result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
\r
1522 result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
\r
1526 else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK
\r
1528 RT_DISP(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n"));
\r
1530 result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
\r
1531 result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
\r
1536 for(i = 0 ; i < retryCount ; i++){
\r
1537 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1538 PathAOK = phy_PathA_RxIQK(pAdapter, is2T);
\r
1540 PathAOK = phy_PathA_RxIQK(pDM_Odm, is2T);
\r
1542 if(PathAOK == 0x03){
\r
1543 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n"));
\r
1544 // result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
\r
1545 // result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
\r
1546 result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
\r
1547 result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
\r
1552 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n"));
\r
1556 if(0x00 == PathAOK){
\r
1557 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n"));
\r
1561 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1562 _PHY_PathAStandBy(pAdapter);
\r
1564 // Turn Path B ADDA on
\r
1565 _PHY_PathADDAOn(pAdapter, ADDA_REG, FALSE, is2T);
\r
1567 _PHY_PathAStandBy(pDM_Odm);
\r
1569 // Turn Path B ADDA on
\r
1570 _PHY_PathADDAOn(pDM_Odm, ADDA_REG, FALSE, is2T);
\r
1573 for(i = 0 ; i < retryCount ; i++){
\r
1574 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1575 PathBOK = phy_PathB_IQK_8188E(pAdapter);
\r
1577 PathBOK = phy_PathB_IQK_8188E(pDM_Odm);
\r
1579 if(PathBOK == 0x03){
\r
1580 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK Success!!\n"));
\r
1581 result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16;
\r
1582 result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16;
\r
1583 result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord)&0x3FF0000)>>16;
\r
1584 result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord)&0x3FF0000)>>16;
\r
1587 else if (i == (retryCount - 1) && PathBOK == 0x01) //Tx IQK OK
\r
1589 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Only Tx IQK Success!!\n"));
\r
1590 result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16;
\r
1591 result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16;
\r
1595 if(0x00 == PathBOK){
\r
1596 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n"));
\r
1600 //Back to BB mode, load original value
\r
1601 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n"));
\r
1602 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0);
\r
1606 if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){
\r
1607 // Switch back BB to SI mode after finish IQ Calibration.
\r
1608 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1609 _PHY_PIModeSwitch(pAdapter, FALSE);
\r
1611 _PHY_PIModeSwitch(pDM_Odm, FALSE);
\r
1614 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1616 // Reload ADDA power saving parameters
\r
1617 _PHY_ReloadADDARegisters(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
\r
1619 // Reload MAC parameters
\r
1620 _PHY_ReloadMACRegisters(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
\r
1622 _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
\r
1624 // Reload ADDA power saving parameters
\r
1625 _PHY_ReloadADDARegisters(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);
\r
1627 // Reload MAC parameters
\r
1628 _PHY_ReloadMACRegisters(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);
\r
1630 _PHY_ReloadADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
\r
1634 // Restore RX initial gain
\r
1635 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3);
\r
1637 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3);
\r
1640 //load 0xe30 IQC default value
\r
1641 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
\r
1642 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
\r
1645 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8188E() <==\n"));
\r
1651 phy_LCCalibrate_8188E(
\r
1652 IN PDM_ODM_T pDM_Odm,
\r
1657 u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal;
\r
1658 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1659 PADAPTER pAdapter = pDM_Odm->Adapter;
\r
1661 //Check continuous TX and Packet TX
\r
1662 tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03);
\r
1664 if((tmpReg&0x70) != 0) //Deal with contisuous TX case
\r
1665 ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg&0x8F); //disable all continuous TX
\r
1666 else // Deal with Packet TX case
\r
1667 ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); // block all queues
\r
1669 if((tmpReg&0x70) != 0)
\r
1671 //1. Read original RF mode
\r
1673 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1674 RF_Amode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, bMask12Bits);
\r
1678 RF_Bmode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_AC, bMask12Bits);
\r
1680 RF_Amode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits);
\r
1684 RF_Bmode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits);
\r
1687 //2. Set RF mode = standby mode
\r
1689 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000);
\r
1693 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000);
\r
1696 //3. Read RF reg18
\r
1697 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1698 LC_Cal = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits);
\r
1700 LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits);
\r
1703 //4. Set LC calibration begin bit15
\r
1704 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000);
\r
1706 ODM_delay_ms(100);
\r
1709 //Restore original situation
\r
1710 if((tmpReg&0x70) != 0) //Deal with contisuous TX case
\r
1713 ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg);
\r
1714 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, RF_Amode);
\r
1718 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode);
\r
1720 else // Deal with Packet TX case
\r
1722 ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00);
\r
1726 //Analog Pre-distortion calibration
\r
1727 #define APK_BB_REG_NUM 8
\r
1728 #define APK_CURVE_REG_NUM 4
\r
1729 #define PATH_NUM 2
\r
1732 phy_APCalibrate_8188E(
\r
1733 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1734 IN PDM_ODM_T pDM_Odm,
\r
1736 IN PADAPTER pAdapter,
\r
1742 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1743 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
1744 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
1745 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
\r
1747 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
1748 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
\r
1751 u4Byte regD[PATH_NUM];
\r
1752 u4Byte tmpReg, index, offset, apkbound;
\r
1753 u1Byte path, i, pathbound = PATH_NUM;
\r
1754 u4Byte BB_backup[APK_BB_REG_NUM];
\r
1755 u4Byte BB_REG[APK_BB_REG_NUM] = {
\r
1756 rFPGA1_TxBlock, rOFDM0_TRxPathEnable,
\r
1757 rFPGA0_RFMOD, rOFDM0_TRMuxPar,
\r
1758 rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW,
\r
1759 rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE };
\r
1760 u4Byte BB_AP_MODE[APK_BB_REG_NUM] = {
\r
1761 0x00000020, 0x00a05430, 0x02040000,
\r
1762 0x000800e4, 0x00204000 };
\r
1763 u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = {
\r
1764 0x00000020, 0x00a05430, 0x02040000,
\r
1765 0x000800e4, 0x22204000 };
\r
1767 u4Byte AFE_backup[IQK_ADDA_REG_NUM];
\r
1768 u4Byte AFE_REG[IQK_ADDA_REG_NUM] = {
\r
1769 rFPGA0_XCD_SwitchControl, rBlue_Tooth,
\r
1770 rRx_Wait_CCA, rTx_CCK_RFON,
\r
1771 rTx_CCK_BBON, rTx_OFDM_RFON,
\r
1772 rTx_OFDM_BBON, rTx_To_Rx,
\r
1773 rTx_To_Tx, rRx_CCK,
\r
1774 rRx_OFDM, rRx_Wait_RIFS,
\r
1775 rRx_TO_Rx, rStandby,
\r
1776 rSleep, rPMPD_ANAEN };
\r
1778 u4Byte MAC_backup[IQK_MAC_REG_NUM];
\r
1779 u4Byte MAC_REG[IQK_MAC_REG_NUM] = {
\r
1780 REG_TXPAUSE, REG_BCN_CTRL,
\r
1781 REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
\r
1783 u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
\r
1784 {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c},
\r
1785 {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e}
\r
1788 u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
\r
1789 {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings
\r
1790 {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c}
\r
1793 u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {
\r
1794 {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d},
\r
1795 {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050}
\r
1798 u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {
\r
1799 {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings
\r
1800 {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}
\r
1803 u4Byte AFE_on_off[PATH_NUM] = {
\r
1804 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on
\r
1806 u4Byte APK_offset[PATH_NUM] = {
\r
1807 rConfig_AntA, rConfig_AntB};
\r
1809 u4Byte APK_normal_offset[PATH_NUM] = {
\r
1810 rConfig_Pmpd_AntA, rConfig_Pmpd_AntB};
\r
1812 u4Byte APK_value[PATH_NUM] = {
\r
1813 0x92fc0000, 0x12fc0000};
\r
1815 u4Byte APK_normal_value[PATH_NUM] = {
\r
1816 0x92680000, 0x12680000};
\r
1818 s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = {
\r
1819 {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
\r
1820 {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
\r
1821 {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
\r
1822 {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6},
\r
1823 {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0}
\r
1826 u4Byte APK_normal_setting_value_1[13] = {
\r
1827 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28,
\r
1828 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3,
\r
1829 0x12680000, 0x00880000, 0x00880000
\r
1832 u4Byte APK_normal_setting_value_2[16] = {
\r
1833 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3,
\r
1834 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025,
\r
1835 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008,
\r
1839 u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a
\r
1840 // u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM];
\r
1842 s4Byte BB_offset, delta_V, delta_offset;
\r
1844 #if MP_DRIVER == 1
\r
1845 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
1846 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
\r
1848 PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx);
\r
1851 if ( *(pDM_Odm->mp_mode) == 1)
\r
1853 pMptCtx->APK_bound[0] = 45;
\r
1854 pMptCtx->APK_bound[1] = 52;
\r
1858 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta));
\r
1859 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R")));
\r
1863 //2 FOR NORMAL CHIP SETTINGS
\r
1865 // Temporarily do not allow normal driver to do the following settings because these offset
\r
1866 // and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal
\r
1867 // will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the
\r
1868 // root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31.
\r
1869 //#if MP_DRIVER != 1
\r
1870 if (*(pDM_Odm->mp_mode) != 1)
\r
1873 //settings adjust for normal chip
\r
1874 for(index = 0; index < PATH_NUM; index ++)
\r
1876 APK_offset[index] = APK_normal_offset[index];
\r
1877 APK_value[index] = APK_normal_value[index];
\r
1878 AFE_on_off[index] = 0x6fdb25a4;
\r
1881 for(index = 0; index < APK_BB_REG_NUM; index ++)
\r
1883 for(path = 0; path < pathbound; path++)
\r
1885 APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index];
\r
1886 APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index];
\r
1888 BB_AP_MODE[index] = BB_normal_AP_MODE[index];
\r
1893 //save BB default value
\r
1894 for(index = 0; index < APK_BB_REG_NUM ; index++)
\r
1896 if(index == 0) //skip
\r
1898 BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord);
\r
1901 //save MAC default value
\r
1902 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1903 _PHY_SaveMACRegisters(pAdapter, MAC_REG, MAC_backup);
\r
1905 //save AFE default value
\r
1906 _PHY_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
\r
1908 _PHY_SaveMACRegisters(pDM_Odm, MAC_REG, MAC_backup);
\r
1910 //save AFE default value
\r
1911 _PHY_SaveADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
\r
1914 for(path = 0; path < pathbound; path++)
\r
1918 if(path == ODM_RF_PATH_A)
\r
1921 //load APK setting
\r
1923 offset = rPdp_AntA;
\r
1924 for(index = 0; index < 11; index ++)
\r
1926 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);
\r
1927 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
\r
1932 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);
\r
1934 offset = rConfig_AntA;
\r
1935 for(; index < 13; index ++)
\r
1937 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);
\r
1938 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
\r
1944 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000);
\r
1947 offset = rPdp_AntA;
\r
1948 for(index = 0; index < 16; index++)
\r
1950 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]);
\r
1951 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
\r
1955 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
\r
1957 else if(path == ODM_RF_PATH_B)
\r
1960 //load APK setting
\r
1962 offset = rPdp_AntB;
\r
1963 for(index = 0; index < 10; index ++)
\r
1965 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);
\r
1966 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
\r
1970 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000);
\r
1971 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
1972 PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);
\r
1974 PHY_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);
\r
1977 offset = rConfig_AntA;
\r
1979 for(; index < 13; index ++) //offset 0xb68, 0xb6c
\r
1981 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);
\r
1982 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
\r
1988 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000);
\r
1992 for(index = 0; index < 16; index++)
\r
1994 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]);
\r
1995 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));
\r
1999 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0);
\r
2002 //save RF default value
\r
2003 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2004 regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord);
\r
2006 regD[path] = ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_TXBIAS_A, bMaskDWord);
\r
2009 //Path A AFE all on, path B AFE All off or vise versa
\r
2010 for(index = 0; index < IQK_ADDA_REG_NUM ; index++)
\r
2011 ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]);
\r
2012 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord)));
\r
2017 for(index = 0; index < APK_BB_REG_NUM ; index++)
\r
2020 if(index == 0) //skip
\r
2022 else if (index < 5)
\r
2023 ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]);
\r
2024 else if (BB_REG[index] == 0x870)
\r
2025 ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26);
\r
2027 ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0);
\r
2030 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
\r
2031 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
\r
2035 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00);
\r
2036 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00);
\r
2040 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord)));
\r
2043 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2044 _PHY_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup);
\r
2046 _PHY_MACSettingCalibration(pDM_Odm, MAC_REG, MAC_backup);
\r
2049 if(path == ODM_RF_PATH_A) //Path B to standby mode
\r
2051 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000);
\r
2053 else //Path A to standby mode
\r
2055 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000);
\r
2056 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f);
\r
2057 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103);
\r
2060 delta_offset = ((delta+14)/2);
\r
2061 if(delta_offset < 0)
\r
2063 else if (delta_offset > 12)
\r
2064 delta_offset = 12;
\r
2067 for(index = 0; index < APK_BB_REG_NUM; index++)
\r
2069 if(index != 1) //only DO PA11+PAD01001, AP RF setting
\r
2072 tmpReg = APK_RF_init_value[path][index];
\r
2074 if(!pDM_Odm->RFCalibrateInfo.bAPKThermalMeterIgnore)
\r
2076 BB_offset = (tmpReg & 0xF0000) >> 16;
\r
2078 if(!(tmpReg & BIT15)) //sign bit 0
\r
2080 BB_offset = -BB_offset;
\r
2083 delta_V = APK_delta_mapping[index][delta_offset];
\r
2085 BB_offset += delta_V;
\r
2087 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset));
\r
2091 tmpReg = tmpReg & (~BIT15);
\r
2092 BB_offset = -BB_offset;
\r
2096 tmpReg = tmpReg | BIT15;
\r
2098 tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16);
\r
2102 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_IPA_A, bMaskDWord, 0x8992e);
\r
2103 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2104 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord)));
\r
2105 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]);
\r
2106 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord)));
\r
2107 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_TXBIAS_A, bMaskDWord, tmpReg);
\r
2108 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord)));
\r
2110 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord)));
\r
2111 ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]);
\r
2112 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord)));
\r
2113 ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg);
\r
2114 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord)));
\r
2117 // PA11+PAD01111, one shot
\r
2121 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80000000);
\r
2123 ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]);
\r
2124 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord)));
\r
2126 ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]);
\r
2127 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord)));
\r
2131 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
\r
2133 if(path == ODM_RF_PATH_A)
\r
2134 tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000);
\r
2136 tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000);
\r
2137 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xbd8[25:21] %x\n", tmpReg));
\r
2142 while(tmpReg > apkbound && i < 4);
\r
2144 APK_result[path][index] = tmpReg;
\r
2148 //reload MAC default value
\r
2149 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2150 _PHY_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup);
\r
2152 _PHY_ReloadMACRegisters(pDM_Odm, MAC_REG, MAC_backup);
\r
2155 //reload BB default value
\r
2156 for(index = 0; index < APK_BB_REG_NUM ; index++)
\r
2159 if(index == 0) //skip
\r
2161 ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]);
\r
2164 //reload AFE default value
\r
2165 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2166 _PHY_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
\r
2168 _PHY_ReloadADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
\r
2171 //reload RF path default value
\r
2172 for(path = 0; path < pathbound; path++)
\r
2174 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0xd, bMaskDWord, regD[path]);
\r
2175 if(path == ODM_RF_PATH_B)
\r
2177 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f);
\r
2178 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101);
\r
2181 //note no index == 0
\r
2182 if (APK_result[path][1] > 6)
\r
2183 APK_result[path][1] = 6;
\r
2184 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1]));
\r
2187 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n"));
\r
2190 for(path = 0; path < pathbound; path++)
\r
2192 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x3, bMaskDWord,
\r
2193 ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1]));
\r
2194 if(path == ODM_RF_PATH_A)
\r
2195 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord,
\r
2196 ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05));
\r
2198 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord,
\r
2199 ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05));
\r
2200 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2201 if(!IS_HARDWARE_TYPE_8723A(pAdapter))
\r
2202 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G9_G11, bMaskDWord,
\r
2203 ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08));
\r
2207 pDM_Odm->RFCalibrateInfo.bAPKdone = TRUE;
\r
2209 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188E()\n"));
\r
2214 #define DP_BB_REG_NUM 7
\r
2215 #define DP_RF_REG_NUM 1
\r
2216 #define DP_RETRY_LIMIT 10
\r
2217 #define DP_PATH_NUM 2
\r
2218 #define DP_DPK_NUM 3
\r
2219 #define DP_DPK_VALUE_NUM 2
\r
2226 PHY_IQCalibrate_8188E(
\r
2227 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2228 IN PDM_ODM_T pDM_Odm,
\r
2230 IN PADAPTER pAdapter,
\r
2232 IN BOOLEAN bReCovery
\r
2235 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2236 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
2238 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
2239 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
\r
2240 #else // (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
2241 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
\r
2244 #if (MP_DRIVER == 1)
\r
2245 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
2246 PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx);
\r
2247 #else// (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
2248 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
\r
2250 #endif//(MP_DRIVER == 1)
\r
2253 s4Byte result[4][8]; //last is final result
\r
2254 u1Byte i, final_candidate, Indexforchannel;
\r
2255 u1Byte channelToIQK = 7;
\r
2256 BOOLEAN bPathAOK, bPathBOK;
\r
2257 s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0;
\r
2258 BOOLEAN is12simular, is13simular, is23simular;
\r
2259 BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE;
\r
2260 u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
\r
2261 rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance,
\r
2262 rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable,
\r
2263 rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance,
\r
2264 rOFDM0_XCTxAFE, rOFDM0_XDTxAFE,
\r
2265 rOFDM0_RxIQExtAnta};
\r
2266 u4Byte StartTime;
\r
2267 s4Byte ProgressingTime;
\r
2269 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) )
\r
2270 if (ODM_CheckPowerStatus(pAdapter) == FALSE)
\r
2273 prtl8192cd_priv priv = pDM_Odm->priv;
\r
2276 if(priv->pshare->rf_ft_var.mp_specific)
\r
2278 if((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST))
\r
2283 if(priv->pshare->IQK_88E_done)
\r
2285 priv->pshare->IQK_88E_done = 1;
\r
2289 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
2290 if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
\r
2296 #if MP_DRIVER == 1
\r
2297 if (*(pDM_Odm->mp_mode) == 1)
\r
2299 bStartContTx = pMptCtx->bStartContTx;
\r
2300 bSingleTone = pMptCtx->bSingleTone;
\r
2301 bCarrierSuppression = pMptCtx->bCarrierSuppression;
\r
2305 // 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu)
\r
2306 if(bSingleTone || bCarrierSuppression)
\r
2313 if (pDM_Odm->RFCalibrateInfo.bIQKInProgress)
\r
2316 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP))
\r
2318 #else//for ODM_WIN
\r
2319 if(bReCovery && (!pAdapter->bInHctTest)) //YJ,add for PowerTest,120405
\r
2322 ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_8188E: Return due to bReCovery!\n"));
\r
2323 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2324 _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);
\r
2326 _PHY_ReloadADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);
\r
2331 ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK);
\r
2332 pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE;
\r
2333 ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK);
\r
2335 StartTime = ODM_GetCurrentTime( pDM_Odm);
\r
2336 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n"));
\r
2340 for(i = 0; i < 8; i++)
\r
2347 final_candidate = 0xff;
\r
2350 is12simular = FALSE;
\r
2351 is23simular = FALSE;
\r
2352 is13simular = FALSE;
\r
2355 for (i=0; i<3; i++)
\r
2357 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2359 if(IS_92C_SERIAL( pHalData->VersionID))
\r
2361 phy_IQCalibrate_8188E(pAdapter, result, i, TRUE);
\r
2367 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2368 phy_IQCalibrate_8188E(pAdapter, result, i, FALSE);
\r
2370 phy_IQCalibrate_8188E(pDM_Odm, result, i, FALSE);
\r
2376 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2377 is12simular = phy_SimularityCompare_8188E(pAdapter, result, 0, 1);
\r
2379 is12simular = phy_SimularityCompare_8188E(pDM_Odm, result, 0, 1);
\r
2383 final_candidate = 0;
\r
2384 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n",final_candidate));
\r
2391 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2392 is13simular = phy_SimularityCompare_8188E(pAdapter, result, 0, 2);
\r
2394 is13simular = phy_SimularityCompare_8188E(pDM_Odm, result, 0, 2);
\r
2398 final_candidate = 0;
\r
2399 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n",final_candidate));
\r
2403 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2404 is23simular = phy_SimularityCompare_8188E(pAdapter, result, 1, 2);
\r
2406 is23simular = phy_SimularityCompare_8188E(pDM_Odm, result, 1, 2);
\r
2410 final_candidate = 1;
\r
2411 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n",final_candidate));
\r
2415 for(i = 0; i < 8; i++)
\r
2416 RegTmp += result[3][i];
\r
2419 final_candidate = 3;
\r
2421 final_candidate = 0xFF;
\r
2425 // RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate \n"));
\r
2427 for (i=0; i<4; i++)
\r
2429 RegE94 = result[i][0];
\r
2430 RegE9C = result[i][1];
\r
2431 RegEA4 = result[i][2];
\r
2432 RegEAC = result[i][3];
\r
2433 RegEB4 = result[i][4];
\r
2434 RegEBC = result[i][5];
\r
2435 RegEC4 = result[i][6];
\r
2436 RegECC = result[i][7];
\r
2437 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC));
\r
2440 if(final_candidate != 0xff)
\r
2442 pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0];
\r
2443 pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1];
\r
2444 RegEA4 = result[final_candidate][2];
\r
2445 RegEAC = result[final_candidate][3];
\r
2446 pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4];
\r
2447 pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5];
\r
2448 RegEC4 = result[final_candidate][6];
\r
2449 RegECC = result[final_candidate][7];
\r
2450 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: final_candidate is %x\n",final_candidate));
\r
2451 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC));
\r
2452 bPathAOK = bPathBOK = TRUE;
\r
2456 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: FAIL use default value\n"));
\r
2458 pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; //X default value
\r
2459 pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; //Y default value
\r
2462 if((RegE94 != 0)/*&&(RegEA4 != 0)*/)
\r
2464 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2465 _PHY_PathAFillIQKMatrix(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0));
\r
2467 _PHY_PathAFillIQKMatrix(pDM_Odm, bPathAOK, result, final_candidate, (RegEA4 == 0));
\r
2471 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2472 if (IS_92C_SERIAL(pHalData->VersionID))
\r
2474 if((RegEB4 != 0)/*&&(RegEC4 != 0)*/)
\r
2476 _PHY_PathBFillIQKMatrix(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0));
\r
2481 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2482 Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel);
\r
2484 Indexforchannel = 0;
\r
2487 //To Fix BSOD when final_candidate is 0xff
\r
2488 //by sherry 20120321
\r
2489 if(final_candidate < 4)
\r
2491 for(i = 0; i < IQK_Matrix_REG_NUM; i++)
\r
2492 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i];
\r
2493 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE;
\r
2495 //RT_DISP(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel));
\r
2496 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel));
\r
2497 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2499 _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);
\r
2501 _PHY_SaveADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, IQK_BB_REG_NUM);
\r
2504 ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK);
\r
2505 pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE;
\r
2506 ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK);
\r
2508 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n"));
\r
2509 ProgressingTime = ODM_GetProgressingTime( pDM_Odm, StartTime);
\r
2510 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK ProgressingTime = %d\n", ProgressingTime));
\r
2516 PHY_LCCalibrate_8188E(
\r
2517 IN PDM_ODM_T pDM_Odm
\r
2520 BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE;
\r
2521 u4Byte timeout = 2000, timecount = 0;
\r
2522 u4Byte StartTime;
\r
2523 s4Byte ProgressingTime;
\r
2527 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2528 PADAPTER pAdapter = pDM_Odm->Adapter;
\r
2529 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
2531 #if (MP_DRIVER == 1)
\r
2532 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
2533 PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx);
\r
2534 #else// (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
2535 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
\r
2537 #endif//(MP_DRIVER == 1)
\r
2540 #if MP_DRIVER == 1
\r
2541 if (*(pDM_Odm->mp_mode) == 1)
\r
2543 bStartContTx = pMptCtx->bStartContTx;
\r
2544 bSingleTone = pMptCtx->bSingleTone;
\r
2545 bCarrierSuppression = pMptCtx->bCarrierSuppression;
\r
2554 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
2555 if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
\r
2560 // 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu)
\r
2561 if(bSingleTone || bCarrierSuppression)
\r
2564 StartTime = ODM_GetCurrentTime( pDM_Odm);
\r
2565 while(*(pDM_Odm->pbScanInProcess) && timecount < timeout)
\r
2571 pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE;
\r
2573 //ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, timecount));
\r
2574 phy_LCCalibrate_8188E(pDM_Odm, FALSE);
\r
2576 pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE;
\r
2578 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex));
\r
2579 ProgressingTime = ODM_GetProgressingTime( pDM_Odm, StartTime);
\r
2580 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK ProgressingTime = %d\n", ProgressingTime));
\r
2584 PHY_APCalibrate_8188E(
\r
2585 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2586 IN PDM_ODM_T pDM_Odm,
\r
2588 IN PADAPTER pAdapter,
\r
2593 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2594 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
2595 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
2596 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
\r
2598 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
2599 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
\r
2607 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
2608 if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))
\r
2614 #if FOR_BRAZIL_PRETEST != 1
\r
2615 if(pDM_Odm->RFCalibrateInfo.bAPKdone)
\r
2619 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2620 if(IS_92C_SERIAL( pHalData->VersionID)){
\r
2621 phy_APCalibrate_8188E(pAdapter, delta, TRUE);
\r
2627 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2628 phy_APCalibrate_8188E(pAdapter, delta, FALSE);
\r
2630 phy_APCalibrate_8188E(pDM_Odm, delta, FALSE);
\r
2634 VOID phy_SetRFPathSwitch_8188E(
\r
2635 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2636 IN PDM_ODM_T pDM_Odm,
\r
2638 IN PADAPTER pAdapter,
\r
2644 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2645 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
2646 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
2647 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
\r
2648 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
2649 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
\r
2652 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
2653 if(!pAdapter->bHWInitReady)
\r
2654 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
2655 if(pAdapter->hw_init_completed == _FALSE)
\r
2659 u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7;
\r
2660 ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp);
\r
2661 //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01);
\r
2662 ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01);
\r
2670 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); //92C_Path_A
\r
2672 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); //BT
\r
2677 // <20120504, Kordan> [8188E] We should make AntDiversity controlled by HW (0x870[9:8] = 0),
\r
2678 // otherwise the following action has no effect. (0x860[9:8] has the effect only if AntDiversity controlled by SW)
\r
2679 ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT8|BIT9, 0x0);
\r
2680 ODM_SetBBReg(pDM_Odm, 0x914, bMaskLWord, 0x0201); // Set up the Ant mapping table
\r
2684 //ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x2); // Tx Main (SW control)(The right antenna)
\r
2686 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT14|BIT13|BIT12, 0x1); // Tx Main (HW control)(The right antenna)
\r
2689 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3, 0x1); // AntDivType = TRDiv, right antenna
\r
2690 if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)
\r
2691 ODM_SetBBReg(pDM_Odm, rConfig_ram64x16, BIT31, 0x1); // RxCG, Default is RxCG. AntDivType = 2RDiv, left antenna
\r
2696 //ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x1); // Tx Aux (SW control)(The left antenna)
\r
2698 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT14|BIT13|BIT12, 0x0); // Tx Aux (HW control)(The left antenna)
\r
2701 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3, 0x0); // AntDivType = TRDiv, left antenna
\r
2702 if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)
\r
2703 ODM_SetBBReg(pDM_Odm, rConfig_ram64x16, BIT31, 0x0); // RxCS, AntDivType = 2RDiv, right antenna
\r
2708 VOID PHY_SetRFPathSwitch_8188E(
\r
2709 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2710 IN PDM_ODM_T pDM_Odm,
\r
2712 IN PADAPTER pAdapter,
\r
2717 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2718 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
2725 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2726 if (IS_92C_SERIAL(pHalData->VersionID))
\r
2728 phy_SetRFPathSwitch_8188E(pAdapter, bMain, TRUE);
\r
2734 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2735 phy_SetRFPathSwitch_8188E(pAdapter, bMain, FALSE);
\r
2737 phy_SetRFPathSwitch_8188E(pDM_Odm, bMain, FALSE);
\r
2742 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
2743 //digital predistortion
\r
2745 phy_DigitalPredistortion(
\r
2746 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2747 IN PADAPTER pAdapter,
\r
2749 IN PDM_ODM_T pDM_Odm,
\r
2754 #if (RT_PLATFORM == PLATFORM_WINDOWS)
\r
2755 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2756 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
2757 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
2758 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
\r
2760 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
2761 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
\r
2765 u4Byte tmpReg, tmpReg2, index, i;
\r
2766 u1Byte path, pathbound = PATH_NUM;
\r
2767 u4Byte AFE_backup[IQK_ADDA_REG_NUM];
\r
2768 u4Byte AFE_REG[IQK_ADDA_REG_NUM] = {
\r
2769 rFPGA0_XCD_SwitchControl, rBlue_Tooth,
\r
2770 rRx_Wait_CCA, rTx_CCK_RFON,
\r
2771 rTx_CCK_BBON, rTx_OFDM_RFON,
\r
2772 rTx_OFDM_BBON, rTx_To_Rx,
\r
2773 rTx_To_Tx, rRx_CCK,
\r
2774 rRx_OFDM, rRx_Wait_RIFS,
\r
2775 rRx_TO_Rx, rStandby,
\r
2776 rSleep, rPMPD_ANAEN };
\r
2778 u4Byte BB_backup[DP_BB_REG_NUM];
\r
2779 u4Byte BB_REG[DP_BB_REG_NUM] = {
\r
2780 rOFDM0_TRxPathEnable, rFPGA0_RFMOD,
\r
2781 rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW,
\r
2782 rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE,
\r
2783 rFPGA0_XB_RFInterfaceOE};
\r
2784 u4Byte BB_settings[DP_BB_REG_NUM] = {
\r
2785 0x00a05430, 0x02040000, 0x000800e4, 0x22208000,
\r
2788 u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM];
\r
2789 u4Byte RF_REG[DP_RF_REG_NUM] = {
\r
2792 u4Byte MAC_backup[IQK_MAC_REG_NUM];
\r
2793 u4Byte MAC_REG[IQK_MAC_REG_NUM] = {
\r
2794 REG_TXPAUSE, REG_BCN_CTRL,
\r
2795 REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
\r
2797 u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = {
\r
2798 {0x1e1e1e1e, 0x03901e1e},
\r
2799 {0x18181818, 0x03901818},
\r
2800 {0x0e0e0e0e, 0x03900e0e}
\r
2803 u4Byte AFE_on_off[PATH_NUM] = {
\r
2804 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on
\r
2806 u1Byte RetryCount = 0;
\r
2809 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion()\n"));
\r
2811 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion for %s\n", (is2T ? "2T2R" : "1T1R")));
\r
2813 //save BB default value
\r
2814 for(index=0; index<DP_BB_REG_NUM; index++)
\r
2815 BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord);
\r
2817 //save MAC default value
\r
2818 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2819 _PHY_SaveMACRegisters(pAdapter, BB_REG, MAC_backup);
\r
2821 _PHY_SaveMACRegisters(pDM_Odm, BB_REG, MAC_backup);
\r
2824 //save RF default value
\r
2825 for(path=0; path<DP_PATH_NUM; path++)
\r
2827 for(index=0; index<DP_RF_REG_NUM; index++)
\r
2828 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2829 RF_backup[path][index] = PHY_QueryRFReg(pAdapter, path, RF_REG[index], bMaskDWord);
\r
2831 RF_backup[path][index] = ODM_GetRFReg(pAdapter, path, RF_REG[index], bMaskDWord);
\r
2835 //save AFE default value
\r
2836 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2837 _PHY_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
\r
2839 _PHY_SaveADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
\r
2842 //Path A/B AFE all on
\r
2843 for(index = 0; index < IQK_ADDA_REG_NUM ; index++)
\r
2844 ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, 0x6fdb25a4);
\r
2846 //BB register setting
\r
2847 for(index = 0; index < DP_BB_REG_NUM; index++)
\r
2850 ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_settings[index]);
\r
2851 else if (index == 4)
\r
2852 ODM_SetBBReg(pDM_Odm,BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26);
\r
2854 ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x00);
\r
2857 //MAC register setting
\r
2858 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
2859 _PHY_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup);
\r
2861 _PHY_MACSettingCalibration(pDM_Odm, MAC_REG, MAC_backup);
\r
2864 //PAGE-E IQC setting
\r
2865 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
\r
2866 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
\r
2867 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00);
\r
2868 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00);
\r
2871 //Path B to standby mode
\r
2872 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000);
\r
2874 // PA gain = 11 & PAD1 => tx_agc 1f ~11
\r
2875 // PA gain = 11 & PAD2 => tx_agc 10~0e
\r
2876 // PA gain = 01 => tx_agc 0b~0d
\r
2877 // PA gain = 00 => tx_agc 0a~00
\r
2878 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000);
\r
2879 ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f);
\r
2880 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
\r
2882 //do inner loopback DPK 3 times
\r
2883 for(i = 0; i < 3; i++)
\r
2885 //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07
\r
2886 for(index = 0; index < 3; index++)
\r
2887 ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, Tx_AGC[i][0]);
\r
2888 ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, Tx_AGC[i][1]);
\r
2889 for(index = 0; index < 4; index++)
\r
2890 ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, Tx_AGC[i][0]);
\r
2892 // PAGE_B for Path-A inner loopback DPK setting
\r
2893 ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02097098);
\r
2894 ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84);
\r
2895 ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87);
\r
2896 ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000);
\r
2898 //----send one shot signal----//
\r
2900 ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x80047788);
\r
2902 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788);
\r
2906 //PA gain = 11 => tx_agc = 1a
\r
2907 for(index = 0; index < 3; index++)
\r
2908 ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, 0x34343434);
\r
2909 ODM_SetBBReg(pDM_Odm,0xe08+index*4, bMaskDWord, 0x03903434);
\r
2910 for(index = 0; index < 4; index++)
\r
2911 ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, 0x34343434);
\r
2913 //====================================
\r
2914 // PAGE_B for Path-A DPK setting
\r
2915 //====================================
\r
2916 // open inner loopback @ b00[19]:10 od 0xb00 0x01097018
\r
2917 ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02017098);
\r
2918 ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84);
\r
2919 ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87);
\r
2920 ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000);
\r
2923 //1.rf 00:5205a, rf 0d:0e52c
\r
2924 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0c, bMaskDWord, 0x8992b);
\r
2925 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c);
\r
2926 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bMaskDWord, 0x5205a );
\r
2928 //----send one shot signal----//
\r
2930 ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0);
\r
2932 ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0);
\r
2935 while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathAOK)
\r
2937 //----read back measurement results----//
\r
2938 ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018);
\r
2939 tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord);
\r
2941 ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f);
\r
2942 tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord);
\r
2945 tmpReg = (tmpReg & bMaskHWord) >> 16;
\r
2946 tmpReg2 = (tmpReg2 & bMaskHWord) >> 16;
\r
2947 if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff )
\r
2949 ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098);
\r
2951 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80000000);
\r
2952 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
\r
2954 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0);
\r
2956 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0);
\r
2957 ODM_delay_ms(50);
\r
2959 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2));
\r
2963 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n"));
\r
2964 pDM_Odm->RFCalibrateInfo.bDPPathAOK = TRUE;
\r
2971 if(pDM_Odm->RFCalibrateInfo.bDPPathAOK)
\r
2974 ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098);
\r
2975 ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84);
\r
2976 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87);
\r
2977 ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000);
\r
2978 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000);
\r
2980 for(i=rPdp_AntA; i<=0xb3c; i+=4)
\r
2982 ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000);
\r
2983 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i));
\r
2987 ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040);
\r
2988 ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040);
\r
2989 ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920);
\r
2991 for(i=0xb4c; i<=0xb5c; i+=4)
\r
2993 ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c);
\r
2997 ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f);
\r
2998 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
\r
3002 ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000);
\r
3003 ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000);
\r
3009 //Path A to standby mode
\r
3010 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000);
\r
3013 // PA gain = 11 & PAD1, => tx_agc 1f ~11
\r
3014 // PA gain = 11 & PAD2, => tx_agc 10 ~0e
\r
3015 // PA gain = 01 => tx_agc 0b ~0d
\r
3016 // PA gain = 00 => tx_agc 0a ~00
\r
3017 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000);
\r
3018 ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f);
\r
3019 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
\r
3021 //do inner loopback DPK 3 times
\r
3022 for(i = 0; i < 3; i++)
\r
3024 //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07
\r
3025 for(index = 0; index < 4; index++)
\r
3026 ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, Tx_AGC[i][0]);
\r
3027 for(index = 0; index < 2; index++)
\r
3028 ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, Tx_AGC[i][0]);
\r
3029 for(index = 0; index < 2; index++)
\r
3030 ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, Tx_AGC[i][0]);
\r
3032 // PAGE_B for Path-A inner loopback DPK setting
\r
3033 ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098);
\r
3034 ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84);
\r
3035 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87);
\r
3036 ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000);
\r
3038 //----send one shot signal----//
\r
3040 ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntB, bMaskDWord, 0x80047788);
\r
3042 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788);
\r
3046 // PA gain = 11 => tx_agc = 1a
\r
3047 for(index = 0; index < 4; index++)
\r
3048 ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, 0x34343434);
\r
3049 for(index = 0; index < 2; index++)
\r
3050 ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, 0x34343434);
\r
3051 for(index = 0; index < 2; index++)
\r
3052 ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, 0x34343434);
\r
3054 // PAGE_B for Path-B DPK setting
\r
3055 ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098);
\r
3056 ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84);
\r
3057 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87);
\r
3058 ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000);
\r
3060 // RF lpbk switches on
\r
3061 ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f);
\r
3062 ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103);
\r
3065 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0c, bMaskDWord, 0x8992b);
\r
3066 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c);
\r
3067 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x5205a);
\r
3069 //----send one shot signal----//
\r
3070 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0);
\r
3072 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0);
\r
3075 while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathBOK)
\r
3077 //----read back measurement results----//
\r
3078 ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018);
\r
3079 tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord);
\r
3080 ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f);
\r
3081 tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord);
\r
3083 tmpReg = (tmpReg & bMaskHWord) >> 16;
\r
3084 tmpReg2 = (tmpReg2 & bMaskHWord) >> 16;
\r
3086 if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff)
\r
3088 ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098);
\r
3090 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80000000);
\r
3091 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
\r
3093 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0);
\r
3095 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0);
\r
3096 ODM_delay_ms(50);
\r
3098 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2));
\r
3102 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n"));
\r
3103 pDM_Odm->RFCalibrateInfo.bDPPathBOK = TRUE;
\r
3109 if(pDM_Odm->RFCalibrateInfo.bDPPathBOK)
\r
3113 ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098);
\r
3114 ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84);
\r
3115 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87);
\r
3116 ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000);
\r
3118 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000);
\r
3119 for(i=0xb60; i<=0xb9c; i+=4)
\r
3121 ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000);
\r
3122 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i));
\r
3126 ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040);
\r
3127 ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050);
\r
3128 ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920);
\r
3130 for(i=0xbac; i<=0xbbc; i+=4)
\r
3132 ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c);
\r
3135 // tx_agc boundary
\r
3136 ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f);
\r
3137 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
\r
3142 ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000);
\r
3143 ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000);
\r
3147 //reload BB default value
\r
3148 for(index=0; index<DP_BB_REG_NUM; index++)
\r
3149 ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]);
\r
3151 //reload RF default value
\r
3152 for(path = 0; path<DP_PATH_NUM; path++)
\r
3154 for( i = 0 ; i < DP_RF_REG_NUM ; i++){
\r
3155 ODM_SetRFReg(pDM_Odm, path, RF_REG[i], bMaskDWord, RF_backup[path][i]);
\r
3158 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); //standby mode
\r
3159 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); //RF lpbk switches off
\r
3161 //reload AFE default value
\r
3162 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
3163 _PHY_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
\r
3165 //reload MAC default value
\r
3166 _PHY_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup);
\r
3168 _PHY_ReloadADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
\r
3170 //reload MAC default value
\r
3171 _PHY_ReloadMACRegisters(pDM_Odm, MAC_REG, MAC_backup);
\r
3174 pDM_Odm->RFCalibrateInfo.bDPdone = TRUE;
\r
3175 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion()\n"));
\r
3180 PHY_DigitalPredistortion_8188E(
\r
3181 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
3182 IN PADAPTER pAdapter
\r
3184 IN PDM_ODM_T pDM_Odm
\r
3188 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
3189 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
3190 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
3191 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
\r
3193 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
3194 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
\r
3203 if(pDM_Odm->RFCalibrateInfo.bDPdone)
\r
3205 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
3207 if(pDM_Odm->RFType == ODM_2T2R){
\r
3208 phy_DigitalPredistortion(pAdapter, TRUE);
\r
3214 phy_DigitalPredistortion(pAdapter, FALSE);
\r
3220 //return value TRUE => Main; FALSE => Aux
\r
3222 BOOLEAN phy_QueryRFPathSwitch_8188E(
\r
3223 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
3224 IN PDM_ODM_T pDM_Odm,
\r
3226 IN PADAPTER pAdapter,
\r
3231 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
3232 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
3233 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
\r
3234 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
\r
3236 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
\r
3237 PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
\r
3240 if(!pAdapter->bHWInitReady)
\r
3243 u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7;
\r
3244 ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp);
\r
3245 //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01);
\r
3246 ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01);
\r
3251 if(ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01)
\r
3258 if((ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3) == 0x1))
\r
3267 //return value TRUE => Main; FALSE => Aux
\r
3268 BOOLEAN PHY_QueryRFPathSwitch_8188E(
\r
3269 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
3270 IN PDM_ODM_T pDM_Odm
\r
3272 IN PADAPTER pAdapter
\r
3276 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
3281 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
3283 //if(IS_92C_SERIAL( pHalData->VersionID)){
\r
3284 if(IS_2T2R( pHalData->VersionID)){
\r
3285 return phy_QueryRFPathSwitch_8188E(pAdapter, TRUE);
\r
3291 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
\r
3292 return phy_QueryRFPathSwitch_8188E(pAdapter, FALSE);
\r
3294 return phy_QueryRFPathSwitch_8188E(pDM_Odm, FALSE);
\r