drivers/net/wireless/rockchip_wlan/rtl8188eu/hal/HalPwrSeqCmd.c

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *\r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *\r
  19  ******************************************************************************/\r
  20 /*++\r
  21 Copyright (c) Realtek Semiconductor Corp. All rights reserved.\r
  22 \r
  23 Module Name:\r
  24         HalPwrSeqCmd.c\r
  25 \r
  26 Abstract:\r
  27         Implement HW Power sequence configuration CMD handling routine for Realtek devices.\r
  28 \r
  29 Major Change History:\r
  30         When       Who               What\r
  31         ---------- ---------------   -------------------------------\r
  32         2011-10-26 Lucas            Modify to be compatible with SD4-CE driver.\r
  33         2011-07-07 Roger            Create.\r
  34 \r
  35 --*/\r
  36 #include <HalPwrSeqCmd.h>\r
  37 \r
  38 \r
  39 //\r
  40 //      Description:\r
  41 //              This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC.\r
  42 //\r
  43 //      Assumption:\r
  44 //              We should follow specific format which was released from HW SD.\r
  45 //\r
  46 //      2011.07.07, added by Roger.\r
  47 //\r
  48 u8 HalPwrSeqCmdParsing(\r
  49         PADAPTER                padapter,\r
  50         u8                              CutVersion,\r
  51         u8                              FabVersion,\r
  52         u8                              InterfaceType,\r
  53         WLAN_PWR_CFG    PwrSeqCmd[])\r
  54 {\r
  55         WLAN_PWR_CFG    PwrCfgCmd = {0};\r
  56         u8                              bPollingBit = _FALSE;\r
  57         u32                             AryIdx = 0;\r
  58         u8                              value = 0;\r
  59         u32                             offset = 0;\r
  60         u32                             pollingCount = 0; // polling autoload done.\r
  61         u32                             maxPollingCnt = 5000;\r
  62 \r
  63         do {\r
  64                 PwrCfgCmd = PwrSeqCmd[AryIdx];\r
  65 \r
  66                 RT_TRACE(_module_hal_init_c_ , _drv_info_,\r
  67                                  ("HalPwrSeqCmdParsing: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n",\r
  68                                         GET_PWR_CFG_OFFSET(PwrCfgCmd),\r
  69                                         GET_PWR_CFG_CUT_MASK(PwrCfgCmd),\r
  70                                         GET_PWR_CFG_FAB_MASK(PwrCfgCmd),\r
  71                                         GET_PWR_CFG_INTF_MASK(PwrCfgCmd),\r
  72                                         GET_PWR_CFG_BASE(PwrCfgCmd),\r
  73                                         GET_PWR_CFG_CMD(PwrCfgCmd),\r
  74                                         GET_PWR_CFG_MASK(PwrCfgCmd),\r
  75                                         GET_PWR_CFG_VALUE(PwrCfgCmd)));\r
  76 \r
  77                 //2 Only Handle the command whose FAB, CUT, and Interface are matched\r
  78                 if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&\r
  79                         (GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&\r
  80                         (GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType))\r
  81                 {\r
  82                         switch (GET_PWR_CFG_CMD(PwrCfgCmd))\r
  83                         {\r
  84                                 case PWR_CMD_READ:\r
  85                                         RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_READ\n"));\r
  86                                         break;\r
  87 \r
  88                                 case PWR_CMD_WRITE:\r
  89                                         RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n"));\r
  90                                         offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);\r
  91 \r
  92 #ifdef CONFIG_SDIO_HCI\r
  93                                         //\r
  94                                         // <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface\r
  95                                         // 2011.07.07.\r
  96                                         //\r
  97                                         if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)\r
  98                                         {\r
  99                                                 // Read Back SDIO Local value\r
 100                                                 value = SdioLocalCmd52Read1Byte(padapter, offset);\r
 101 \r
 102                                                 value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));\r
 103                                                 value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));\r
 104 \r
 105                                                 // Write Back SDIO Local value\r
 106                                                 SdioLocalCmd52Write1Byte(padapter, offset, value);\r
 107                                         }\r
 108                                         else\r
 109 #endif\r
 110                                         {\r
 111 #ifdef CONFIG_GSPI_HCI\r
 112                                                 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)\r
 113                                                         offset = SPI_LOCAL_OFFSET | offset;\r
 114 #endif\r
 115                                                 // Read the value from system register\r
 116                                                 value = rtw_read8(padapter, offset);\r
 117 \r
 118                                                 value=value&(~(GET_PWR_CFG_MASK(PwrCfgCmd)));\r
 119                                                 value=value|(GET_PWR_CFG_VALUE(PwrCfgCmd)&GET_PWR_CFG_MASK(PwrCfgCmd));\r
 120 \r
 121                                                 // Write the value back to sytem register\r
 122                                                 rtw_write8(padapter, offset, value);\r
 123                                         }\r
 124                                         break;\r
 125 \r
 126                                 case PWR_CMD_POLLING:\r
 127                                         RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n"));\r
 128 \r
 129                                         bPollingBit = _FALSE;\r
 130                                         offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);\r
 131 #ifdef CONFIG_GSPI_HCI\r
 132                                         if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)\r
 133                                                 offset = SPI_LOCAL_OFFSET | offset;\r
 134 #endif\r
 135                                         do {\r
 136 #ifdef CONFIG_SDIO_HCI\r
 137                                                 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)\r
 138                                                         value = SdioLocalCmd52Read1Byte(padapter, offset);\r
 139                                                 else\r
 140 #endif\r
 141                                                         value = rtw_read8(padapter, offset);\r
 142 \r
 143                                                 value=value&GET_PWR_CFG_MASK(PwrCfgCmd);\r
 144                                                 if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)))\r
 145                                                         bPollingBit = _TRUE;\r
 146                                                 else\r
 147                                                         rtw_udelay_os(10);\r
 148 \r
 149                                                 if (pollingCount++ > maxPollingCnt) {\r
 150                                                         DBG_871X_LEVEL(_drv_err_, "HalPwrSeqCmdParsing: Fail to polling Offset[%#x]=%02x\n", offset, value);\r
 151                                                         return _FALSE;\r
 152                                                 }\r
 153                                         } while (!bPollingBit);\r
 154 \r
 155                                         break;\r
 156 \r
 157                                 case PWR_CMD_DELAY:\r
 158                                         RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_DELAY\n"));\r
 159                                         if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)\r
 160                                                 rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd));\r
 161                                         else\r
 162                                                 rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000);\r
 163                                         break;\r
 164 \r
 165                                 case PWR_CMD_END:\r
 166                                         // When this command is parsed, end the process\r
 167                                         RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_END\n"));\r
 168                                         return _TRUE;\r
 169                                         break;\r
 170 \r
 171                                 default:\r
 172                                         RT_TRACE(_module_hal_init_c_ , _drv_err_, ("HalPwrSeqCmdParsing: Unknown CMD!!\n"));\r
 173                                         break;\r
 174                         }\r
 175                 }\r
 176 \r
 177                 AryIdx++;//Add Array Index\r
 178         }while(1);\r
 179 \r
 180         return _TRUE;\r
 181 }\r
 182 \r
 183 \r