3 * Contains PCIe related functions that are shared between different driver models (e.g. firmware
4 * builds, DHD builds, BMAC builds), in order to avoid code duplication.
6 * Copyright (C) 1999-2016, Broadcom Corporation
8 * Unless you and Broadcom execute a separate written software license
9 * agreement governing use of this software, this software is licensed to you
10 * under the terms of the GNU General Public License version 2 (the "GPL"),
11 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
12 * following added to such license:
14 * As a special exception, the copyright holders of this software give you
15 * permission to link this software with independent modules, and to copy and
16 * distribute the resulting executable under terms of your choice, provided that
17 * you also meet, for each linked independent module, the terms and conditions of
18 * the license of that module. An independent module is a module which is not
19 * derived from this software. The special exception does not apply to any
20 * modifications of the software.
22 * Notwithstanding the above, under no circumstances may you combine this
23 * software in any way with any other Broadcom software provided under a license
24 * other than the GPL, without Broadcom's express prior written consent.
27 * <<Broadcom-WL-IPTag/Open:>>
29 * $Id: pcie_core.c 591285 2015-10-07 11:56:29Z $
41 #include "pcie_core.h"
43 /* local prototypes */
47 /* function definitions */
51 void pcie_watchdog_reset(osl_t *osh, si_t *sih, sbpcieregs_t *sbpcieregs)
54 uint16 cfg_offset[] = {PCIECFGREG_STATUS_CMD, PCIECFGREG_PM_CSR,
55 PCIECFGREG_MSI_CAP, PCIECFGREG_MSI_ADDR_L,
56 PCIECFGREG_MSI_ADDR_H, PCIECFGREG_MSI_DATA,
57 PCIECFGREG_LINK_STATUS_CTRL2, PCIECFGREG_RBAR_CTRL,
58 PCIECFGREG_PML1_SUB_CTRL1, PCIECFGREG_REG_BAR2_CONFIG,
59 PCIECFGREG_REG_BAR3_CONFIG};
60 sbpcieregs_t *pcie = NULL;
61 uint32 origidx = si_coreidx(sih);
63 /* Switch to PCIE2 core */
64 pcie = (sbpcieregs_t *)si_setcore(sih, PCIE2_CORE_ID, 0);
68 /* Disable/restore ASPM Control to protect the watchdog reset */
69 W_REG(osh, &sbpcieregs->configaddr, PCIECFGREG_LINK_STATUS_CTRL);
70 lsc = R_REG(osh, &sbpcieregs->configdata);
71 val = lsc & (~PCIE_ASPM_ENAB);
72 W_REG(osh, &sbpcieregs->configdata, val);
74 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), ~0, 4);
77 W_REG(osh, &sbpcieregs->configaddr, PCIECFGREG_LINK_STATUS_CTRL);
78 W_REG(osh, &sbpcieregs->configdata, lsc);
80 if (sih->buscorerev <= 13) {
81 /* Write configuration registers back to the shadow registers
82 * cause shadow registers are cleared out after watchdog reset.
84 for (i = 0; i < ARRAYSIZE(cfg_offset); i++) {
85 W_REG(osh, &sbpcieregs->configaddr, cfg_offset[i]);
86 val = R_REG(osh, &sbpcieregs->configdata);
87 W_REG(osh, &sbpcieregs->configdata, val);
90 si_setcoreidx(sih, origidx);
94 /* CRWLPCIEGEN2-117 pcie_pipe_Iddq should be controlled
95 * by the L12 state from MAC to save power by putting the
96 * SerDes analog in IDDQ mode
98 void pcie_serdes_iddqdisable(osl_t *osh, si_t *sih, sbpcieregs_t *sbpcieregs)
100 sbpcieregs_t *pcie = NULL;
101 uint crwlpciegen2_117_disable = 0;
102 uint32 origidx = si_coreidx(sih);
104 crwlpciegen2_117_disable = PCIE_PipeIddqDisable0 | PCIE_PipeIddqDisable1;
105 /* Switch to PCIE2 core */
106 pcie = (sbpcieregs_t *)si_setcore(sih, PCIE2_CORE_ID, 0);
108 ASSERT(pcie != NULL);
110 OR_REG(osh, &sbpcieregs->control,
111 crwlpciegen2_117_disable);
113 si_setcoreidx(sih, origidx);
115 #endif /* BCMDRIVER */