2 * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
4 * Copyright (C) 1999-2016, Broadcom Corporation
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16 * the license of that module. An independent module is a module which is not
17 * derived from this software. The special exception does not apply to any
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25 * <<Broadcom-WL-IPTag/Open:>>
27 * $Id: sbpcmcia.h 521344 2014-12-17 10:03:55Z $
33 /* All the addresses that are offsets in attribute space are divided
34 * by two to account for the fact that odd bytes are invalid in
35 * attribute space and our read/write routines make the space appear
36 * as if they didn't exist. Still we want to show the original numbers
37 * as documented in the hnd_pcmcia core manual.
40 /* PCMCIA Function Configuration Registers */
41 #define PCMCIA_FCR (0x700 / 2)
44 #define FCR1_OFF (0x40 / 2)
45 #define FCR2_OFF (0x80 / 2)
46 #define FCR3_OFF (0xc0 / 2)
48 #define PCMCIA_FCR0 (0x700 / 2)
49 #define PCMCIA_FCR1 (0x740 / 2)
50 #define PCMCIA_FCR2 (0x780 / 2)
51 #define PCMCIA_FCR3 (0x7c0 / 2)
53 /* Standard PCMCIA FCR registers */
59 #define COR_IRQEN 0x04
60 #define COR_BLREN 0x01
61 #define COR_FUNEN 0x01
64 #define PCICIA_FCSR (2 / 2)
65 #define PCICIA_PRR (4 / 2)
66 #define PCICIA_SCR (6 / 2)
67 #define PCICIA_ESR (8 / 2)
70 #define PCM_MEMOFF 0x0000
71 #define F0_MEMOFF 0x1000
72 #define F1_MEMOFF 0x2000
73 #define F2_MEMOFF 0x3000
74 #define F3_MEMOFF 0x4000
76 /* Memory base in the function fcr's */
77 #define MEM_ADDR0 (0x728 / 2)
78 #define MEM_ADDR1 (0x72a / 2)
79 #define MEM_ADDR2 (0x72c / 2)
81 /* PCMCIA base plus Srom access in fcr0: */
82 #define PCMCIA_ADDR0 (0x072e / 2)
83 #define PCMCIA_ADDR1 (0x0730 / 2)
84 #define PCMCIA_ADDR2 (0x0732 / 2)
86 #define MEM_SEG (0x0734 / 2)
87 #define SROM_CS (0x0736 / 2)
88 #define SROM_DATAL (0x0738 / 2)
89 #define SROM_DATAH (0x073a / 2)
90 #define SROM_ADDRL (0x073c / 2)
91 #define SROM_ADDRH (0x073e / 2)
92 #define SROM_INFO2 (0x0772 / 2) /* Corerev >= 2 && <= 5 */
93 #define SROM_INFO (0x07be / 2) /* Corerev >= 6 */
95 /* Values for srom_cs: */
103 /* Fields in srom_info: */
104 #define SRI_SZ_MASK 0x03
105 #define SRI_BLANK 0x04
110 #define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */
111 #define SBTML_INT_EN 0x20000 /* enable sb interrupt */
114 #define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */
116 #endif /* _SBPCMCIA_H */