2 * Broadcom SiliconBackplane hardware register definitions.
4 * $Copyright Open Broadcom Corporation$
6 * $Id: sbconfig.h 456346 2014-02-18 16:48:52Z $
12 /* cpp contortions to concatenate w/arg prescan */
14 #define _PADLINE(line) pad ## line
15 #define _XSTR(line) _PADLINE(line)
16 #define PAD _XSTR(__LINE__)
19 /* enumeration in SB is based on the premise that cores are contiguos in the
22 #define SB_BUS_SIZE 0x10000 /* Each bus gets 64Kbytes for cores */
23 #define SB_BUS_BASE(b) (SI_ENUM_BASE + (b) * SB_BUS_SIZE)
24 #define SB_BUS_MAXCORES (SB_BUS_SIZE / SI_CORE_SIZE) /* Max cores per bus */
27 * Sonics Configuration Space Registers.
29 #define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
30 #define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
32 #define SBIPSFLAG 0x08
33 #define SBTPSFLAG 0x18
34 #define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
35 #define SBTMERRLOG 0x50 /* sonics >= 2.3 */
36 #define SBADMATCH3 0x60
37 #define SBADMATCH2 0x68
38 #define SBADMATCH1 0x70
39 #define SBIMSTATE 0x90
41 #define SBTMSTATELOW 0x98
42 #define SBTMSTATEHIGH 0x9c
44 #define SBIMCONFIGLOW 0xa8
45 #define SBIMCONFIGHIGH 0xac
46 #define SBADMATCH0 0xb0
47 #define SBTMCONFIGLOW 0xb8
48 #define SBTMCONFIGHIGH 0xbc
49 #define SBBCONFIG 0xc0
51 #define SBACTCNFG 0xd8
56 /* All the previous registers are above SBCONFIGOFF, but with Sonics 2.3, we have
57 * a few registers *below* that line. I think it would be very confusing to try
58 * and change the value of SBCONFIGOFF, so I'm definig them as absolute offsets here,
61 #define SBIMERRLOGA 0xea8
62 #define SBIMERRLOG 0xeb0
63 #define SBTMPORTCONNID0 0xed8
64 #define SBTMPORTLOCK0 0xef8
66 #if !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__)
68 typedef volatile struct _sbconfig {
70 uint32 sbipsflag; /* initiator port ocp slave flag */
72 uint32 sbtpsflag; /* target port ocp slave flag */
74 uint32 sbtmerrloga; /* (sonics >= 2.3) */
76 uint32 sbtmerrlog; /* (sonics >= 2.3) */
78 uint32 sbadmatch3; /* address match3 */
80 uint32 sbadmatch2; /* address match2 */
82 uint32 sbadmatch1; /* address match1 */
84 uint32 sbimstate; /* initiator agent state */
85 uint32 sbintvec; /* interrupt mask */
86 uint32 sbtmstatelow; /* target state */
87 uint32 sbtmstatehigh; /* target state */
88 uint32 sbbwa0; /* bandwidth allocation table0 */
90 uint32 sbimconfiglow; /* initiator configuration */
91 uint32 sbimconfighigh; /* initiator configuration */
92 uint32 sbadmatch0; /* address match0 */
94 uint32 sbtmconfiglow; /* target configuration */
95 uint32 sbtmconfighigh; /* target configuration */
96 uint32 sbbconfig; /* broadcast configuration */
98 uint32 sbbstate; /* broadcast state */
100 uint32 sbactcnfg; /* activate configuration */
102 uint32 sbflagst; /* current sbflags */
104 uint32 sbidlow; /* identification */
105 uint32 sbidhigh; /* identification */
108 #endif /* !_LANGUAGE_ASSEMBLY && !__ASSEMBLY__ */
111 #define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
112 #define SBIPS_INT1_SHIFT 0
113 #define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
114 #define SBIPS_INT2_SHIFT 8
115 #define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
116 #define SBIPS_INT3_SHIFT 16
117 #define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
118 #define SBIPS_INT4_SHIFT 24
121 #define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
122 #define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
125 #define SBTMEL_CM 0x00000007 /* command */
126 #define SBTMEL_CI 0x0000ff00 /* connection id */
127 #define SBTMEL_EC 0x0f000000 /* error code */
128 #define SBTMEL_ME 0x80000000 /* multiple error */
131 #define SBIM_PC 0xf /* pipecount */
132 #define SBIM_AP_MASK 0x30 /* arbitration policy */
133 #define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
134 #define SBIM_AP_TS 0x10 /* use timesliaces only */
135 #define SBIM_AP_TK 0x20 /* use token only */
136 #define SBIM_AP_RSV 0x30 /* reserved */
137 #define SBIM_IBE 0x20000 /* inbanderror */
138 #define SBIM_TO 0x40000 /* timeout */
139 #define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
140 #define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
143 #define SBTML_RESET 0x0001 /* reset */
144 #define SBTML_REJ_MASK 0x0006 /* reject field */
145 #define SBTML_REJ 0x0002 /* reject */
146 #define SBTML_TMPREJ 0x0004 /* temporary reject, for error recovery */
148 #define SBTML_SICF_SHIFT 16 /* Shift to locate the SI control flags in sbtml */
151 #define SBTMH_SERR 0x0001 /* serror */
152 #define SBTMH_INT 0x0002 /* interrupt */
153 #define SBTMH_BUSY 0x0004 /* busy */
154 #define SBTMH_TO 0x0020 /* timeout (sonics >= 2.3) */
156 #define SBTMH_SISF_SHIFT 16 /* Shift to locate the SI status flags in sbtmh */
159 #define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
160 #define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
161 #define SBBWA_TAB1_SHIFT 16
164 #define SBIMCL_STO_MASK 0x7 /* service timeout */
165 #define SBIMCL_RTO_MASK 0x70 /* request timeout */
166 #define SBIMCL_RTO_SHIFT 4
167 #define SBIMCL_CID_MASK 0xff0000 /* connection id */
168 #define SBIMCL_CID_SHIFT 16
171 #define SBIMCH_IEM_MASK 0xc /* inband error mode */
172 #define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
173 #define SBIMCH_TEM_SHIFT 4
174 #define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
175 #define SBIMCH_BEM_SHIFT 6
178 #define SBAM_TYPE_MASK 0x3 /* address type */
179 #define SBAM_AD64 0x4 /* reserved */
180 #define SBAM_ADINT0_MASK 0xf8 /* type0 size */
181 #define SBAM_ADINT0_SHIFT 3
182 #define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
183 #define SBAM_ADINT1_SHIFT 3
184 #define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
185 #define SBAM_ADINT2_SHIFT 3
186 #define SBAM_ADEN 0x400 /* enable */
187 #define SBAM_ADNEG 0x800 /* negative decode */
188 #define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
189 #define SBAM_BASE0_SHIFT 8
190 #define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
191 #define SBAM_BASE1_SHIFT 12
192 #define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
193 #define SBAM_BASE2_SHIFT 16
196 #define SBTMCL_CD_MASK 0xff /* clock divide */
197 #define SBTMCL_CO_MASK 0xf800 /* clock offset */
198 #define SBTMCL_CO_SHIFT 11
199 #define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
200 #define SBTMCL_IF_SHIFT 18
201 #define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
202 #define SBTMCL_IM_SHIFT 24
205 #define SBTMCH_BM_MASK 0x3 /* busy mode */
206 #define SBTMCH_RM_MASK 0x3 /* retry mode */
207 #define SBTMCH_RM_SHIFT 2
208 #define SBTMCH_SM_MASK 0x30 /* stop mode */
209 #define SBTMCH_SM_SHIFT 4
210 #define SBTMCH_EM_MASK 0x300 /* sb error mode */
211 #define SBTMCH_EM_SHIFT 8
212 #define SBTMCH_IM_MASK 0xc00 /* int mode */
213 #define SBTMCH_IM_SHIFT 10
216 #define SBBC_LAT_MASK 0x3 /* sb latency */
217 #define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
218 #define SBBC_MAX0_SHIFT 16
219 #define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
220 #define SBBC_MAX1_SHIFT 20
223 #define SBBS_SRD 0x1 /* st reg disable */
224 #define SBBS_HRD 0x2 /* hold reg disable */
227 #define SBIDL_CS_MASK 0x3 /* config space */
228 #define SBIDL_AR_MASK 0x38 /* # address ranges supported */
229 #define SBIDL_AR_SHIFT 3
230 #define SBIDL_SYNCH 0x40 /* sync */
231 #define SBIDL_INIT 0x80 /* initiator */
232 #define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
233 #define SBIDL_MINLAT_SHIFT 8
234 #define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
235 #define SBIDL_MAXLAT_SHIFT 12
236 #define SBIDL_FIRST 0x10000 /* this initiator is first */
237 #define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
238 #define SBIDL_CW_SHIFT 18
239 #define SBIDL_TP_MASK 0xf00000 /* target ports */
240 #define SBIDL_TP_SHIFT 20
241 #define SBIDL_IP_MASK 0xf000000 /* initiator ports */
242 #define SBIDL_IP_SHIFT 24
243 #define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
244 #define SBIDL_RV_SHIFT 28
245 #define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
246 #define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
249 #define SBIDH_RC_MASK 0x000f /* revision code */
250 #define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
251 #define SBIDH_RCE_SHIFT 8
252 #define SBCOREREV(sbidh) \
253 ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
254 #define SBIDH_CC_MASK 0x8ff0 /* core code */
255 #define SBIDH_CC_SHIFT 4
256 #define SBIDH_VC_MASK 0xffff0000 /* vendor code */
257 #define SBIDH_VC_SHIFT 16
259 #define SB_COMMIT 0xfd8 /* update buffered registers value */
262 #define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
264 #endif /* _SBCONFIG_H */