2 * Broadcom SiliconBackplane hardware register definitions.
4 * Copyright (C) 1999-2016, Broadcom Corporation
6 * Unless you and Broadcom execute a separate written software license
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12 * As a special exception, the copyright holders of this software give you
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16 * the license of that module. An independent module is a module which is not
17 * derived from this software. The special exception does not apply to any
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20 * Notwithstanding the above, under no circumstances may you combine this
21 * software in any way with any other Broadcom software provided under a license
22 * other than the GPL, without Broadcom's express prior written consent.
25 * <<Broadcom-WL-IPTag/Open:>>
27 * $Id: sbconfig.h 530150 2015-01-29 08:43:40Z $
33 /* cpp contortions to concatenate w/arg prescan */
35 #define _PADLINE(line) pad ## line
36 #define _XSTR(line) _PADLINE(line)
37 #define PAD _XSTR(__LINE__)
40 /* enumeration in SB is based on the premise that cores are contiguos in the
43 #define SB_BUS_SIZE 0x10000 /**< Each bus gets 64Kbytes for cores */
44 #define SB_BUS_BASE(b) (SI_ENUM_BASE + (b) * SB_BUS_SIZE)
45 #define SB_BUS_MAXCORES (SB_BUS_SIZE / SI_CORE_SIZE) /**< Max cores per bus */
48 * Sonics Configuration Space Registers.
50 #define SBCONFIGOFF 0xf00 /**< core sbconfig regs are top 256bytes of regs */
51 #define SBCONFIGSIZE 256 /**< sizeof (sbconfig_t) */
53 #define SBIPSFLAG 0x08
54 #define SBTPSFLAG 0x18
55 #define SBTMERRLOGA 0x48 /**< sonics >= 2.3 */
56 #define SBTMERRLOG 0x50 /**< sonics >= 2.3 */
57 #define SBADMATCH3 0x60
58 #define SBADMATCH2 0x68
59 #define SBADMATCH1 0x70
60 #define SBIMSTATE 0x90
62 #define SBTMSTATELOW 0x98
63 #define SBTMSTATEHIGH 0x9c
65 #define SBIMCONFIGLOW 0xa8
66 #define SBIMCONFIGHIGH 0xac
67 #define SBADMATCH0 0xb0
68 #define SBTMCONFIGLOW 0xb8
69 #define SBTMCONFIGHIGH 0xbc
70 #define SBBCONFIG 0xc0
72 #define SBACTCNFG 0xd8
77 /* All the previous registers are above SBCONFIGOFF, but with Sonics 2.3, we have
78 * a few registers *below* that line. I think it would be very confusing to try
79 * and change the value of SBCONFIGOFF, so I'm definig them as absolute offsets here,
82 #define SBIMERRLOGA 0xea8
83 #define SBIMERRLOG 0xeb0
84 #define SBTMPORTCONNID0 0xed8
85 #define SBTMPORTLOCK0 0xef8
87 #if !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__)
89 typedef volatile struct _sbconfig {
91 uint32 sbipsflag; /**< initiator port ocp slave flag */
93 uint32 sbtpsflag; /**< target port ocp slave flag */
95 uint32 sbtmerrloga; /**< (sonics >= 2.3) */
97 uint32 sbtmerrlog; /**< (sonics >= 2.3) */
99 uint32 sbadmatch3; /**< address match3 */
101 uint32 sbadmatch2; /**< address match2 */
103 uint32 sbadmatch1; /**< address match1 */
105 uint32 sbimstate; /**< initiator agent state */
106 uint32 sbintvec; /**< interrupt mask */
107 uint32 sbtmstatelow; /**< target state */
108 uint32 sbtmstatehigh; /**< target state */
109 uint32 sbbwa0; /**< bandwidth allocation table0 */
111 uint32 sbimconfiglow; /**< initiator configuration */
112 uint32 sbimconfighigh; /**< initiator configuration */
113 uint32 sbadmatch0; /**< address match0 */
115 uint32 sbtmconfiglow; /**< target configuration */
116 uint32 sbtmconfighigh; /**< target configuration */
117 uint32 sbbconfig; /**< broadcast configuration */
119 uint32 sbbstate; /**< broadcast state */
121 uint32 sbactcnfg; /**< activate configuration */
123 uint32 sbflagst; /**< current sbflags */
125 uint32 sbidlow; /**< identification */
126 uint32 sbidhigh; /**< identification */
129 #endif /* !_LANGUAGE_ASSEMBLY && !__ASSEMBLY__ */
132 #define SBIPS_INT1_MASK 0x3f /**< which sbflags get routed to mips interrupt 1 */
133 #define SBIPS_INT1_SHIFT 0
134 #define SBIPS_INT2_MASK 0x3f00 /**< which sbflags get routed to mips interrupt 2 */
135 #define SBIPS_INT2_SHIFT 8
136 #define SBIPS_INT3_MASK 0x3f0000 /**< which sbflags get routed to mips interrupt 3 */
137 #define SBIPS_INT3_SHIFT 16
138 #define SBIPS_INT4_MASK 0x3f000000 /**< which sbflags get routed to mips interrupt 4 */
139 #define SBIPS_INT4_SHIFT 24
142 #define SBTPS_NUM0_MASK 0x3f /**< interrupt sbFlag # generated by this core */
143 #define SBTPS_F0EN0 0x40 /**< interrupt is always sent on the backplane */
146 #define SBTMEL_CM 0x00000007 /**< command */
147 #define SBTMEL_CI 0x0000ff00 /**< connection id */
148 #define SBTMEL_EC 0x0f000000 /**< error code */
149 #define SBTMEL_ME 0x80000000 /**< multiple error */
152 #define SBIM_PC 0xf /**< pipecount */
153 #define SBIM_AP_MASK 0x30 /**< arbitration policy */
154 #define SBIM_AP_BOTH 0x00 /**< use both timeslaces and token */
155 #define SBIM_AP_TS 0x10 /**< use timesliaces only */
156 #define SBIM_AP_TK 0x20 /**< use token only */
157 #define SBIM_AP_RSV 0x30 /**< reserved */
158 #define SBIM_IBE 0x20000 /**< inbanderror */
159 #define SBIM_TO 0x40000 /**< timeout */
160 #define SBIM_BY 0x01800000 /**< busy (sonics >= 2.3) */
161 #define SBIM_RJ 0x02000000 /**< reject (sonics >= 2.3) */
164 #define SBTML_RESET 0x0001 /**< reset */
165 #define SBTML_REJ_MASK 0x0006 /**< reject field */
166 #define SBTML_REJ 0x0002 /**< reject */
167 #define SBTML_TMPREJ 0x0004 /**< temporary reject, for error recovery */
169 #define SBTML_SICF_SHIFT 16 /**< Shift to locate the SI control flags in sbtml */
172 #define SBTMH_SERR 0x0001 /**< serror */
173 #define SBTMH_INT 0x0002 /**< interrupt */
174 #define SBTMH_BUSY 0x0004 /**< busy */
175 #define SBTMH_TO 0x0020 /**< timeout (sonics >= 2.3) */
177 #define SBTMH_SISF_SHIFT 16 /**< Shift to locate the SI status flags in sbtmh */
180 #define SBBWA_TAB0_MASK 0xffff /**< lookup table 0 */
181 #define SBBWA_TAB1_MASK 0xffff /**< lookup table 1 */
182 #define SBBWA_TAB1_SHIFT 16
185 #define SBIMCL_STO_MASK 0x7 /**< service timeout */
186 #define SBIMCL_RTO_MASK 0x70 /**< request timeout */
187 #define SBIMCL_RTO_SHIFT 4
188 #define SBIMCL_CID_MASK 0xff0000 /**< connection id */
189 #define SBIMCL_CID_SHIFT 16
192 #define SBIMCH_IEM_MASK 0xc /**< inband error mode */
193 #define SBIMCH_TEM_MASK 0x30 /**< timeout error mode */
194 #define SBIMCH_TEM_SHIFT 4
195 #define SBIMCH_BEM_MASK 0xc0 /**< bus error mode */
196 #define SBIMCH_BEM_SHIFT 6
199 #define SBAM_TYPE_MASK 0x3 /**< address type */
200 #define SBAM_AD64 0x4 /**< reserved */
201 #define SBAM_ADINT0_MASK 0xf8 /**< type0 size */
202 #define SBAM_ADINT0_SHIFT 3
203 #define SBAM_ADINT1_MASK 0x1f8 /**< type1 size */
204 #define SBAM_ADINT1_SHIFT 3
205 #define SBAM_ADINT2_MASK 0x1f8 /**< type2 size */
206 #define SBAM_ADINT2_SHIFT 3
207 #define SBAM_ADEN 0x400 /**< enable */
208 #define SBAM_ADNEG 0x800 /**< negative decode */
209 #define SBAM_BASE0_MASK 0xffffff00 /**< type0 base address */
210 #define SBAM_BASE0_SHIFT 8
211 #define SBAM_BASE1_MASK 0xfffff000 /**< type1 base address for the core */
212 #define SBAM_BASE1_SHIFT 12
213 #define SBAM_BASE2_MASK 0xffff0000 /**< type2 base address for the core */
214 #define SBAM_BASE2_SHIFT 16
217 #define SBTMCL_CD_MASK 0xff /**< clock divide */
218 #define SBTMCL_CO_MASK 0xf800 /**< clock offset */
219 #define SBTMCL_CO_SHIFT 11
220 #define SBTMCL_IF_MASK 0xfc0000 /**< interrupt flags */
221 #define SBTMCL_IF_SHIFT 18
222 #define SBTMCL_IM_MASK 0x3000000 /**< interrupt mode */
223 #define SBTMCL_IM_SHIFT 24
226 #define SBTMCH_BM_MASK 0x3 /**< busy mode */
227 #define SBTMCH_RM_MASK 0x3 /**< retry mode */
228 #define SBTMCH_RM_SHIFT 2
229 #define SBTMCH_SM_MASK 0x30 /**< stop mode */
230 #define SBTMCH_SM_SHIFT 4
231 #define SBTMCH_EM_MASK 0x300 /**< sb error mode */
232 #define SBTMCH_EM_SHIFT 8
233 #define SBTMCH_IM_MASK 0xc00 /**< int mode */
234 #define SBTMCH_IM_SHIFT 10
237 #define SBBC_LAT_MASK 0x3 /**< sb latency */
238 #define SBBC_MAX0_MASK 0xf0000 /**< maxccntr0 */
239 #define SBBC_MAX0_SHIFT 16
240 #define SBBC_MAX1_MASK 0xf00000 /**< maxccntr1 */
241 #define SBBC_MAX1_SHIFT 20
244 #define SBBS_SRD 0x1 /**< st reg disable */
245 #define SBBS_HRD 0x2 /**< hold reg disable */
248 #define SBIDL_CS_MASK 0x3 /**< config space */
249 #define SBIDL_AR_MASK 0x38 /**< # address ranges supported */
250 #define SBIDL_AR_SHIFT 3
251 #define SBIDL_SYNCH 0x40 /**< sync */
252 #define SBIDL_INIT 0x80 /**< initiator */
253 #define SBIDL_MINLAT_MASK 0xf00 /**< minimum backplane latency */
254 #define SBIDL_MINLAT_SHIFT 8
255 #define SBIDL_MAXLAT 0xf000 /**< maximum backplane latency */
256 #define SBIDL_MAXLAT_SHIFT 12
257 #define SBIDL_FIRST 0x10000 /**< this initiator is first */
258 #define SBIDL_CW_MASK 0xc0000 /**< cycle counter width */
259 #define SBIDL_CW_SHIFT 18
260 #define SBIDL_TP_MASK 0xf00000 /**< target ports */
261 #define SBIDL_TP_SHIFT 20
262 #define SBIDL_IP_MASK 0xf000000 /**< initiator ports */
263 #define SBIDL_IP_SHIFT 24
264 #define SBIDL_RV_MASK 0xf0000000 /**< sonics backplane revision code */
265 #define SBIDL_RV_SHIFT 28
266 #define SBIDL_RV_2_2 0x00000000 /**< version 2.2 or earlier */
267 #define SBIDL_RV_2_3 0x10000000 /**< version 2.3 */
270 #define SBIDH_RC_MASK 0x000f /**< revision code */
271 #define SBIDH_RCE_MASK 0x7000 /**< revision code extension field */
272 #define SBIDH_RCE_SHIFT 8
273 #define SBCOREREV(sbidh) \
274 ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
275 #define SBIDH_CC_MASK 0x8ff0 /**< core code */
276 #define SBIDH_CC_SHIFT 4
277 #define SBIDH_VC_MASK 0xffff0000 /**< vendor code */
278 #define SBIDH_VC_SHIFT 16
280 #define SB_COMMIT 0xfd8 /**< update buffered registers value */
283 #define SB_VEND_BCM 0x4243 /**< Broadcom's SB vendor code */
285 #endif /* _SBCONFIG_H */