2 * MSGBUF network driver ioctl/indication encoding
3 * Broadcom 802.11abg Networking Device Driver
5 * Definitions subject to change without notice.
7 * Copyright (C) 1999-2016, Broadcom Corporation
9 * Unless you and Broadcom execute a separate written software license
10 * agreement governing use of this software, this software is licensed to you
11 * under the terms of the GNU General Public License version 2 (the "GPL"),
12 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
13 * following added to such license:
15 * As a special exception, the copyright holders of this software give you
16 * permission to link this software with independent modules, and to copy and
17 * distribute the resulting executable under terms of your choice, provided that
18 * you also meet, for each linked independent module, the terms and conditions of
19 * the license of that module. An independent module is a module which is not
20 * derived from this software. The special exception does not apply to any
21 * modifications of the software.
23 * Notwithstanding the above, under no circumstances may you combine this
24 * software in any way with any other Broadcom software provided under a license
25 * other than the GPL, without Broadcom's express prior written consent.
28 * <<Broadcom-WL-IPTag/Open:>>
30 * $Id: bcmmsgbuf.h 541060 2015-03-13 23:28:01Z $
35 #include <proto/ethernet.h>
39 #define MSGBUF_MAX_MSG_SIZE ETHER_MAX_LEN
41 #define D2H_EPOCH_MODULO 253 /* sequence number wrap */
42 #define D2H_EPOCH_INIT_VAL (D2H_EPOCH_MODULO + 1)
44 #define H2D_EPOCH_MODULO 253 /* sequence number wrap */
45 #define H2D_EPOCH_INIT_VAL (H2D_EPOCH_MODULO + 1)
47 #define H2DRING_TXPOST_ITEMSIZE 48
48 #define H2DRING_RXPOST_ITEMSIZE 32
49 #define H2DRING_CTRL_SUB_ITEMSIZE 40
50 #define D2HRING_TXCMPLT_ITEMSIZE 16
51 #define D2HRING_RXCMPLT_ITEMSIZE 32
52 #define D2HRING_CTRL_CMPLT_ITEMSIZE 24
54 #define H2DRING_TXPOST_MAX_ITEM 512
55 #define H2DRING_RXPOST_MAX_ITEM 512
56 #define H2DRING_CTRL_SUB_MAX_ITEM 64
57 #define D2HRING_TXCMPLT_MAX_ITEM 1024
58 #define D2HRING_RXCMPLT_MAX_ITEM 512
60 #define D2HRING_CTRL_CMPLT_MAX_ITEM 64
68 HOST_TO_DNGL_TXP_DATA,
69 HOST_TO_DNGL_RXP_DATA,
75 #define MESSAGE_PAYLOAD(a) (a & MSG_TYPE_INTERNAL_USE_START) ? TRUE : FALSE
79 #define BCMMSGBUF_DUMMY_REF(a, b) do {BCM_REFERENCE((a));BCM_REFERENCE((b));} while (0)
81 #define BCMMSGBUF_API_IFIDX(a) 0
82 #define BCMMSGBUF_API_SEQNUM(a) 0
83 #define BCMMSGBUF_IOCTL_XTID(a) 0
84 #define BCMMSGBUF_IOCTL_PKTID(a) ((a)->cmd_id)
86 #define BCMMSGBUF_SET_API_IFIDX(a, b) BCMMSGBUF_DUMMY_REF(a, b)
87 #define BCMMSGBUF_SET_API_SEQNUM(a, b) BCMMSGBUF_DUMMY_REF(a, b)
88 #define BCMMSGBUF_IOCTL_SET_PKTID(a, b) (BCMMSGBUF_IOCTL_PKTID(a) = (b))
89 #define BCMMSGBUF_IOCTL_SET_XTID(a, b) BCMMSGBUF_DUMMY_REF(a, b)
91 #else /* PCIE_API_REV1 */
93 #define BCMMSGBUF_API_IFIDX(a) ((a)->if_id)
94 #define BCMMSGBUF_IOCTL_PKTID(a) ((a)->pkt_id)
95 #define BCMMSGBUF_API_SEQNUM(a) ((a)->u.seq.seq_no)
96 #define BCMMSGBUF_IOCTL_XTID(a) ((a)->xt_id)
98 #define BCMMSGBUF_SET_API_IFIDX(a, b) (BCMMSGBUF_API_IFIDX((a)) = (b))
99 #define BCMMSGBUF_SET_API_SEQNUM(a, b) (BCMMSGBUF_API_SEQNUM((a)) = (b))
100 #define BCMMSGBUF_IOCTL_SET_PKTID(a, b) (BCMMSGBUF_IOCTL_PKTID((a)) = (b))
101 #define BCMMSGBUF_IOCTL_SET_XTID(a, b) (BCMMSGBUF_IOCTL_XTID((a)) = (b))
103 #endif /* PCIE_API_REV1 */
105 /* utility data structures */
119 typedef union addr64 bcm_addr64_t;
123 typedef struct cmn_msg_hdr {
126 /** interface index this is valid for */
130 /** sequence number */
132 /** packet Identifier for the associated host buffer */
137 typedef enum bcmpcie_msgtype {
138 MSG_TYPE_GEN_STATUS = 0x1,
139 MSG_TYPE_RING_STATUS = 0x2,
140 MSG_TYPE_FLOW_RING_CREATE = 0x3,
141 MSG_TYPE_FLOW_RING_CREATE_CMPLT = 0x4,
142 MSG_TYPE_FLOW_RING_DELETE = 0x5,
143 MSG_TYPE_FLOW_RING_DELETE_CMPLT = 0x6,
144 MSG_TYPE_FLOW_RING_FLUSH = 0x7,
145 MSG_TYPE_FLOW_RING_FLUSH_CMPLT = 0x8,
146 MSG_TYPE_IOCTLPTR_REQ = 0x9,
147 MSG_TYPE_IOCTLPTR_REQ_ACK = 0xA,
148 MSG_TYPE_IOCTLRESP_BUF_POST = 0xB,
149 MSG_TYPE_IOCTL_CMPLT = 0xC,
150 MSG_TYPE_EVENT_BUF_POST = 0xD,
151 MSG_TYPE_WL_EVENT = 0xE,
152 MSG_TYPE_TX_POST = 0xF,
153 MSG_TYPE_TX_STATUS = 0x10,
154 MSG_TYPE_RXBUF_POST = 0x11,
155 MSG_TYPE_RX_CMPLT = 0x12,
156 MSG_TYPE_LPBK_DMAXFER = 0x13,
157 MSG_TYPE_LPBK_DMAXFER_CMPLT = 0x14,
158 MSG_TYPE_FLOW_RING_RESUME = 0x15,
159 MSG_TYPE_FLOW_RING_RESUME_CMPLT = 0x16,
160 MSG_TYPE_FLOW_RING_SUSPEND = 0x17,
161 MSG_TYPE_FLOW_RING_SUSPEND_CMPLT = 0x18,
162 MSG_TYPE_INFO_BUF_POST = 0x19,
163 MSG_TYPE_INFO_BUF_CMPLT = 0x1A,
164 MSG_TYPE_H2D_RING_CREATE = 0x1B,
165 MSG_TYPE_D2H_RING_CREATE = 0x1C,
166 MSG_TYPE_H2D_RING_CREATE_CMPLT = 0x1D,
167 MSG_TYPE_D2H_RING_CREATE_CMPLT = 0x1E,
168 MSG_TYPE_H2D_RING_CONFIG = 0x1F,
169 MSG_TYPE_D2H_RING_CONFIG = 0x20,
170 MSG_TYPE_H2D_RING_CONFIG_CMPLT = 0x21,
171 MSG_TYPE_D2H_RING_CONFIG_CMPLT = 0x22,
172 MSG_TYPE_H2D_MAILBOX_DATA = 0x23,
173 MSG_TYPE_D2H_MAILBOX_DATA = 0x24,
175 MSG_TYPE_API_MAX_RSVD = 0x3F
176 } bcmpcie_msg_type_t;
178 typedef enum bcmpcie_msgtype_int {
179 MSG_TYPE_INTERNAL_USE_START = 0x40,
180 MSG_TYPE_EVENT_PYLD = 0x41,
181 MSG_TYPE_IOCT_PYLD = 0x42,
182 MSG_TYPE_RX_PYLD = 0x43,
183 MSG_TYPE_HOST_FETCH = 0x44,
184 MSG_TYPE_LPBK_DMAXFER_PYLD = 0x45,
185 MSG_TYPE_TXMETADATA_PYLD = 0x46,
186 MSG_TYPE_INDX_UPDATE = 0x47
187 } bcmpcie_msgtype_int_t;
189 typedef enum bcmpcie_msgtype_u {
190 MSG_TYPE_TX_BATCH_POST = 0x80,
191 MSG_TYPE_IOCTL_REQ = 0x81,
192 MSG_TYPE_HOST_EVNT = 0x82, /* console related */
193 MSG_TYPE_LOOPBACK = 0x83
194 } bcmpcie_msgtype_u_t;
197 * D2H ring host wakeup soft doorbell, override the PCIE doorbell.
198 * Host configures an <32bit address,value> tuple, and dongle uses SBTOPCIE
199 * Transl0 to write specified value to host address.
201 * Use case: 32bit Address mapped to HW Accelerator Core/Thread Wakeup Register
202 * and value is Core/Thread context. Host will ensure routing the 32bit address
203 * offerred to PCIE to the mapped register.
205 * D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL
207 typedef struct bcmpcie_soft_doorbell {
208 uint32 value; /* host defined value to be written, eg HW threadid */
209 bcm_addr64_t haddr; /* host address, eg thread wakeup register address */
210 uint16 items; /* interrupt coalescing: item count before wakeup */
211 uint16 msecs; /* interrupt coalescing: timeout in millisecs */
212 } bcmpcie_soft_doorbell_t;
216 #define BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT 5
217 #define BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX 0x7
218 #define BCMPCIE_CMNHDR_IFIDX_PHYINTF_MASK \
219 (BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX << BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT)
220 #define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_SHFT 0
221 #define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_MAX 0x1F
222 #define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_MASK \
223 (BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX << BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT)
226 #define BCMPCIE_CMNHDR_FLAGS_DMA_R_IDX 0x1
227 #define BCMPCIE_CMNHDR_FLAGS_DMA_R_IDX_INTR 0x2
228 #define BCMPCIE_CMNHDR_FLAGS_PHASE_BIT 0x80
231 /* IOCTL request message */
232 typedef struct ioctl_req_msg {
233 /** common message header */
234 cmn_msg_hdr_t cmn_hdr;
235 /** ioctl command type */
237 /** ioctl transaction ID, to pair with a ioctl response */
239 /** input arguments buffer len */
240 uint16 input_buf_len;
241 /** expected output len */
242 uint16 output_buf_len;
243 /** to align the host address on 8 byte boundary */
245 /** always align on 8 byte boundary */
246 bcm_addr64_t host_input_buf_addr;
251 /** buffer post messages for device to use to return IOCTL responses, Events */
252 typedef struct ioctl_resp_evt_buf_post_msg {
253 /** common message header */
254 cmn_msg_hdr_t cmn_hdr;
255 /** length of the host buffer supplied */
257 /** to align the host address on 8 byte boundary */
259 /** always align on 8 byte boundary */
260 bcm_addr64_t host_buf_addr;
262 } ioctl_resp_evt_buf_post_msg_t;
265 typedef struct pcie_dma_xfer_params {
266 /** common message header */
267 cmn_msg_hdr_t cmn_hdr;
269 /** always align on 8 byte boundary */
270 bcm_addr64_t host_input_buf_addr;
272 /** always align on 8 byte boundary */
273 bcm_addr64_t host_ouput_buf_addr;
275 /** length of transfer */
277 /** delay before doing the src txfer */
279 /** delay before doing the dest txfer */
282 } pcie_dma_xfer_params_t;
284 /** Complete msgbuf hdr for flow ring update from host to dongle */
285 typedef struct tx_flowring_create_request {
287 uint8 da[ETHER_ADDR_LEN];
288 uint8 sa[ETHER_ADDR_LEN];
297 bcm_addr64_t flow_ring_ptr;
298 } tx_flowring_create_request_t;
300 typedef struct tx_flowring_delete_request {
305 } tx_flowring_delete_request_t;
307 typedef struct tx_flowring_flush_request {
312 } tx_flowring_flush_request_t;
314 /** Subtypes for ring_config_req control message */
315 typedef enum ring_config_subtype {
316 /** Default D2H PCIE doorbell override using ring_config_req msg */
317 D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL = 1, /* Software doorbell */
318 D2H_RING_CONFIG_SUBTYPE_MSI_DOORBELL = 2 /* MSI configuration */
319 } ring_config_subtype_t;
321 typedef struct ring_config_req {
328 /** D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL */
329 bcmpcie_soft_doorbell_t soft_doorbell;
333 typedef union ctrl_submit_item {
334 ioctl_req_msg_t ioctl_req;
335 ioctl_resp_evt_buf_post_msg_t resp_buf_post;
336 pcie_dma_xfer_params_t dma_xfer;
337 tx_flowring_create_request_t flow_create;
338 tx_flowring_delete_request_t flow_delete;
339 tx_flowring_flush_request_t flow_flush;
340 ring_config_req_t ring_config_req;
341 unsigned char check[H2DRING_CTRL_SUB_ITEMSIZE];
342 } ctrl_submit_item_t;
344 /** Control Completion messages (20 bytes) */
345 typedef struct compl_msg_hdr {
346 /** status for the completion */
348 /** submisison flow ring id which generated this status */
352 /** XOR checksum or a magic number to audit DMA done */
353 typedef uint32 dma_done_t;
355 /* completion header status codes */
356 #define BCMPCIE_SUCCESS 0
357 #define BCMPCIE_NOTFOUND 1
358 #define BCMPCIE_NOMEM 2
359 #define BCMPCIE_BADOPTION 3
360 #define BCMPCIE_RING_IN_USE 4
361 #define BCMPCIE_RING_ID_INVALID 5
362 #define BCMPCIE_PKT_FLUSH 6
363 #define BCMPCIE_NO_EVENT_BUF 7
364 #define BCMPCIE_NO_RX_BUF 8
365 #define BCMPCIE_NO_IOCTLRESP_BUF 9
366 #define BCMPCIE_MAX_IOCTLRESP_BUF 10
367 #define BCMPCIE_MAX_EVENT_BUF 11
369 /** IOCTL completion response */
370 typedef struct ioctl_compl_resp_msg {
371 /** common message header */
372 cmn_msg_hdr_t cmn_hdr;
373 /** completion message header */
374 compl_msg_hdr_t compl_hdr;
375 /** response buffer len where a host buffer is involved */
377 /** transaction id to pair with a request */
381 /** XOR checksum or a magic number to audit DMA done */
383 } ioctl_comp_resp_msg_t;
385 /** IOCTL request acknowledgement */
386 typedef struct ioctl_req_ack_msg {
387 /** common message header */
388 cmn_msg_hdr_t cmn_hdr;
389 /** completion message header */
390 compl_msg_hdr_t compl_hdr;
394 /** XOR checksum or a magic number to audit DMA done */
396 } ioctl_req_ack_msg_t;
398 /** WL event message: send from device to host */
399 typedef struct wlevent_req_msg {
400 /** common message header */
401 cmn_msg_hdr_t cmn_hdr;
402 /** completion message header */
403 compl_msg_hdr_t compl_hdr;
404 /** event data len valid with the event buffer */
405 uint16 event_data_len;
406 /** sequence number */
410 /** XOR checksum or a magic number to audit DMA done */
414 /** dma xfer complete message */
415 typedef struct pcie_dmaxfer_cmplt {
416 /** common message header */
417 cmn_msg_hdr_t cmn_hdr;
418 /** completion message header */
419 compl_msg_hdr_t compl_hdr;
421 /** XOR checksum or a magic number to audit DMA done */
423 } pcie_dmaxfer_cmplt_t;
425 /** general status message */
426 typedef struct pcie_gen_status {
427 /** common message header */
428 cmn_msg_hdr_t cmn_hdr;
429 /** completion message header */
430 compl_msg_hdr_t compl_hdr;
432 /** XOR checksum or a magic number to audit DMA done */
436 /** ring status message */
437 typedef struct pcie_ring_status {
438 /** common message header */
439 cmn_msg_hdr_t cmn_hdr;
440 /** completion message header */
441 compl_msg_hdr_t compl_hdr;
442 /** message which firmware couldn't decode */
445 /** XOR checksum or a magic number to audit DMA done */
447 } pcie_ring_status_t;
449 typedef struct tx_flowring_create_response {
451 compl_msg_hdr_t cmplt;
453 /** XOR checksum or a magic number to audit DMA done */
455 } tx_flowring_create_response_t;
457 typedef struct tx_flowring_delete_response {
459 compl_msg_hdr_t cmplt;
461 /** XOR checksum or a magic number to audit DMA done */
463 } tx_flowring_delete_response_t;
465 typedef struct tx_flowring_flush_response {
467 compl_msg_hdr_t cmplt;
469 /** XOR checksum or a magic number to audit DMA done */
471 } tx_flowring_flush_response_t;
473 /** Common layout of all d2h control messages */
474 typedef struct ctrl_compl_msg {
475 /** common message header */
476 cmn_msg_hdr_t cmn_hdr;
477 /** completion message header */
478 compl_msg_hdr_t compl_hdr;
480 /** XOR checksum or a magic number to audit DMA done */
484 typedef struct ring_config_resp {
485 /** common message header */
486 cmn_msg_hdr_t cmn_hdr;
487 /** completion message header */
488 compl_msg_hdr_t compl_hdr;
490 /** XOR checksum or a magic number to audit DMA done */
492 } ring_config_resp_t;
494 typedef union ctrl_completion_item {
495 ioctl_comp_resp_msg_t ioctl_resp;
496 wlevent_req_msg_t event;
497 ioctl_req_ack_msg_t ioct_ack;
498 pcie_dmaxfer_cmplt_t pcie_xfer_cmplt;
499 pcie_gen_status_t pcie_gen_status;
500 pcie_ring_status_t pcie_ring_status;
501 tx_flowring_create_response_t txfl_create_resp;
502 tx_flowring_delete_response_t txfl_delete_resp;
503 tx_flowring_flush_response_t txfl_flush_resp;
504 ctrl_compl_msg_t ctrl_compl;
505 ring_config_resp_t ring_config_resp;
506 unsigned char check[D2HRING_CTRL_CMPLT_ITEMSIZE];
507 } ctrl_completion_item_t;
509 /** H2D Rxpost ring work items */
510 typedef struct host_rxbuf_post {
511 /** common message header */
512 cmn_msg_hdr_t cmn_hdr;
513 /** provided meta data buffer len */
514 uint16 metadata_buf_len;
515 /** provided data buffer len to receive data */
517 /** alignment to make the host buffers start on 8 byte boundary */
519 /** provided meta data buffer */
520 bcm_addr64_t metadata_buf_addr;
521 /** provided data buffer to receive data */
522 bcm_addr64_t data_buf_addr;
525 typedef union rxbuf_submit_item {
526 host_rxbuf_post_t rxpost;
527 unsigned char check[H2DRING_RXPOST_ITEMSIZE];
528 } rxbuf_submit_item_t;
531 /** D2H Rxcompletion ring work items */
532 typedef struct host_rxbuf_cmpl {
533 /** common message header */
534 cmn_msg_hdr_t cmn_hdr;
535 /** completion message header */
536 compl_msg_hdr_t compl_hdr;
537 /** filled up meta data len */
539 /** filled up buffer len to receive data */
541 /** offset in the host rx buffer where the data starts */
543 /** offset in the host rx buffer where the data starts */
548 /** XOR checksum or a magic number to audit DMA done */
552 typedef union rxbuf_complete_item {
553 host_rxbuf_cmpl_t rxcmpl;
554 unsigned char check[D2HRING_RXCMPLT_ITEMSIZE];
555 } rxbuf_complete_item_t;
558 typedef struct host_txbuf_post {
559 /** common message header */
560 cmn_msg_hdr_t cmn_hdr;
562 uint8 txhdr[ETHER_HDR_LEN];
565 /** number of segments */
568 /** provided meta data buffer for txstatus */
569 bcm_addr64_t metadata_buf_addr;
570 /** provided data buffer to receive data */
571 bcm_addr64_t data_buf_addr;
572 /** provided meta data buffer len */
573 uint16 metadata_buf_len;
574 /** provided data buffer len to receive data */
576 /** XOR checksum or a magic number to audit DMA done */
580 #define BCMPCIE_PKT_FLAGS_FRAME_802_3 0x01
581 #define BCMPCIE_PKT_FLAGS_FRAME_802_11 0x02
583 #define BCMPCIE_PKT_FLAGS_FRAME_EXEMPT_MASK 0x03 /* Exempt uses 2 bits */
584 #define BCMPCIE_PKT_FLAGS_FRAME_EXEMPT_SHIFT 0x02 /* needs to be shifted past other bits */
587 #define BCMPCIE_PKT_FLAGS_PRIO_SHIFT 5
588 #define BCMPCIE_PKT_FLAGS_PRIO_MASK (7 << BCMPCIE_PKT_FLAGS_PRIO_SHIFT)
590 /* These are added to fix up compile issues */
591 #define BCMPCIE_TXPOST_FLAGS_FRAME_802_3 BCMPCIE_PKT_FLAGS_FRAME_802_3
592 #define BCMPCIE_TXPOST_FLAGS_FRAME_802_11 BCMPCIE_PKT_FLAGS_FRAME_802_11
593 #define BCMPCIE_TXPOST_FLAGS_PRIO_SHIFT BCMPCIE_PKT_FLAGS_PRIO_SHIFT
594 #define BCMPCIE_TXPOST_FLAGS_PRIO_MASK BCMPCIE_PKT_FLAGS_PRIO_MASK
596 /** H2D Txpost ring work items */
597 typedef union txbuf_submit_item {
598 host_txbuf_post_t txpost;
599 unsigned char check[H2DRING_TXPOST_ITEMSIZE];
600 } txbuf_submit_item_t;
602 /** D2H Txcompletion ring work items */
603 typedef struct host_txbuf_cmpl {
604 /** common message header */
605 cmn_msg_hdr_t cmn_hdr;
606 /** completion message header */
607 compl_msg_hdr_t compl_hdr;
610 /** provided meta data len */
612 /** WLAN side txstatus */
615 /** XOR checksum or a magic number to audit DMA done */
620 typedef union txbuf_complete_item {
621 host_txbuf_cmpl_t txcmpl;
622 unsigned char check[D2HRING_TXCMPLT_ITEMSIZE];
623 } txbuf_complete_item_t;
625 #define BCMPCIE_D2H_METADATA_HDRLEN 4
626 #define BCMPCIE_D2H_METADATA_MINLEN (BCMPCIE_D2H_METADATA_HDRLEN + 4)
628 /** ret buf struct */
629 typedef struct ret_buf_ptr {
637 /* ioctl specific hdr */
638 typedef struct ioctl_hdr {
644 typedef struct ioctlptr_hdr {
652 #else /* PCIE_API_REV1 */
654 typedef struct ioctl_req_hdr {
655 uint32 pkt_id; /**< Packet ID */
656 uint32 cmd; /**< IOCTL ID */
659 uint16 xt_id; /**< transaction ID */
663 #endif /* PCIE_API_REV1 */
666 /** Complete msgbuf hdr for ioctl from host to dongle */
667 typedef struct ioct_reqst_hdr {
670 ioctl_hdr_t ioct_hdr;
672 ioctl_req_hdr_t ioct_hdr;
677 typedef struct ioctptr_reqst_hdr {
680 ioctlptr_hdr_t ioct_hdr;
682 ioctl_req_hdr_t ioct_hdr;
686 } ioctptr_reqst_hdr_t;
688 /** ioctl response header */
689 typedef struct ioct_resp_hdr {
701 uint16 xt_id; /**< transaction ID */
706 /* ioct resp header used in dongle */
707 /* ret buf hdr will be stripped off inside dongle itself */
708 typedef struct msgbuf_ioctl_resp {
709 ioct_resp_hdr_t ioct_hdr;
710 ret_buf_t ret_buf; /**< ret buf pointers */
711 } msgbuf_ioct_resp_t;
713 /** WL event hdr info */
714 typedef struct wl_event_hdr {
724 #define TXDESCR_FLOWID_PCIELPBK_1 0xFF
725 #define TXDESCR_FLOWID_PCIELPBK_2 0xFE
727 typedef struct txbatch_lenptr_tup {
731 ret_buf_t ret_buf; /**< ret buf pointers */
732 } txbatch_lenptr_tup_t;
734 typedef struct txbatch_cmn_msghdr {
740 uint8 txhdr[ETHER_HDR_LEN];
742 } txbatch_cmn_msghdr_t;
744 typedef struct txbatch_msghdr {
745 txbatch_cmn_msghdr_t txcmn;
746 txbatch_lenptr_tup_t tx_tup[0]; /**< Based on packet count */
749 /* TX desc posting header */
750 typedef struct tx_lenptr_tup {
753 ret_buf_t ret_buf; /**< ret buf pointers */
756 typedef struct txdescr_cmn_msghdr {
763 } txdescr_cmn_msghdr_t;
765 typedef struct txdescr_msghdr {
766 txdescr_cmn_msghdr_t txcmn;
767 uint8 txhdr[ETHER_HDR_LEN];
769 tx_lenptr_tup_t tx_tup[0]; /**< Based on descriptor count */
772 /** Tx status header info */
773 typedef struct txstatus_hdr {
778 /** RX bufid-len-ptr tuple */
779 typedef struct rx_lenptr_tup {
783 ret_buf_t ret_buf; /**< ret buf pointers */
786 /** Rx descr Post hdr info */
787 typedef struct rxdesc_msghdr {
792 rx_lenptr_tup_t rx_tup[0];
795 /** RX complete tuples */
796 typedef struct rxcmplt_tup {
804 /** RX complete messge hdr */
805 typedef struct rxcmplt_hdr {
809 rxcmplt_tup_t rx_tup[0];
812 typedef struct hostevent_hdr {
817 typedef struct dma_xfer_params {
818 uint32 src_physaddr_hi;
819 uint32 src_physaddr_lo;
820 uint32 dest_physaddr_hi;
821 uint32 dest_physaddr_lo;
828 HOST_EVENT_CONS_CMD = 1
831 /* defines for flags */
832 #define MSGBUF_IOC_ACTION_MASK 0x1
834 #define MAX_SUSPEND_REQ 15
836 typedef struct tx_idle_flowring_suspend_request {
838 uint16 ring_id[MAX_SUSPEND_REQ]; /**< ring Id's */
839 uint16 num; /**< number of flowid's to suspend */
840 } tx_idle_flowring_suspend_request_t;
842 typedef struct tx_idle_flowring_suspend_response {
844 compl_msg_hdr_t cmplt;
847 } tx_idle_flowring_suspend_response_t;
849 typedef struct tx_idle_flowring_resume_request {
854 } tx_idle_flowring_resume_request_t;
856 typedef struct tx_idle_flowring_resume_response {
858 compl_msg_hdr_t cmplt;
861 } tx_idle_flowring_resume_response_t;
863 #endif /* _bcmmsgbuf_h_ */