2 * Broadcom device-specific manifest constants.
4 * Copyright (C) 1999-2016, Broadcom Corporation
6 * Unless you and Broadcom execute a separate written software license
7 * agreement governing use of this software, this software is licensed to you
8 * under the terms of the GNU General Public License version 2 (the "GPL"),
9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
10 * following added to such license:
12 * As a special exception, the copyright holders of this software give you
13 * permission to link this software with independent modules, and to copy and
14 * distribute the resulting executable under terms of your choice, provided that
15 * you also meet, for each linked independent module, the terms and conditions of
16 * the license of that module. An independent module is a module which is not
17 * derived from this software. The special exception does not apply to any
18 * modifications of the software.
20 * Notwithstanding the above, under no circumstances may you combine this
21 * software in any way with any other Broadcom software provided under a license
22 * other than the GPL, without Broadcom's express prior written consent.
25 * <<Broadcom-WL-IPTag/Open:>>
27 * $Id: bcmdevs.h 582052 2015-08-26 09:30:53Z $
34 #define VENDOR_EPIGRAM 0xfeda
35 #define VENDOR_BROADCOM 0x14e4
36 #define VENDOR_3COM 0x10b7
37 #define VENDOR_NETGEAR 0x1385
38 #define VENDOR_DIAMOND 0x1092
39 #define VENDOR_INTEL 0x8086
40 #define VENDOR_DELL 0x1028
41 #define VENDOR_HP 0x103c
42 #define VENDOR_HP_COMPAQ 0x0e11
43 #define VENDOR_APPLE 0x106b
44 #define VENDOR_SI_IMAGE 0x1095 /* Silicon Image, used by Arasan SDIO Host */
45 #define VENDOR_BUFFALO 0x1154 /* Buffalo vendor id */
46 #define VENDOR_TI 0x104c /* Texas Instruments */
47 #define VENDOR_RICOH 0x1180 /* Ricoh */
48 #define VENDOR_JMICRON 0x197b
51 /* PCMCIA vendor IDs */
52 #define VENDOR_BROADCOM_PCMCIA 0x02d0
55 #define VENDOR_BROADCOM_SDIO 0x00BF
58 #define BCM_DNGL_VID 0x0a5c
59 #define BCM_DNGL_BL_PID_4328 0xbd12
60 #define BCM_DNGL_BL_PID_4322 0xbd13
61 #define BCM_DNGL_BL_PID_4319 0xbd16
62 #define BCM_DNGL_BL_PID_43236 0xbd17
63 #define BCM_DNGL_BL_PID_4332 0xbd18
64 #define BCM_DNGL_BL_PID_4330 0xbd19
65 #define BCM_DNGL_BL_PID_4334 0xbd1a
66 #define BCM_DNGL_BL_PID_43239 0xbd1b
67 #define BCM_DNGL_BL_PID_4324 0xbd1c
68 #define BCM_DNGL_BL_PID_4360 0xbd1d
69 #define BCM_DNGL_BL_PID_43143 0xbd1e
70 #define BCM_DNGL_BL_PID_43242 0xbd1f
71 #define BCM_DNGL_BL_PID_43342 0xbd21
72 #define BCM_DNGL_BL_PID_4335 0xbd20
73 #define BCM_DNGL_BL_PID_43341 0xbd22
74 #define BCM_DNGL_BL_PID_4350 0xbd23
75 #define BCM_DNGL_BL_PID_4345 0xbd24
76 #define BCM_DNGL_BL_PID_4349 0xbd25
77 #define BCM_DNGL_BL_PID_4354 0xbd26
78 #define BCM_DNGL_BL_PID_43569 0xbd27
79 #define BCM_DNGL_BL_PID_43909 0xbd28
81 #define BCM_DNGL_BDC_PID 0x0bdc
82 #define BCM_DNGL_JTAG_PID 0x4a44
84 /* HW USB BLOCK [CPULESS USB] PIDs */
85 #define BCM_HWUSB_PID_43239 43239
88 #define BCM4210_DEVICE_ID 0x1072 /* never used */
89 #define BCM4230_DEVICE_ID 0x1086 /* never used */
90 #define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
91 #define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
92 #define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
93 #define BCM4211_DEVICE_ID 0x4211
94 #define BCM4231_DEVICE_ID 0x4231
95 #define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
96 #define BCM4311_D11G_ID 0x4311 /* 4311 802.11b/g id */
97 #define BCM4311_D11DUAL_ID 0x4312 /* 4311 802.11a/b/g id */
98 #define BCM4311_D11A_ID 0x4313 /* 4311 802.11a id */
99 #define BCM4328_D11DUAL_ID 0x4314 /* 4328/4312 802.11a/g id */
100 #define BCM4328_D11G_ID 0x4315 /* 4328/4312 802.11g id */
101 #define BCM4328_D11A_ID 0x4316 /* 4328/4312 802.11a id */
102 #define BCM4318_D11G_ID 0x4318 /* 4318 802.11b/g id */
103 #define BCM4318_D11DUAL_ID 0x4319 /* 4318 802.11a/b/g id */
104 #define BCM4318_D11A_ID 0x431a /* 4318 802.11a id */
105 #define BCM4325_D11DUAL_ID 0x431b /* 4325 802.11a/g id */
106 #define BCM4325_D11G_ID 0x431c /* 4325 802.11g id */
107 #define BCM4325_D11A_ID 0x431d /* 4325 802.11a id */
108 #define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
109 #define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
110 #define BCM4306_UART_ID 0x4322 /* 4306 uart */
111 #define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
112 #define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
113 #define BCM4306_D11G_ID2 0x4325 /* BCM4306_D11G_ID; INF w/loose binding war */
114 #define BCM4321_D11N_ID 0x4328 /* 4321 802.11n dualband id */
115 #define BCM4321_D11N2G_ID 0x4329 /* 4321 802.11n 2.4Ghz band id */
116 #define BCM4321_D11N5G_ID 0x432a /* 4321 802.11n 5Ghz band id */
117 #define BCM4322_D11N_ID 0x432b /* 4322 802.11n dualband device */
118 #define BCM4322_D11N2G_ID 0x432c /* 4322 802.11n 2.4GHz device */
119 #define BCM4322_D11N5G_ID 0x432d /* 4322 802.11n 5GHz device */
120 #define BCM4329_D11N_ID 0x432e /* 4329 802.11n dualband device */
121 #define BCM4329_D11N2G_ID 0x432f /* 4329 802.11n 2.4G device */
122 #define BCM4329_D11N5G_ID 0x4330 /* 4329 802.11n 5G device */
123 #define BCM4315_D11DUAL_ID 0x4334 /* 4315 802.11a/g id */
124 #define BCM4315_D11G_ID 0x4335 /* 4315 802.11g id */
125 #define BCM4315_D11A_ID 0x4336 /* 4315 802.11a id */
126 #define BCM4319_D11N_ID 0x4337 /* 4319 802.11n dualband device */
127 #define BCM4319_D11N2G_ID 0x4338 /* 4319 802.11n 2.4G device */
128 #define BCM4319_D11N5G_ID 0x4339 /* 4319 802.11n 5G device */
129 #define BCM43231_D11N2G_ID 0x4340 /* 43231 802.11n 2.4GHz device */
130 #define BCM43221_D11N2G_ID 0x4341 /* 43221 802.11n 2.4GHz device */
131 #define BCM43222_D11N_ID 0x4350 /* 43222 802.11n dualband device */
132 #define BCM43222_D11N2G_ID 0x4351 /* 43222 802.11n 2.4GHz device */
133 #define BCM43222_D11N5G_ID 0x4352 /* 43222 802.11n 5GHz device */
134 #define BCM43224_D11N_ID 0x4353 /* 43224 802.11n dualband device */
135 #define BCM43224_D11N_ID_VEN1 0x0576 /* Vendor specific 43224 802.11n db device */
136 #define BCM43226_D11N_ID 0x4354 /* 43226 802.11n dualband device */
137 #define BCM43236_D11N_ID 0x4346 /* 43236 802.11n dualband device */
138 #define BCM43236_D11N2G_ID 0x4347 /* 43236 802.11n 2.4GHz device */
139 #define BCM43236_D11N5G_ID 0x4348 /* 43236 802.11n 5GHz device */
140 #define BCM43225_D11N2G_ID 0x4357 /* 43225 802.11n 2.4GHz device */
141 #define BCM43421_D11N_ID 0xA99D /* 43421 802.11n dualband device */
142 #define BCM4313_D11N2G_ID 0x4727 /* 4313 802.11n 2.4G device */
143 #define BCM4330_D11N_ID 0x4360 /* 4330 802.11n dualband device */
144 #define BCM4330_D11N2G_ID 0x4361 /* 4330 802.11n 2.4G device */
145 #define BCM4330_D11N5G_ID 0x4362 /* 4330 802.11n 5G device */
146 #define BCM4336_D11N_ID 0x4343 /* 4336 802.11n 2.4GHz device */
147 #define BCM6362_D11N_ID 0x435f /* 6362 802.11n dualband device */
148 #define BCM6362_D11N2G_ID 0x433f /* 6362 802.11n 2.4Ghz band id */
149 #define BCM6362_D11N5G_ID 0x434f /* 6362 802.11n 5Ghz band id */
150 #define BCM4331_D11N_ID 0x4331 /* 4331 802.11n dualband id */
151 #define BCM4331_D11N2G_ID 0x4332 /* 4331 802.11n 2.4Ghz band id */
152 #define BCM4331_D11N5G_ID 0x4333 /* 4331 802.11n 5Ghz band id */
153 #define BCM43237_D11N_ID 0x4355 /* 43237 802.11n dualband device */
154 #define BCM43237_D11N5G_ID 0x4356 /* 43237 802.11n 5GHz device */
155 #define BCM43227_D11N2G_ID 0x4358 /* 43228 802.11n 2.4GHz device */
156 #define BCM43228_D11N_ID 0x4359 /* 43228 802.11n DualBand device */
157 #define BCM43228_D11N5G_ID 0x435a /* 43228 802.11n 5GHz device */
158 #define BCM43362_D11N_ID 0x4363 /* 43362 802.11n 2.4GHz device */
159 #define BCM43239_D11N_ID 0x4370 /* 43239 802.11n dualband device */
160 #define BCM4324_D11N_ID 0x4374 /* 4324 802.11n dualband device */
161 #define BCM43217_D11N2G_ID 0x43a9 /* 43217 802.11n 2.4GHz device */
162 #define BCM43131_D11N2G_ID 0x43aa /* 43131 802.11n 2.4GHz device */
163 #define BCM4314_D11N2G_ID 0x4364 /* 4314 802.11n 2.4G device */
164 #define BCM43142_D11N2G_ID 0x4365 /* 43142 802.11n 2.4G device */
165 #define BCM43143_D11N2G_ID 0x4366 /* 43143 802.11n 2.4G device */
166 #define BCM4334_D11N_ID 0x4380 /* 4334 802.11n dualband device */
167 #define BCM4334_D11N2G_ID 0x4381 /* 4334 802.11n 2.4G device */
168 #define BCM4334_D11N5G_ID 0x4382 /* 4334 802.11n 5G device */
169 #define BCM43342_D11N_ID 0x4383 /* 43342 802.11n dualband device */
170 #define BCM43342_D11N2G_ID 0x4384 /* 43342 802.11n 2.4G device */
171 #define BCM43342_D11N5G_ID 0x4385 /* 43342 802.11n 5G device */
172 #define BCM43341_D11N_ID 0x4386 /* 43341 802.11n dualband device */
173 #define BCM43341_D11N2G_ID 0x4387 /* 43341 802.11n 2.4G device */
174 #define BCM43341_D11N5G_ID 0x4388 /* 43341 802.11n 5G device */
175 #define BCM4360_D11AC_ID 0x43a0
176 #define BCM4360_D11AC2G_ID 0x43a1
177 #define BCM4360_D11AC5G_ID 0x43a2
178 #define BCM4345_D11AC_ID 0x43ab /* 4345 802.11ac dualband device */
179 #define BCM4345_D11AC2G_ID 0x43ac /* 4345 802.11ac 2.4G device */
180 #define BCM4345_D11AC5G_ID 0x43ad /* 4345 802.11ac 5G device */
181 #define BCM4335_D11AC_ID 0x43ae
182 #define BCM4335_D11AC2G_ID 0x43af
183 #define BCM4335_D11AC5G_ID 0x43b0
184 #define BCM4352_D11AC_ID 0x43b1 /* 4352 802.11ac dualband device */
185 #define BCM4352_D11AC2G_ID 0x43b2 /* 4352 802.11ac 2.4G device */
186 #define BCM4352_D11AC5G_ID 0x43b3 /* 4352 802.11ac 5G device */
187 #define BCM43602_D11AC_ID 0x43ba /* ac dualband PCI devid SPROM programmed */
188 #define BCM43602_D11AC2G_ID 0x43bb /* 43602 802.11ac 2.4G device */
189 #define BCM43602_D11AC5G_ID 0x43bc /* 43602 802.11ac 5G device */
190 #define BCM4349_D11AC_ID 0x4349 /* 4349 802.11ac dualband device */
191 #define BCM4349_D11AC2G_ID 0x43dd /* 4349 802.11ac 2.4G device */
192 #define BCM4349_D11AC5G_ID 0x43de /* 4349 802.11ac 5G device */
193 #define BCM53573_D11AC_ID 0x43b4 /* 53573 802.11ac dualband device */
194 #define BCM53573_D11AC2G_ID 0x43b5 /* 53573 802.11ac 2.4G device */
195 #define BCM53573_D11AC5G_ID 0x43b6 /* 53573 802.11ac 5G device */
196 #define BCM47189_D11AC_ID 0x43c6 /* 47189 802.11ac dualband device */
197 #define BCM47189_D11AC2G_ID 0x43c7 /* 47189 802.11ac 2.4G device */
198 #define BCM47189_D11AC5G_ID 0x43c8 /* 47189 802.11ac 5G device */
199 #define BCM4355_D11AC_ID 0x43dc /* 4355 802.11ac dualband device */
200 #define BCM4355_D11AC2G_ID 0x43fc /* 4355 802.11ac 2.4G device */
201 #define BCM4355_D11AC5G_ID 0x43fd /* 4355 802.11ac 5G device */
202 #define BCM4359_D11AC_ID 0x43ef /* 4359 802.11ac dualband device */
203 #define BCM4359_D11AC2G_ID 0x43fe /* 4359 802.11ac 2.4G device */
204 #define BCM4359_D11AC5G_ID 0x43ff /* 4359 802.11ac 5G device */
205 #define BCM43596_D11AC_ID 0x4415 /* 43596 802.11ac dualband device */
206 #define BCM43596_D11AC2G_ID 0x4416 /* 43596 802.11ac 2.4G device */
207 #define BCM43596_D11AC5G_ID 0x4417 /* 43596 802.11ac 5G device */
208 #define BCM43909_D11AC_ID 0x43d0 /* 43909 802.11ac dualband device */
209 #define BCM43909_D11AC2G_ID 0x43d1 /* 43909 802.11ac 2.4G device */
210 #define BCM43909_D11AC5G_ID 0x43d2 /* 43909 802.11ac 5G device */
212 /* PCI Subsystem ID */
213 #define BCM943228HMB_SSID_VEN1 0x0607
214 #define BCM94313HMGBL_SSID_VEN1 0x0608
215 #define BCM94313HMG_SSID_VEN1 0x0609
216 #define BCM943142HM_SSID_VEN1 0x0611
218 #define BCM43143_D11N2G_ID 0x4366 /* 43143 802.11n 2.4G device */
220 #define BCM43242_D11N_ID 0x4367 /* 43242 802.11n dualband device */
221 #define BCM43242_D11N2G_ID 0x4368 /* 43242 802.11n 2.4G device */
222 #define BCM43242_D11N5G_ID 0x4369 /* 43242 802.11n 5G device */
224 #define BCM4350_D11AC_ID 0x43a3
225 #define BCM4350_D11AC2G_ID 0x43a4
226 #define BCM4350_D11AC5G_ID 0x43a5
228 #define BCM43556_D11AC_ID 0x43b7
229 #define BCM43556_D11AC2G_ID 0x43b8
230 #define BCM43556_D11AC5G_ID 0x43b9
232 #define BCM43558_D11AC_ID 0x43c0
233 #define BCM43558_D11AC2G_ID 0x43c1
234 #define BCM43558_D11AC5G_ID 0x43c2
236 #define BCM43566_D11AC_ID 0x43d3
237 #define BCM43566_D11AC2G_ID 0x43d4
238 #define BCM43566_D11AC5G_ID 0x43d5
240 #define BCM43568_D11AC_ID 0x43d6
241 #define BCM43568_D11AC2G_ID 0x43d7
242 #define BCM43568_D11AC5G_ID 0x43d8
244 #define BCM43569_D11AC_ID 0x43d9
245 #define BCM43569_D11AC2G_ID 0x43da
246 #define BCM43569_D11AC5G_ID 0x43db
248 #define BCM43570_D11AC_ID 0x43d9
249 #define BCM43570_D11AC2G_ID 0x43da
250 #define BCM43570_D11AC5G_ID 0x43db
252 #define BCM4354_D11AC_ID 0x43df /* 4354 802.11ac dualband device */
253 #define BCM4354_D11AC2G_ID 0x43e0 /* 4354 802.11ac 2.4G device */
254 #define BCM4354_D11AC5G_ID 0x43e1 /* 4354 802.11ac 5G device */
255 #define BCM43430_D11N2G_ID 0x43e2 /* 43430 802.11n 2.4G device */
258 #define BCM4365_D11AC_ID 0x43ca
259 #define BCM4365_D11AC2G_ID 0x43cb
260 #define BCM4365_D11AC5G_ID 0x43cc
262 #define BCM4366_D11AC_ID 0x43c3
263 #define BCM4366_D11AC2G_ID 0x43c4
264 #define BCM4366_D11AC5G_ID 0x43c5
266 #define BCM43349_D11N_ID 0x43e6 /* 43349 802.11n dualband id */
267 #define BCM43349_D11N2G_ID 0x43e7 /* 43349 802.11n 2.4Ghz band id */
268 #define BCM43349_D11N5G_ID 0x43e8 /* 43349 802.11n 5Ghz band id */
270 #define BCM4358_D11AC_ID 0x43e9 /* 4358 802.11ac dualband device */
271 #define BCM4358_D11AC2G_ID 0x43ea /* 4358 802.11ac 2.4G device */
272 #define BCM4358_D11AC5G_ID 0x43eb /* 4358 802.11ac 5G device */
274 #define BCM4356_D11AC_ID 0x43ec /* 4356 802.11ac dualband device */
275 #define BCM4356_D11AC2G_ID 0x43ed /* 4356 802.11ac 2.4G device */
276 #define BCM4356_D11AC5G_ID 0x43ee /* 4356 802.11ac 5G device */
278 #define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
279 #define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
280 #define FPGA_JTAGM_ID 0x43f0 /* FPGA jtagm device id */
281 #define BCM_JTAGM_ID 0x43f1 /* BCM jtagm device id */
282 #define SDIOH_FPGA_ID 0x43f2 /* sdio host fpga */
283 #define BCM_SDIOH_ID 0x43f3 /* BCM sdio host id */
284 #define SDIOD_FPGA_ID 0x43f4 /* sdio device fpga */
285 #define SPIH_FPGA_ID 0x43f5 /* PCI SPI Host Controller FPGA */
286 #define BCM_SPIH_ID 0x43f6 /* Synopsis SPI Host Controller */
287 #define MIMO_FPGA_ID 0x43f8 /* FPGA mimo minimacphy device id */
288 #define BCM_JTAGM2_ID 0x43f9 /* BCM alternate jtagm device id */
289 #define SDHCI_FPGA_ID 0x43fa /* Standard SDIO Host Controller FPGA */
290 #define BCM4402_ENET_ID 0x4402 /* 4402 enet */
291 #define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
292 #define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
293 #define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
294 #define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
295 #define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
296 #define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
297 #define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
298 #define BCM47XX_AUDIO_ID 0x4711 /* 47xx audio codec */
299 #define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
300 #define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
301 #define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
302 #define BCM47XX_GMAC_ID 0x4715 /* 47xx Unimac based GbE */
303 #define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
304 #define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
305 #define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
306 #define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
307 #define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
308 #define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
309 #define BCM47XX_ATA100_ID 0x471d /* 47xx parallel ATA */
310 #define BCM47XX_SATAXOR_ID 0x471e /* 47xx serial ATA & XOR DMA */
311 #define BCM47XX_GIGETH_ID 0x471f /* 47xx GbE (5700) */
312 #define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
313 #define BCM4716_DEVICE_ID 0x4722 /* 4716 base devid */
314 #define BCM47XX_USB30H_ID 0x472a /* 47xx usb 3.0 host */
315 #define BCM47XX_USB30D_ID 0x472b /* 47xx usb 3.0 device */
316 #define BCM47XX_SMBUS_EMU_ID 0x47fe /* 47xx emulated SMBus device */
317 #define BCM47XX_XOR_EMU_ID 0x47ff /* 47xx emulated XOR engine */
318 #define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
319 #define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
320 #define JINVANI_SDIOH_ID 0x4743 /* Jinvani SDIO Gold Host */
321 #define BCM27XX_SDIOH_ID 0x2702 /* BCM27xx Standard SDIO Host */
322 #define PCIXX21_FLASHMEDIA_ID 0x803b /* TI PCI xx21 Standard Host Controller */
323 #define PCIXX21_SDIOH_ID 0x803c /* TI PCI xx21 Standard Host Controller */
324 #define R5C822_SDIOH_ID 0x0822 /* Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host */
325 #define JMICRON_SDIOH_ID 0x2381 /* JMicron Standard SDIO Host Controller */
328 #define BCM4306_CHIP_ID 0x4306 /* 4306 chipcommon chipid */
329 #define BCM4311_CHIP_ID 0x4311 /* 4311 PCIe 802.11a/b/g */
330 #define BCM43111_CHIP_ID 43111 /* 43111 chipcommon chipid (OTP chipid) */
331 #define BCM43112_CHIP_ID 43112 /* 43112 chipcommon chipid (OTP chipid) */
332 #define BCM4312_CHIP_ID 0x4312 /* 4312 chipcommon chipid */
333 #define BCM4313_CHIP_ID 0x4313 /* 4313 chip id */
334 #define BCM43131_CHIP_ID 43131 /* 43131 chip id (OTP chipid) */
335 #define BCM4315_CHIP_ID 0x4315 /* 4315 chip id */
336 #define BCM4318_CHIP_ID 0x4318 /* 4318 chipcommon chipid */
337 #define BCM4319_CHIP_ID 0x4319 /* 4319 chip id */
338 #define BCM4320_CHIP_ID 0x4320 /* 4320 chipcommon chipid */
339 #define BCM4321_CHIP_ID 0x4321 /* 4321 chipcommon chipid */
340 #define BCM43217_CHIP_ID 43217 /* 43217 chip id (OTP chipid) */
341 #define BCM4322_CHIP_ID 0x4322 /* 4322 chipcommon chipid */
342 #define BCM43221_CHIP_ID 43221 /* 43221 chipcommon chipid (OTP chipid) */
343 #define BCM43222_CHIP_ID 43222 /* 43222 chipcommon chipid */
344 #define BCM43224_CHIP_ID 43224 /* 43224 chipcommon chipid */
345 #define BCM43225_CHIP_ID 43225 /* 43225 chipcommon chipid */
346 #define BCM43227_CHIP_ID 43227 /* 43227 chipcommon chipid */
347 #define BCM43228_CHIP_ID 43228 /* 43228 chipcommon chipid */
348 #define BCM43226_CHIP_ID 43226 /* 43226 chipcommon chipid */
349 #define BCM43231_CHIP_ID 43231 /* 43231 chipcommon chipid (OTP chipid) */
350 #define BCM43234_CHIP_ID 43234 /* 43234 chipcommon chipid */
351 #define BCM43235_CHIP_ID 43235 /* 43235 chipcommon chipid */
352 #define BCM43236_CHIP_ID 43236 /* 43236 chipcommon chipid */
353 #define BCM43237_CHIP_ID 43237 /* 43237 chipcommon chipid */
354 #define BCM43238_CHIP_ID 43238 /* 43238 chipcommon chipid */
355 #define BCM43239_CHIP_ID 43239 /* 43239 chipcommon chipid */
356 #define BCM43420_CHIP_ID 43420 /* 43222 chipcommon chipid (OTP, RBBU) */
357 #define BCM43421_CHIP_ID 43421 /* 43224 chipcommon chipid (OTP, RBBU) */
358 #define BCM43428_CHIP_ID 43428 /* 43228 chipcommon chipid (OTP, RBBU) */
359 #define BCM43431_CHIP_ID 43431 /* 4331 chipcommon chipid (OTP, RBBU) */
360 #define BCM43460_CHIP_ID 43460 /* 4360 chipcommon chipid (OTP, RBBU) */
361 #define BCM4325_CHIP_ID 0x4325 /* 4325 chip id */
362 #define BCM4328_CHIP_ID 0x4328 /* 4328 chip id */
363 #define BCM4329_CHIP_ID 0x4329 /* 4329 chipcommon chipid */
364 #define BCM4331_CHIP_ID 0x4331 /* 4331 chipcommon chipid */
365 #define BCM4336_CHIP_ID 0x4336 /* 4336 chipcommon chipid */
366 #define BCM43362_CHIP_ID 43362 /* 43362 chipcommon chipid */
367 #define BCM4330_CHIP_ID 0x4330 /* 4330 chipcommon chipid */
368 #define BCM6362_CHIP_ID 0x6362 /* 6362 chipcommon chipid */
369 #define BCM4314_CHIP_ID 0x4314 /* 4314 chipcommon chipid */
370 #define BCM43142_CHIP_ID 43142 /* 43142 chipcommon chipid */
371 #define BCM43143_CHIP_ID 43143 /* 43143 chipcommon chipid */
372 #define BCM4324_CHIP_ID 0x4324 /* 4324 chipcommon chipid */
373 #define BCM43242_CHIP_ID 43242 /* 43242 chipcommon chipid */
374 #define BCM43243_CHIP_ID 43243 /* 43243 chipcommon chipid */
375 #define BCM4334_CHIP_ID 0x4334 /* 4334 chipcommon chipid */
376 #define BCM4335_CHIP_ID 0x4335 /* 4335 chipcommon chipid */
377 #define BCM4339_CHIP_ID 0x4339 /* 4339 chipcommon chipid */
378 #define BCM43349_CHIP_ID 43349 /* 43349(0xA955) chipcommon chipid */
379 #define BCM4360_CHIP_ID 0x4360 /* 4360 chipcommon chipid */
380 #define BCM4364_CHIP_ID 0x4364 /* 4364 chipcommon chipid */
381 #define BCM4352_CHIP_ID 0x4352 /* 4352 chipcommon chipid */
382 #define BCM43526_CHIP_ID 0xAA06
383 #define BCM43340_CHIP_ID 43340 /* 43340 chipcommon chipid */
384 #define BCM43341_CHIP_ID 43341 /* 43341 chipcommon chipid */
385 #define BCM43342_CHIP_ID 43342 /* 43342 chipcommon chipid */
386 #define BCM4350_CHIP_ID 0x4350 /* 4350 chipcommon chipid */
387 #define BCM4354_CHIP_ID 0x4354 /* 4354 chipcommon chipid */
388 #define BCM4356_CHIP_ID 0x4356 /* 4356 chipcommon chipid */
389 #define BCM43556_CHIP_ID 0xAA24 /* 43556 chipcommon chipid */
390 #define BCM43558_CHIP_ID 0xAA26 /* 43558 chipcommon chipid */
391 #define BCM43566_CHIP_ID 0xAA2E /* 43566 chipcommon chipid */
392 #define BCM43567_CHIP_ID 0xAA2F /* 43567 chipcommon chipid */
393 #define BCM43568_CHIP_ID 0xAA30 /* 43568 chipcommon chipid */
394 #define BCM43569_CHIP_ID 0xAA31 /* 43569 chipcommon chipid */
395 #define BCM43570_CHIP_ID 0xAA32 /* 43570 chipcommon chipid */
396 #define BCM4358_CHIP_ID 0x4358 /* 4358 chipcommon chipid */
397 #define BCM4371_CHIP_ID 0x4371 /* 4371 chipcommon chipid */
398 #define BCM43012_CHIP_ID 0xA804 /* 43012 chipcommon chipid */
399 #define BCM4350_CHIP(chipid) ((CHIPID(chipid) == BCM4350_CHIP_ID) || \
400 (CHIPID(chipid) == BCM4354_CHIP_ID) || \
401 (CHIPID(chipid) == BCM4356_CHIP_ID) || \
402 (CHIPID(chipid) == BCM43556_CHIP_ID) || \
403 (CHIPID(chipid) == BCM43558_CHIP_ID) || \
404 (CHIPID(chipid) == BCM43566_CHIP_ID) || \
405 (CHIPID(chipid) == BCM43567_CHIP_ID) || \
406 (CHIPID(chipid) == BCM43568_CHIP_ID) || \
407 (CHIPID(chipid) == BCM43569_CHIP_ID) || \
408 (CHIPID(chipid) == BCM43570_CHIP_ID) || \
409 (CHIPID(chipid) == BCM4358_CHIP_ID)) /* 4350 variations */
410 #define BCM4345_CHIP_ID 0x4345 /* 4345 chipcommon chipid */
411 #define BCM43454_CHIP_ID 43454 /* 43454 chipcommon chipid */
412 #define BCM43455_CHIP_ID 43455 /* 43455 chipcommon chipid */
413 #define BCM43457_CHIP_ID 43457 /* 43457 chipcommon chipid */
414 #define BCM43458_CHIP_ID 43458 /* 43458 chipcommon chipid */
415 #define BCM43430_CHIP_ID 43430 /* 43430 chipcommon chipid */
416 #define BCM4349_CHIP_ID 0x4349 /* 4349 chipcommon chipid */
417 #define BCM4355_CHIP_ID 0x4355 /* 4355 chipcommon chipid */
418 #define BCM4359_CHIP_ID 0x4359 /* 4359 chipcommon chipid */
419 #define BCM4349_CHIP(chipid) ((CHIPID(chipid) == BCM4349_CHIP_ID) || \
420 (CHIPID(chipid) == BCM4355_CHIP_ID) || \
421 (CHIPID(chipid) == BCM4359_CHIP_ID))
423 #define BCM4345_CHIP(chipid) (CHIPID(chipid) == BCM4345_CHIP_ID || \
424 CHIPID(chipid) == BCM43454_CHIP_ID || \
425 CHIPID(chipid) == BCM43455_CHIP_ID || \
426 CHIPID(chipid) == BCM43457_CHIP_ID || \
427 CHIPID(chipid) == BCM43458_CHIP_ID)
429 #define CASE_BCM4345_CHIP case BCM4345_CHIP_ID: /* fallthrough */ \
430 case BCM43454_CHIP_ID: /* fallthrough */ \
431 case BCM43455_CHIP_ID: /* fallthrough */ \
432 case BCM43457_CHIP_ID: /* fallthrough */ \
433 case BCM43458_CHIP_ID
435 #define BCM4349_CHIP_GRPID BCM4349_CHIP_ID: \
436 case BCM4355_CHIP_ID: \
439 #define BCM4365_CHIP_ID 0x4365 /* 4365 chipcommon chipid */
440 #define BCM4366_CHIP_ID 0x4366 /* 4366 chipcommon chipid */
442 #define BCM43909_CHIP_ID 0xab85 /* 43909 chipcommon chipid */
444 #define BCM43602_CHIP_ID 0xaa52 /* 43602 chipcommon chipid */
445 #define BCM43462_CHIP_ID 0xa9c6 /* 43462 chipcommon chipid */
446 #define BCM43522_CHIP_ID 0xaa02 /* 43522 chipcommon chipid */
447 #define BCM43602_CHIP(chipid) ((CHIPID(chipid) == BCM43602_CHIP_ID) || \
448 (CHIPID(chipid) == BCM43462_CHIP_ID) || \
449 (CHIPID(chipid) == BCM43522_CHIP_ID)) /* 43602 variations */
450 #define CASE_BCM43602_CHIP case BCM43602_CHIP_ID: /* fallthrough */ \
451 case BCM43462_CHIP_ID: /* fallthrough */ \
452 case BCM43522_CHIP_ID
454 #define BCM4342_CHIP_ID 4342 /* 4342 chipcommon chipid (OTP, RBBU) */
455 #define BCM4402_CHIP_ID 0x4402 /* 4402 chipid */
456 #define BCM4704_CHIP_ID 0x4704 /* 4704 chipcommon chipid */
457 #define BCM4706_CHIP_ID 0x5300 /* 4706 chipcommon chipid */
458 #define BCM4707_CHIP_ID 53010 /* 4707 chipcommon chipid */
459 #define BCM47094_CHIP_ID 53030 /* 47094 chipcommon chipid */
460 #define BCM53018_CHIP_ID 53018 /* 53018 chipcommon chipid */
461 #define BCM4707_CHIP(chipid) (((chipid) == BCM4707_CHIP_ID) || \
462 ((chipid) == BCM53018_CHIP_ID) || \
463 ((chipid) == BCM47094_CHIP_ID))
464 #define BCM4710_CHIP_ID 0x4710 /* 4710 chipid */
465 #define BCM4712_CHIP_ID 0x4712 /* 4712 chipcommon chipid */
466 #define BCM4716_CHIP_ID 0x4716 /* 4716 chipcommon chipid */
467 #define BCM47162_CHIP_ID 47162 /* 47162 chipcommon chipid */
468 #define BCM4748_CHIP_ID 0x4748 /* 4716 chipcommon chipid (OTP, RBBU) */
469 #define BCM4749_CHIP_ID 0x4749 /* 5357 chipcommon chipid (OTP, RBBU) */
470 #define BCM4785_CHIP_ID 0x4785 /* 4785 chipcommon chipid */
471 #define BCM5350_CHIP_ID 0x5350 /* 5350 chipcommon chipid */
472 #define BCM5352_CHIP_ID 0x5352 /* 5352 chipcommon chipid */
473 #define BCM5354_CHIP_ID 0x5354 /* 5354 chipcommon chipid */
474 #define BCM5365_CHIP_ID 0x5365 /* 5365 chipcommon chipid */
475 #define BCM5356_CHIP_ID 0x5356 /* 5356 chipcommon chipid */
476 #define BCM5357_CHIP_ID 0x5357 /* 5357 chipcommon chipid */
477 #define BCM53572_CHIP_ID 53572 /* 53572 chipcommon chipid */
478 #define BCM53573_CHIP_ID 53573 /* 53573 chipcommon chipid */
479 #define BCM53573_CHIP(chipid) (CHIPID(chipid) == BCM53573_CHIP_ID)
480 #define BCM53573_CHIP_GRPID BCM53573_CHIP_ID
483 #define BCM4303_PKG_ID 2 /* 4303 package id */
484 #define BCM4309_PKG_ID 1 /* 4309 package id */
485 #define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
486 #define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
487 #define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
488 #define BCM4328USBD11G_PKG_ID 2 /* 4328 802.11g USB package id */
489 #define BCM4328USBDUAL_PKG_ID 3 /* 4328 802.11a/g USB package id */
490 #define BCM4328SDIOD11G_PKG_ID 4 /* 4328 802.11g SDIO package id */
491 #define BCM4328SDIODUAL_PKG_ID 5 /* 4328 802.11a/g SDIO package id */
492 #define BCM4329_289PIN_PKG_ID 0 /* 4329 289-pin package id */
493 #define BCM4329_182PIN_PKG_ID 1 /* 4329N 182-pin package id */
494 #define BCM5354E_PKG_ID 1 /* 5354E package id */
495 #define BCM4716_PKG_ID 8 /* 4716 package id */
496 #define BCM4717_PKG_ID 9 /* 4717 package id */
497 #define BCM4718_PKG_ID 10 /* 4718 package id */
498 #define BCM5356_PKG_NONMODE 1 /* 5356 package without nmode suppport */
499 #define BCM5358U_PKG_ID 8 /* 5358U package id */
500 #define BCM5358_PKG_ID 9 /* 5358 package id */
501 #define BCM47186_PKG_ID 10 /* 47186 package id */
502 #define BCM5357_PKG_ID 11 /* 5357 package id */
503 #define BCM5356U_PKG_ID 12 /* 5356U package id */
504 #define BCM53572_PKG_ID 8 /* 53572 package id */
505 #define BCM5357C0_PKG_ID 8 /* 5357c0 package id (the same as 53572) */
506 #define BCM47188_PKG_ID 9 /* 47188 package id */
507 #define BCM5358C0_PKG_ID 0xa /* 5358c0 package id */
508 #define BCM5356C0_PKG_ID 0xb /* 5356c0 package id */
509 #define BCM4331TT_PKG_ID 8 /* 4331 12x12 package id */
510 #define BCM4331TN_PKG_ID 9 /* 4331 12x9 package id */
511 #define BCM4331TNA0_PKG_ID 0xb /* 4331 12x9 package id */
512 #define BCM47189_PKG_ID 1 /* 47189 package id */
513 #define BCM53573_PKG_ID 0 /* 53573 package id */
514 #define BCM4706L_PKG_ID 1 /* 4706L package id */
516 #define HDLSIM5350_PKG_ID 1 /* HDL simulator package id for a 5350 */
517 #define HDLSIM_PKG_ID 14 /* HDL simulator package id */
518 #define HWSIM_PKG_ID 15 /* Hardware simulator package id */
519 #define BCM43224_FAB_CSM 0x8 /* the chip is manufactured by CSM */
520 #define BCM43224_FAB_SMIC 0xa /* the chip is manufactured by SMIC */
521 #define BCM4336_WLBGA_PKG_ID 0x8
522 #define BCM4330_WLBGA_PKG_ID 0x0
523 #define BCM4314PCIE_ARM_PKG_ID (8 | 0) /* 4314 QFN PCI package id, bit 3 tie high */
524 #define BCM4314SDIO_PKG_ID (8 | 1) /* 4314 QFN SDIO package id */
525 #define BCM4314PCIE_PKG_ID (8 | 2) /* 4314 QFN PCI (ARM-less) package id */
526 #define BCM4314SDIO_ARM_PKG_ID (8 | 3) /* 4314 QFN SDIO (ARM-less) package id */
527 #define BCM4314SDIO_FPBGA_PKG_ID (8 | 4) /* 4314 FpBGA SDIO package id */
528 #define BCM4314DEV_PKG_ID (8 | 6) /* 4314 Developement package id */
530 #define BCM4707_PKG_ID 1 /* 4707 package id */
531 #define BCM4708_PKG_ID 2 /* 4708 package id */
532 #define BCM4709_PKG_ID 0 /* 4709 package id */
534 #define PCIXX21_FLASHMEDIA0_ID 0x8033 /* TI PCI xx21 Standard Host Controller */
535 #define PCIXX21_SDIOH0_ID 0x8034 /* TI PCI xx21 Standard Host Controller */
537 #define BCM4335_WLCSP_PKG_ID (0x0) /* WLCSP Module/Mobile SDIO/HSIC. */
538 #define BCM4335_FCBGA_PKG_ID (0x1) /* FCBGA PC/Embeded/Media PCIE/SDIO */
539 #define BCM4335_WLBGA_PKG_ID (0x2) /* WLBGA COB/Mobile SDIO/HSIC. */
540 #define BCM4335_FCBGAD_PKG_ID (0x3) /* FCBGA Debug Debug/Dev All if's. */
541 #define BCM4335_PKG_MASK (0x3)
542 #define BCM43602_12x12_PKG_ID (0x1) /* 12x12 pins package, used for e.g. router designs */
545 #define BFL_BTC2WIRE 0x00000001 /* old 2wire Bluetooth coexistence, OBSOLETE */
546 #define BFL_BTCOEX 0x00000001 /* Board supports BTCOEX */
547 #define BFL_PACTRL 0x00000002 /* Board has gpio 9 controlling the PA */
548 #define BFL_AIRLINEMODE 0x00000004 /* Board implements gpio 13 radio disable indication, UNUSED */
549 #define BFL_ADCDIV 0x00000008 /* Board has the rssi ADC divider */
550 #define BFL_DIS_256QAM 0x00000008
551 #define BFL_ENETROBO 0x00000010 /* Board has robo switch or core */
552 #define BFL_TSSIAVG 0x00000010 /* TSSI averaging for ACPHY chips */
553 #define BFL_NOPLLDOWN 0x00000020 /* Not ok to power down the chip pll and oscillator */
554 #define BFL_CCKHIPWR 0x00000040 /* Can do high-power CCK transmission */
555 #define BFL_ENETADM 0x00000080 /* Board has ADMtek switch */
556 #define BFL_ENETVLAN 0x00000100 /* Board has VLAN capability */
557 #define BFL_LTECOEX 0x00000200 /* LTE Coex enabled */
558 #define BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
559 #define BFL_FEM 0x00000800 /* Board supports the Front End Module */
560 #define BFL_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */
561 #define BFL_HGPA 0x00002000 /* Board has a high gain PA */
562 #define BFL_BTC2WIRE_ALTGPIO 0x00004000 /* Board's BTC 2wire is in the alternate gpios */
563 #define BFL_ALTIQ 0x00008000 /* Alternate I/Q settings */
564 #define BFL_NOPA 0x00010000 /* Board has no PA */
565 #define BFL_RSSIINV 0x00020000 /* Board's RSSI uses positive slope(not TSSI) */
566 #define BFL_PAREF 0x00040000 /* Board uses the PARef LDO */
567 #define BFL_3TSWITCH 0x00080000 /* Board uses a triple throw switch shared with BT */
568 #define BFL_PHASESHIFT 0x00100000 /* Board can support phase shifter */
569 #define BFL_BUCKBOOST 0x00200000 /* Power topology uses BUCKBOOST */
570 #define BFL_FEM_BT 0x00400000 /* Board has FEM and switch to share antenna w/ BT */
571 #define BFL_NOCBUCK 0x00800000 /* Power topology doesn't use CBUCK */
572 #define BFL_CCKFAVOREVM 0x01000000 /* Favor CCK EVM over spectral mask */
573 #define BFL_PALDO 0x02000000 /* Power topology uses PALDO */
574 #define BFL_LNLDO2_2P5 0x04000000 /* Select 2.5V as LNLDO2 output voltage */
575 #define BFL_FASTPWR 0x08000000
576 #define BFL_UCPWRCTL_MININDX 0x08000000 /* Enforce min power index to avoid FEM damage */
577 #define BFL_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */
578 #define BFL_TRSW_1by2 0x20000000 /* Board has 2 TRSW's in 1by2 designs */
579 #define BFL_GAINBOOSTA01 0x20000000 /* 5g Gainboost for core0 and core1 */
580 #define BFL_LO_TRSW_R_5GHz 0x40000000 /* In 5G do not throw TRSW to T for clipLO gain */
581 #define BFL_ELNA_GAINDEF 0x80000000 /* Backoff InitGain based on elna_2g/5g field
582 * when this flag is set
584 #define BFL_EXTLNA_TX 0x20000000 /* Temp boardflag to indicate to */
587 #define BFL2_RXBB_INT_REG_DIS 0x00000001 /* Board has an external rxbb regulator */
588 #define BFL2_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */
589 #define BFL2_TXPWRCTRL_EN 0x00000004 /* Board permits enabling TX Power Control */
590 #define BFL2_2X4_DIV 0x00000008 /* Board supports the 2X4 diversity switch */
591 #define BFL2_5G_PWRGAIN 0x00000010 /* Board supports 5G band power gain */
592 #define BFL2_PCIEWAR_OVR 0x00000020 /* Board overrides ASPM and Clkreq settings */
593 #define BFL2_CAESERS_BRD 0x00000040 /* Board is Caesers brd (unused by sw) */
594 #define BFL2_BTC3WIRE 0x00000080 /* Board support legacy 3 wire or 4 wire */
595 #define BFL2_BTCLEGACY 0x00000080 /* Board support legacy 3/4 wire, to replace
598 #define BFL2_SKWRKFEM_BRD 0x00000100 /* 4321mcm93 board uses Skyworks FEM */
599 #define BFL2_SPUR_WAR 0x00000200 /* Board has a WAR for clock-harmonic spurs */
600 #define BFL2_GPLL_WAR 0x00000400 /* Flag to narrow G-band PLL loop b/w */
601 #define BFL2_TRISTATE_LED 0x00000800 /* Tri-state the LED */
602 #define BFL2_SINGLEANT_CCK 0x00001000 /* Tx CCK pkts on Ant 0 only */
603 #define BFL2_2G_SPUR_WAR 0x00002000 /* WAR to reduce and avoid clock-harmonic spurs in 2G */
604 #define BFL2_BPHY_ALL_TXCORES 0x00004000 /* Transmit bphy frames using all tx cores */
605 #define BFL2_FCC_BANDEDGE_WAR 0x00008000 /* Activates WAR to improve FCC bandedge performance */
606 #define BFL2_DAC_SPUR_IMPROVEMENT 0x00008000 /* Reducing DAC Spurs */
607 #define BFL2_GPLL_WAR2 0x00010000 /* Flag to widen G-band PLL loop b/w */
608 #define BFL2_REDUCED_PA_TURNONTIME 0x00010000 /* Flag to reduce PA turn on Time */
609 #define BFL2_IPALVLSHIFT_3P3 0x00020000
610 #define BFL2_INTERNDET_TXIQCAL 0x00040000 /* Use internal envelope detector for TX IQCAL */
611 #define BFL2_XTALBUFOUTEN 0x00080000 /* Keep the buffered Xtal output from radio on */
612 /* Most drivers will turn it off without this flag */
615 #define BFL2_ANAPACTRL_2G 0x00100000 /* 2G ext PAs are controlled by analog PA ctrl lines */
616 #define BFL2_ANAPACTRL_5G 0x00200000 /* 5G ext PAs are controlled by analog PA ctrl lines */
617 #define BFL2_ELNACTRL_TRSW_2G 0x00400000 /* AZW4329: 2G gmode_elna_gain controls TR Switch */
618 #define BFL2_BT_SHARE_ANT0 0x00800000 /* share core0 antenna with BT */
619 #define BFL2_TEMPSENSE_HIGHER 0x01000000 /* The tempsense threshold can sustain higher value
620 * than programmed. The exact delta is decided by
621 * driver per chip/boardtype. This can be used
622 * when tempsense qualification happens after shipment
624 #define BFL2_BTC3WIREONLY 0x02000000 /* standard 3 wire btc only. 4 wire not supported */
625 #define BFL2_PWR_NOMINAL 0x04000000 /* 0: power reduction on, 1: no power reduction */
626 #define BFL2_EXTLNA_PWRSAVE 0x08000000 /* boardflag to enable ucode to apply power save */
627 /* ucode control of eLNA during Tx */
628 #define BFL2_4313_RADIOREG 0x10000000
630 #define BFL2_DYNAMIC_VMID 0x10000000 /* enable dynamic Vmid in idle TSSI CAL for 4331 */
632 #define BFL2_SDR_EN 0x20000000 /* SDR enabled or disabled */
633 #define BFL2_DYNAMIC_VMID 0x10000000 /* boardflag to enable dynamic Vmid idle TSSI CAL */
634 #define BFL2_LNA1BYPFORTR2G 0x40000000 /* acphy, enable lna1 bypass for clip gain, 2g */
635 #define BFL2_LNA1BYPFORTR5G 0x80000000 /* acphy, enable lna1 bypass for clip gain, 5g */
637 /* SROM 11 - 11ac boardflag definitions */
638 #define BFL_SROM11_BTCOEX 0x00000001 /* Board supports BTCOEX */
639 #define BFL_SROM11_WLAN_BT_SH_XTL 0x00000002 /* bluetooth and wlan share same crystal */
640 #define BFL_SROM11_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */
641 #define BFL_SROM11_EPA_TURNON_TIME 0x00018000 /* 2 bits for different PA turn on times */
642 #define BFL_SROM11_EPA_TURNON_TIME_SHIFT 15
643 #define BFL_SROM11_PRECAL_TX_IDX 0x00040000 /* Dedicated TX IQLOCAL IDX values */
644 /* per subband, as derived from 43602A1 MCH5 */
645 #define BFL_SROM11_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */
646 #define BFL_SROM11_GAINBOOSTA01 0x20000000 /* 5g Gainboost for core0 and core1 */
647 #define BFL2_SROM11_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */
648 #define BFL2_SROM11_ANAPACTRL_2G 0x00100000 /* 2G ext PAs are ctrl-ed by analog PA ctrl lines */
649 #define BFL2_SROM11_ANAPACTRL_5G 0x00200000 /* 5G ext PAs are ctrl-ed by analog PA ctrl lines */
650 #define BFL2_SROM11_SINGLEANT_CCK 0x00001000 /* Tx CCK pkts on Ant 0 only */
651 #define BFL2_SROM11_EPA_ON_DURING_TXIQLOCAL 0x00020000 /* Keep ext. PA's on in TX IQLO CAL */
654 #define BFL3_FEMCTRL_SUB 0x00000007 /* acphy, subrevs of femctrl on top of srom_femctrl */
655 #define BFL3_RCAL_WAR 0x00000008 /* acphy, rcal war active on this board (4335a0) */
656 #define BFL3_TXGAINTBLID 0x00000070 /* acphy, txgain table id */
657 #define BFL3_TXGAINTBLID_SHIFT 0x4 /* acphy, txgain table id shift bit */
658 #define BFL3_TSSI_DIV_WAR 0x00000080 /* acphy, Seperate paparam for 20/40/80 */
659 #define BFL3_TSSI_DIV_WAR_SHIFT 0x7 /* acphy, Seperate paparam for 20/40/80 shift bit */
660 #define BFL3_FEMTBL_FROM_NVRAM 0x00000100 /* acphy, femctrl table is read from nvram */
661 #define BFL3_FEMTBL_FROM_NVRAM_SHIFT 0x8 /* acphy, femctrl table is read from nvram */
662 #define BFL3_AGC_CFG_2G 0x00000200 /* acphy, gain control configuration for 2G */
663 #define BFL3_AGC_CFG_5G 0x00000400 /* acphy, gain control configuration for 5G */
664 #define BFL3_PPR_BIT_EXT 0x00000800 /* acphy, bit position for 1bit extension for ppr */
665 #define BFL3_PPR_BIT_EXT_SHIFT 11 /* acphy, bit shift for 1bit extension for ppr */
666 #define BFL3_BBPLL_SPR_MODE_DIS 0x00001000 /* acphy, disables bbpll spur modes */
667 #define BFL3_RCAL_OTP_VAL_EN 0x00002000 /* acphy, to read rcal_trim value from otp */
668 #define BFL3_2GTXGAINTBL_BLANK 0x00004000 /* acphy, blank the first X ticks of 2g gaintbl */
669 #define BFL3_2GTXGAINTBL_BLANK_SHIFT 14 /* acphy, blank the first X ticks of 2g gaintbl */
670 #define BFL3_5GTXGAINTBL_BLANK 0x00008000 /* acphy, blank the first X ticks of 5g gaintbl */
671 #define BFL3_5GTXGAINTBL_BLANK_SHIFT 15 /* acphy, blank the first X ticks of 5g gaintbl */
672 #define BFL3_PHASETRACK_MAX_ALPHABETA 0x00010000 /* acphy, to max out alpha,beta to 511 */
673 #define BFL3_PHASETRACK_MAX_ALPHABETA_SHIFT 16 /* acphy, to max out alpha,beta to 511 */
674 /* acphy, to use backed off gaintbl for lte-coex */
675 #define BFL3_LTECOEX_GAINTBL_EN 0x00060000
676 /* acphy, to use backed off gaintbl for lte-coex */
677 #define BFL3_LTECOEX_GAINTBL_EN_SHIFT 17
678 #define BFL3_5G_SPUR_WAR 0x00080000 /* acphy, enable spur WAR in 5G band */
679 #define BFL3_1X1_RSDB_ANT 0x01000000 /* to find if 2-ant RSDB board or 1-ant RSDB board */
680 #define BFL3_1X1_RSDB_ANT_SHIFT 24
682 /* acphy: lpmode2g and lpmode_5g related boardflags */
683 #define BFL3_ACPHY_LPMODE_2G 0x00300000 /* bits 20:21 for lpmode_2g choice */
684 #define BFL3_ACPHY_LPMODE_2G_SHIFT 20
686 #define BFL3_ACPHY_LPMODE_5G 0x00C00000 /* bits 22:23 for lpmode_5g choice */
687 #define BFL3_ACPHY_LPMODE_5G_SHIFT 22
689 #define BFL3_EXT_LPO_ISCLOCK 0x02000000 /* External LPO is clock, not x-tal */
690 #define BFL3_FORCE_INT_LPO_SEL 0x04000000 /* Force internal lpo */
691 #define BFL3_FORCE_EXT_LPO_SEL 0x08000000 /* Force external lpo */
693 #define BFL3_EN_BRCM_IMPBF 0x10000000 /* acphy, Allow BRCM Implicit TxBF */
694 #define BFL3_AVVMID_FROM_NVRAM 0x40000000 /* Read Av Vmid from NVRAM */
695 #define BFL3_VLIN_EN_FROM_NVRAM 0x80000000 /* Read Vlin En from NVRAM */
697 #define BFL3_AVVMID_FROM_NVRAM_SHIFT 30 /* Read Av Vmid from NVRAM */
698 #define BFL3_VLIN_EN_FROM_NVRAM_SHIFT 31 /* Enable Vlin from NVRAM */
700 /* boardflags4 for SROM12 */
701 #define BFL4_SROM12_4dBPAD (1 << 0) /* To distinguigh between normal and 4dB pad board */
704 /* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
705 #define BOARD_GPIO_BTC3W_IN 0x850 /* bit 4 is RF_ACTIVE, bit 6 is STATUS, bit 11 is PRI */
706 #define BOARD_GPIO_BTC3W_OUT 0x020 /* bit 5 is TX_CONF */
707 #define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistence Input */
708 #define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistence Out */
709 #define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistence Input */
710 #define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistence Out */
711 #define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
712 #define BOARD_GPIO_12 0x1000 /* gpio 12 */
713 #define BOARD_GPIO_13 0x2000 /* gpio 13 */
714 #define BOARD_GPIO_BTC4_IN 0x0800 /* gpio 11, coex4, in */
715 #define BOARD_GPIO_BTC4_BT 0x2000 /* gpio 12, coex4, bt active */
716 #define BOARD_GPIO_BTC4_STAT 0x4000 /* gpio 14, coex4, status */
717 #define BOARD_GPIO_BTC4_WLAN 0x8000 /* gpio 15, coex4, wlan active */
718 #define BOARD_GPIO_1_WLAN_PWR 0x02 /* throttle WLAN power on X21 board */
719 #define BOARD_GPIO_2_WLAN_PWR 0x04 /* throttle WLAN power on X29C board */
720 #define BOARD_GPIO_3_WLAN_PWR 0x08 /* throttle WLAN power on X28 board */
721 #define BOARD_GPIO_4_WLAN_PWR 0x10 /* throttle WLAN power on X19 board */
722 #define BOARD_GPIO_13_WLAN_PWR 0x2000 /* throttle WLAN power on X14 board */
724 #define GPIO_BTC4W_OUT_4312 0x010 /* bit 4 is BT_IODISABLE */
725 #define GPIO_BTC4W_OUT_43224 0x020 /* bit 5 is BT_IODISABLE */
726 #define GPIO_BTC4W_OUT_43224_SHARED 0x0e0 /* bit 5 is BT_IODISABLE */
727 #define GPIO_BTC4W_OUT_43225 0x0e0 /* bit 5 BT_IODISABLE, bit 6 SW_BT, bit 7 SW_WL */
728 #define GPIO_BTC4W_OUT_43421 0x020 /* bit 5 is BT_IODISABLE */
729 #define GPIO_BTC4W_OUT_4313 0x060 /* bit 5 SW_BT, bit 6 SW_WL */
730 #define GPIO_BTC4W_OUT_4331_SHARED 0x010 /* GPIO 4 */
732 #define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
733 #define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
734 #define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal power-up */
735 #define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL power-down */
737 /* power control defines */
738 #define PLL_DELAY 150 /* us pll on delay */
739 #define FREF_DELAY 200 /* us fref change delay */
740 #define MIN_SLOW_CLK 32 /* us Slow clock period */
741 #define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
745 #define BCM943341WLABGS_SSID 0x062d
748 #define BCM943342FCAGBI_SSID 0x0641
750 /* 43602 Boards, unclear yet what boards will be created. */
751 #define BCM943602RSVD1_SSID 0x06a5
752 #define BCM943602RSVD2_SSID 0x06a6
753 #define BCM943602X87 0X0133
754 #define BCM943602X87P2 0X0143
755 #define BCM943602X238 0X0132
756 #define BCM943602X238D 0X014A
759 #define GPIO_NUMPINS 32
761 /* These values are used by dhd host driver. */
762 #define RDL_RAM_BASE_4319 0x60000000
763 #define RDL_RAM_BASE_4329 0x60000000
764 #define RDL_RAM_SIZE_4319 0x48000
765 #define RDL_RAM_SIZE_4329 0x48000
766 #define RDL_RAM_SIZE_43236 0x70000
767 #define RDL_RAM_BASE_43236 0x60000000
768 #define RDL_RAM_SIZE_4328 0x60000
769 #define RDL_RAM_BASE_4328 0x80000000
770 #define RDL_RAM_SIZE_4322 0x60000
771 #define RDL_RAM_BASE_4322 0x60000000
772 #define RDL_RAM_SIZE_4360 0xA0000
773 #define RDL_RAM_BASE_4360 0x60000000
774 #define RDL_RAM_SIZE_43242 0x90000
775 #define RDL_RAM_BASE_43242 0x60000000
776 #define RDL_RAM_SIZE_43143 0x70000
777 #define RDL_RAM_BASE_43143 0x60000000
778 #define RDL_RAM_SIZE_4350 0xC0000
779 #define RDL_RAM_BASE_4350 0x180800
781 /* generic defs for nvram "muxenab" bits
782 * Note: these differ for 4335a0. refer bcmchipc.h for specific mux options.
784 #define MUXENAB_UART 0x00000001
785 #define MUXENAB_GPIO 0x00000002
786 #define MUXENAB_ERCX 0x00000004 /* External Radio BT coex */
787 #define MUXENAB_JTAG 0x00000008
788 #define MUXENAB_HOST_WAKE 0x00000010 /* configure GPIO for SDIO host_wake */
789 #define MUXENAB_I2S_EN 0x00000020
790 #define MUXENAB_I2S_MASTER 0x00000040
791 #define MUXENAB_I2S_FULL 0x00000080
792 #define MUXENAB_SFLASH 0x00000100
793 #define MUXENAB_RFSWCTRL0 0x00000200
794 #define MUXENAB_RFSWCTRL1 0x00000400
795 #define MUXENAB_RFSWCTRL2 0x00000800
796 #define MUXENAB_SECI 0x00001000
797 #define MUXENAB_BT_LEGACY 0x00002000
798 #define MUXENAB_HOST_WAKE1 0x00004000 /* configure alternative GPIO for SDIO host_wake */
801 #define FLASH_KERNEL_NFLASH 0x00000001
802 #define FLASH_BOOT_NFLASH 0x00000002
804 #endif /* _BCMDEVS_H */
projects / firefly-linux-kernel-4.4.55.git / blob