2 * Broadcom device-specific manifest constants.
4 * $Copyright Open Broadcom Corporation$
6 * $Id: bcmdevs.h 484136 2014-06-12 04:36:10Z $
13 #define VENDOR_EPIGRAM 0xfeda
14 #define VENDOR_BROADCOM 0x14e4
15 #define VENDOR_3COM 0x10b7
16 #define VENDOR_NETGEAR 0x1385
17 #define VENDOR_DIAMOND 0x1092
18 #define VENDOR_INTEL 0x8086
19 #define VENDOR_DELL 0x1028
20 #define VENDOR_HP 0x103c
21 #define VENDOR_HP_COMPAQ 0x0e11
22 #define VENDOR_APPLE 0x106b
23 #define VENDOR_SI_IMAGE 0x1095 /* Silicon Image, used by Arasan SDIO Host */
24 #define VENDOR_BUFFALO 0x1154 /* Buffalo vendor id */
25 #define VENDOR_TI 0x104c /* Texas Instruments */
26 #define VENDOR_RICOH 0x1180 /* Ricoh */
27 #define VENDOR_JMICRON 0x197b
30 /* PCMCIA vendor IDs */
31 #define VENDOR_BROADCOM_PCMCIA 0x02d0
34 #define VENDOR_BROADCOM_SDIO 0x00BF
37 #define BCM_DNGL_VID 0x0a5c
38 #define BCM_DNGL_BL_PID_4328 0xbd12
39 #define BCM_DNGL_BL_PID_4322 0xbd13
40 #define BCM_DNGL_BL_PID_4319 0xbd16
41 #define BCM_DNGL_BL_PID_43236 0xbd17
42 #define BCM_DNGL_BL_PID_4332 0xbd18
43 #define BCM_DNGL_BL_PID_4330 0xbd19
44 #define BCM_DNGL_BL_PID_4334 0xbd1a
45 #define BCM_DNGL_BL_PID_43239 0xbd1b
46 #define BCM_DNGL_BL_PID_4324 0xbd1c
47 #define BCM_DNGL_BL_PID_4360 0xbd1d
48 #define BCM_DNGL_BL_PID_43143 0xbd1e
49 #define BCM_DNGL_BL_PID_43242 0xbd1f
50 #define BCM_DNGL_BL_PID_43342 0xbd21
51 #define BCM_DNGL_BL_PID_4335 0xbd20
52 #define BCM_DNGL_BL_PID_43341 0xbd22
53 #define BCM_DNGL_BL_PID_4350 0xbd23
54 #define BCM_DNGL_BL_PID_4345 0xbd24
55 #define BCM_DNGL_BL_PID_4349 0xbd25
56 #define BCM_DNGL_BL_PID_4354 0xbd26
57 #define BCM_DNGL_BL_PID_43569 0xbd27
58 #define BCM_DNGL_BL_PID_43909 0xbd28
60 #define BCM_DNGL_BDC_PID 0x0bdc
61 #define BCM_DNGL_JTAG_PID 0x4a44
63 /* HW USB BLOCK [CPULESS USB] PIDs */
64 #define BCM_HWUSB_PID_43239 43239
67 #define BCM4210_DEVICE_ID 0x1072 /* never used */
68 #define BCM4230_DEVICE_ID 0x1086 /* never used */
69 #define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
70 #define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
71 #define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
72 #define BCM4211_DEVICE_ID 0x4211
73 #define BCM4231_DEVICE_ID 0x4231
74 #define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
75 #define BCM4311_D11G_ID 0x4311 /* 4311 802.11b/g id */
76 #define BCM4311_D11DUAL_ID 0x4312 /* 4311 802.11a/b/g id */
77 #define BCM4311_D11A_ID 0x4313 /* 4311 802.11a id */
78 #define BCM4328_D11DUAL_ID 0x4314 /* 4328/4312 802.11a/g id */
79 #define BCM4328_D11G_ID 0x4315 /* 4328/4312 802.11g id */
80 #define BCM4328_D11A_ID 0x4316 /* 4328/4312 802.11a id */
81 #define BCM4318_D11G_ID 0x4318 /* 4318 802.11b/g id */
82 #define BCM4318_D11DUAL_ID 0x4319 /* 4318 802.11a/b/g id */
83 #define BCM4318_D11A_ID 0x431a /* 4318 802.11a id */
84 #define BCM4325_D11DUAL_ID 0x431b /* 4325 802.11a/g id */
85 #define BCM4325_D11G_ID 0x431c /* 4325 802.11g id */
86 #define BCM4325_D11A_ID 0x431d /* 4325 802.11a id */
87 #define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
88 #define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
89 #define BCM4306_UART_ID 0x4322 /* 4306 uart */
90 #define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
91 #define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
92 #define BCM4306_D11G_ID2 0x4325 /* BCM4306_D11G_ID; INF w/loose binding war */
93 #define BCM4321_D11N_ID 0x4328 /* 4321 802.11n dualband id */
94 #define BCM4321_D11N2G_ID 0x4329 /* 4321 802.11n 2.4Ghz band id */
95 #define BCM4321_D11N5G_ID 0x432a /* 4321 802.11n 5Ghz band id */
96 #define BCM4322_D11N_ID 0x432b /* 4322 802.11n dualband device */
97 #define BCM4322_D11N2G_ID 0x432c /* 4322 802.11n 2.4GHz device */
98 #define BCM4322_D11N5G_ID 0x432d /* 4322 802.11n 5GHz device */
99 #define BCM4329_D11N_ID 0x432e /* 4329 802.11n dualband device */
100 #define BCM4329_D11N2G_ID 0x432f /* 4329 802.11n 2.4G device */
101 #define BCM4329_D11N5G_ID 0x4330 /* 4329 802.11n 5G device */
102 #define BCM4315_D11DUAL_ID 0x4334 /* 4315 802.11a/g id */
103 #define BCM4315_D11G_ID 0x4335 /* 4315 802.11g id */
104 #define BCM4315_D11A_ID 0x4336 /* 4315 802.11a id */
105 #define BCM4319_D11N_ID 0x4337 /* 4319 802.11n dualband device */
106 #define BCM4319_D11N2G_ID 0x4338 /* 4319 802.11n 2.4G device */
107 #define BCM4319_D11N5G_ID 0x4339 /* 4319 802.11n 5G device */
108 #define BCM43231_D11N2G_ID 0x4340 /* 43231 802.11n 2.4GHz device */
109 #define BCM43221_D11N2G_ID 0x4341 /* 43221 802.11n 2.4GHz device */
110 #define BCM43222_D11N_ID 0x4350 /* 43222 802.11n dualband device */
111 #define BCM43222_D11N2G_ID 0x4351 /* 43222 802.11n 2.4GHz device */
112 #define BCM43222_D11N5G_ID 0x4352 /* 43222 802.11n 5GHz device */
113 #define BCM43224_D11N_ID 0x4353 /* 43224 802.11n dualband device */
114 #define BCM43224_D11N_ID_VEN1 0x0576 /* Vendor specific 43224 802.11n db device */
115 #define BCM43226_D11N_ID 0x4354 /* 43226 802.11n dualband device */
116 #define BCM43236_D11N_ID 0x4346 /* 43236 802.11n dualband device */
117 #define BCM43236_D11N2G_ID 0x4347 /* 43236 802.11n 2.4GHz device */
118 #define BCM43236_D11N5G_ID 0x4348 /* 43236 802.11n 5GHz device */
119 #define BCM43225_D11N2G_ID 0x4357 /* 43225 802.11n 2.4GHz device */
120 #define BCM43421_D11N_ID 0xA99D /* 43421 802.11n dualband device */
121 #define BCM4313_D11N2G_ID 0x4727 /* 4313 802.11n 2.4G device */
122 #define BCM4330_D11N_ID 0x4360 /* 4330 802.11n dualband device */
123 #define BCM4330_D11N2G_ID 0x4361 /* 4330 802.11n 2.4G device */
124 #define BCM4330_D11N5G_ID 0x4362 /* 4330 802.11n 5G device */
125 #define BCM4336_D11N_ID 0x4343 /* 4336 802.11n 2.4GHz device */
126 #define BCM6362_D11N_ID 0x435f /* 6362 802.11n dualband device */
127 #define BCM6362_D11N2G_ID 0x433f /* 6362 802.11n 2.4Ghz band id */
128 #define BCM6362_D11N5G_ID 0x434f /* 6362 802.11n 5Ghz band id */
129 #define BCM4331_D11N_ID 0x4331 /* 4331 802.11n dualband id */
130 #define BCM4331_D11N2G_ID 0x4332 /* 4331 802.11n 2.4Ghz band id */
131 #define BCM4331_D11N5G_ID 0x4333 /* 4331 802.11n 5Ghz band id */
132 #define BCM43237_D11N_ID 0x4355 /* 43237 802.11n dualband device */
133 #define BCM43237_D11N5G_ID 0x4356 /* 43237 802.11n 5GHz device */
134 #define BCM43227_D11N2G_ID 0x4358 /* 43228 802.11n 2.4GHz device */
135 #define BCM43228_D11N_ID 0x4359 /* 43228 802.11n DualBand device */
136 #define BCM43228_D11N5G_ID 0x435a /* 43228 802.11n 5GHz device */
137 #define BCM43362_D11N_ID 0x4363 /* 43362 802.11n 2.4GHz device */
138 #define BCM43239_D11N_ID 0x4370 /* 43239 802.11n dualband device */
139 #define BCM4324_D11N_ID 0x4374 /* 4324 802.11n dualband device */
140 #define BCM43217_D11N2G_ID 0x43a9 /* 43217 802.11n 2.4GHz device */
141 #define BCM43131_D11N2G_ID 0x43aa /* 43131 802.11n 2.4GHz device */
142 #define BCM4314_D11N2G_ID 0x4364 /* 4314 802.11n 2.4G device */
143 #define BCM43142_D11N2G_ID 0x4365 /* 43142 802.11n 2.4G device */
144 #define BCM43143_D11N2G_ID 0x4366 /* 43143 802.11n 2.4G device */
145 #define BCM4334_D11N_ID 0x4380 /* 4334 802.11n dualband device */
146 #define BCM4334_D11N2G_ID 0x4381 /* 4334 802.11n 2.4G device */
147 #define BCM4334_D11N5G_ID 0x4382 /* 4334 802.11n 5G device */
148 #define BCM43342_D11N_ID 0x4383 /* 43342 802.11n dualband device */
149 #define BCM43342_D11N2G_ID 0x4384 /* 43342 802.11n 2.4G device */
150 #define BCM43342_D11N5G_ID 0x4385 /* 43342 802.11n 5G device */
151 #define BCM43341_D11N_ID 0x4386 /* 43341 802.11n dualband device */
152 #define BCM43341_D11N2G_ID 0x4387 /* 43341 802.11n 2.4G device */
153 #define BCM43341_D11N5G_ID 0x4388 /* 43341 802.11n 5G device */
154 #define BCM4360_D11AC_ID 0x43a0
155 #define BCM4360_D11AC2G_ID 0x43a1
156 #define BCM4360_D11AC5G_ID 0x43a2
157 #define BCM4345_D11AC_ID 0x43ab /* 4345 802.11ac dualband device */
158 #define BCM4345_D11AC2G_ID 0x43ac /* 4345 802.11ac 2.4G device */
159 #define BCM4345_D11AC5G_ID 0x43ad /* 4345 802.11ac 5G device */
160 #define BCM4335_D11AC_ID 0x43ae
161 #define BCM4335_D11AC2G_ID 0x43af
162 #define BCM4335_D11AC5G_ID 0x43b0
163 #define BCM4352_D11AC_ID 0x43b1 /* 4352 802.11ac dualband device */
164 #define BCM4352_D11AC2G_ID 0x43b2 /* 4352 802.11ac 2.4G device */
165 #define BCM4352_D11AC5G_ID 0x43b3 /* 4352 802.11ac 5G device */
166 #define BCM43602_D11AC_ID 0x43ba /* ac dualband PCI devid SPROM programmed */
167 #define BCM43602_D11AC2G_ID 0x43bb /* 43602 802.11ac 2.4G device */
168 #define BCM43602_D11AC5G_ID 0x43bc /* 43602 802.11ac 5G device */
169 #define BCM4349_D11AC_ID 0x4349 /* 4349 802.11ac dualband device */
170 #define BCM4349_D11AC2G_ID 0x43dd /* 4349 802.11ac 2.4G device */
171 #define BCM4349_D11AC5G_ID 0x43de /* 4349 802.11ac 5G device */
172 #define BCM4355_D11AC_ID 0x43d3 /* 4355 802.11ac dualband device */
173 #define BCM4355_D11AC2G_ID 0x43d4 /* 4355 802.11ac 2.4G device */
174 #define BCM4355_D11AC5G_ID 0x43d5 /* 4355 802.11ac 5G device */
175 #define BCM4359_D11AC_ID 0x43d6 /* 4359 802.11ac dualband device */
176 #define BCM4359_D11AC2G_ID 0x43d7 /* 4359 802.11ac 2.4G device */
177 #define BCM4359_D11AC5G_ID 0x43d8 /* 4359 802.11ac 5G device */
179 /* PCI Subsystem ID */
180 #define BCM943228HMB_SSID_VEN1 0x0607
181 #define BCM94313HMGBL_SSID_VEN1 0x0608
182 #define BCM94313HMG_SSID_VEN1 0x0609
183 #define BCM943142HM_SSID_VEN1 0x0611
185 #define BCM43143_D11N2G_ID 0x4366 /* 43143 802.11n 2.4G device */
187 #define BCM43242_D11N_ID 0x4367 /* 43242 802.11n dualband device */
188 #define BCM43242_D11N2G_ID 0x4368 /* 43242 802.11n 2.4G device */
189 #define BCM43242_D11N5G_ID 0x4369 /* 43242 802.11n 5G device */
191 #define BCM4350_D11AC_ID 0x43a3
192 #define BCM4350_D11AC2G_ID 0x43a4
193 #define BCM4350_D11AC5G_ID 0x43a5
195 #define BCM43556_D11AC_ID 0x43b7
196 #define BCM43556_D11AC2G_ID 0x43b8
197 #define BCM43556_D11AC5G_ID 0x43b9
199 #define BCM43558_D11AC_ID 0x43c0
200 #define BCM43558_D11AC2G_ID 0x43c1
201 #define BCM43558_D11AC5G_ID 0x43c2
203 #define BCM43566_D11AC_ID 0x43d3
204 #define BCM43566_D11AC2G_ID 0x43d4
205 #define BCM43566_D11AC5G_ID 0x43d5
207 #define BCM43568_D11AC_ID 0x43d6
208 #define BCM43568_D11AC2G_ID 0x43d7
209 #define BCM43568_D11AC5G_ID 0x43d8
211 #define BCM43569_D11AC_ID 0x43d9
212 #define BCM43569_D11AC2G_ID 0x43da
213 #define BCM43569_D11AC5G_ID 0x43db
215 #define BCM43570_D11AC_ID 0x43d9
216 #define BCM43570_D11AC2G_ID 0x43da
217 #define BCM43570_D11AC5G_ID 0x43db
219 #define BCM4354_D11AC_ID 0x43df /* 4354 802.11ac dualband device */
220 #define BCM4354_D11AC2G_ID 0x43e0 /* 4354 802.11ac 2.4G device */
221 #define BCM4354_D11AC5G_ID 0x43e1 /* 4354 802.11ac 5G device */
222 #define BCM43430_D11N2G_ID 0x43e2 /* 43430 802.11n 2.4G device */
225 #define BCM43349_D11N_ID 0x43e6 /* 43349 802.11n dualband id */
226 #define BCM43349_D11N2G_ID 0x43e7 /* 43349 802.11n 2.4Ghz band id */
227 #define BCM43349_D11N5G_ID 0x43e8 /* 43349 802.11n 5Ghz band id */
229 #define BCM4358_D11AC_ID 0x43e9 /* 4358 802.11ac dualband device */
230 #define BCM4358_D11AC2G_ID 0x43ea /* 4358 802.11ac 2.4G device */
231 #define BCM4358_D11AC5G_ID 0x43eb /* 4358 802.11ac 5G device */
233 #define BCM4356_D11AC_ID 0x43ec /* 4356 802.11ac dualband device */
234 #define BCM4356_D11AC2G_ID 0x43ed /* 4356 802.11ac 2.4G device */
235 #define BCM4356_D11AC5G_ID 0x43ee /* 4356 802.11ac 5G device */
237 #define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
238 #define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
239 #define FPGA_JTAGM_ID 0x43f0 /* FPGA jtagm device id */
240 #define BCM_JTAGM_ID 0x43f1 /* BCM jtagm device id */
241 #define SDIOH_FPGA_ID 0x43f2 /* sdio host fpga */
242 #define BCM_SDIOH_ID 0x43f3 /* BCM sdio host id */
243 #define SDIOD_FPGA_ID 0x43f4 /* sdio device fpga */
244 #define SPIH_FPGA_ID 0x43f5 /* PCI SPI Host Controller FPGA */
245 #define BCM_SPIH_ID 0x43f6 /* Synopsis SPI Host Controller */
246 #define MIMO_FPGA_ID 0x43f8 /* FPGA mimo minimacphy device id */
247 #define BCM_JTAGM2_ID 0x43f9 /* BCM alternate jtagm device id */
248 #define SDHCI_FPGA_ID 0x43fa /* Standard SDIO Host Controller FPGA */
249 #define BCM4402_ENET_ID 0x4402 /* 4402 enet */
250 #define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
251 #define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
252 #define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
253 #define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
254 #define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
255 #define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
256 #define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
257 #define BCM47XX_AUDIO_ID 0x4711 /* 47xx audio codec */
258 #define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
259 #define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
260 #define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
261 #define BCM47XX_GMAC_ID 0x4715 /* 47xx Unimac based GbE */
262 #define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
263 #define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
264 #define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
265 #define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
266 #define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
267 #define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
268 #define BCM47XX_ATA100_ID 0x471d /* 47xx parallel ATA */
269 #define BCM47XX_SATAXOR_ID 0x471e /* 47xx serial ATA & XOR DMA */
270 #define BCM47XX_GIGETH_ID 0x471f /* 47xx GbE (5700) */
271 #define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
272 #define BCM4716_DEVICE_ID 0x4722 /* 4716 base devid */
273 #define BCM47XX_USB30H_ID 0x472a /* 47xx usb 3.0 host */
274 #define BCM47XX_USB30D_ID 0x472b /* 47xx usb 3.0 device */
275 #define BCM47XX_SMBUS_EMU_ID 0x47fe /* 47xx emulated SMBus device */
276 #define BCM47XX_XOR_EMU_ID 0x47ff /* 47xx emulated XOR engine */
277 #define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
278 #define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
279 #define JINVANI_SDIOH_ID 0x4743 /* Jinvani SDIO Gold Host */
280 #define BCM27XX_SDIOH_ID 0x2702 /* BCM27xx Standard SDIO Host */
281 #define PCIXX21_FLASHMEDIA_ID 0x803b /* TI PCI xx21 Standard Host Controller */
282 #define PCIXX21_SDIOH_ID 0x803c /* TI PCI xx21 Standard Host Controller */
283 #define R5C822_SDIOH_ID 0x0822 /* Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host */
284 #define JMICRON_SDIOH_ID 0x2381 /* JMicron Standard SDIO Host Controller */
287 #define BCM4306_CHIP_ID 0x4306 /* 4306 chipcommon chipid */
288 #define BCM4311_CHIP_ID 0x4311 /* 4311 PCIe 802.11a/b/g */
289 #define BCM43111_CHIP_ID 43111 /* 43111 chipcommon chipid (OTP chipid) */
290 #define BCM43112_CHIP_ID 43112 /* 43112 chipcommon chipid (OTP chipid) */
291 #define BCM4312_CHIP_ID 0x4312 /* 4312 chipcommon chipid */
292 #define BCM4313_CHIP_ID 0x4313 /* 4313 chip id */
293 #define BCM43131_CHIP_ID 43131 /* 43131 chip id (OTP chipid) */
294 #define BCM4315_CHIP_ID 0x4315 /* 4315 chip id */
295 #define BCM4318_CHIP_ID 0x4318 /* 4318 chipcommon chipid */
296 #define BCM4319_CHIP_ID 0x4319 /* 4319 chip id */
297 #define BCM4320_CHIP_ID 0x4320 /* 4320 chipcommon chipid */
298 #define BCM4321_CHIP_ID 0x4321 /* 4321 chipcommon chipid */
299 #define BCM43217_CHIP_ID 43217 /* 43217 chip id (OTP chipid) */
300 #define BCM4322_CHIP_ID 0x4322 /* 4322 chipcommon chipid */
301 #define BCM43221_CHIP_ID 43221 /* 43221 chipcommon chipid (OTP chipid) */
302 #define BCM43222_CHIP_ID 43222 /* 43222 chipcommon chipid */
303 #define BCM43224_CHIP_ID 43224 /* 43224 chipcommon chipid */
304 #define BCM43225_CHIP_ID 43225 /* 43225 chipcommon chipid */
305 #define BCM43227_CHIP_ID 43227 /* 43227 chipcommon chipid */
306 #define BCM43228_CHIP_ID 43228 /* 43228 chipcommon chipid */
307 #define BCM43226_CHIP_ID 43226 /* 43226 chipcommon chipid */
308 #define BCM43231_CHIP_ID 43231 /* 43231 chipcommon chipid (OTP chipid) */
309 #define BCM43234_CHIP_ID 43234 /* 43234 chipcommon chipid */
310 #define BCM43235_CHIP_ID 43235 /* 43235 chipcommon chipid */
311 #define BCM43236_CHIP_ID 43236 /* 43236 chipcommon chipid */
312 #define BCM43237_CHIP_ID 43237 /* 43237 chipcommon chipid */
313 #define BCM43238_CHIP_ID 43238 /* 43238 chipcommon chipid */
314 #define BCM43239_CHIP_ID 43239 /* 43239 chipcommon chipid */
315 #define BCM43420_CHIP_ID 43420 /* 43222 chipcommon chipid (OTP, RBBU) */
316 #define BCM43421_CHIP_ID 43421 /* 43224 chipcommon chipid (OTP, RBBU) */
317 #define BCM43428_CHIP_ID 43428 /* 43228 chipcommon chipid (OTP, RBBU) */
318 #define BCM43431_CHIP_ID 43431 /* 4331 chipcommon chipid (OTP, RBBU) */
319 #define BCM43460_CHIP_ID 43460 /* 4360 chipcommon chipid (OTP, RBBU) */
320 #define BCM4325_CHIP_ID 0x4325 /* 4325 chip id */
321 #define BCM4328_CHIP_ID 0x4328 /* 4328 chip id */
322 #define BCM4329_CHIP_ID 0x4329 /* 4329 chipcommon chipid */
323 #define BCM4331_CHIP_ID 0x4331 /* 4331 chipcommon chipid */
324 #define BCM4336_CHIP_ID 0x4336 /* 4336 chipcommon chipid */
325 #define BCM43362_CHIP_ID 43362 /* 43362 chipcommon chipid */
326 #define BCM4330_CHIP_ID 0x4330 /* 4330 chipcommon chipid */
327 #define BCM6362_CHIP_ID 0x6362 /* 6362 chipcommon chipid */
328 #define BCM4314_CHIP_ID 0x4314 /* 4314 chipcommon chipid */
329 #define BCM43142_CHIP_ID 43142 /* 43142 chipcommon chipid */
330 #define BCM43143_CHIP_ID 43143 /* 43143 chipcommon chipid */
331 #define BCM4324_CHIP_ID 0x4324 /* 4324 chipcommon chipid */
332 #define BCM43242_CHIP_ID 43242 /* 43242 chipcommon chipid */
333 #define BCM43243_CHIP_ID 43243 /* 43243 chipcommon chipid */
334 #define BCM4334_CHIP_ID 0x4334 /* 4334 chipcommon chipid */
335 #define BCM4335_CHIP_ID 0x4335 /* 4335 chipcommon chipid */
336 #define BCM4339_CHIP_ID 0x4339 /* 4339 chipcommon chipid */
337 #define BCM43349_CHIP_ID 43349 /* 43349(0xA955) chipcommon chipid */
338 #define BCM4360_CHIP_ID 0x4360 /* 4360 chipcommon chipid */
339 #define BCM4352_CHIP_ID 0x4352 /* 4352 chipcommon chipid */
340 #define BCM43526_CHIP_ID 0xAA06
341 #define BCM43340_CHIP_ID 43340 /* 43340 chipcommon chipid */
342 #define BCM43341_CHIP_ID 43341 /* 43341 chipcommon chipid */
343 #define BCM43342_CHIP_ID 43342 /* 43342 chipcommon chipid */
344 #define BCM4350_CHIP_ID 0x4350 /* 4350 chipcommon chipid */
345 #define BCM4354_CHIP_ID 0x4354 /* 4354 chipcommon chipid */
346 #define BCM4356_CHIP_ID 0x4356 /* 4356 chipcommon chipid */
347 #define BCM43556_CHIP_ID 0xAA24 /* 43556 chipcommon chipid */
348 #define BCM43558_CHIP_ID 0xAA26 /* 43558 chipcommon chipid */
349 #define BCM43566_CHIP_ID 0xAA2E /* 43566 chipcommon chipid */
350 #define BCM43567_CHIP_ID 0xAA2F /* 43567 chipcommon chipid */
351 #define BCM43568_CHIP_ID 0xAA30 /* 43568 chipcommon chipid */
352 #define BCM43569_CHIP_ID 0xAA31 /* 43569 chipcommon chipid */
353 #define BCM43570_CHIP_ID 0xAA32 /* 43570 chipcommon chipid */
354 #define BCM4358_CHIP_ID 0x4358 /* 4358 chipcommon chipid */
355 #define BCM4371_CHIP_ID 0x4371 /* 4371 chipcommon chipid */
356 #define BCM4350_CHIP(chipid) ((CHIPID(chipid) == BCM4350_CHIP_ID) || \
357 (CHIPID(chipid) == BCM4354_CHIP_ID) || \
358 (CHIPID(chipid) == BCM4356_CHIP_ID) || \
359 (CHIPID(chipid) == BCM43556_CHIP_ID) || \
360 (CHIPID(chipid) == BCM43558_CHIP_ID) || \
361 (CHIPID(chipid) == BCM43566_CHIP_ID) || \
362 (CHIPID(chipid) == BCM43567_CHIP_ID) || \
363 (CHIPID(chipid) == BCM43568_CHIP_ID) || \
364 (CHIPID(chipid) == BCM43569_CHIP_ID) || \
365 (CHIPID(chipid) == BCM43570_CHIP_ID) || \
366 (CHIPID(chipid) == BCM4358_CHIP_ID)) /* 4350 variations */
367 #define BCM4345_CHIP_ID 0x4345 /* 4345 chipcommon chipid */
368 #define BCM43430_CHIP_ID 43430 /* 43430 chipcommon chipid */
369 #define BCM4349_CHIP_ID 0x4349 /* 4349 chipcommon chipid */
370 #define BCM4355_CHIP_ID 0x4355 /* 4355 chipcommon chipid */
371 #define BCM4359_CHIP_ID 0x4359 /* 4359 chipcommon chipid */
372 #define BCM4349_CHIP(chipid) ((CHIPID(chipid) == BCM4349_CHIP_ID) || \
373 (CHIPID(chipid) == BCM4355_CHIP_ID) || \
374 (CHIPID(chipid) == BCM4359_CHIP_ID))
375 #define BCM4349_CHIP_GRPID BCM4349_CHIP_ID: \
376 case BCM4355_CHIP_ID: \
379 #define BCM43602_CHIP_ID 0xaa52 /* 43602 chipcommon chipid */
380 #define BCM43462_CHIP_ID 0xa9c6 /* 43462 chipcommon chipid */
382 #define BCM4342_CHIP_ID 4342 /* 4342 chipcommon chipid (OTP, RBBU) */
383 #define BCM4402_CHIP_ID 0x4402 /* 4402 chipid */
384 #define BCM4704_CHIP_ID 0x4704 /* 4704 chipcommon chipid */
385 #define BCM4706_CHIP_ID 0x5300 /* 4706 chipcommon chipid */
386 #define BCM4707_CHIP_ID 53010 /* 4707 chipcommon chipid */
387 #define BCM53018_CHIP_ID 53018 /* 53018 chipcommon chipid */
388 #define BCM4707_CHIP(chipid) (((chipid) == BCM4707_CHIP_ID) || ((chipid) == BCM53018_CHIP_ID))
389 #define BCM4710_CHIP_ID 0x4710 /* 4710 chipid */
390 #define BCM4712_CHIP_ID 0x4712 /* 4712 chipcommon chipid */
391 #define BCM4716_CHIP_ID 0x4716 /* 4716 chipcommon chipid */
392 #define BCM47162_CHIP_ID 47162 /* 47162 chipcommon chipid */
393 #define BCM4748_CHIP_ID 0x4748 /* 4716 chipcommon chipid (OTP, RBBU) */
394 #define BCM4749_CHIP_ID 0x4749 /* 5357 chipcommon chipid (OTP, RBBU) */
395 #define BCM4785_CHIP_ID 0x4785 /* 4785 chipcommon chipid */
396 #define BCM5350_CHIP_ID 0x5350 /* 5350 chipcommon chipid */
397 #define BCM5352_CHIP_ID 0x5352 /* 5352 chipcommon chipid */
398 #define BCM5354_CHIP_ID 0x5354 /* 5354 chipcommon chipid */
399 #define BCM5365_CHIP_ID 0x5365 /* 5365 chipcommon chipid */
400 #define BCM5356_CHIP_ID 0x5356 /* 5356 chipcommon chipid */
401 #define BCM5357_CHIP_ID 0x5357 /* 5357 chipcommon chipid */
402 #define BCM53572_CHIP_ID 53572 /* 53572 chipcommon chipid */
405 #define BCM4303_PKG_ID 2 /* 4303 package id */
406 #define BCM4309_PKG_ID 1 /* 4309 package id */
407 #define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
408 #define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
409 #define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
410 #define BCM4328USBD11G_PKG_ID 2 /* 4328 802.11g USB package id */
411 #define BCM4328USBDUAL_PKG_ID 3 /* 4328 802.11a/g USB package id */
412 #define BCM4328SDIOD11G_PKG_ID 4 /* 4328 802.11g SDIO package id */
413 #define BCM4328SDIODUAL_PKG_ID 5 /* 4328 802.11a/g SDIO package id */
414 #define BCM4329_289PIN_PKG_ID 0 /* 4329 289-pin package id */
415 #define BCM4329_182PIN_PKG_ID 1 /* 4329N 182-pin package id */
416 #define BCM5354E_PKG_ID 1 /* 5354E package id */
417 #define BCM4716_PKG_ID 8 /* 4716 package id */
418 #define BCM4717_PKG_ID 9 /* 4717 package id */
419 #define BCM4718_PKG_ID 10 /* 4718 package id */
420 #define BCM5356_PKG_NONMODE 1 /* 5356 package without nmode suppport */
421 #define BCM5358U_PKG_ID 8 /* 5358U package id */
422 #define BCM5358_PKG_ID 9 /* 5358 package id */
423 #define BCM47186_PKG_ID 10 /* 47186 package id */
424 #define BCM5357_PKG_ID 11 /* 5357 package id */
425 #define BCM5356U_PKG_ID 12 /* 5356U package id */
426 #define BCM53572_PKG_ID 8 /* 53572 package id */
427 #define BCM5357C0_PKG_ID 8 /* 5357c0 package id (the same as 53572) */
428 #define BCM47188_PKG_ID 9 /* 47188 package id */
429 #define BCM5358C0_PKG_ID 0xa /* 5358c0 package id */
430 #define BCM5356C0_PKG_ID 0xb /* 5356c0 package id */
431 #define BCM4331TT_PKG_ID 8 /* 4331 12x12 package id */
432 #define BCM4331TN_PKG_ID 9 /* 4331 12x9 package id */
433 #define BCM4331TNA0_PKG_ID 0xb /* 4331 12x9 package id */
434 #define BCM4706L_PKG_ID 1 /* 4706L package id */
436 #define HDLSIM5350_PKG_ID 1 /* HDL simulator package id for a 5350 */
437 #define HDLSIM_PKG_ID 14 /* HDL simulator package id */
438 #define HWSIM_PKG_ID 15 /* Hardware simulator package id */
439 #define BCM43224_FAB_CSM 0x8 /* the chip is manufactured by CSM */
440 #define BCM43224_FAB_SMIC 0xa /* the chip is manufactured by SMIC */
441 #define BCM4336_WLBGA_PKG_ID 0x8
442 #define BCM4330_WLBGA_PKG_ID 0x0
443 #define BCM4314PCIE_ARM_PKG_ID (8 | 0) /* 4314 QFN PCI package id, bit 3 tie high */
444 #define BCM4314SDIO_PKG_ID (8 | 1) /* 4314 QFN SDIO package id */
445 #define BCM4314PCIE_PKG_ID (8 | 2) /* 4314 QFN PCI (ARM-less) package id */
446 #define BCM4314SDIO_ARM_PKG_ID (8 | 3) /* 4314 QFN SDIO (ARM-less) package id */
447 #define BCM4314SDIO_FPBGA_PKG_ID (8 | 4) /* 4314 FpBGA SDIO package id */
448 #define BCM4314DEV_PKG_ID (8 | 6) /* 4314 Developement package id */
450 #define BCM4707_PKG_ID 1 /* 4707 package id */
451 #define BCM4708_PKG_ID 2 /* 4708 package id */
452 #define BCM4709_PKG_ID 0 /* 4709 package id */
454 #define PCIXX21_FLASHMEDIA0_ID 0x8033 /* TI PCI xx21 Standard Host Controller */
455 #define PCIXX21_SDIOH0_ID 0x8034 /* TI PCI xx21 Standard Host Controller */
457 #define BCM4335_WLCSP_PKG_ID (0x0) /* WLCSP Module/Mobile SDIO/HSIC. */
458 #define BCM4335_FCBGA_PKG_ID (0x1) /* FCBGA PC/Embeded/Media PCIE/SDIO */
459 #define BCM4335_WLBGA_PKG_ID (0x2) /* WLBGA COB/Mobile SDIO/HSIC. */
460 #define BCM4335_FCBGAD_PKG_ID (0x3) /* FCBGA Debug Debug/Dev All if's. */
461 #define BCM4335_PKG_MASK (0x3)
464 #define BFL_BTC2WIRE 0x00000001 /* old 2wire Bluetooth coexistence, OBSOLETE */
465 #define BFL_BTCOEX 0x00000001 /* Board supports BTCOEX */
466 #define BFL_PACTRL 0x00000002 /* Board has gpio 9 controlling the PA */
467 #define BFL_AIRLINEMODE 0x00000004 /* Board implements gpio 13 radio disable indication, UNUSED */
468 #define BFL_ADCDIV 0x00000008 /* Board has the rssi ADC divider */
469 #define BFL_DIS_256QAM 0x00000008
470 #define BFL_ENETROBO 0x00000010 /* Board has robo switch or core */
471 #define BFL_TSSIAVG 0x00000010 /* TSSI averaging for ACPHY chips */
472 #define BFL_NOPLLDOWN 0x00000020 /* Not ok to power down the chip pll and oscillator */
473 #define BFL_CCKHIPWR 0x00000040 /* Can do high-power CCK transmission */
474 #define BFL_ENETADM 0x00000080 /* Board has ADMtek switch */
475 #define BFL_ENETVLAN 0x00000100 /* Board has VLAN capability */
476 #define BFL_LTECOEX 0x00000200 /* LTE Coex enabled */
477 #define BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
478 #define BFL_FEM 0x00000800 /* Board supports the Front End Module */
479 #define BFL_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */
480 #define BFL_HGPA 0x00002000 /* Board has a high gain PA */
481 #define BFL_BTC2WIRE_ALTGPIO 0x00004000 /* Board's BTC 2wire is in the alternate gpios */
482 #define BFL_ALTIQ 0x00008000 /* Alternate I/Q settings */
483 #define BFL_NOPA 0x00010000 /* Board has no PA */
484 #define BFL_RSSIINV 0x00020000 /* Board's RSSI uses positive slope(not TSSI) */
485 #define BFL_PAREF 0x00040000 /* Board uses the PARef LDO */
486 #define BFL_3TSWITCH 0x00080000 /* Board uses a triple throw switch shared with BT */
487 #define BFL_PHASESHIFT 0x00100000 /* Board can support phase shifter */
488 #define BFL_BUCKBOOST 0x00200000 /* Power topology uses BUCKBOOST */
489 #define BFL_FEM_BT 0x00400000 /* Board has FEM and switch to share antenna w/ BT */
490 #define BFL_NOCBUCK 0x00800000 /* Power topology doesn't use CBUCK */
491 #define BFL_CCKFAVOREVM 0x01000000 /* Favor CCK EVM over spectral mask */
492 #define BFL_PALDO 0x02000000 /* Power topology uses PALDO */
493 #define BFL_LNLDO2_2P5 0x04000000 /* Select 2.5V as LNLDO2 output voltage */
494 #define BFL_FASTPWR 0x08000000
495 #define BFL_UCPWRCTL_MININDX 0x08000000 /* Enforce min power index to avoid FEM damage */
496 #define BFL_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */
497 #define BFL_TRSW_1by2 0x20000000 /* Board has 2 TRSW's in 1by2 designs */
498 #define BFL_GAINBOOSTA01 0x20000000 /* 5g Gainboost for core0 and core1 */
499 #define BFL_LO_TRSW_R_5GHz 0x40000000 /* In 5G do not throw TRSW to T for clipLO gain */
500 #define BFL_ELNA_GAINDEF 0x80000000 /* Backoff InitGain based on elna_2g/5g field
501 * when this flag is set
503 #define BFL_EXTLNA_TX 0x20000000 /* Temp boardflag to indicate to */
506 #define BFL2_RXBB_INT_REG_DIS 0x00000001 /* Board has an external rxbb regulator */
507 #define BFL2_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */
508 #define BFL2_TXPWRCTRL_EN 0x00000004 /* Board permits enabling TX Power Control */
509 #define BFL2_2X4_DIV 0x00000008 /* Board supports the 2X4 diversity switch */
510 #define BFL2_5G_PWRGAIN 0x00000010 /* Board supports 5G band power gain */
511 #define BFL2_PCIEWAR_OVR 0x00000020 /* Board overrides ASPM and Clkreq settings */
512 #define BFL2_CAESERS_BRD 0x00000040 /* Board is Caesers brd (unused by sw) */
513 #define BFL2_BTC3WIRE 0x00000080 /* Board support legacy 3 wire or 4 wire */
514 #define BFL2_BTCLEGACY 0x00000080 /* Board support legacy 3/4 wire, to replace
517 #define BFL2_SKWRKFEM_BRD 0x00000100 /* 4321mcm93 board uses Skyworks FEM */
518 #define BFL2_SPUR_WAR 0x00000200 /* Board has a WAR for clock-harmonic spurs */
519 #define BFL2_GPLL_WAR 0x00000400 /* Flag to narrow G-band PLL loop b/w */
520 #define BFL2_TRISTATE_LED 0x00000800 /* Tri-state the LED */
521 #define BFL2_SINGLEANT_CCK 0x00001000 /* Tx CCK pkts on Ant 0 only */
522 #define BFL2_2G_SPUR_WAR 0x00002000 /* WAR to reduce and avoid clock-harmonic spurs in 2G */
523 #define BFL2_BPHY_ALL_TXCORES 0x00004000 /* Transmit bphy frames using all tx cores */
524 #define BFL2_FCC_BANDEDGE_WAR 0x00008000 /* Activates WAR to improve FCC bandedge performance */
525 #define BFL2_DAC_SPUR_IMPROVEMENT 0x00008000 /* Reducing DAC Spurs */
526 #define BFL2_GPLL_WAR2 0x00010000 /* Flag to widen G-band PLL loop b/w */
527 #define BFL2_REDUCED_PA_TURNONTIME 0x00010000 /* Flag to reduce PA turn on Time */
528 #define BFL2_IPALVLSHIFT_3P3 0x00020000
529 #define BFL2_INTERNDET_TXIQCAL 0x00040000 /* Use internal envelope detector for TX IQCAL */
530 #define BFL2_XTALBUFOUTEN 0x00080000 /* Keep the buffered Xtal output from radio on */
531 /* Most drivers will turn it off without this flag */
534 #define BFL2_ANAPACTRL_2G 0x00100000 /* 2G ext PAs are controlled by analog PA ctrl lines */
535 #define BFL2_ANAPACTRL_5G 0x00200000 /* 5G ext PAs are controlled by analog PA ctrl lines */
536 #define BFL2_ELNACTRL_TRSW_2G 0x00400000 /* AZW4329: 2G gmode_elna_gain controls TR Switch */
537 #define BFL2_BT_SHARE_ANT0 0x00800000 /* share core0 antenna with BT */
538 #define BFL2_TEMPSENSE_HIGHER 0x01000000 /* The tempsense threshold can sustain higher value
539 * than programmed. The exact delta is decided by
540 * driver per chip/boardtype. This can be used
541 * when tempsense qualification happens after shipment
543 #define BFL2_BTC3WIREONLY 0x02000000 /* standard 3 wire btc only. 4 wire not supported */
544 #define BFL2_PWR_NOMINAL 0x04000000 /* 0: power reduction on, 1: no power reduction */
545 #define BFL2_EXTLNA_PWRSAVE 0x08000000 /* boardflag to enable ucode to apply power save */
546 /* ucode control of eLNA during Tx */
547 #define BFL2_4313_RADIOREG 0x10000000
549 #define BFL2_DYNAMIC_VMID 0x10000000 /* enable dynamic Vmid in idle TSSI CAL for 4331 */
551 #define BFL2_SDR_EN 0x20000000 /* SDR enabled or disabled */
552 #define BFL2_DYNAMIC_VMID 0x10000000 /* boardflag to enable dynamic Vmid idle TSSI CAL */
553 #define BFL2_LNA1BYPFORTR2G 0x40000000 /* acphy, enable lna1 bypass for clip gain, 2g */
554 #define BFL2_LNA1BYPFORTR5G 0x80000000 /* acphy, enable lna1 bypass for clip gain, 5g */
556 /* SROM 11 - 11ac boardflag definitions */
557 #define BFL_SROM11_BTCOEX 0x00000001 /* Board supports BTCOEX */
558 #define BFL_SROM11_WLAN_BT_SH_XTL 0x00000002 /* bluetooth and wlan share same crystal */
559 #define BFL_SROM11_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */
560 #define BFL_SROM11_EPA_TURNON_TIME 0x00018000 /* 2 bits for different PA turn on times */
561 #define BFL_SROM11_EPA_TURNON_TIME_SHIFT 15
562 #define BFL_SROM11_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */
563 #define BFL_SROM11_GAINBOOSTA01 0x20000000 /* 5g Gainboost for core0 and core1 */
564 #define BFL2_SROM11_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */
565 #define BFL2_SROM11_ANAPACTRL_2G 0x00100000 /* 2G ext PAs are ctrl-ed by analog PA ctrl lines */
566 #define BFL2_SROM11_ANAPACTRL_5G 0x00200000 /* 5G ext PAs are ctrl-ed by analog PA ctrl lines */
567 #define BFL2_SROM11_SINGLEANT_CCK 0x00001000 /* Tx CCK pkts on Ant 0 only */
570 #define BFL3_FEMCTRL_SUB 0x00000007 /* acphy, subrevs of femctrl on top of srom_femctrl */
571 #define BFL3_RCAL_WAR 0x00000008 /* acphy, rcal war active on this board (4335a0) */
572 #define BFL3_TXGAINTBLID 0x00000070 /* acphy, txgain table id */
573 #define BFL3_TXGAINTBLID_SHIFT 0x4 /* acphy, txgain table id shift bit */
574 #define BFL3_TSSI_DIV_WAR 0x00000080 /* acphy, Seperate paparam for 20/40/80 */
575 #define BFL3_TSSI_DIV_WAR_SHIFT 0x7 /* acphy, Seperate paparam for 20/40/80 shift bit */
576 #define BFL3_FEMTBL_FROM_NVRAM 0x00000100 /* acphy, femctrl table is read from nvram */
577 #define BFL3_FEMTBL_FROM_NVRAM_SHIFT 0x8 /* acphy, femctrl table is read from nvram */
578 #define BFL3_AGC_CFG_2G 0x00000200 /* acphy, gain control configuration for 2G */
579 #define BFL3_AGC_CFG_5G 0x00000400 /* acphy, gain control configuration for 5G */
580 #define BFL3_PPR_BIT_EXT 0x00000800 /* acphy, bit position for 1bit extension for ppr */
581 #define BFL3_PPR_BIT_EXT_SHIFT 11 /* acphy, bit shift for 1bit extension for ppr */
582 #define BFL3_BBPLL_SPR_MODE_DIS 0x00001000 /* acphy, disables bbpll spur modes */
583 #define BFL3_RCAL_OTP_VAL_EN 0x00002000 /* acphy, to read rcal_trim value from otp */
584 #define BFL3_2GTXGAINTBL_BLANK 0x00004000 /* acphy, blank the first X ticks of 2g gaintbl */
585 #define BFL3_2GTXGAINTBL_BLANK_SHIFT 14 /* acphy, blank the first X ticks of 2g gaintbl */
586 #define BFL3_5GTXGAINTBL_BLANK 0x00008000 /* acphy, blank the first X ticks of 5g gaintbl */
587 #define BFL3_5GTXGAINTBL_BLANK_SHIFT 15 /* acphy, blank the first X ticks of 5g gaintbl */
588 #define BFL3_PHASETRACK_MAX_ALPHABETA 0x00010000 /* acphy, to max out alpha,beta to 511 */
589 #define BFL3_PHASETRACK_MAX_ALPHABETA_SHIFT 16 /* acphy, to max out alpha,beta to 511 */
590 /* acphy, to use backed off gaintbl for lte-coex */
591 #define BFL3_LTECOEX_GAINTBL_EN 0x00060000
592 /* acphy, to use backed off gaintbl for lte-coex */
593 #define BFL3_LTECOEX_GAINTBL_EN_SHIFT 17
594 #define BFL3_5G_SPUR_WAR 0x00080000 /* acphy, enable spur WAR in 5G band */
595 #define BFL3_1X1_RSDB_ANT 0x01000000 /* to find if 2-ant RSDB board or 1-ant RSDB board */
596 #define BFL3_1X1_RSDB_ANT_SHIFT 24
598 /* acphy: lpmode2g and lpmode_5g related boardflags */
599 #define BFL3_ACPHY_LPMODE_2G 0x00300000 /* bits 20:21 for lpmode_2g choice */
600 #define BFL3_ACPHY_LPMODE_2G_SHIFT 20
602 #define BFL3_ACPHY_LPMODE_5G 0x00C00000 /* bits 22:23 for lpmode_5g choice */
603 #define BFL3_ACPHY_LPMODE_5G_SHIFT 22
605 #define BFL3_EXT_LPO_ISCLOCK 0x02000000 /* External LPO is clock, not x-tal */
606 #define BFL3_FORCE_INT_LPO_SEL 0x04000000 /* Force internal lpo */
607 #define BFL3_FORCE_EXT_LPO_SEL 0x08000000 /* Force external lpo */
609 #define BFL3_EN_BRCM_IMPBF 0x10000000 /* acphy, Allow BRCM Implicit TxBF */
610 #define BFL3_AVVMID_FROM_NVRAM 0x40000000 /* Read Av Vmid from NVRAM */
611 #define BFL3_VLIN_EN_FROM_NVRAM 0x80000000 /* Read Vlin En from NVRAM */
613 #define BFL3_AVVMID_FROM_NVRAM_SHIFT 30 /* Read Av Vmid from NVRAM */
614 #define BFL3_VLIN_EN_FROM_NVRAM_SHIFT 31 /* Enable Vlin from NVRAM */
617 /* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
618 #define BOARD_GPIO_BTC3W_IN 0x850 /* bit 4 is RF_ACTIVE, bit 6 is STATUS, bit 11 is PRI */
619 #define BOARD_GPIO_BTC3W_OUT 0x020 /* bit 5 is TX_CONF */
620 #define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistence Input */
621 #define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistence Out */
622 #define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistence Input */
623 #define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistence Out */
624 #define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
625 #define BOARD_GPIO_12 0x1000 /* gpio 12 */
626 #define BOARD_GPIO_13 0x2000 /* gpio 13 */
627 #define BOARD_GPIO_BTC4_IN 0x0800 /* gpio 11, coex4, in */
628 #define BOARD_GPIO_BTC4_BT 0x2000 /* gpio 12, coex4, bt active */
629 #define BOARD_GPIO_BTC4_STAT 0x4000 /* gpio 14, coex4, status */
630 #define BOARD_GPIO_BTC4_WLAN 0x8000 /* gpio 15, coex4, wlan active */
631 #define BOARD_GPIO_1_WLAN_PWR 0x02 /* throttle WLAN power on X21 board */
632 #define BOARD_GPIO_2_WLAN_PWR 0x04 /* throttle WLAN power on X29C board */
633 #define BOARD_GPIO_3_WLAN_PWR 0x08 /* throttle WLAN power on X28 board */
634 #define BOARD_GPIO_4_WLAN_PWR 0x10 /* throttle WLAN power on X19 board */
636 #define GPIO_BTC4W_OUT_4312 0x010 /* bit 4 is BT_IODISABLE */
637 #define GPIO_BTC4W_OUT_43224 0x020 /* bit 5 is BT_IODISABLE */
638 #define GPIO_BTC4W_OUT_43224_SHARED 0x0e0 /* bit 5 is BT_IODISABLE */
639 #define GPIO_BTC4W_OUT_43225 0x0e0 /* bit 5 BT_IODISABLE, bit 6 SW_BT, bit 7 SW_WL */
640 #define GPIO_BTC4W_OUT_43421 0x020 /* bit 5 is BT_IODISABLE */
641 #define GPIO_BTC4W_OUT_4313 0x060 /* bit 5 SW_BT, bit 6 SW_WL */
642 #define GPIO_BTC4W_OUT_4331_SHARED 0x010 /* GPIO 4 */
644 #define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
645 #define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
646 #define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal power-up */
647 #define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL power-down */
649 /* power control defines */
650 #define PLL_DELAY 150 /* us pll on delay */
651 #define FREF_DELAY 200 /* us fref change delay */
652 #define MIN_SLOW_CLK 32 /* us Slow clock period */
653 #define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
655 #ifndef LINUX_POSTMOGRIFY_REMOVAL
656 /* Reference Board Types */
657 #define BU4710_BOARD 0x0400
658 #define VSIM4710_BOARD 0x0401
659 #define QT4710_BOARD 0x0402
661 #define BU4309_BOARD 0x040a
662 #define BCM94309CB_BOARD 0x040b
663 #define BCM94309MP_BOARD 0x040c
664 #define BCM4309AP_BOARD 0x040d
666 #define BCM94302MP_BOARD 0x040e
668 #define BU4306_BOARD 0x0416
669 #define BCM94306CB_BOARD 0x0417
670 #define BCM94306MP_BOARD 0x0418
672 #define BCM94710D_BOARD 0x041a
673 #define BCM94710R1_BOARD 0x041b
674 #define BCM94710R4_BOARD 0x041c
675 #define BCM94710AP_BOARD 0x041d
677 #define BU2050_BOARD 0x041f
679 #define BCM94306P50_BOARD 0x0420
681 #define BCM94309G_BOARD 0x0421
683 #define BU4704_BOARD 0x0423
684 #define BU4702_BOARD 0x0424
686 #define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
688 #define MPSG4306_BOARD 0x0427
690 #define BCM94702MN_BOARD 0x0428
692 /* BCM4702 1U CompactPCI Board */
693 #define BCM94702CPCI_BOARD 0x0429
695 /* BCM4702 with BCM95380 VLAN Router */
696 #define BCM95380RR_BOARD 0x042a
698 /* cb4306 with SiGe PA */
699 #define BCM94306CBSG_BOARD 0x042b
701 /* cb4306 with SiGe PA */
702 #define PCSG94306_BOARD 0x042d
704 /* bu4704 with sdram */
705 #define BU4704SD_BOARD 0x042e
707 /* Dual 11a/11g Router */
708 #define BCM94704AGR_BOARD 0x042f
710 /* 11a-only minipci */
711 #define BCM94308MP_BOARD 0x0430
713 /* 4306/gprs combo */
714 #define BCM94306GPRS_BOARD 0x0432
716 /* BCM5365/BCM4704 FPGA Bringup Board */
717 #define BU5365_FPGA_BOARD 0x0433
719 #define BU4712_BOARD 0x0444
720 #define BU4712SD_BOARD 0x045d
721 #define BU4712L_BOARD 0x045f
724 #define BCM94712AP_BOARD 0x0445
725 #define BCM94712P_BOARD 0x0446
728 #define BU4318_BOARD 0x0447
729 #define CB4318_BOARD 0x0448
730 #define MPG4318_BOARD 0x0449
731 #define MP4318_BOARD 0x044a
732 #define SD4318_BOARD 0x044b
735 #define BCM94313BU_BOARD 0x050f
736 #define BCM94313HM_BOARD 0x0510
737 #define BCM94313EPA_BOARD 0x0511
738 #define BCM94313HMG_BOARD 0x051C
741 #define BCM96338_BOARD 0x6338
742 #define BCM96348_BOARD 0x6348
743 #define BCM96358_BOARD 0x6358
744 #define BCM96368_BOARD 0x6368
746 /* Another mp4306 with SiGe */
747 #define BCM94306P_BOARD 0x044c
750 #define BCM94303MP_BOARD 0x044e
753 #define BCM94306MPSGH_BOARD 0x044f
755 /* BRCM 4306 w/ Front End Modules */
756 #define BCM94306MPM 0x0450
757 #define BCM94306MPL 0x0453
760 #define BCM94712AGR_BOARD 0x0451
763 #define PC4303_BOARD 0x0454
766 #define BCM95350K_BOARD 0x0455
769 #define BCM95350R_BOARD 0x0456
772 #define BCM94306MPLNA_BOARD 0x0457
775 #define BU4320_BOARD 0x0458
776 #define BU4320S_BOARD 0x0459
777 #define BCM94320PH_BOARD 0x045a
780 #define BCM94306MPH_BOARD 0x045b
783 #define BCM94306PCIV_BOARD 0x045c
785 #define BU4712SD_BOARD 0x045d
787 #define BCM94320PFLSH_BOARD 0x045e
789 #define BU4712L_BOARD 0x045f
790 #define BCM94712LGR_BOARD 0x0460
791 #define BCM94320R_BOARD 0x0461
793 #define BU5352_BOARD 0x0462
795 #define BCM94318MPGH_BOARD 0x0463
797 #define BU4311_BOARD 0x0464
798 #define BCM94311MC_BOARD 0x0465
799 #define BCM94311MCAG_BOARD 0x0466
801 #define BCM95352GR_BOARD 0x0467
804 #define BCM95351AGR_BOARD 0x0470
807 #define BCM94704MPCB_BOARD 0x0472
810 #define BU4785_BOARD 0x0478
813 #define BU4321_BOARD 0x046b
814 #define BU4321E_BOARD 0x047c
815 #define MP4321_BOARD 0x046c
816 #define CB2_4321_BOARD 0x046d
817 #define CB2_4321_AG_BOARD 0x0066
818 #define MC4321_BOARD 0x046e
821 #define BU4328_BOARD 0x0481
822 #define BCM4328SDG_BOARD 0x0482
823 #define BCM4328SDAG_BOARD 0x0483
824 #define BCM4328UG_BOARD 0x0484
825 #define BCM4328UAG_BOARD 0x0485
826 #define BCM4328PC_BOARD 0x0486
827 #define BCM4328CF_BOARD 0x0487
830 #define BCM94325DEVBU_BOARD 0x0490
831 #define BCM94325BGABU_BOARD 0x0491
833 #define BCM94325SDGWB_BOARD 0x0492
835 #define BCM94325SDGMDL_BOARD 0x04aa
836 #define BCM94325SDGMDL2_BOARD 0x04c6
837 #define BCM94325SDGMDL3_BOARD 0x04c9
839 #define BCM94325SDABGWBA_BOARD 0x04e1
842 #define BCM94322MC_SSID 0x04a4
843 #define BCM94322USB_SSID 0x04a8 /* dualband */
844 #define BCM94322HM_SSID 0x04b0
845 #define BCM94322USB2D_SSID 0x04bf /* single band discrete front end */
848 #define BCM4312MCGSG_BOARD 0x04b5
851 #define BCM94315DEVBU_SSID 0x04c2
852 #define BCM94315USBGP_SSID 0x04c7
853 #define BCM94315BGABU_SSID 0x04ca
854 #define BCM94315USBGP41_SSID 0x04cb
857 #define BCM94319DEVBU_SSID 0X04e5
858 #define BCM94319USB_SSID 0X04e6
859 #define BCM94319SD_SSID 0X04e7
862 #define BCM94716NR2_SSID 0x04cd
865 #define BCM94319DEVBU_SSID 0X04e5
866 #define BCM94319USBNP4L_SSID 0X04e6
867 #define BCM94319WLUSBN4L_SSID 0X04e7
868 #define BCM94319SDG_SSID 0X04ea
869 #define BCM94319LCUSBSDN4L_SSID 0X04eb
870 #define BCM94319USBB_SSID 0x04ee
871 #define BCM94319LCSDN4L_SSID 0X0507
872 #define BCM94319LSUSBN4L_SSID 0X0508
873 #define BCM94319SDNA4L_SSID 0X0517
874 #define BCM94319SDELNA4L_SSID 0X0518
875 #define BCM94319SDELNA6L_SSID 0X0539
876 #define BCM94319ARCADYAN_SSID 0X0546
877 #define BCM94319WINDSOR_SSID 0x0561
878 #define BCM94319MLAP_SSID 0x0562
879 #define BCM94319SDNA_SSID 0x058b
880 #define BCM94319BHEMU3_SSID 0x0563
881 #define BCM94319SDHMB_SSID 0x058c
882 #define BCM94319SDBREF_SSID 0x05a1
883 #define BCM94319USBSDB_SSID 0x05a2
887 #define BCM94329AGB_SSID 0X04b9
888 #define BCM94329TDKMDL1_SSID 0X04ba
889 #define BCM94329TDKMDL11_SSID 0X04fc
890 #define BCM94329OLYMPICN18_SSID 0X04fd
891 #define BCM94329OLYMPICN90_SSID 0X04fe
892 #define BCM94329OLYMPICN90U_SSID 0X050c
893 #define BCM94329OLYMPICN90M_SSID 0X050b
894 #define BCM94329AGBF_SSID 0X04ff
895 #define BCM94329OLYMPICX17_SSID 0X0504
896 #define BCM94329OLYMPICX17M_SSID 0X050a
897 #define BCM94329OLYMPICX17U_SSID 0X0509
898 #define BCM94329OLYMPICUNO_SSID 0X0564
899 #define BCM94329MOTOROLA_SSID 0X0565
900 #define BCM94329OLYMPICLOCO_SSID 0X0568
901 /* 4336 SDIO board types */
902 #define BCM94336SD_WLBGABU_SSID 0x0511
903 #define BCM94336SD_WLBGAREF_SSID 0x0519
904 #define BCM94336SDGP_SSID 0x0538
905 #define BCM94336SDG_SSID 0x0519
906 #define BCM94336SDGN_SSID 0x0538
907 #define BCM94336SDGFC_SSID 0x056B
909 /* 4330 SDIO board types */
910 #define BCM94330SDG_SSID 0x0528
911 #define BCM94330SD_FCBGABU_SSID 0x052e
912 #define BCM94330SD_WLBGABU_SSID 0x052f
913 #define BCM94330SD_FCBGA_SSID 0x0530
914 #define BCM94330FCSDAGB_SSID 0x0532
915 #define BCM94330OLYMPICAMG_SSID 0x0549
916 #define BCM94330OLYMPICAMGEPA_SSID 0x054F
917 #define BCM94330OLYMPICUNO3_SSID 0x0551
918 #define BCM94330WLSDAGB_SSID 0x0547
919 #define BCM94330CSPSDAGBB_SSID 0x054A
922 #define BCM943224X21 0x056e
923 #define BCM943224X21_FCC 0x00d1
924 #define BCM943224X21B 0x00e9
925 #define BCM943224M93 0x008b
926 #define BCM943224M93A 0x0090
927 #define BCM943224X16 0x0093
928 #define BCM94322X9 0x008d
929 #define BCM94322M35e 0x008e
932 #define BCM943228BU8_SSID 0x0540
933 #define BCM943228BU9_SSID 0x0541
934 #define BCM943228BU_SSID 0x0542
935 #define BCM943227HM4L_SSID 0x0543
936 #define BCM943227HMB_SSID 0x0544
937 #define BCM943228HM4L_SSID 0x0545
938 #define BCM943228SD_SSID 0x0573
941 #define BCM943239MOD_SSID 0x05ac
942 #define BCM943239REF_SSID 0x05aa
945 #define BCM94331X19 0x00D6 /* X19B */
946 #define BCM94331X28 0x00E4 /* X28 */
947 #define BCM94331X28B 0x010E /* X28B */
948 #define BCM94331PCIEBT3Ax_SSID BCM94331X28
949 #define BCM94331X12_2G_SSID 0x00EC /* X12 2G */
950 #define BCM94331X12_5G_SSID 0x00ED /* X12 5G */
951 #define BCM94331X29B 0x00EF /* X29B */
952 #define BCM94331X29D 0x010F /* X29D */
953 #define BCM94331CSAX_SSID BCM94331X29B
954 #define BCM94331X19C 0x00F5 /* X19C */
955 #define BCM94331X33 0x00F4 /* X33 */
956 #define BCM94331BU_SSID 0x0523
957 #define BCM94331S9BU_SSID 0x0524
958 #define BCM94331MC_SSID 0x0525
959 #define BCM94331MCI_SSID 0x0526
960 #define BCM94331PCIEBT4_SSID 0x0527
961 #define BCM94331HM_SSID 0x0574
962 #define BCM94331PCIEDUAL_SSID 0x059B
963 #define BCM94331MCH5_SSID 0x05A9
964 #define BCM94331CS_SSID 0x05C6
965 #define BCM94331CD_SSID 0x05DA
968 #define BCM94314BU_SSID 0x05b1
971 #define BCM953572BU_SSID 0x058D
972 #define BCM953572NR2_SSID 0x058E
973 #define BCM947188NR2_SSID 0x058F
974 #define BCM953572SDRNR2_SSID 0x0590
977 #define BCM943236OLYMPICSULLEY_SSID 0x594
978 #define BCM943236PREPROTOBLU2O3_SSID 0x5b9
979 #define BCM943236USBELNA_SSID 0x5f8
982 #define BCM94314BUSDIO_SSID 0x05c8
983 #define BCM94314BGABU_SSID 0x05c9
984 #define BCM94314HMEPA_SSID 0x05ca
985 #define BCM94314HMEPABK_SSID 0x05cb
986 #define BCM94314SUHMEPA_SSID 0x05cc
987 #define BCM94314SUHM_SSID 0x05cd
988 #define BCM94314HM_SSID 0x05d1
991 #define BCM94334FCAGBI_SSID 0x05df
992 #define BCM94334WLAGBI_SSID 0x05dd
995 #define BCM94335X52 0x0114
998 #define BCM94345_SSID 0x0687
1001 #define BCM94360X52C 0X0117
1002 #define BCM94360X52D 0X0137
1003 #define BCM94360X29C 0X0112
1004 #define BCM94360X29CP2 0X0134
1005 #define BCM94360X29CP3 0X013B
1006 #define BCM94360X51 0x0111
1007 #define BCM94360X51P2 0x0129
1008 #define BCM94360X51P3 0x0142
1009 #define BCM94360X51A 0x0135
1010 #define BCM94360X51B 0x0136
1011 #define BCM94360CS 0x061B
1012 #define BCM94360J28_D11AC2G 0x0c00
1013 #define BCM94360J28_D11AC5G 0x0c01
1014 #define BCM94360USBH5_D11AC5G 0x06aa
1015 #define BCM94360MCM5 0x06d8
1018 #define BCM94350X52B 0X0116
1019 #define BCM94350X14 0X0131
1022 #define BCM943217BU_SSID 0x05d5
1023 #define BCM943217HM2L_SSID 0x05d6
1024 #define BCM943217HMITR2L_SSID 0x05d7
1027 #define BCM943142HM_SSID 0x05e0
1028 #endif /* LINUX_POSTMOGRIFY_REMOVAL */
1031 #define BCM943341WLABGS_SSID 0x062d
1034 #define BCM943342FCAGBI_SSID 0x0641
1036 /* 43602 Boards, unclear yet what boards will be created. */
1037 #define BCM943602RSVD1_SSID 0x06a5
1038 #define BCM943602RSVD2_SSID 0x06a6
1039 #define BCM943602X87 0X0133
1040 #define BCM943602X238 0X0132
1042 /* # of GPIO pins */
1043 #define GPIO_NUMPINS 32
1045 /* These values are used by dhd host driver. */
1046 #define RDL_RAM_BASE_4319 0x60000000
1047 #define RDL_RAM_BASE_4329 0x60000000
1048 #define RDL_RAM_SIZE_4319 0x48000
1049 #define RDL_RAM_SIZE_4329 0x48000
1050 #define RDL_RAM_SIZE_43236 0x70000
1051 #define RDL_RAM_BASE_43236 0x60000000
1052 #define RDL_RAM_SIZE_4328 0x60000
1053 #define RDL_RAM_BASE_4328 0x80000000
1054 #define RDL_RAM_SIZE_4322 0x60000
1055 #define RDL_RAM_BASE_4322 0x60000000
1056 #define RDL_RAM_SIZE_4360 0xA0000
1057 #define RDL_RAM_BASE_4360 0x60000000
1058 #define RDL_RAM_SIZE_43242 0x90000
1059 #define RDL_RAM_BASE_43242 0x60000000
1060 #define RDL_RAM_SIZE_43143 0x70000
1061 #define RDL_RAM_BASE_43143 0x60000000
1062 #define RDL_RAM_SIZE_4350 0xC0000
1063 #define RDL_RAM_BASE_4350 0x180800
1065 /* generic defs for nvram "muxenab" bits
1066 * Note: these differ for 4335a0. refer bcmchipc.h for specific mux options.
1068 #define MUXENAB_UART 0x00000001
1069 #define MUXENAB_GPIO 0x00000002
1070 #define MUXENAB_ERCX 0x00000004 /* External Radio BT coex */
1071 #define MUXENAB_JTAG 0x00000008
1072 #define MUXENAB_HOST_WAKE 0x00000010 /* configure GPIO for SDIO host_wake */
1073 #define MUXENAB_I2S_EN 0x00000020
1074 #define MUXENAB_I2S_MASTER 0x00000040
1075 #define MUXENAB_I2S_FULL 0x00000080
1076 #define MUXENAB_SFLASH 0x00000100
1077 #define MUXENAB_RFSWCTRL0 0x00000200
1078 #define MUXENAB_RFSWCTRL1 0x00000400
1079 #define MUXENAB_RFSWCTRL2 0x00000800
1080 #define MUXENAB_SECI 0x00001000
1081 #define MUXENAB_BT_LEGACY 0x00002000
1082 #define MUXENAB_HOST_WAKE1 0x00004000 /* configure alternative GPIO for SDIO host_wake */
1085 #define FLASH_KERNEL_NFLASH 0x00000001
1086 #define FLASH_BOOT_NFLASH 0x00000002
1088 #endif /* _BCMDEVS_H */
projects / firefly-linux-kernel-4.4.55.git / blob