2 * Linux DHD Bus Module for PCIE
4 * Copyright (C) 1999-2016, Broadcom Corporation
6 * Unless you and Broadcom execute a separate written software license
7 * agreement governing use of this software, this software is licensed to you
8 * under the terms of the GNU General Public License version 2 (the "GPL"),
9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
10 * following added to such license:
12 * As a special exception, the copyright holders of this software give you
13 * permission to link this software with independent modules, and to copy and
14 * distribute the resulting executable under terms of your choice, provided that
15 * you also meet, for each linked independent module, the terms and conditions of
16 * the license of that module. An independent module is a module which is not
17 * derived from this software. The special exception does not apply to any
18 * modifications of the software.
20 * Notwithstanding the above, under no circumstances may you combine this
21 * software in any way with any other Broadcom software provided under a license
22 * other than the GPL, without Broadcom's express prior written consent.
25 * <<Broadcom-WL-IPTag/Open:>>
27 * $Id: dhd_pcie.h 607608 2015-12-21 13:14:19Z $
36 #ifdef SUPPORT_LINKDOWN_RECOVERY
37 #ifdef CONFIG_ARCH_MSM
39 #include <linux/msm_pcie.h>
41 #include <mach/msm_pcie.h>
42 #endif /* CONFIG_PCI_MSM */
43 #endif /* CONFIG_ARCH_MSM */
44 #ifdef EXYNOS_PCIE_LINKDOWN_RECOVERY
45 #ifdef CONFIG_SOC_EXYNOS8890
46 #include <linux/exynos-pci-noti.h>
47 extern int exynos_pcie_register_event(struct exynos_pcie_register_event *reg);
48 extern int exynos_pcie_deregister_event(struct exynos_pcie_register_event *reg);
49 #endif /* CONFIG_SOC_EXYNOS8890 */
50 #endif /* EXYNOS_PCIE_LINKDOWN_RECOVERY */
51 #endif /* SUPPORT_LINKDOWN_RECOVERY */
53 #ifdef DHD_PCIE_RUNTIMEPM
54 #include <linux/mutex.h>
55 #include <linux/wait.h>
57 #define DEFAULT_DHD_RUNTIME_MS 100
58 #ifndef CUSTOM_DHD_RUNTIME_MS
59 #define CUSTOM_DHD_RUNTIME_MS DEFAULT_DHD_RUNTIME_MS
60 #endif /* CUSTOM_DHD_RUNTIME_MS */
63 #ifndef MAX_IDLE_COUNT
64 #define MAX_IDLE_COUNT 16
65 #endif /* MAX_IDLE_COUNT */
67 #ifndef MAX_RESUME_WAIT
68 #define MAX_RESUME_WAIT 100
69 #endif /* MAX_RESUME_WAIT */
70 #endif /* DHD_PCIE_RUNTIMEPM */
74 #define PCMSGBUF_HDRLEN 0
75 #define DONGLE_REG_MAP_SIZE (32 * 1024)
76 #define DONGLE_TCM_MAP_SIZE (4096 * 1024)
77 #define DONGLE_MIN_MEMSIZE (128 *1024)
79 #define DHD_PCIE_SUCCESS 0
80 #define DHD_PCIE_FAILURE 1
81 #endif /* DHD_DEBUG */
82 #define REMAP_ENAB(bus) ((bus)->remap)
83 #define REMAP_ISADDR(bus, a) (((a) >= ((bus)->orig_ramsize)) && ((a) < ((bus)->ramsize)))
85 #ifdef SUPPORT_LINKDOWN_RECOVERY
86 #ifdef CONFIG_ARCH_MSM
87 #define struct_pcie_notify struct msm_pcie_notify
88 #define struct_pcie_register_event struct msm_pcie_register_event
89 #endif /* CONFIG_ARCH_MSM */
90 #ifdef EXYNOS_PCIE_LINKDOWN_RECOVERY
91 #ifdef CONFIG_SOC_EXYNOS8890
92 #define struct_pcie_notify struct exynos_pcie_notify
93 #define struct_pcie_register_event struct exynos_pcie_register_event
94 #endif /* CONFIG_SOC_EXYNOS8890 */
95 #endif /* EXYNOS_PCIE_LINKDOWN_RECOVERY */
96 #endif /* SUPPORT_LINKDOWN_RECOVERY */
99 * Router with 4366 can have 128 stations and 16 BSS,
100 * hence (128 stations x 4 access categories for ucast) + 16 bc/mc flowrings
102 #define MAX_DHD_TX_FLOWS 320
104 /* user defined data structures */
105 /* Device console log buffer state */
106 #define CONSOLE_LINE_MAX 192
107 #define CONSOLE_BUFFER_MAX (8 * 1024)
109 #ifndef MAX_CNTL_D3ACK_TIMEOUT
110 #define MAX_CNTL_D3ACK_TIMEOUT 2
111 #endif /* MAX_CNTL_D3ACK_TIMEOUT */
115 typedef struct dhd_console {
116 uint count; /* Poll interval msec counter */
117 uint log_addr; /* Log struct address (fixed) */
118 hnd_log_t log; /* Log struct (host copy) */
119 uint bufsize; /* Size of log buffer */
120 uint8 *buf; /* Log buffer (host copy) */
121 uint last; /* Last buffer read index */
123 #endif /* DHD_DEBUG */
124 typedef struct ring_sh_info {
125 uint32 ring_mem_addr;
130 typedef struct dhd_bus {
132 struct pci_dev *dev; /* pci device handle */
133 dll_t const_flowring; /* constructed list of tx flowring queues */
135 si_t *sih; /* Handle for SI calls */
136 char *vars; /* Variables (from CIS and/or other) */
137 uint varsz; /* Size of variables buffer */
138 uint32 sbaddr; /* Current SB window pointer (-1, invalid) */
139 sbpcieregs_t *reg; /* Registers for PCIE core */
141 uint armrev; /* CPU core revision */
142 uint ramrev; /* SOCRAM core revision */
143 uint32 ramsize; /* Size of RAM in SOCRAM (bytes) */
144 uint32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
145 uint32 srmemsize; /* Size of SRMEM */
147 uint32 bus; /* gSPI or SDIO bus */
148 uint32 intstatus; /* Intstatus bits (events) pending */
149 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
150 bool fcstate; /* State of dongle flow-control */
152 uint16 cl_devid; /* cached devid for dhdsdio_probe_attach() */
153 char *fw_path; /* module_param: path to firmware image */
154 char *nv_path; /* module_param: path to nvram vars file */
155 #ifdef CACHE_FW_IMAGES
156 int processed_nvram_params_len; /* Modified len of NVRAM info */
160 struct pktq txq; /* Queue length used for flow-control */
162 bool intr; /* Use interrupts */
163 bool ipend; /* Device interrupt is pending */
164 bool intdis; /* Interrupts disabled by isr */
165 uint intrcount; /* Count of device interrupt callbacks */
166 uint lastintrs; /* Count as of last watchdog timer */
169 dhd_console_t console; /* Console output polling support */
170 uint console_addr; /* Console address from shared struct */
171 #endif /* DHD_DEBUG */
173 bool alp_only; /* Don't use HT clock (ALP only) */
175 bool remap; /* Contiguous 1MB RAM: 512K socram + 512K devram
176 * Available with socram rev 16
177 * Remap region not DMA-able
180 uint32 dongle_ram_base;
183 pciedev_shared_t *pcie_sh;
186 volatile char *regs; /* pci device memory va */
187 volatile char *tcm; /* pci device memory va */
189 uint32 nvram_csm; /* Nvram checksum */
193 uint32 *pcie_mb_intr_addr;
194 void *pcie_mb_intr_osh;
197 /* version 3 shared struct related info start */
198 ring_sh_info_t ring_sh[BCMPCIE_COMMON_MSGRINGS + MAX_DHD_TX_FLOWS];
199 uint8 h2d_ring_count;
200 uint8 d2h_ring_count;
202 uint32 ring_state_ptr;
204 uint32 d2h_dma_scratch_buffer_mem_addr;
206 uint32 h2d_mb_data_ptr_addr;
207 uint32 d2h_mb_data_ptr_addr;
208 /* version 3 shared struct related info end */
211 bool ltrsleep_on_unload;
212 uint wait_for_d3_ack;
213 uint32 max_sub_queues;
218 dhd_timeout_t doorbell_timer;
219 bool device_wake_state;
223 #endif /* PCIE_OOB */
224 #ifdef SUPPORT_LINKDOWN_RECOVERY
225 #if defined(CONFIG_ARCH_MSM) || (defined(EXYNOS_PCIE_LINKDOWN_RECOVERY) && \
226 defined(CONFIG_SOC_EXYNOS8890))
227 #ifdef CONFIG_ARCH_MSM
228 uint8 no_cfg_restore;
229 #endif /* CONFIG_ARCH_MSM */
230 struct_pcie_register_event pcie_event;
231 #endif /* CONFIG_ARCH_MSM || (EXYNOS_PCIE_LINKDOWN_RECOVERY && CONFIG_SOC_EXYNOS8890) */
232 #endif /* SUPPORT_LINKDOWN_RECOVERY */
233 #ifdef DHD_PCIE_RUNTIMEPM
234 int32 idlecount; /* Activity timeout counter */
235 int32 idletime; /* Control for activity timeout */
236 int32 bus_wake; /* For wake up the bus */
237 bool runtime_resume_done; /* For check runtime suspend end */
238 struct mutex pm_lock; /* Synchronize for system PM & runtime PM */
239 wait_queue_head_t rpm_queue; /* wait-queue for bus wake up */
240 #endif /* DHD_PCIE_RUNTIMEPM */
241 uint32 d3_inform_cnt;
242 uint32 d0_inform_cnt;
243 uint32 d0_inform_in_use_cnt;
245 uint32 d3_ack_war_cnt;
247 uint32 pci_d3hot_done;
250 /* function declarations */
252 extern uint32* dhdpcie_bus_reg_map(osl_t *osh, ulong addr, int size);
253 extern int dhdpcie_bus_register(void);
254 extern void dhdpcie_bus_unregister(void);
255 extern bool dhdpcie_chipmatch(uint16 vendor, uint16 device);
257 extern struct dhd_bus* dhdpcie_bus_attach(osl_t *osh,
258 volatile char *regs, volatile char *tcm, void *pci_dev);
259 extern uint32 dhdpcie_bus_cfg_read_dword(struct dhd_bus *bus, uint32 addr, uint32 size);
260 extern void dhdpcie_bus_cfg_write_dword(struct dhd_bus *bus, uint32 addr, uint32 size, uint32 data);
261 extern void dhdpcie_bus_intr_enable(struct dhd_bus *bus);
262 extern void dhdpcie_bus_intr_disable(struct dhd_bus *bus);
263 extern void dhdpcie_bus_release(struct dhd_bus *bus);
264 extern int32 dhdpcie_bus_isr(struct dhd_bus *bus);
265 extern void dhdpcie_free_irq(dhd_bus_t *bus);
266 extern void dhdpcie_bus_ringbell_fast(struct dhd_bus *bus, uint32 value);
267 extern int dhdpcie_bus_suspend(struct dhd_bus *bus, bool state);
268 extern int dhdpcie_pci_suspend_resume(struct dhd_bus *bus, bool state);
269 extern bool dhdpcie_tcm_valid(dhd_bus_t *bus);
270 extern void dhdpcie_bus_dongle_print_hwregs(struct dhd_bus *bus);
271 #ifndef BCMPCIE_OOB_HOST_WAKE
272 extern void dhdpcie_pme_active(osl_t *osh, bool enable);
273 #endif /* !BCMPCIE_OOB_HOST_WAKE */
274 extern bool dhdpcie_pme_cap(osl_t *osh);
275 extern int dhdpcie_start_host_pcieclock(dhd_bus_t *bus);
276 extern int dhdpcie_stop_host_pcieclock(dhd_bus_t *bus);
277 extern int dhdpcie_disable_device(dhd_bus_t *bus);
278 extern int dhdpcie_enable_device(dhd_bus_t *bus);
279 extern int dhdpcie_alloc_resource(dhd_bus_t *bus);
280 extern void dhdpcie_free_resource(dhd_bus_t *bus);
281 extern int dhdpcie_bus_request_irq(struct dhd_bus *bus);
282 #ifdef BCMPCIE_OOB_HOST_WAKE
283 extern int dhdpcie_oob_intr_register(dhd_bus_t *bus);
284 extern void dhdpcie_oob_intr_unregister(dhd_bus_t *bus);
285 extern void dhdpcie_oob_intr_set(dhd_bus_t *bus, bool enable);
286 #endif /* BCMPCIE_OOB_HOST_WAKE */
288 extern void dhd_oob_set_bt_reg_on(struct dhd_bus *bus, bool val);
289 extern int dhd_oob_get_bt_reg_on(struct dhd_bus *bus);
290 #endif /* PCIE_OOB */
292 #ifdef USE_EXYNOS_PCIE_RC_PMPATCH
293 #if defined(CONFIG_MACH_UNIVERSAL5433)
294 #define SAMSUNG_PCIE_DEVICE_ID 0xa5e3
295 #define SAMSUNG_PCIE_CH_NUM
296 #elif defined(CONFIG_MACH_UNIVERSAL7420)
297 #define SAMSUNG_PCIE_DEVICE_ID 0xa575
298 #define SAMSUNG_PCIE_CH_NUM 1
299 #elif defined(CONFIG_SOC_EXYNOS8890)
300 #define SAMSUNG_PCIE_DEVICE_ID 0xa544
301 #define SAMSUNG_PCIE_CH_NUM 0
303 #error "Not supported platform"
305 #ifdef CONFIG_MACH_UNIVERSAL5433
306 extern int exynos_pcie_pm_suspend(void);
307 extern int exynos_pcie_pm_resume(void);
309 extern int exynos_pcie_pm_suspend(int ch_num);
310 extern int exynos_pcie_pm_resume(int ch_num);
311 #endif /* CONFIG_MACH_UNIVERSAL5433 */
312 #endif /* USE_EXYNOS_PCIE_RC_PMPATCH */
314 extern int dhd_buzzz_dump_dngl(dhd_bus_t *bus);
315 #endif /* dhd_pcie_h */