2 ** $Id: //Department/DaVinci/BRANCHES/MT662X_593X_WIFI_DRIVER_V2_3/include/nic/mt6620_reg.h#1 $
5 /*! \file "mt6620_reg.h"
6 \brief The common register definition of mt6620
11 /*******************************************************************************
12 * Copyright (c) 2007 MediaTek Inc.
14 * All rights reserved. Copying, compilation, modification, distribution
15 * or any other use whatsoever of this material is strictly prohibited
16 * except in accordance with a Software License Agreement with
18 ********************************************************************************
21 /*******************************************************************************
24 * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND
25 * AGREES THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK
26 * SOFTWARE") RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE
27 * PROVIDED TO BUYER ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY
28 * DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT
29 * LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
30 * PARTICULAR PURPOSE OR NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE
31 * ANY WARRANTY WHATSOEVER WITH RESPECT TO THE SOFTWARE OF ANY THIRD PARTY
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39 * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL
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50 ********************************************************************************
54 ** $Log: mt6620_reg.h $
57 * [WCXRP00000412] [MT6620 Wi-Fi][FW/Driver] Dump firmware assert info at android kernel log
58 * Print firmware ASSERT info at Android kernel log, driver side
62 * [WPD00003833] [MT6620 and MT5931] Driver migration - move to new repository.
64 * 06 06 2010 kevin.huang
65 * [WPD00003832][MT6620 5931] Create driver base
66 * [MT6620 5931] Create driver base
69 * [WPD00001943]Create WiFi test driver framework on WinXP
70 * 1) add ACPI D0/D3 state switching support
71 * * * * 2) use more formal way to handle interrupt when the status is retrieved from enhanced RX response
72 ** \main\maintrunk.MT6620WiFiDriver_Prj\15 2009-12-10 16:44:18 GMT mtk02752
73 ** remove 5921 definitions
74 ** \main\maintrunk.MT6620WiFiDriver_Prj\14 2009-11-09 22:56:32 GMT mtk01084
75 ** modify HW register definitions
76 ** \main\maintrunk.MT6620WiFiDriver_Prj\13 2009-11-04 14:11:04 GMT mtk01084
77 ** modify default IER bits
78 ** \main\maintrunk.MT6620WiFiDriver_Prj\12 2009-10-29 19:52:32 GMT mtk01084
79 ** modify data struture
80 ** \main\maintrunk.MT6620WiFiDriver_Prj\11 2009-10-23 16:08:20 GMT mtk01084
81 ** \main\maintrunk.MT6620WiFiDriver_Prj\10 2009-10-13 21:58:53 GMT mtk01084
82 ** update for new HW architecture design
83 ** \main\maintrunk.MT6620WiFiDriver_Prj\9 2009-09-09 17:26:11 GMT mtk01084
84 ** add CFG_TEST_WITH_MT5921
85 ** \main\maintrunk.MT6620WiFiDriver_Prj\8 2009-05-18 20:59:57 GMT mtk01426
86 ** Update WHIER_DEFAULT value
87 ** \main\maintrunk.MT6620WiFiDriver_Prj\7 2009-05-07 16:57:36 GMT mtk01426
88 ** Update CHIP ID to 0x6620, and WHLPCR bit definition
89 ** \main\maintrunk.MT6620WiFiDriver_Prj\6 2009-04-28 10:34:57 GMT mtk01461
90 ** Add read WTSR and fix RX STATUS is DW align for SDIO_STATUS_ENHANCE mode
91 ** \main\maintrunk.MT6620WiFiDriver_Prj\5 2009-03-24 09:46:52 GMT mtk01084
93 ** \main\maintrunk.MT6620WiFiDriver_Prj\4 2009-03-23 00:32:24 GMT mtk01461
94 ** Define constants for TX PATH
95 ** \main\maintrunk.MT6620WiFiDriver_Prj\3 2009-03-18 20:54:10 GMT mtk01426
96 ** Add WHCR_MAX_HIF_RX_AGG_LEN_OFFSET definition
97 ** \main\maintrunk.MT6620WiFiDriver_Prj\2 2009-03-10 20:16:29 GMT mtk01426
102 #ifndef _MT6620_REG_H
103 #define _MT6620_REG_H
105 /*******************************************************************************
106 * C O M P I L E R F L A G S
107 ********************************************************************************
110 /*******************************************************************************
111 * E X T E R N A L R E F E R E N C E S
112 ********************************************************************************
115 /*******************************************************************************
117 ********************************************************************************
120 /*******************************************************************************
122 ********************************************************************************
126 /*******************************************************************************
127 * P U B L I C D A T A
128 ********************************************************************************
131 /*******************************************************************************
132 * P R I V A T E D A T A
133 ********************************************************************************
136 /*******************************************************************************
138 ********************************************************************************
141 /*******************************************************************************
142 * F U N C T I O N D E C L A R A T I O N S
143 ********************************************************************************
146 /*******************************************************************************
148 ********************************************************************************
151 //1 MT6620 MCR Definition
156 #define MCR_WCIR 0x0000
158 //4 HIF Low Power Control Register
159 #define MCR_WHLPCR 0x0004
160 //#define MCR_WHLPCR_BYTE1 0x0005
163 //4 Control Status Register
164 #define MCR_WSDIOCSR 0x0008
165 #define MCR_WSPICSR 0x0008
167 //4 HIF Control Register
168 #define MCR_WHCR 0x000C
170 //4 HIF Interrupt Status Register
171 #define MCR_WHISR 0x0010
173 //4 HIF Interrupt Enable Register
174 #define MCR_WHIER 0x0014
176 //4 Abnormal Status Register
177 #define MCR_WASR 0x0018
179 //4 WLAN Software Interrupt Control Register
180 #define MCR_WSICR 0x001C
182 //4 WLAN TX Status Register
183 #define MCR_WTSR0 0x0020
185 //4 WLAN TX Status Register
186 #define MCR_WTSR1 0x0024
188 //4 WLAN TX Data Register 0
189 #define MCR_WTDR0 0x0028
191 //4 WLAN TX Data Register 1
192 #define MCR_WTDR1 0x002C
194 //4 WLAN RX Data Register 0
195 #define MCR_WRDR0 0x0030
197 //4 WLAN RX Data Register 1
198 #define MCR_WRDR1 0x0034
200 //4 Host to Device Send Mailbox 0 Register
201 #define MCR_H2DSM0R 0x0038
203 //4 Host to Device Send Mailbox 1 Register
204 #define MCR_H2DSM1R 0x003c
206 //4 Device to Host Receive Mailbox 0 Register
207 #define MCR_D2HRM0R 0x0040
209 //4 Device to Host Receive Mailbox 1 Register
210 #define MCR_D2HRM1R 0x0044
212 //4 WLAN RX Packet Length Register
213 #define MCR_WRPLR 0x0048
218 //temp //#if CFG_SDIO_INTR_ENHANCE
219 typedef struct _ENHANCE_MODE_DATA_STRUCT_T {
235 UINT_16 u2NumValidRx0Len;
236 UINT_16 u2NumValidRx1Len;
237 UINT_16 au2Rx0Len[16];
238 UINT_16 au2Rx1Len[16];
240 UINT_32 au4RxStatusRaw[17];
242 UINT_32 u4RcvMailbox0;
243 UINT_32 u4RcvMailbox1;
244 } ENHANCE_MODE_DATA_STRUCT_T, *P_ENHANCE_MODE_DATA_STRUCT_T;
245 // #endif /* ENHANCE_MODE_DATA_STRUCT_T */
248 //2 Definition in each register
250 #define WCIR_WLAN_READY BIT(21)
251 #define WCIR_POR_INDICATOR BIT(20)
252 #define WCIR_REVISION_ID BITS(16,19)
253 #define WCIR_CHIP_ID BITS(0,15)
255 #define MTK_CHIP_REV 0x00006620
256 #define MTK_CHIP_MP_REVERSION_ID 0x0
259 #define WHLPCR_FW_OWN_REQ_CLR BIT(9)
260 #define WHLPCR_FW_OWN_REQ_SET BIT(8)
261 #define WHLPCR_IS_DRIVER_OWN BIT(8)
262 #define WHLPCR_INT_EN_CLR BIT(1)
263 #define WHLPCR_INT_EN_SET BIT(0)
266 #define WSDIOCSR_SDIO_RE_INIT_EN BIT(0)
269 #define WCSR_SPI_MODE_SEL BITS(3,4)
270 #define WCSR_SPI_ENDIAN_BIG BIT(2)
271 #define WCSR_SPI_INT_OUT_MODE BIT(1)
272 #define WCSR_SPI_DATA_OUT_MODE BIT(0)
275 #define WHCR_RX_ENHANCE_MODE_EN BIT(16)
276 #define WHCR_MAX_HIF_RX_LEN_NUM BITS(4,7)
277 #define WHCR_W_MAILBOX_RD_CLR_EN BIT(2)
278 #define WHCR_W_INT_CLR_CTRL BIT(1)
279 #define WHCR_MCU_DBG_EN BIT(0)
280 #define WHCR_OFFSET_MAX_HIF_RX_LEN_NUM 4
283 #define WHISR_D2H_SW_INT BITS(8,31)
284 #define WHISR_D2H_SW_ASSERT_INFO_INT BIT(31)
285 #define WHISR_FW_INT_INDICATOR BIT(7)
286 #define WHISR_FW_OWN_BACK_INT BIT(4)
287 #define WHISR_ABNORMAL_INT BIT(3)
288 #define WHISR_RX1_DONE_INT BIT(2)
289 #define WHISR_RX0_DONE_INT BIT(1)
290 #define WHISR_TX_DONE_INT BIT(0)
294 #define WHIER_D2H_SW_INT BITS(8,31)
295 #define WHIER_FW_INT_INDICATOR_EN BIT(7)
296 #define WHIER_FW_OWN_BACK_INT_EN BIT(4)
297 #define WHIER_ABNORMAL_INT_EN BIT(3)
298 #define WHIER_RX1_DONE_INT_EN BIT(2)
299 #define WHIER_RX0_DONE_INT_EN BIT(1)
300 #define WHIER_TX_DONE_INT_EN BIT(0)
301 #define WHIER_DEFAULT (WHIER_RX0_DONE_INT_EN | \
302 WHIER_RX1_DONE_INT_EN | \
303 WHIER_TX_DONE_INT_EN | \
304 WHIER_ABNORMAL_INT_EN | \
310 #define WASR_FW_OWN_INVALID_ACCESS BIT(4)
311 #define WASR_RX1_UNDER_FLOW BIT(3)
312 #define WASR_RX0_UNDER_FLOW BIT(2)
313 #define WASR_TX1_OVER_FLOW BIT(1)
314 #define WASR_TX0_OVER_FLOW BIT(0)
318 #define WSICR_H2D_SW_INT_SET BITS(16,31)
322 #define WRPLR_RX1_PACKET_LENGTH BITS(16,31)
323 #define WRPLR_RX0_PACKET_LENGTH BITS(0,15)
325 #endif /* _MT6620_REG_H */