drivers/net/wireless/rockchip_wlan/mt5931_kk/drv_wlan/include/nic/hal.h

   1 /*
   2 ** $Id: //Department/DaVinci/BRANCHES/MT662X_593X_WIFI_DRIVER_V2_3/include/nic/hal.h#1 $
   3 */
   4
   5 /*! \file   "hal.h"
   6     \brief  The declaration of hal functions
   7
   8     N/A
   9 */
  10
  11 /*******************************************************************************
  12 * Copyright (c) 2007 MediaTek Inc.
  13 *
  14 * All rights reserved. Copying, compilation, modification, distribution
  15 * or any other use whatsoever of this material is strictly prohibited
  16 * except in accordance with a Software License Agreement with
  17 * MediaTek Inc.
  18 ********************************************************************************
  19 */
  20
  21 /*******************************************************************************
  22 * LEGAL DISCLAIMER
  23 *
  24 * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND
  25 * AGREES THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK
  26 * SOFTWARE") RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE
  27 * PROVIDED TO BUYER ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY
  28 * DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT
  29 * LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
  30 * PARTICULAR PURPOSE OR NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE
  31 * ANY WARRANTY WHATSOEVER WITH RESPECT TO THE SOFTWARE OF ANY THIRD PARTY
  32 * WHICH MAY BE USED BY, INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK
  33 * SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY
  34 * WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE
  35 * FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S SPECIFICATION OR TO
  36 * CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
  37 *
  38 * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
  39 * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL
  40 * BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT
  41 * ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY
  42 * BUYER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
  43 *
  44 * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
  45 * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT
  46 * OF LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING
  47 * THEREOF AND RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN
  48 * FRANCISCO, CA, UNDER THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE
  49 * (ICC).
  50 ********************************************************************************
  51 */
  52
  53 /*
  54 ** $Log: hal.h $
  55  *
  56  * 04 01 2011 tsaiyuan.hsu
  57  * [WCXRP00000615] [MT 6620 Wi-Fi][Driver] Fix klocwork issues
  58  * fix the klocwork issues, 57500, 57501, 57502 and 57503.
  59  *
  60  * 03 21 2011 cp.wu
  61  * [WCXRP00000540] [MT5931][Driver] Add eHPI8/eHPI16 support to Linux Glue Layer
  62  * portability improvement
  63  *
  64  * 03 07 2011 terry.wu
  65  * [WCXRP00000521] [MT6620 Wi-Fi][Driver] Remove non-standard debug message
  66  * Toggle non-standard debug messages to comments.
  67  *
  68  * 11 08 2010 cp.wu
  69  * [WCXRP00000166] [MT6620 Wi-Fi][Driver] use SDIO CMD52 for enabling/disabling interrupt to reduce transaction period
  70  * change to use CMD52 for enabling/disabling interrupt to reduce SDIO transaction time
  71  *
  72  * 09 01 2010 cp.wu
  73  * NULL
  74  * move HIF CR initialization from where after sdioSetupCardFeature() to wlanAdapterStart()
  75  *
  76  * 07 08 2010 cp.wu
  77  *
  78  * [WPD00003833] [MT6620 and MT5931] Driver migration - move to new repository.
  79  *
  80  * 06 15 2010 cp.wu
  81  * [WPD00003833][MT6620 and MT5931] Driver migration
  82  * change zero-padding for TX port access to HAL.
  83  *
  84  * 06 06 2010 kevin.huang
  85  * [WPD00003832][MT6620 5931] Create driver base
  86  * [MT6620 5931] Create driver base
  87  *
  88  * 04 06 2010 cp.wu
  89  * [WPD00001943]Create WiFi test driver framework on WinXP
  90  * eliminate direct access for prGlueInfo->fgIsCardRemoved in non-glue layer
  91  *
  92  * 01 27 2010 cp.wu
  93  * [WPD00001943]Create WiFi test driver framework on WinXP
  94  * 1. eliminate improper variable in rHifInfo
  95  *  *  *  * 2. block TX/ordinary OID when RF test mode is engaged
  96  *  *  *  * 3. wait until firmware finish operation when entering into and leaving from RF test mode
  97  *  *  *  * 4. correct some HAL implementation
  98 **  \main\maintrunk.MT6620WiFiDriver_Prj\17 2009-12-16 18:02:26 GMT mtk02752
  99 **  include precomp.h
 100 **  \main\maintrunk.MT6620WiFiDriver_Prj\16 2009-12-10 16:43:16 GMT mtk02752
 101 **  code clean
 102 **  \main\maintrunk.MT6620WiFiDriver_Prj\15 2009-11-13 13:54:15 GMT mtk01084
 103 **  \main\maintrunk.MT6620WiFiDriver_Prj\14 2009-11-11 10:36:01 GMT mtk01084
 104 **  modify HAL functions
 105 **  \main\maintrunk.MT6620WiFiDriver_Prj\13 2009-11-09 22:56:28 GMT mtk01084
 106 **  modify HW access routines
 107 **  \main\maintrunk.MT6620WiFiDriver_Prj\12 2009-10-29 19:50:09 GMT mtk01084
 108 **  add new macro HAL_TX_PORT_WR
 109 **  \main\maintrunk.MT6620WiFiDriver_Prj\11 2009-10-23 16:08:10 GMT mtk01084
 110 **  \main\maintrunk.MT6620WiFiDriver_Prj\10 2009-10-13 21:58:50 GMT mtk01084
 111 **  update for new HW architecture design
 112 **  \main\maintrunk.MT6620WiFiDriver_Prj\9 2009-05-18 14:28:10 GMT mtk01084
 113 **  fix issue in HAL_DRIVER_OWN_BY_SDIO_CMD52()
 114 **  \main\maintrunk.MT6620WiFiDriver_Prj\8 2009-05-11 17:26:33 GMT mtk01084
 115 **  modify the bit definition to check driver own status
 116 **  \main\maintrunk.MT6620WiFiDriver_Prj\7 2009-04-28 10:30:22 GMT mtk01461
 117 **  Fix typo
 118 **  \main\maintrunk.MT6620WiFiDriver_Prj\6 2009-04-01 10:50:34 GMT mtk01461
 119 **  Redefine HAL_PORT_RD/WR macro for SW pre test
 120 **  \main\maintrunk.MT6620WiFiDriver_Prj\5 2009-03-24 09:46:49 GMT mtk01084
 121 **  fix LINT error
 122 **  \main\maintrunk.MT6620WiFiDriver_Prj\4 2009-03-23 16:53:38 GMT mtk01084
 123 **  add HAL_DRIVER_OWN_BY_SDIO_CMD52()
 124 **  \main\maintrunk.MT6620WiFiDriver_Prj\3 2009-03-18 20:53:13 GMT mtk01426
 125 **  Fixed lint warn
 126 **  \main\maintrunk.MT6620WiFiDriver_Prj\2 2009-03-10 20:16:20 GMT mtk01426
 127 **  Init for develop
 128 **
 129 */
 130
 131 #ifndef _HAL_H
 132 #define _HAL_H
 133
 134 /*******************************************************************************
 135 *                         C O M P I L E R   F L A G S
 136 ********************************************************************************
 137 */
 138
 139 /*******************************************************************************
 140 *                    E X T E R N A L   R E F E R E N C E S
 141 ********************************************************************************
 142 */
 143
 144 /*******************************************************************************
 145 *                              C O N S T A N T S
 146 ********************************************************************************
 147 */
 148
 149 /*******************************************************************************
 150 *                             D A T A   T Y P E S
 151 ********************************************************************************
 152 */
 153
 154 /*******************************************************************************
 155 *                            P U B L I C   D A T A
 156 ********************************************************************************
 157 */
 158
 159 /*******************************************************************************
 160 *                           P R I V A T E   D A T A
 161 ********************************************************************************
 162 */
 163
 164 /*******************************************************************************
 165 *                                 M A C R O S
 166 ********************************************************************************
 167 */
 168
 169 /* Macros for flag operations for the Adapter structure */
 170 #define HAL_SET_FLAG(_M, _F)             ((_M)->u4HwFlags |= (_F))
 171 #define HAL_CLEAR_FLAG(_M, _F)           ((_M)->u4HwFlags &= ~(_F))
 172 #define HAL_TEST_FLAG(_M, _F)            ((_M)->u4HwFlags & (_F))
 173 #define HAL_TEST_FLAGS(_M, _F)           (((_M)->u4HwFlags & (_F)) == (_F))
 174
 175 #if defined(_HIF_SDIO)
 176 #define HAL_MCR_RD(_prAdapter, _u4Offset, _pu4Value) \
 177     { \
 178         if (HAL_TEST_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR) == FALSE) { \
 179             if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
 180                 ASSERT(0); \
 181             } \
 182             if (kalDevRegRead(_prAdapter->prGlueInfo, _u4Offset, _pu4Value) == FALSE) {\
 183                 HAL_SET_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR); \
 184                 fgIsBusAccessFailed = TRUE; \
 185                 DBGLOG(HAL, ERROR, ("HAL_MCR_RD access fail! 0x%x: 0x%x \n", _u4Offset, *_pu4Value)); \
 186             } \
 187         } else { \
 188             DBGLOG(HAL, WARN, ("ignore HAL_MCR_RD access! 0x%x\n", _u4Offset)); \
 189         } \
 190     }
 191
 192 #define HAL_MCR_WR(_prAdapter, _u4Offset, _u4Value) \
 193     { \
 194         if (HAL_TEST_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR) == FALSE) { \
 195             if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
 196                 ASSERT(0); \
 197             } \
 198             if (kalDevRegWrite(_prAdapter->prGlueInfo, _u4Offset, _u4Value) == FALSE) {\
 199                 HAL_SET_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR); \
 200                 fgIsBusAccessFailed = TRUE; \
 201                 DBGLOG(HAL, ERROR, ("HAL_MCR_WR access fail! 0x%x: 0x%x \n", _u4Offset, _u4Value)); \
 202             } \
 203         } else { \
 204             DBGLOG(HAL, WARN, ("ignore HAL_MCR_WR access! 0x%x: 0x%x \n", _u4Offset, _u4Value)); \
 205         } \
 206      }
 207
 208 #define HAL_PORT_RD(_prAdapter, _u4Port, _u4Len, _pucBuf, _u4ValidBufSize) \
 209     { \
 210         /*fgResult = FALSE; */\
 211         if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
 212             ASSERT(0); \
 213         } \
 214         if (HAL_TEST_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR) == FALSE) { \
 215             if (kalDevPortRead(_prAdapter->prGlueInfo, _u4Port, _u4Len, _pucBuf, _u4ValidBufSize) == FALSE) {\
 216                 HAL_SET_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR); \
 217                 fgIsBusAccessFailed = TRUE; \
 218                 DBGLOG(HAL, ERROR, ("HAL_PORT_RD access fail! 0x%x\n", _u4Port)); \
 219             } \
 220             else { \
 221                 /*fgResult = TRUE;*/ } \
 222         } else { \
 223             DBGLOG(HAL, WARN, ("ignore HAL_PORT_RD access! 0x%x\n", _u4Port)); \
 224         } \
 225     }
 226
 227 #define HAL_PORT_WR(_prAdapter, _u4Port, _u4Len, _pucBuf, _u4ValidBufSize) \
 228     { \
 229         /*fgResult = FALSE; */\
 230         if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
 231             ASSERT(0); \
 232         } \
 233         if (HAL_TEST_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR) == FALSE) { \
 234             if (kalDevPortWrite(_prAdapter->prGlueInfo, _u4Port, _u4Len, _pucBuf, _u4ValidBufSize) == FALSE) {\
 235                 HAL_SET_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR); \
 236                 fgIsBusAccessFailed = TRUE; \
 237                 DBGLOG(HAL, ERROR, ("HAL_PORT_WR access fail! 0x%x\n", _u4Port)); \
 238             } \
 239             else { \
 240                 /*fgResult = TRUE;*/ } \
 241         } else { \
 242             DBGLOG(HAL, WARN, ("ignore HAL_PORT_WR access! 0x%x\n", _u4Port)); \
 243         } \
 244     }
 245
 246 #define HAL_BYTE_WR(_prAdapter, _u4Port, _ucBuf) \
 247     { \
 248         if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
 249             ASSERT(0); \
 250         } \
 251         if (HAL_TEST_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR) == FALSE) { \
 252             if (kalDevWriteWithSdioCmd52(_prAdapter->prGlueInfo, _u4Port, _ucBuf) == FALSE) {\
 253                 HAL_SET_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR); \
 254                 fgIsBusAccessFailed = TRUE; \
 255                 DBGLOG(HAL, ERROR, ("HAL_BYTE_WR access fail! 0x%x\n", _u4Port)); \
 256             } \
 257             else { \
 258             } \
 259         } \
 260         else { \
 261             DBGLOG(HAL, WARN, ("ignore HAL_BYTE_WR access! 0x%x\n", _u4Port)); \
 262         } \
 263     }
 264
 265
 266 #define HAL_DRIVER_OWN_BY_SDIO_CMD52(_prAdapter, _pfgDriverIsOwnReady) \
 267     { \
 268         UINT_8 ucBuf = BIT(1); \
 269         if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
 270             ASSERT(0); \
 271         } \
 272         if (HAL_TEST_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR) == FALSE) { \
 273             if (kalDevReadAfterWriteWithSdioCmd52(_prAdapter->prGlueInfo, MCR_WHLPCR_BYTE1, &ucBuf, 1) == FALSE) {\
 274                 HAL_SET_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR); \
 275                 fgIsBusAccessFailed = TRUE; \
 276                 DBGLOG(HAL, ERROR, ("kalDevReadAfterWriteWithSdioCmd52 access fail!\n")); \
 277             } \
 278             else { \
 279                 *_pfgDriverIsOwnReady = (ucBuf & BIT(0)) ? TRUE : FALSE; \
 280             } \
 281         } else { \
 282             DBGLOG(HAL, WARN, ("ignore HAL_DRIVER_OWN_BY_SDIO_CMD52 access!\n")); \
 283         } \
 284     }
 285
 286 #else /* #if defined(_HIF_SDIO) */
 287 #define HAL_MCR_RD(_prAdapter, _u4Offset, _pu4Value) \
 288     { \
 289         if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
 290             ASSERT(0); \
 291         } \
 292         kalDevRegRead(_prAdapter->prGlueInfo, _u4Offset, _pu4Value); \
 293     }
 294
 295 #define HAL_MCR_WR(_prAdapter, _u4Offset, _u4Value) \
 296     { \
 297         if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
 298             ASSERT(0); \
 299         } \
 300         kalDevRegWrite(_prAdapter->prGlueInfo, _u4Offset, _u4Value); \
 301     }
 302
 303 #define HAL_PORT_RD(_prAdapter, _u4Port, _u4Len, _pucBuf, _u4ValidBufSize) \
 304     { \
 305         if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
 306             ASSERT(0); \
 307         } \
 308         kalDevPortRead(_prAdapter->prGlueInfo, _u4Port, _u4Len, _pucBuf, _u4ValidBufSize); \
 309     }
 310
 311 #define HAL_PORT_WR(_prAdapter, _u4Port, _u4Len, _pucBuf, _u4ValidBufSize) \
 312     { \
 313         if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
 314             ASSERT(0); \
 315         } \
 316         kalDevPortWrite(_prAdapter->prGlueInfo, _u4Port, _u4Len, _pucBuf, _u4ValidBufSize); \
 317     }
 318
 319 #define HAL_BYTE_WR(_prAdapter, _u4Port, _ucBuf) \
 320     { \
 321         if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
 322             ASSERT(0); \
 323         } \
 324         kalDevWriteWithSdioCmd52(_prAdapter->prGlueInfo, _u4Port, _ucBuf); \
 325     }
 326
 327 #endif /* #if defined(_HIF_SDIO) */
 328
 329
 330 #define HAL_READ_RX_PORT(prAdapter, u4PortId, u4Len, pvBuf, _u4ValidBufSize) \
 331     { \
 332     ASSERT(u4PortId < 2); \
 333     HAL_PORT_RD(prAdapter, \
 334         ((u4PortId == 0) ? MCR_WRDR0 : MCR_WRDR1), \
 335         u4Len, \
 336         pvBuf, \
 337         _u4ValidBufSize/*temp!!*//*4Kbyte*/) \
 338     }
 339
 340 #define HAL_WRITE_TX_PORT(_prAdapter, _ucTxPortIdx, _u4Len, _pucBuf, _u4ValidBufSize) \
 341     { \
 342     ASSERT(_ucTxPortIdx < 2); \
 343     if((_u4ValidBufSize - _u4Len) >= sizeof(UINT_32)) { \
 344         /* fill with single dword of zero as TX-aggregation termination */ \
 345         *(PUINT_32) (&((_pucBuf)[ALIGN_4(_u4Len)])) = 0; \
 346     } \
 347     HAL_PORT_WR(_prAdapter, \
 348                 (_ucTxPortIdx == 0) ? MCR_WTDR0 : MCR_WTDR1, \
 349                 _u4Len, \
 350                 _pucBuf, \
 351                 _u4ValidBufSize/*temp!!*//*4KByte*/) \
 352     }
 353
 354 /* The macro to read the given MCR several times to check if the wait
 355    condition come true. */
 356 #define HAL_MCR_RD_AND_WAIT(_pAdapter, _offset, _pReadValue, _waitCondition, _waitDelay, _waitCount, _status) \
 357         { \
 358             UINT_32 count; \
 359             (_status) = FALSE; \
 360             for (count = 0; count < (_waitCount); count++) { \
 361                 HAL_MCR_RD((_pAdapter), (_offset), (_pReadValue)); \
 362                 if ((_waitCondition)) { \
 363                     (_status) = TRUE; \
 364                     break; \
 365                 } \
 366                 kalUdelay((_waitDelay)); \
 367             } \
 368         }
 369
 370
 371 /* The macro to write 1 to a R/S bit and read it several times to check if the
 372    command is done */
 373 #define HAL_MCR_WR_AND_WAIT(_pAdapter, _offset, _writeValue, _busyMask, _waitDelay, _waitCount, _status) \
 374         { \
 375             UINT_32 u4Temp; \
 376             UINT_32 u4Count = _waitCount; \
 377             (_status) = FALSE; \
 378             HAL_MCR_WR((_pAdapter), (_offset), (_writeValue)); \
 379             do { \
 380                 kalUdelay((_waitDelay)); \
 381                 HAL_MCR_RD((_pAdapter), (_offset), &u4Temp); \
 382                 if (!(u4Temp & (_busyMask))) { \
 383                     (_status) = TRUE; \
 384                     break; \
 385                 } \
 386                 u4Count--; \
 387             } while (u4Count); \
 388         }
 389
 390 #define HAL_GET_CHIP_ID_VER(_prAdapter, pu2ChipId, pu2Version) \
 391     { \
 392     UINT_32 u4Value; \
 393     HAL_MCR_RD(_prAdapter, \
 394         MCR_WCIR, \
 395         &u4Value); \
 396     *pu2ChipId = (UINT_16)(u4Value & WCIR_CHIP_ID); \
 397     *pu2Version = (UINT_16)(u4Value & WCIR_REVISION_ID) >> 16; \
 398     }
 399
 400 #define HAL_WAIT_WIFI_FUNC_READY(_prAdapter) \
 401     { \
 402     UINT_32 u4Value; \
 403     UINT_32 i; \
 404     for (i = 0; i < 100; i++) { \
 405         HAL_MCR_RD(_prAdapter, \
 406             MCR_WCIR, \
 407             &u4Value); \
 408          if (u4Value & WCIR_WLAN_READY) { \
 409             break; \
 410          } \
 411         NdisMSleep(10); \
 412     } \
 413     }
 414
 415 #define HAL_INTR_DISABLE(_prAdapter) \
 416     HAL_MCR_WR(_prAdapter, \
 417         MCR_WHLPCR, \
 418         WHLPCR_INT_EN_CLR)
 419
 420 #define HAL_INTR_ENABLE(_prAdapter) \
 421     HAL_MCR_WR(_prAdapter, \
 422         MCR_WHLPCR, \
 423         WHLPCR_INT_EN_SET)
 424
 425 #define HAL_INTR_ENABLE_AND_LP_OWN_SET(_prAdapter) \
 426     HAL_MCR_WR(_prAdapter, \
 427         MCR_WHLPCR, \
 428         (WHLPCR_INT_EN_SET | WHLPCR_FW_OWN_REQ_SET))
 429
 430 #define HAL_LP_OWN_SET(_prAdapter) \
 431     HAL_MCR_WR(_prAdapter, \
 432         MCR_WHLPCR, \
 433         WHLPCR_FW_OWN_REQ_SET)
 434
 435 #define HAL_LP_OWN_CLR_OK(_prAdapter, _pfgResult) \
 436     { \
 437         UINT_32 i; \
 438         UINT_32 u4RegValue; \
 439         UINT_32 u4LoopCnt = 2048 / 8; \
 440         *_pfgResult = TRUE; \
 441         /* Software get LP ownership */ \
 442         HAL_MCR_WR(_prAdapter, \
 443             MCR_WHLPCR, \
 444             WHLPCR_FW_OWN_REQ_CLR) \
 445         for (i = 0; i < u4LoopCnt; i++) { \
 446             HAL_MCR_RD(_prAdapter, MCR_WHLPCR, &u4RegValue); \
 447             if (u4RegValue & WHLPCR_IS_DRIVER_OWN) { \
 448                 break; \
 449             } \
 450             else { \
 451                 kalUdelay(8); \
 452             } \
 453         } \
 454         if (i == u4LoopCnt) { \
 455             *_pfgResult = FALSE; \
 456             /*ERRORLOG(("LP cannot be own back (%ld)", u4LoopCnt));*/ \
 457             /* check the time of LP instructions need to perform from Sleep to On */ \
 458             /*ASSERT(0); */ \
 459         } \
 460     }
 461
 462 #define HAL_GET_ABNORMAL_INTERRUPT_REASON_CODE(_prAdapter, pu4AbnormalReason) \
 463     { \
 464     HAL_MCR_RD(_prAdapter, \
 465         MCR_WASR, \
 466         pu4AbnormalReason); \
 467     }
 468
 469
 470 #define HAL_DISABLE_RX_ENHANCE_MODE(_prAdapter) \
 471     { \
 472     UINT_32 u4Value; \
 473     HAL_MCR_RD(_prAdapter, \
 474         MCR_WHCR, \
 475         &u4Value); \
 476     HAL_MCR_WR(_prAdapter, \
 477         MCR_WHCR, \
 478         u4Value & ~WHCR_RX_ENHANCE_MODE_EN); \
 479     }
 480
 481 #define HAL_ENABLE_RX_ENHANCE_MODE(_prAdapter) \
 482     { \
 483     UINT_32 u4Value; \
 484     HAL_MCR_RD(_prAdapter, \
 485         MCR_WHCR, \
 486         &u4Value); \
 487     HAL_MCR_WR(_prAdapter, \
 488         MCR_WHCR, \
 489         u4Value | WHCR_RX_ENHANCE_MODE_EN); \
 490     }
 491
 492 #define HAL_CFG_MAX_HIF_RX_LEN_NUM(_prAdapter, _ucNumOfRxLen) \
 493     { \
 494     UINT_32 u4Value, ucNum; \
 495     ucNum = ((_ucNumOfRxLen >= 16) ? 0 : _ucNumOfRxLen); \
 496     u4Value = 0; \
 497     HAL_MCR_RD(_prAdapter, \
 498         MCR_WHCR, \
 499         &u4Value); \
 500     u4Value &= ~WHCR_MAX_HIF_RX_LEN_NUM; \
 501     u4Value |= ((((UINT_32)ucNum) << 4) & WHCR_MAX_HIF_RX_LEN_NUM); \
 502     HAL_MCR_WR(_prAdapter, \
 503         MCR_WHCR, \
 504         u4Value); \
 505     }
 506
 507 #define HAL_SET_INTR_STATUS_READ_CLEAR(prAdapter) \
 508     { \
 509     UINT_32 u4Value; \
 510     HAL_MCR_RD(prAdapter, \
 511         MCR_WHCR, \
 512         &u4Value); \
 513     HAL_MCR_WR(prAdapter, \
 514         MCR_WHCR, \
 515         u4Value & ~WHCR_W_INT_CLR_CTRL); \
 516     prAdapter->prGlueInfo->rHifInfo.fgIntReadClear = TRUE;\
 517     }
 518
 519 #define HAL_SET_INTR_STATUS_WRITE_1_CLEAR(prAdapter) \
 520     { \
 521     UINT_32 u4Value; \
 522     HAL_MCR_RD(prAdapter, \
 523         MCR_WHCR, \
 524         &u4Value); \
 525     HAL_MCR_WR(prAdapter, \
 526         MCR_WHCR, \
 527         u4Value | WHCR_W_INT_CLR_CTRL); \
 528     prAdapter->prGlueInfo->rHifInfo.fgIntReadClear = FALSE;\
 529     }
 530
 531 /* Note: enhance mode structure may also carried inside the buffer,
 532          if the length of the buffer is long enough */
 533 #define HAL_READ_INTR_STATUS(prAdapter, length, pvBuf) \
 534     HAL_PORT_RD(prAdapter, \
 535         MCR_WHISR, \
 536         length, \
 537         pvBuf, \
 538         length)
 539
 540 #define HAL_READ_TX_RELEASED_COUNT(_prAdapter, aucTxReleaseCount) \
 541     { \
 542     PUINT_32 pu4Value = (PUINT_32)aucTxReleaseCount; \
 543     HAL_MCR_RD(_prAdapter, \
 544         MCR_WTSR0, \
 545         &pu4Value[0]); \
 546     HAL_MCR_RD(_prAdapter, \
 547         MCR_WTSR1, \
 548         &pu4Value[1]); \
 549     }
 550
 551 #define HAL_READ_RX_LENGTH(prAdapter, pu2Rx0Len, pu2Rx1Len) \
 552     { \
 553     UINT_32 u4Value; \
 554     u4Value = 0; \
 555     HAL_MCR_RD(prAdapter, \
 556         MCR_WRPLR, \
 557         &u4Value); \
 558     *pu2Rx0Len = (UINT_16)u4Value; \
 559     *pu2Rx1Len = (UINT_16)(u4Value >> 16); \
 560     }
 561
 562 #define HAL_GET_INTR_STATUS_FROM_ENHANCE_MODE_STRUCT(pvBuf, u2Len, pu4Status) \
 563     { \
 564     PUINT_32 pu4Buf = (PUINT_32)pvBuf; \
 565     *pu4Status = pu4Buf[0]; \
 566     }
 567
 568 #define HAL_GET_TX_STATUS_FROM_ENHANCE_MODE_STRUCT(pvInBuf, pu4BufOut, u4LenBufOut) \
 569     { \
 570     PUINT_32 pu4Buf = (PUINT_32)pvInBuf; \
 571     ASSERT(u4LenBufOut >= 8); \
 572     pu4BufOut[0] = pu4Buf[1]; \
 573     pu4BufOut[1] = pu4Buf[2]; \
 574     }
 575
 576 #define HAL_GET_RX_LENGTH_FROM_ENHANCE_MODE_STRUCT(pvInBuf, pu2Rx0Num, au2Rx0Len, pu2Rx1Num, au2Rx1Len) \
 577     { \
 578     PUINT_32 pu4Buf = (PUINT_32)pvInBuf; \
 579     ASSERT((sizeof(au2Rx0Len) / sizeof(UINT_16)) >= 16); \
 580     ASSERT((sizeof(au2Rx1Len) / sizeof(UINT_16)) >= 16); \
 581     *pu2Rx0Num = (UINT_16)pu4Buf[3]; \
 582     *pu2Rx1Num = (UINT_16)(pu4Buf[3] >> 16); \
 583     kalMemCopy(au2Rx0Len, &pu4Buf[4], 8); \
 584     kalMemCopy(au2Rx1Len, &pu4Buf[12], 8); \
 585     }
 586
 587 #define HAL_GET_MAILBOX_FROM_ENHANCE_MODE_STRUCT(pvInBuf, pu4Mailbox0, pu4Mailbox1) \
 588     { \
 589     PUINT_32 pu4Buf = (PUINT_32)pvInBuf; \
 590     *pu4Mailbox0 = (UINT_16)pu4Buf[21]; \
 591     *pu4Mailbox1 = (UINT_16)pu4Buf[22]; \
 592     }
 593
 594 #define HAL_IS_TX_DONE_INTR(u4IntrStatus) \
 595    ((u4IntrStatus & WHISR_TX_DONE_INT) ? TRUE : FALSE)
 596
 597 #define HAL_IS_RX_DONE_INTR(u4IntrStatus) \
 598     ((u4IntrStatus & (WHISR_RX0_DONE_INT | WHISR_RX1_DONE_INT)) ? TRUE : FALSE)
 599
 600 #define HAL_IS_ABNORMAL_INTR(u4IntrStatus) \
 601     ((u4IntrStatus & WHISR_ABNORMAL_INT) ? TRUE : FALSE)
 602
 603 #define HAL_IS_FW_OWNBACK_INTR(u4IntrStatus) \
 604     ((u4IntrStatus & WHISR_FW_OWN_BACK_INT) ? TRUE : FALSE)
 605
 606 #define HAL_PUT_MAILBOX(prAdapter, u4MboxId, u4Data) \
 607     { \
 608     ASSERT(u4MboxId < 2); \
 609     HAL_MCR_WR(prAdapter, \
 610         ((u4MboxId == 0) ? MCR_H2DSM0R : MCR_H2DSM1R), \
 611         u4Data); \
 612     }
 613
 614 #define HAL_GET_MAILBOX(prAdapter, u4MboxId, pu4Data) \
 615     { \
 616     ASSERT(u4MboxId < 2); \
 617     HAL_MCR_RD(prAdapter, \
 618         ((u4MboxId == 0) ? MCR_D2HRM0R : MCR_D2HRM1R), \
 619         pu4Data); \
 620     }
 621
 622 #define HAL_SET_MAILBOX_READ_CLEAR(prAdapter, fgEnableReadClear) \
 623     { \
 624         UINT_32 u4Value; \
 625         HAL_MCR_RD(prAdapter, MCR_WHCR, &u4Value);\
 626         HAL_MCR_WR(prAdapter, MCR_WHCR, \
 627                     (fgEnableReadClear) ? \
 628                         (u4Value | WHCR_W_MAILBOX_RD_CLR_EN) : \
 629                         (u4Value & ~WHCR_W_MAILBOX_RD_CLR_EN)); \
 630         prAdapter->prGlueInfo->rHifInfo.fgMbxReadClear = fgEnableReadClear;\
 631     }
 632
 633 #define HAL_GET_MAILBOX_READ_CLEAR(prAdapter) (prAdapter->prGlueInfo->rHifInfo.fgMbxReadClear)
 634
 635
 636 /*******************************************************************************
 637 *                   F U N C T I O N   D E C L A R A T I O N S
 638 ********************************************************************************
 639 */
 640
 641
 642
 643 /*******************************************************************************
 644 *                              F U N C T I O N S
 645 ********************************************************************************
 646 */
 647
 648 #endif /* _HAL_H */
 649