2 ** $Id: //Department/DaVinci/BRANCHES/MT662X_593X_WIFI_DRIVER_V2_3/include/nic/hal.h#1 $
6 \brief The declaration of hal functions
11 /*******************************************************************************
12 * Copyright (c) 2007 MediaTek Inc.
14 * All rights reserved. Copying, compilation, modification, distribution
15 * or any other use whatsoever of this material is strictly prohibited
16 * except in accordance with a Software License Agreement with
18 ********************************************************************************
21 /*******************************************************************************
24 * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND
25 * AGREES THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK
26 * SOFTWARE") RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE
27 * PROVIDED TO BUYER ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY
28 * DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT
29 * LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
30 * PARTICULAR PURPOSE OR NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE
31 * ANY WARRANTY WHATSOEVER WITH RESPECT TO THE SOFTWARE OF ANY THIRD PARTY
32 * WHICH MAY BE USED BY, INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK
33 * SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY
34 * WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE
35 * FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S SPECIFICATION OR TO
36 * CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
38 * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
39 * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL
40 * BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT
41 * ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY
42 * BUYER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
44 * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
45 * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT
46 * OF LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING
47 * THEREOF AND RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN
48 * FRANCISCO, CA, UNDER THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE
50 ********************************************************************************
56 * 04 01 2011 tsaiyuan.hsu
57 * [WCXRP00000615] [MT 6620 Wi-Fi][Driver] Fix klocwork issues
58 * fix the klocwork issues, 57500, 57501, 57502 and 57503.
61 * [WCXRP00000540] [MT5931][Driver] Add eHPI8/eHPI16 support to Linux Glue Layer
62 * portability improvement
65 * [WCXRP00000521] [MT6620 Wi-Fi][Driver] Remove non-standard debug message
66 * Toggle non-standard debug messages to comments.
69 * [WCXRP00000166] [MT6620 Wi-Fi][Driver] use SDIO CMD52 for enabling/disabling interrupt to reduce transaction period
70 * change to use CMD52 for enabling/disabling interrupt to reduce SDIO transaction time
74 * move HIF CR initialization from where after sdioSetupCardFeature() to wlanAdapterStart()
78 * [WPD00003833] [MT6620 and MT5931] Driver migration - move to new repository.
81 * [WPD00003833][MT6620 and MT5931] Driver migration
82 * change zero-padding for TX port access to HAL.
84 * 06 06 2010 kevin.huang
85 * [WPD00003832][MT6620 5931] Create driver base
86 * [MT6620 5931] Create driver base
89 * [WPD00001943]Create WiFi test driver framework on WinXP
90 * eliminate direct access for prGlueInfo->fgIsCardRemoved in non-glue layer
93 * [WPD00001943]Create WiFi test driver framework on WinXP
94 * 1. eliminate improper variable in rHifInfo
95 * * * * 2. block TX/ordinary OID when RF test mode is engaged
96 * * * * 3. wait until firmware finish operation when entering into and leaving from RF test mode
97 * * * * 4. correct some HAL implementation
98 ** \main\maintrunk.MT6620WiFiDriver_Prj\17 2009-12-16 18:02:26 GMT mtk02752
100 ** \main\maintrunk.MT6620WiFiDriver_Prj\16 2009-12-10 16:43:16 GMT mtk02752
102 ** \main\maintrunk.MT6620WiFiDriver_Prj\15 2009-11-13 13:54:15 GMT mtk01084
103 ** \main\maintrunk.MT6620WiFiDriver_Prj\14 2009-11-11 10:36:01 GMT mtk01084
104 ** modify HAL functions
105 ** \main\maintrunk.MT6620WiFiDriver_Prj\13 2009-11-09 22:56:28 GMT mtk01084
106 ** modify HW access routines
107 ** \main\maintrunk.MT6620WiFiDriver_Prj\12 2009-10-29 19:50:09 GMT mtk01084
108 ** add new macro HAL_TX_PORT_WR
109 ** \main\maintrunk.MT6620WiFiDriver_Prj\11 2009-10-23 16:08:10 GMT mtk01084
110 ** \main\maintrunk.MT6620WiFiDriver_Prj\10 2009-10-13 21:58:50 GMT mtk01084
111 ** update for new HW architecture design
112 ** \main\maintrunk.MT6620WiFiDriver_Prj\9 2009-05-18 14:28:10 GMT mtk01084
113 ** fix issue in HAL_DRIVER_OWN_BY_SDIO_CMD52()
114 ** \main\maintrunk.MT6620WiFiDriver_Prj\8 2009-05-11 17:26:33 GMT mtk01084
115 ** modify the bit definition to check driver own status
116 ** \main\maintrunk.MT6620WiFiDriver_Prj\7 2009-04-28 10:30:22 GMT mtk01461
118 ** \main\maintrunk.MT6620WiFiDriver_Prj\6 2009-04-01 10:50:34 GMT mtk01461
119 ** Redefine HAL_PORT_RD/WR macro for SW pre test
120 ** \main\maintrunk.MT6620WiFiDriver_Prj\5 2009-03-24 09:46:49 GMT mtk01084
122 ** \main\maintrunk.MT6620WiFiDriver_Prj\4 2009-03-23 16:53:38 GMT mtk01084
123 ** add HAL_DRIVER_OWN_BY_SDIO_CMD52()
124 ** \main\maintrunk.MT6620WiFiDriver_Prj\3 2009-03-18 20:53:13 GMT mtk01426
126 ** \main\maintrunk.MT6620WiFiDriver_Prj\2 2009-03-10 20:16:20 GMT mtk01426
134 /*******************************************************************************
135 * C O M P I L E R F L A G S
136 ********************************************************************************
139 /*******************************************************************************
140 * E X T E R N A L R E F E R E N C E S
141 ********************************************************************************
144 /*******************************************************************************
146 ********************************************************************************
149 /*******************************************************************************
151 ********************************************************************************
154 /*******************************************************************************
155 * P U B L I C D A T A
156 ********************************************************************************
159 /*******************************************************************************
160 * P R I V A T E D A T A
161 ********************************************************************************
164 /*******************************************************************************
166 ********************************************************************************
169 /* Macros for flag operations for the Adapter structure */
170 #define HAL_SET_FLAG(_M, _F) ((_M)->u4HwFlags |= (_F))
171 #define HAL_CLEAR_FLAG(_M, _F) ((_M)->u4HwFlags &= ~(_F))
172 #define HAL_TEST_FLAG(_M, _F) ((_M)->u4HwFlags & (_F))
173 #define HAL_TEST_FLAGS(_M, _F) (((_M)->u4HwFlags & (_F)) == (_F))
175 #if defined(_HIF_SDIO)
176 #define HAL_MCR_RD(_prAdapter, _u4Offset, _pu4Value) \
178 if (HAL_TEST_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR) == FALSE) { \
179 if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
182 if (kalDevRegRead(_prAdapter->prGlueInfo, _u4Offset, _pu4Value) == FALSE) {\
183 HAL_SET_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR); \
184 fgIsBusAccessFailed = TRUE; \
185 DBGLOG(HAL, ERROR, ("HAL_MCR_RD access fail! 0x%x: 0x%x \n", _u4Offset, *_pu4Value)); \
188 DBGLOG(HAL, WARN, ("ignore HAL_MCR_RD access! 0x%x\n", _u4Offset)); \
192 #define HAL_MCR_WR(_prAdapter, _u4Offset, _u4Value) \
194 if (HAL_TEST_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR) == FALSE) { \
195 if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
198 if (kalDevRegWrite(_prAdapter->prGlueInfo, _u4Offset, _u4Value) == FALSE) {\
199 HAL_SET_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR); \
200 fgIsBusAccessFailed = TRUE; \
201 DBGLOG(HAL, ERROR, ("HAL_MCR_WR access fail! 0x%x: 0x%x \n", _u4Offset, _u4Value)); \
204 DBGLOG(HAL, WARN, ("ignore HAL_MCR_WR access! 0x%x: 0x%x \n", _u4Offset, _u4Value)); \
208 #define HAL_PORT_RD(_prAdapter, _u4Port, _u4Len, _pucBuf, _u4ValidBufSize) \
210 /*fgResult = FALSE; */\
211 if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
214 if (HAL_TEST_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR) == FALSE) { \
215 if (kalDevPortRead(_prAdapter->prGlueInfo, _u4Port, _u4Len, _pucBuf, _u4ValidBufSize) == FALSE) {\
216 HAL_SET_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR); \
217 fgIsBusAccessFailed = TRUE; \
218 DBGLOG(HAL, ERROR, ("HAL_PORT_RD access fail! 0x%x\n", _u4Port)); \
221 /*fgResult = TRUE;*/ } \
223 DBGLOG(HAL, WARN, ("ignore HAL_PORT_RD access! 0x%x\n", _u4Port)); \
227 #define HAL_PORT_WR(_prAdapter, _u4Port, _u4Len, _pucBuf, _u4ValidBufSize) \
229 /*fgResult = FALSE; */\
230 if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
233 if (HAL_TEST_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR) == FALSE) { \
234 if (kalDevPortWrite(_prAdapter->prGlueInfo, _u4Port, _u4Len, _pucBuf, _u4ValidBufSize) == FALSE) {\
235 HAL_SET_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR); \
236 fgIsBusAccessFailed = TRUE; \
237 DBGLOG(HAL, ERROR, ("HAL_PORT_WR access fail! 0x%x\n", _u4Port)); \
240 /*fgResult = TRUE;*/ } \
242 DBGLOG(HAL, WARN, ("ignore HAL_PORT_WR access! 0x%x\n", _u4Port)); \
246 #define HAL_BYTE_WR(_prAdapter, _u4Port, _ucBuf) \
248 if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
251 if (HAL_TEST_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR) == FALSE) { \
252 if (kalDevWriteWithSdioCmd52(_prAdapter->prGlueInfo, _u4Port, _ucBuf) == FALSE) {\
253 HAL_SET_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR); \
254 fgIsBusAccessFailed = TRUE; \
255 DBGLOG(HAL, ERROR, ("HAL_BYTE_WR access fail! 0x%x\n", _u4Port)); \
261 DBGLOG(HAL, WARN, ("ignore HAL_BYTE_WR access! 0x%x\n", _u4Port)); \
266 #define HAL_DRIVER_OWN_BY_SDIO_CMD52(_prAdapter, _pfgDriverIsOwnReady) \
268 UINT_8 ucBuf = BIT(1); \
269 if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
272 if (HAL_TEST_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR) == FALSE) { \
273 if (kalDevReadAfterWriteWithSdioCmd52(_prAdapter->prGlueInfo, MCR_WHLPCR_BYTE1, &ucBuf, 1) == FALSE) {\
274 HAL_SET_FLAG(_prAdapter, ADAPTER_FLAG_HW_ERR); \
275 fgIsBusAccessFailed = TRUE; \
276 DBGLOG(HAL, ERROR, ("kalDevReadAfterWriteWithSdioCmd52 access fail!\n")); \
279 *_pfgDriverIsOwnReady = (ucBuf & BIT(0)) ? TRUE : FALSE; \
282 DBGLOG(HAL, WARN, ("ignore HAL_DRIVER_OWN_BY_SDIO_CMD52 access!\n")); \
286 #else /* #if defined(_HIF_SDIO) */
287 #define HAL_MCR_RD(_prAdapter, _u4Offset, _pu4Value) \
289 if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
292 kalDevRegRead(_prAdapter->prGlueInfo, _u4Offset, _pu4Value); \
295 #define HAL_MCR_WR(_prAdapter, _u4Offset, _u4Value) \
297 if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
300 kalDevRegWrite(_prAdapter->prGlueInfo, _u4Offset, _u4Value); \
303 #define HAL_PORT_RD(_prAdapter, _u4Port, _u4Len, _pucBuf, _u4ValidBufSize) \
305 if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
308 kalDevPortRead(_prAdapter->prGlueInfo, _u4Port, _u4Len, _pucBuf, _u4ValidBufSize); \
311 #define HAL_PORT_WR(_prAdapter, _u4Port, _u4Len, _pucBuf, _u4ValidBufSize) \
313 if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
316 kalDevPortWrite(_prAdapter->prGlueInfo, _u4Port, _u4Len, _pucBuf, _u4ValidBufSize); \
319 #define HAL_BYTE_WR(_prAdapter, _u4Port, _ucBuf) \
321 if (_prAdapter->rAcpiState == ACPI_STATE_D3) { \
324 kalDevWriteWithSdioCmd52(_prAdapter->prGlueInfo, _u4Port, _ucBuf); \
327 #endif /* #if defined(_HIF_SDIO) */
330 #define HAL_READ_RX_PORT(prAdapter, u4PortId, u4Len, pvBuf, _u4ValidBufSize) \
332 ASSERT(u4PortId < 2); \
333 HAL_PORT_RD(prAdapter, \
334 ((u4PortId == 0) ? MCR_WRDR0 : MCR_WRDR1), \
337 _u4ValidBufSize/*temp!!*//*4Kbyte*/) \
340 #define HAL_WRITE_TX_PORT(_prAdapter, _ucTxPortIdx, _u4Len, _pucBuf, _u4ValidBufSize) \
342 ASSERT(_ucTxPortIdx < 2); \
343 if((_u4ValidBufSize - _u4Len) >= sizeof(UINT_32)) { \
344 /* fill with single dword of zero as TX-aggregation termination */ \
345 *(PUINT_32) (&((_pucBuf)[ALIGN_4(_u4Len)])) = 0; \
347 HAL_PORT_WR(_prAdapter, \
348 (_ucTxPortIdx == 0) ? MCR_WTDR0 : MCR_WTDR1, \
351 _u4ValidBufSize/*temp!!*//*4KByte*/) \
354 /* The macro to read the given MCR several times to check if the wait
355 condition come true. */
356 #define HAL_MCR_RD_AND_WAIT(_pAdapter, _offset, _pReadValue, _waitCondition, _waitDelay, _waitCount, _status) \
360 for (count = 0; count < (_waitCount); count++) { \
361 HAL_MCR_RD((_pAdapter), (_offset), (_pReadValue)); \
362 if ((_waitCondition)) { \
366 kalUdelay((_waitDelay)); \
371 /* The macro to write 1 to a R/S bit and read it several times to check if the
373 #define HAL_MCR_WR_AND_WAIT(_pAdapter, _offset, _writeValue, _busyMask, _waitDelay, _waitCount, _status) \
376 UINT_32 u4Count = _waitCount; \
378 HAL_MCR_WR((_pAdapter), (_offset), (_writeValue)); \
380 kalUdelay((_waitDelay)); \
381 HAL_MCR_RD((_pAdapter), (_offset), &u4Temp); \
382 if (!(u4Temp & (_busyMask))) { \
390 #define HAL_GET_CHIP_ID_VER(_prAdapter, pu2ChipId, pu2Version) \
393 HAL_MCR_RD(_prAdapter, \
396 *pu2ChipId = (UINT_16)(u4Value & WCIR_CHIP_ID); \
397 *pu2Version = (UINT_16)(u4Value & WCIR_REVISION_ID) >> 16; \
400 #define HAL_WAIT_WIFI_FUNC_READY(_prAdapter) \
404 for (i = 0; i < 100; i++) { \
405 HAL_MCR_RD(_prAdapter, \
408 if (u4Value & WCIR_WLAN_READY) { \
415 #define HAL_INTR_DISABLE(_prAdapter) \
416 HAL_MCR_WR(_prAdapter, \
420 #define HAL_INTR_ENABLE(_prAdapter) \
421 HAL_MCR_WR(_prAdapter, \
425 #define HAL_INTR_ENABLE_AND_LP_OWN_SET(_prAdapter) \
426 HAL_MCR_WR(_prAdapter, \
428 (WHLPCR_INT_EN_SET | WHLPCR_FW_OWN_REQ_SET))
430 #define HAL_LP_OWN_SET(_prAdapter) \
431 HAL_MCR_WR(_prAdapter, \
433 WHLPCR_FW_OWN_REQ_SET)
435 #define HAL_LP_OWN_CLR_OK(_prAdapter, _pfgResult) \
438 UINT_32 u4RegValue; \
439 UINT_32 u4LoopCnt = 2048 / 8; \
440 *_pfgResult = TRUE; \
441 /* Software get LP ownership */ \
442 HAL_MCR_WR(_prAdapter, \
444 WHLPCR_FW_OWN_REQ_CLR) \
445 for (i = 0; i < u4LoopCnt; i++) { \
446 HAL_MCR_RD(_prAdapter, MCR_WHLPCR, &u4RegValue); \
447 if (u4RegValue & WHLPCR_IS_DRIVER_OWN) { \
454 if (i == u4LoopCnt) { \
455 *_pfgResult = FALSE; \
456 /*ERRORLOG(("LP cannot be own back (%ld)", u4LoopCnt));*/ \
457 /* check the time of LP instructions need to perform from Sleep to On */ \
462 #define HAL_GET_ABNORMAL_INTERRUPT_REASON_CODE(_prAdapter, pu4AbnormalReason) \
464 HAL_MCR_RD(_prAdapter, \
466 pu4AbnormalReason); \
470 #define HAL_DISABLE_RX_ENHANCE_MODE(_prAdapter) \
473 HAL_MCR_RD(_prAdapter, \
476 HAL_MCR_WR(_prAdapter, \
478 u4Value & ~WHCR_RX_ENHANCE_MODE_EN); \
481 #define HAL_ENABLE_RX_ENHANCE_MODE(_prAdapter) \
484 HAL_MCR_RD(_prAdapter, \
487 HAL_MCR_WR(_prAdapter, \
489 u4Value | WHCR_RX_ENHANCE_MODE_EN); \
492 #define HAL_CFG_MAX_HIF_RX_LEN_NUM(_prAdapter, _ucNumOfRxLen) \
494 UINT_32 u4Value, ucNum; \
495 ucNum = ((_ucNumOfRxLen >= 16) ? 0 : _ucNumOfRxLen); \
497 HAL_MCR_RD(_prAdapter, \
500 u4Value &= ~WHCR_MAX_HIF_RX_LEN_NUM; \
501 u4Value |= ((((UINT_32)ucNum) << 4) & WHCR_MAX_HIF_RX_LEN_NUM); \
502 HAL_MCR_WR(_prAdapter, \
507 #define HAL_SET_INTR_STATUS_READ_CLEAR(prAdapter) \
510 HAL_MCR_RD(prAdapter, \
513 HAL_MCR_WR(prAdapter, \
515 u4Value & ~WHCR_W_INT_CLR_CTRL); \
516 prAdapter->prGlueInfo->rHifInfo.fgIntReadClear = TRUE;\
519 #define HAL_SET_INTR_STATUS_WRITE_1_CLEAR(prAdapter) \
522 HAL_MCR_RD(prAdapter, \
525 HAL_MCR_WR(prAdapter, \
527 u4Value | WHCR_W_INT_CLR_CTRL); \
528 prAdapter->prGlueInfo->rHifInfo.fgIntReadClear = FALSE;\
531 /* Note: enhance mode structure may also carried inside the buffer,
532 if the length of the buffer is long enough */
533 #define HAL_READ_INTR_STATUS(prAdapter, length, pvBuf) \
534 HAL_PORT_RD(prAdapter, \
540 #define HAL_READ_TX_RELEASED_COUNT(_prAdapter, aucTxReleaseCount) \
542 PUINT_32 pu4Value = (PUINT_32)aucTxReleaseCount; \
543 HAL_MCR_RD(_prAdapter, \
546 HAL_MCR_RD(_prAdapter, \
551 #define HAL_READ_RX_LENGTH(prAdapter, pu2Rx0Len, pu2Rx1Len) \
555 HAL_MCR_RD(prAdapter, \
558 *pu2Rx0Len = (UINT_16)u4Value; \
559 *pu2Rx1Len = (UINT_16)(u4Value >> 16); \
562 #define HAL_GET_INTR_STATUS_FROM_ENHANCE_MODE_STRUCT(pvBuf, u2Len, pu4Status) \
564 PUINT_32 pu4Buf = (PUINT_32)pvBuf; \
565 *pu4Status = pu4Buf[0]; \
568 #define HAL_GET_TX_STATUS_FROM_ENHANCE_MODE_STRUCT(pvInBuf, pu4BufOut, u4LenBufOut) \
570 PUINT_32 pu4Buf = (PUINT_32)pvInBuf; \
571 ASSERT(u4LenBufOut >= 8); \
572 pu4BufOut[0] = pu4Buf[1]; \
573 pu4BufOut[1] = pu4Buf[2]; \
576 #define HAL_GET_RX_LENGTH_FROM_ENHANCE_MODE_STRUCT(pvInBuf, pu2Rx0Num, au2Rx0Len, pu2Rx1Num, au2Rx1Len) \
578 PUINT_32 pu4Buf = (PUINT_32)pvInBuf; \
579 ASSERT((sizeof(au2Rx0Len) / sizeof(UINT_16)) >= 16); \
580 ASSERT((sizeof(au2Rx1Len) / sizeof(UINT_16)) >= 16); \
581 *pu2Rx0Num = (UINT_16)pu4Buf[3]; \
582 *pu2Rx1Num = (UINT_16)(pu4Buf[3] >> 16); \
583 kalMemCopy(au2Rx0Len, &pu4Buf[4], 8); \
584 kalMemCopy(au2Rx1Len, &pu4Buf[12], 8); \
587 #define HAL_GET_MAILBOX_FROM_ENHANCE_MODE_STRUCT(pvInBuf, pu4Mailbox0, pu4Mailbox1) \
589 PUINT_32 pu4Buf = (PUINT_32)pvInBuf; \
590 *pu4Mailbox0 = (UINT_16)pu4Buf[21]; \
591 *pu4Mailbox1 = (UINT_16)pu4Buf[22]; \
594 #define HAL_IS_TX_DONE_INTR(u4IntrStatus) \
595 ((u4IntrStatus & WHISR_TX_DONE_INT) ? TRUE : FALSE)
597 #define HAL_IS_RX_DONE_INTR(u4IntrStatus) \
598 ((u4IntrStatus & (WHISR_RX0_DONE_INT | WHISR_RX1_DONE_INT)) ? TRUE : FALSE)
600 #define HAL_IS_ABNORMAL_INTR(u4IntrStatus) \
601 ((u4IntrStatus & WHISR_ABNORMAL_INT) ? TRUE : FALSE)
603 #define HAL_IS_FW_OWNBACK_INTR(u4IntrStatus) \
604 ((u4IntrStatus & WHISR_FW_OWN_BACK_INT) ? TRUE : FALSE)
606 #define HAL_PUT_MAILBOX(prAdapter, u4MboxId, u4Data) \
608 ASSERT(u4MboxId < 2); \
609 HAL_MCR_WR(prAdapter, \
610 ((u4MboxId == 0) ? MCR_H2DSM0R : MCR_H2DSM1R), \
614 #define HAL_GET_MAILBOX(prAdapter, u4MboxId, pu4Data) \
616 ASSERT(u4MboxId < 2); \
617 HAL_MCR_RD(prAdapter, \
618 ((u4MboxId == 0) ? MCR_D2HRM0R : MCR_D2HRM1R), \
622 #define HAL_SET_MAILBOX_READ_CLEAR(prAdapter, fgEnableReadClear) \
625 HAL_MCR_RD(prAdapter, MCR_WHCR, &u4Value);\
626 HAL_MCR_WR(prAdapter, MCR_WHCR, \
627 (fgEnableReadClear) ? \
628 (u4Value | WHCR_W_MAILBOX_RD_CLR_EN) : \
629 (u4Value & ~WHCR_W_MAILBOX_RD_CLR_EN)); \
630 prAdapter->prGlueInfo->rHifInfo.fgMbxReadClear = fgEnableReadClear;\
633 #define HAL_GET_MAILBOX_READ_CLEAR(prAdapter) (prAdapter->prGlueInfo->rHifInfo.fgMbxReadClear)
636 /*******************************************************************************
637 * F U N C T I O N D E C L A R A T I O N S
638 ********************************************************************************
643 /*******************************************************************************
645 ********************************************************************************