2 ** $Id: //Department/DaVinci/TRUNK/MT6620_5931_WiFi_Driver/include/nic/mt5931_reg.h#3 $
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5 /*! \file "mt5931_reg.h"
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6 \brief The common register definition of mt5931
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11 /*******************************************************************************
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12 * Copyright (c) 2010 MediaTek Inc.
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14 * All rights reserved. Copying, compilation, modification, distribution
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15 * or any other use whatsoever of this material is strictly prohibited
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16 * except in accordance with a Software License Agreement with
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18 ********************************************************************************
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21 /*******************************************************************************
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24 * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND
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25 * AGREES THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK
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26 * SOFTWARE") RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE
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27 * PROVIDED TO BUYER ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY
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28 * DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT
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29 * LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
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30 * PARTICULAR PURPOSE OR NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE
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31 * ANY WARRANTY WHATSOEVER WITH RESPECT TO THE SOFTWARE OF ANY THIRD PARTY
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32 * WHICH MAY BE USED BY, INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK
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33 * SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY
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34 * WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE
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35 * FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S SPECIFICATION OR TO
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36 * CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
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38 * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
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39 * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL
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40 * BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT
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41 * ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY
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42 * BUYER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
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44 * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
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45 * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT
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46 * OF LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING
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47 * THEREOF AND RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN
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48 * FRANCISCO, CA, UNDER THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE
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50 ********************************************************************************
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54 ** $Log: mt5931_reg.h $
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57 * [WCXRP00000496] [MT5931][Driver] Apply host-triggered chip reset before initializing firmware download procedures
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58 * apply host-triggered chip reset mechanism before initializing firmware download procedures.
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60 * 02 18 2011 terry.wu
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61 * [WCXRP00000412] [MT6620 Wi-Fi][FW/Driver] Dump firmware assert info at android kernel log
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62 * Add WHISR_D2H_SW_ASSERT_INFO_INT to MT5931_reg.
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65 * [WCXRP00000083] [MT5931][Driver][FW] Add necessary logic for MT5931 first connection
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66 * add firmware download for MT5931.
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70 #ifndef _MT5931_REG_H
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71 #define _MT5931_REG_H
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73 /*******************************************************************************
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74 * C O M P I L E R F L A G S
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75 ********************************************************************************
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78 /*******************************************************************************
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79 * E X T E R N A L R E F E R E N C E S
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80 ********************************************************************************
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83 /*******************************************************************************
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85 ********************************************************************************
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88 /*******************************************************************************
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90 ********************************************************************************
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94 /*******************************************************************************
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95 * P U B L I C D A T A
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96 ********************************************************************************
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99 /*******************************************************************************
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100 * P R I V A T E D A T A
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101 ********************************************************************************
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104 /*******************************************************************************
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106 ********************************************************************************
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109 /*******************************************************************************
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110 * F U N C T I O N D E C L A R A T I O N S
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111 ********************************************************************************
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114 /*******************************************************************************
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115 * F U N C T I O N S
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116 ********************************************************************************
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119 //1 MT5931 MCR Definition
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123 //4 CHIP ID Register
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124 #define MCR_WCIR 0x0000
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126 //4 HIF Low Power Control Register
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127 #define MCR_WHLPCR 0x0004
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129 //4 Control Status Register
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130 #define MCR_WSDIOCSR 0x0008
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131 #define MCR_WSPICSR 0x0008
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133 //4 HIF Control Register
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134 #define MCR_WHCR 0x000C
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136 //4 HIF Interrupt Status Register
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137 #define MCR_WHISR 0x0010
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139 //4 HIF Interrupt Enable Register
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140 #define MCR_WHIER 0x0014
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142 //4 Abnormal Status Register
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143 #define MCR_WASR 0x0018
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145 //4 WLAN Software Interrupt Control Register
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146 #define MCR_WSICR 0x001C
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148 //4 WLAN TX Status Register
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149 #define MCR_WTSR0 0x0020
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151 //4 WLAN TX Status Register
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152 #define MCR_WTSR1 0x0024
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154 //4 WLAN TX Data Register 0
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155 #define MCR_WTDR0 0x0028
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157 //4 WLAN TX Data Register 1
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158 #define MCR_WTDR1 0x002C
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160 //4 WLAN RX Data Register 0
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161 #define MCR_WRDR0 0x0030
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163 //4 WLAN RX Data Register 1
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164 #define MCR_WRDR1 0x0034
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166 //4 Host to Device Send Mailbox 0 Register
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167 #define MCR_H2DSM0R 0x0038
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169 //4 Host to Device Send Mailbox 1 Register
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170 #define MCR_H2DSM1R 0x003c
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172 //4 Device to Host Receive Mailbox 0 Register
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173 #define MCR_D2HRM0R 0x0040
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175 //4 Device to Host Receive Mailbox 1 Register
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176 #define MCR_D2HRM1R 0x0044
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178 //4 Device to Host Receive Mailbox 2 Register
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179 #define MCR_D2HRM2R 0x0048
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181 //4 WLAN RX Packet Length Register
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182 #define MCR_WRPLR 0x0050
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184 //4 EHPI Transaction Count Register
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185 #define MCR_EHTCR 0x0054
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187 //4 Firmware Download Data Register
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188 #define MCR_FWDLDR 0x0080
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190 //4 Firmware Download Destination Starting Address Register
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191 #define MCR_FWDLDSAR 0x0084
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193 //4 Firmware Download Status Register
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194 #define MCR_FWDLSR 0x0088
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196 //4 WLAN MCU Control & Status Register
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197 #define MCR_WMCSR 0x008c
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199 //4 WLAN Firmware Download Configuration
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200 #define MCR_FWCFG 0x0090
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203 //#if CFG_SDIO_INTR_ENHANCE
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204 typedef struct _ENHANCE_MODE_DATA_STRUCT_T {
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216 UINT_32 au4WTSR[2];
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220 UINT_16 u2NumValidRx0Len;
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221 UINT_16 u2NumValidRx1Len;
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222 UINT_16 au2Rx0Len[16];
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223 UINT_16 au2Rx1Len[16];
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225 UINT_32 au4RxStatusRaw[17];
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227 UINT_32 u4RcvMailbox0;
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228 UINT_32 u4RcvMailbox1;
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229 } ENHANCE_MODE_DATA_STRUCT_T, *P_ENHANCE_MODE_DATA_STRUCT_T;
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230 // #endif /* ENHANCE_MODE_DATA_STRUCT_T */
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233 //2 Definition in each register
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235 #define WCIR_WLAN_READY BIT(21)
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236 #define WCIR_POR_INDICATOR BIT(20)
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237 #define WCIR_REVISION_ID BITS(16,19)
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238 #define WCIR_CHIP_ID BITS(0,15)
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240 #define MTK_CHIP_REV 0x00005931
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241 #define MTK_CHIP_MP_REVERSION_ID 0x0
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244 #define WHLPCR_FW_OWN_REQ_CLR BIT(9)
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245 #define WHLPCR_FW_OWN_REQ_SET BIT(8)
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246 #define WHLPCR_IS_DRIVER_OWN BIT(8)
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247 #define WHLPCR_INT_EN_CLR BIT(1)
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248 #define WHLPCR_INT_EN_SET BIT(0)
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250 //3 WSDIOCSR 0x0008
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251 #define WSDIOCSR_SDIO_RE_INIT_EN BIT(0)
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254 #define WCSR_SPI_MODE_SEL BITS(3,4)
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255 #define WCSR_SPI_ENDIAN_BIG BIT(2)
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256 #define WCSR_SPI_INT_OUT_MODE BIT(1)
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257 #define WCSR_SPI_DATA_OUT_MODE BIT(0)
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260 #define WHCR_RX_ENHANCE_MODE_EN BIT(16)
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261 #define WHCR_MAX_HIF_RX_LEN_NUM BITS(4,7)
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262 #define WHCR_W_MAILBOX_RD_CLR_EN BIT(2)
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263 #define WHCR_W_INT_CLR_CTRL BIT(1)
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264 #define WHCR_MCU_DBG_EN BIT(0)
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265 #define WHCR_OFFSET_MAX_HIF_RX_LEN_NUM 4
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268 #define WHISR_D2H_SW_INT BITS(8,31)
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269 #define WHISR_D2H_SW_ASSERT_INFO_INT BIT(31)
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270 #define WHISR_FW_OWN_BACK_INT BIT(4)
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271 #define WHISR_ABNORMAL_INT BIT(3)
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272 #define WHISR_RX1_DONE_INT BIT(2)
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273 #define WHISR_RX0_DONE_INT BIT(1)
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274 #define WHISR_TX_DONE_INT BIT(0)
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278 #define WHIER_D2H_SW_INT BITS(8,31)
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279 #define WHIER_FW_OWN_BACK_INT_EN BIT(4)
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280 #define WHIER_ABNORMAL_INT_EN BIT(3)
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281 #define WHIER_RX1_DONE_INT_EN BIT(2)
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282 #define WHIER_RX0_DONE_INT_EN BIT(1)
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283 #define WHIER_TX_DONE_INT_EN BIT(0)
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284 #define WHIER_DEFAULT (WHIER_RX0_DONE_INT_EN | \
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285 WHIER_RX1_DONE_INT_EN | \
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286 WHIER_TX_DONE_INT_EN | \
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287 WHIER_ABNORMAL_INT_EN | \
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293 #define WASR_FW_OWN_INVALID_ACCESS BIT(4)
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294 #define WASR_RX1_UNDER_FLOW BIT(3)
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295 #define WASR_RX0_UNDER_FLOW BIT(2)
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296 #define WASR_TX1_OVER_FLOW BIT(1)
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297 #define WASR_TX0_OVER_FLOW BIT(0)
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301 #define WSICR_H2D_SW_INT_SET BITS(16,31)
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305 #define WRPLR_RX1_PACKET_LENGTH BITS(16,31)
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306 #define WRPLR_RX0_PACKET_LENGTH BITS(0,15)
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310 #define FWDLSR_FWDL_RDY BIT(8)
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311 #define FWDLSR_FWDL_MODE BIT(0)
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315 #define WMCSR_CHIP_RST BIT(15) /* write */
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316 #define WMCSR_DL_OK BIT(15) /* read */
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317 #define WMCSR_DL_FAIL BIT(14)
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318 #define WMCSR_PLLRDY BIT(13)
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319 #define WMCSR_WF_ON BIT(12)
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320 #define WMCSR_INI_RDY BIT(11)
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321 #define WMCSR_WF_EN BIT(6)
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322 #define WMCSR_SW_EN BIT(5)
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323 #define WMCSR_SPLLEN BIT(4)
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324 #define WMCSR_SPWREN BIT(3)
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325 #define WMCSR_HSTOPIL BIT(2)
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326 #define WMCSR_FWDLRST BIT(1)
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327 #define WMCSR_FWDLEN BIT(0)
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331 #define FWCFG_KSEL BITS(14,15)
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332 #define FWCFG_FLEN BITS(0,13)
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335 #endif /* _MT5931_REG_H */
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