drivers/net/wireless/rockchip_wlan/esp8089/esp_driver/spi_sif_esp.c

   1 /*
   2  * Copyright (c) 2010 -2014 Espressif System.
   3  *
   4  *   spi serial i/f driver
   5  *    - sdio device control routines
   6  *    - sync/async DMA/PIO read/write
   7  *
   8  */
   9 #ifdef ESP_USE_SPI
  10
  11 #include <linux/module.h>
  12 #include <net/mac80211.h>
  13 #include <linux/time.h>
  14 #include <linux/pm.h>
  15 #include <linux/spi/spi.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/kthread.h>
  18
  19
  20 #include "esp_pub.h"
  21 #include "esp_sif.h"
  22 #include "esp_sip.h"
  23 #include "esp_debug.h"
  24 #include "slc_host_register.h"
  25 #include "esp_version.h"
  26 #include "esp_ctrl.h"
  27 #include "esp_file.h"
  28 #ifdef USE_EXT_GPIO
  29 #include "esp_ext.h"
  30 #endif /* USE_EXT_GPIO */
  31
  32 static int /*__init */ esp_spi_init(void);
  33 static void /* __exit */ esp_spi_exit(void);
  34
  35 #ifdef ESP_PREALLOC
  36 extern u8 *esp_get_lspi_buf(void);
  37 extern void esp_put_lspi_buf(u8 **p);
  38 #endif
  39
  40 #define SPI_BLOCK_SIZE              (512)
  41
  42 #define MAX_BUF_SIZE        (48*1024)
  43
  44 static unsigned char *buf_addr = NULL;
  45 static unsigned char *tx_cmd;
  46 static unsigned char *rx_cmd;
  47 static unsigned char *check_buf = NULL;
  48 static unsigned char *ff_buf = NULL;
  49
  50 unsigned int crc_ta_8[256]={
  51                                 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7,
  52                                 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef,
  53                                 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6,
  54                                 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de,
  55                                 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485,
  56                                 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d,
  57                                 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4,
  58                                 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc,
  59                                 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823,
  60                                 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b,
  61                                 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12,
  62                                 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a,
  63                                 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41,
  64                                 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49,
  65                                 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70,
  66                                 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78,
  67                                 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f,
  68                                 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067,
  69                                 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e,
  70                                 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256,
  71                                 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d,
  72                                 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
  73                                 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c,
  74                                 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634,
  75                                 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab,
  76                                 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3,
  77                                 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a,
  78                                 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92,
  79                                 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9,
  80                                 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1,
  81                                 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8,
  82                                 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0
  83                                 };
  84
  85
  86 unsigned int crc_cal_by_byte(unsigned char* ptr, int len)
  87 {
  88     unsigned short crc = 0;
  89
  90     while(len-- != 0)
  91     {
  92         unsigned int high = (unsigned int)(crc >> 8);
  93         crc <<= 8;
  94         crc ^= crc_ta_8[high^*ptr];
  95         ptr++;
  96     }
  97
  98     return crc;
  99 }
 100
 101 struct task_struct *sif_irq_thread;
 102
 103 #define ESP_DMA_IBUFSZ   2048
 104
 105 //unsigned int esp_msg_level = 0;
 106 unsigned int esp_msg_level = ESP_DBG_ERROR | ESP_SHOW;
 107
 108 static struct semaphore esp_powerup_sem;
 109
 110 static enum esp_sdio_state sif_sdio_state;
 111 struct esp_spi_ctrl *sif_sctrl = NULL;
 112 static struct esp_spi_resp spi_resp;
 113
 114 #ifdef ESP_ANDROID_LOGGER
 115 bool log_off = false;
 116 #endif /* ESP_ANDROID_LOGGER */
 117
 118 #ifdef REQUEST_RTC_IRQ
 119 extern int request_rtc_irq(void);
 120 #endif
 121
 122 #include "spi_stub.c"
 123
 124 struct esp_spi_resp *sif_get_spi_resp(void)
 125 {
 126     return &spi_resp;
 127 }
 128
 129 void sif_lock_bus(struct esp_pub *epub)
 130 {
 131         EPUB_FUNC_CHECK(epub, _exit);
 132
 133         spi_bus_lock(EPUB_TO_FUNC(epub)->master);
 134 _exit:
 135         return;
 136 }
 137
 138 void sif_unlock_bus(struct esp_pub *epub)
 139 {
 140         EPUB_FUNC_CHECK(epub, _exit);
 141
 142         spi_bus_unlock(EPUB_TO_FUNC(epub)->master);
 143 _exit:
 144         return;
 145 }
 146
 147 int sif_spi_write_then_read(struct spi_device *spi, unsigned char* bufwrite, int sizesend, unsigned char* bufread, int sizeread)
 148 {
 149         int error;
 150
 151         error = spi_write_then_read(spi, bufwrite,sizesend, bufread, sizeread);
 152
 153         if (error) {
 154                 esp_dbg(ESP_DBG_ERROR, "%s: failed, error: %d\n",
 155                         __func__, error);
 156                 return error;
 157         }
 158
 159         return 0;
 160 }
 161
 162 int sif_spi_write_async_read(struct spi_device *spi, unsigned char* bufwrite,unsigned char* bufread,int size)
 163 {
 164         struct spi_transfer xfer = {
 165               .rx_buf           = bufread,
 166                 .tx_buf         = bufwrite,
 167                 .len            = size,
 168                 .bits_per_word  = 8,
 169                 .speed_hz       = SPI_FREQ,
 170         };
 171         struct spi_message msg;
 172         int error;
 173
 174         spi_message_init(&msg);
 175         spi_message_add_tail(&xfer, &msg);
 176
 177         error = spi_sync_locked(spi, &msg);
 178         if (error) {
 179                 esp_dbg(ESP_DBG_ERROR, "spierr %s: failed, error: %d\n",
 180                         __func__, error);
 181                 return error;
 182         }
 183
 184         return 0;
 185 }
 186
 187 int sif_spi_write_raw(struct spi_device *spi, unsigned char* buf, int size)
 188 {
 189         int err;
 190         struct spi_transfer xfer = {
 191                 .tx_buf         = buf,
 192                 .len            = size,
 193                 .bits_per_word  = 8,
 194                 .speed_hz       = SPI_FREQ,
 195         };
 196         struct spi_message msg;
 197
 198         spi_message_init(&msg);
 199         spi_message_add_tail(&xfer, &msg);
 200
 201         err = spi_sync_locked(spi, &msg);
 202
 203         if (err) {
 204                 esp_dbg(ESP_DBG_ERROR, "%s: failed, error: %d\n",
 205                         __func__, err);
 206                 return err;
 207         }
 208
 209         return 0;
 210 }
 211
 212 int sif_spi_read_raw(struct spi_device *spi, unsigned char* buf, int size)
 213 {
 214         memset(buf,0xff,size);
 215         return sif_spi_write_async_read(spi,buf,buf,size);
 216 }
 217
 218 int sif_spi_write_bytes(struct spi_device *spi, unsigned int addr, unsigned char *src,int count, int dummymode)
 219 {
 220     int i;
 221     int pos,len;
 222     unsigned char *tx_data = (unsigned char*)src;
 223     int err_ret = 0;
 224     u32 timeout = 200;
 225     spi_resp.data_resp_size_w = ((((((count>>5)+1) *75)) +44)>>3) +1;
 226
 227     if (spi == NULL) {
 228         ESSERT(0);
 229         err_ret = -EINVAL;
 230         goto goto_err;
 231     }
 232
 233     if(count > 512 )
 234     {
 235         err_ret = -1;
 236         goto goto_err;
 237     }
 238
 239     tx_cmd[0]=0x75;
 240
 241     if( addr >= (1<<17) )
 242     {
 243         err_ret = -2;
 244         goto goto_err;
 245
 246     }
 247     else
 248     {
 249         tx_cmd[1]=0x90|0x04|(addr>>15);    //0x94;
 250         tx_cmd[2]=addr>>7;
 251
 252         if(count == 512 )
 253         {
 254             tx_cmd[3]=( addr<<1|0x0 );
 255             tx_cmd[4]= 0x00;     //0x08;
 256         }
 257         else
 258         {
 259             tx_cmd[3]=( addr<<1|(count>>8 & 0x01) );
 260             tx_cmd[4]= count & 0xff;     //0x08;
 261         }
 262     }
 263
 264     tx_cmd[5]=0x01;
 265     pos = 5+1;
 266
 267     //Add cmd respon
 268     memset(tx_cmd+pos,0xff,CMD_RESP_SIZE);
 269     pos =pos+ CMD_RESP_SIZE;
 270
 271     //Add token
 272     tx_cmd[pos]=0xFE;
 273     pos = pos+1;
 274
 275     //Add data
 276     memcpy(tx_cmd+pos,tx_data,count);
 277     pos = pos+count;
 278
 279     //Add data respon
 280     memset(tx_cmd+pos,0xff,spi_resp.data_resp_size_w);
 281     pos = pos+ spi_resp.data_resp_size_w ;
 282
 283
 284     if(pos <128)
 285     {
 286         len = 128-pos;
 287         memset(tx_cmd+pos,0xff,len);
 288     }
 289     else
 290     {
 291         if( pos%8 )
 292         {
 293             len = (8 - pos%8);
 294             memset(tx_cmd+pos,0xff,len);
 295         }
 296         else
 297             len = 0;
 298     }
 299
 300     sif_spi_write_async_read(spi, tx_cmd,tx_cmd,pos+len);
 301
 302     pos = 5+1;
 303     for(i=0;i<CMD_RESP_SIZE;i++)
 304     {
 305         if(tx_cmd[pos+i] == 0x00 && tx_cmd[pos+i-1] == 0xff)
 306         {
 307             if(tx_cmd[pos+i+1] == 0x00 && tx_cmd[pos+i+2] == 0xff)
 308                 break;
 309         }
 310     }
 311
 312     if(i>spi_resp.max_cmd_resp_size)
 313     {
 314         spi_resp.max_cmd_resp_size = i;
 315     }
 316
 317     if(i>=CMD_RESP_SIZE)
 318     {
 319         esp_dbg(ESP_DBG_ERROR, "byte write cmd resp 0x00 no recv\n");
 320         err_ret = -3;
 321         goto goto_err;
 322     }
 323
 324     pos = pos+CMD_RESP_SIZE+count+1;
 325     for(i=0;i<spi_resp.data_resp_size_w;i++)
 326     {
 327         if(tx_cmd[pos+i] == 0xE5)
 328         {
 329             //esp_dbg(ESP_DBG_ERROR, "0xE5 pos:%d",i);
 330             for(i++;i<spi_resp.data_resp_size_w ;i++)
 331             {
 332                 if( tx_cmd[pos+i] == 0xFF)
 333                 {
 334        //     esp_dbg(ESP_DBG_ERROR, "find ff pos = %d,i = %d\n",pos+i,i);
 335
 336                     if(i>spi_resp.max_dataW_resp_size)
 337                     {
 338                         spi_resp.max_dataW_resp_size = i;
 339                        // printk(KERN_ERR "new data write MAX 0xFF pos:%d",spi_resp.max_dataW_resp_size);
 340                     }
 341
 342                     //esp_dbg(ESP_DBG_ERROR, "0xFF pos:%d",i);
 343                     break;
 344                 }
 345             }
 346             break;
 347         }
 348     }
 349     if(i>=spi_resp.data_resp_size_w)
 350     {
 351         if(dummymode == 0)
 352             esp_dbg(ESP_DBG, "normal byte write data no-busy wait byte 0xff no recv at the first time\n");
 353
 354         timeout = 200;
 355         do {
 356             timeout --;
 357             //memset(check_buf,0x00,256);
 358
 359             sif_spi_read_raw(spi, check_buf, 256);
 360         } while( memcmp(check_buf,ff_buf,256) != 0 && timeout >0 ) ;
 361
 362         if(timeout == 0)
 363         {
 364             esp_dbg(ESP_DBG_ERROR, "spierr byte write data no-busy wait byte 0xff no recv \n");
 365             err_ret = -4;
 366             goto goto_err;
 367         }
 368     }
 369
 370 goto_err:
 371     return err_ret;
 372 }
 373
 374 int sif_spi_write_blocks(struct spi_device *spi, unsigned int addr,unsigned char *src, int count)
 375 {
 376     int err_ret = 0;
 377     int i,j;
 378     int n;
 379     int pos,len;
 380     unsigned char *tx_data = (unsigned char*)src;
 381     int find_w_rsp = 0;
 382     int timeout = 200;
 383
 384     if (spi == NULL) {
 385         ESSERT(0);
 386         err_ret = -EINVAL;
 387         goto goto_err;
 388     }
 389
 390     tx_cmd[0]=0x75;
 391
 392     if( count <=0 )
 393     {
 394         err_ret = -1;
 395         goto goto_err;
 396     }
 397
 398     if( addr >= (1<<17) )
 399     {
 400         err_ret = -2;
 401         goto goto_err;
 402     }
 403     else
 404     {
 405         tx_cmd[1]=0x90|0x0C|(addr>>15);
 406         tx_cmd[2]=addr>>7;
 407
 408         if(count >= 512 )
 409         {
 410             tx_cmd[3]=( addr<<1|0x0 );
 411             tx_cmd[4]= 0x00;
 412         }
 413         else
 414         {
 415             tx_cmd[3]=( addr<<1|(count>>8 & 0x01) );
 416             tx_cmd[4]= count & 0xff ;
 417         }
 418     }
 419     tx_cmd[5]=0x01;
 420
 421     pos = 5+1;
 422     //Add cmd respon
 423     memset(tx_cmd+pos,0xff,CMD_RESP_SIZE);
 424     pos =pos+ CMD_RESP_SIZE;
 425     if(count < 3)
 426     {
 427         for(j=0;j<count;j++)
 428         {
 429             //Add token
 430             tx_cmd[pos]=0xFC;
 431             pos = pos+1;
 432             //Add data
 433             memcpy(tx_cmd+pos,tx_data+j*SPI_BLOCK_SIZE, SPI_BLOCK_SIZE);
 434             pos = pos+SPI_BLOCK_SIZE;
 435             //Add data respon
 436             if( j==(count- 1) )
 437             {
 438                 memset(tx_cmd+pos , 0xff , spi_resp.block_w_data_resp_size_final);
 439                 pos = pos+ spi_resp.block_w_data_resp_size_final;
 440                 continue;
 441             }
 442             memset(tx_cmd+pos , 0xff , BLOCK_W_DATA_RESP_SIZE_EACH);
 443             pos = pos+ BLOCK_W_DATA_RESP_SIZE_EACH;
 444         }
 445
 446         if( pos%8 )
 447         {
 448             len = (8 - pos%8);
 449             memset(tx_cmd+pos,0xff,len);
 450         }
 451         else
 452             len = 0;
 453
 454         sif_spi_write_async_read(spi, tx_cmd,tx_cmd,pos+len);
 455
 456         //Judge Write cmd resp, and 1st block data resp.
 457         pos = 5+1;
 458         for(i=0;i<CMD_RESP_SIZE;i++)
 459         {
 460             if(tx_cmd[pos+i] == 0x00 && tx_cmd[pos+i-1] == 0xff)
 461             {
 462                 if(tx_cmd[pos+i+1] == 0x00 && tx_cmd[pos+i+2] == 0xff)
 463                     break;
 464             }
 465
 466         }
 467
 468         if(i>spi_resp.max_cmd_resp_size)
 469         {
 470             spi_resp.max_cmd_resp_size = i;
 471         }
 472
 473         if(i>=CMD_RESP_SIZE)
 474         {
 475             esp_dbg(ESP_DBG_ERROR, "spierr 1st block write cmd resp 0x00 no recv, %d\n", count);
 476             err_ret = -3;
 477             goto goto_err;
 478         }
 479
 480         pos = pos+CMD_RESP_SIZE;
 481
 482         for(j=0;j<count;j++)
 483         {
 484             find_w_rsp = 0;
 485             //Judge block data resp
 486             pos = pos+1;
 487             pos = pos+SPI_BLOCK_SIZE;
 488
 489             if( j==(count-1) )
 490                 n = spi_resp.block_w_data_resp_size_final;
 491             else
 492                 n= BLOCK_W_DATA_RESP_SIZE_EACH;
 493
 494             for(i =0 ;i<4;i++)
 495             {
 496                 if((tx_cmd[pos+i] & 0x0F) == 0x05)
 497                 {
 498                     find_w_rsp = 1;
 499                     break;
 500                 }
 501             }
 502
 503             if(find_w_rsp == 1)
 504             {
 505                 if(memcmp(tx_cmd+pos+n-4,ff_buf,4) != 0)
 506                 {
 507
 508                     esp_dbg(ESP_DBG, "block write  sleep 1\n");
 509                     if(j == count-1)
 510                     {
 511                         timeout = 200;
 512                         do {
 513                             timeout --;
 514                             //memset(check_buf,0x00,256);
 515
 516                             sif_spi_read_raw(spi, check_buf, 256);
 517                         } while( memcmp(check_buf,ff_buf,256) != 0 && timeout >0 ) ;
 518
 519                         if(timeout == 0)
 520                         {
 521                             err_ret = -7;
 522                             esp_dbg(ESP_DBG_ERROR, "spierr block write data no-busy wait byte 0xff no recv \n");
 523                             goto goto_err;
 524                         }
 525                     }
 526                     else
 527                     {
 528                         err_ret = -5;
 529                         esp_dbg(ESP_DBG_ERROR, "spierr %s block%d write data not-busy wait error, %d\n", __func__, j+1, count);
 530                         goto goto_err;
 531                     }
 532                 }
 533             }
 534             else
 535             {
 536                 err_ret = -6;
 537                 esp_dbg(ESP_DBG_ERROR, "spierr %s block%d write data no data res error, %d\n", __func__, j+1, count);
 538                 goto goto_err;
 539             }
 540
 541             pos = pos+n;
 542         }
 543     }
 544     else
 545     {
 546         for(j=0;j<2;j++)
 547         {
 548             //Add token
 549             tx_cmd[pos]=0xFC;
 550             pos = pos+1;
 551
 552             //Add data
 553             memcpy(tx_cmd+pos,tx_data+j*SPI_BLOCK_SIZE, SPI_BLOCK_SIZE);
 554             pos = pos+SPI_BLOCK_SIZE;
 555
 556             memset(tx_cmd+pos , 0xff , BLOCK_W_DATA_RESP_SIZE_EACH);
 557             pos = pos+ BLOCK_W_DATA_RESP_SIZE_EACH;
 558         }
 559
 560         if( pos%8 )
 561         {
 562             len = (8 - pos%8);
 563             memset(tx_cmd+pos,0xff,len);
 564         }
 565         else
 566             len = 0;
 567
 568         sif_spi_write_async_read(spi, tx_cmd,tx_cmd,pos+len);
 569
 570         //Judge Write cmd resp, and 1st block data resp.
 571         pos = 5+1;
 572         for(i=0;i<CMD_RESP_SIZE;i++)
 573         {
 574             if(tx_cmd[pos+i] == 0x00 && tx_cmd[pos+i-1] == 0xff)
 575             {
 576                 if(tx_cmd[pos+i+1] == 0x00 && tx_cmd[pos+i+2] == 0xff)
 577                     break;
 578             }
 579
 580         }
 581
 582         if(i>spi_resp.max_cmd_resp_size)
 583         {
 584             spi_resp.max_cmd_resp_size = i;
 585         }
 586
 587         if(i>=CMD_RESP_SIZE)
 588         {
 589             esp_dbg(ESP_DBG_ERROR, "spierr 1st block write cmd resp 0x00 no recv, %d\n", count);
 590             err_ret = -3;
 591             goto goto_err;
 592         }
 593
 594         pos = pos+CMD_RESP_SIZE;
 595
 596         for(j=0;j<2;j++)
 597         {
 598             find_w_rsp = 0;
 599             //Judge block data resp
 600             pos = pos+1;
 601             pos = pos+SPI_BLOCK_SIZE;
 602
 603             n = BLOCK_W_DATA_RESP_SIZE_EACH;
 604
 605             for(i =0 ;i<4;i++)
 606             {
 607                 if((tx_cmd[pos+i] & 0x0F) == 0x05)
 608                 {
 609                     find_w_rsp = 1;
 610                     break;
 611                 }
 612             }
 613
 614             if(find_w_rsp == 1)
 615             {
 616                 if(memcmp(tx_cmd+pos+n-4,ff_buf,4) != 0 )
 617                 {
 618                     esp_dbg(ESP_DBG, "block write data during sleep \n");
 619
 620                     if(j == 1)
 621                     {
 622                         timeout = 200;
 623                         do {
 624                             timeout --;
 625
 626                             sif_spi_read_raw(spi, check_buf, 256);
 627                         } while( memcmp(check_buf,ff_buf,256) != 0 && timeout >0 ) ;
 628
 629                         if(timeout == 0)
 630                         {
 631                             err_ret = -7;
 632                             esp_dbg(ESP_DBG_ERROR, "spierr block write data no-busy wait byte 0xff no recv \n");
 633                             goto goto_err;
 634                         }
 635                     }
 636                     else
 637                     {
 638                         err_ret = -5;
 639                         esp_dbg(ESP_DBG_ERROR, "spierr %s block%d write data not-busy wait error, %d\n", __func__, j+1, count);
 640                         goto goto_err;
 641                     }
 642                 }
 643             }
 644             else
 645             {
 646                 err_ret = -6;
 647                 esp_dbg(ESP_DBG_ERROR, "spierr %s block%d write data no data res error, %d\n", __func__, j+1, count);
 648                 goto goto_err;
 649             }
 650
 651             pos = pos+n;
 652         }
 653
 654
 655         pos = 0;
 656         for(j=2;j<count;j++)
 657         {
 658             //Add token
 659             tx_cmd[pos]=0xFC;
 660             pos = 1+pos ;
 661             //Add data
 662             memcpy(tx_cmd+pos,tx_data+j*SPI_BLOCK_SIZE, SPI_BLOCK_SIZE);
 663             pos = pos+SPI_BLOCK_SIZE;
 664             //Add data respon
 665             if(j == count-1)
 666             {
 667                 memset(tx_cmd+pos , 0xff ,spi_resp.block_w_data_resp_size_final);
 668                 pos = pos+spi_resp.block_w_data_resp_size_final;
 669                 continue;
 670             }
 671             memset(tx_cmd+pos , 0xff , BLOCK_W_DATA_RESP_SIZE_EACH);
 672             pos = pos+ BLOCK_W_DATA_RESP_SIZE_EACH;
 673         }
 674
 675         if( pos%8 )
 676         {
 677             len = (8 - pos%8);
 678             memset(tx_cmd+pos,0xff,len);
 679         }
 680         else
 681             len = 0;
 682
 683         sif_spi_write_async_read(spi, tx_cmd,tx_cmd,pos+len);
 684
 685         pos = 0;
 686         for(j=2;j<count;j++)
 687         {
 688             find_w_rsp = 0;
 689             //Judge block data resp
 690             pos = pos+1;
 691             pos = pos+SPI_BLOCK_SIZE;
 692
 693             if( j==(count-1) )
 694                 n = spi_resp.block_w_data_resp_size_final;
 695             else
 696                 n= BLOCK_W_DATA_RESP_SIZE_EACH;
 697
 698             for(i =0 ;i<4;i++)
 699             {
 700                 if((tx_cmd[pos+i] & 0x0F) == 0x05)
 701                 {
 702                     find_w_rsp = 1;
 703                     break;
 704                 }
 705             }
 706
 707             if(find_w_rsp == 1)
 708             {
 709                 if(memcmp(tx_cmd+pos+n-4,ff_buf,4) != 0)
 710                 {
 711                     err_ret = -5;
 712                     esp_dbg(ESP_DBG_ERROR, "spierr %s block%d write data not-busy wait error, %d\n", __func__, j+1, count);
 713                     goto goto_err;
 714                 }
 715             }
 716             else
 717             {
 718                 err_ret = -6;
 719                 esp_dbg(ESP_DBG_ERROR, "spierr %s block%d write data no data res error, %d\n", __func__, j+1, count);
 720                 goto goto_err;
 721             }
 722
 723             pos = pos+n;
 724         }
 725     }
 726
 727 goto_err:
 728
 729     return err_ret;
 730 }
 731
 732 int sif_spi_write_mix_nosync(struct spi_device *spi, unsigned int addr, unsigned char *buf, int len, int dummymode)
 733 {
 734         int blk_cnt;
 735         int remain_len;
 736         int err;
 737         do {
 738                 blk_cnt = len/SPI_BLOCK_SIZE;
 739                 remain_len = len%SPI_BLOCK_SIZE;
 740
 741                 if (blk_cnt > 0) {
 742                         err  = sif_spi_write_blocks(spi, addr, buf, blk_cnt);
 743                         if (err)
 744                                 return err;
 745                 }
 746
 747                 if (remain_len > 0) {
 748                         err = sif_spi_write_bytes(spi, addr, (buf + (blk_cnt*SPI_BLOCK_SIZE)), remain_len, dummymode);
 749                         if (err)
 750                                 return err;
 751                 }
 752         } while(0);
 753         return 0;
 754
 755 }
 756
 757 int sif_spi_write_mix_sync(struct spi_device *spi, unsigned int addr, unsigned char *buf, int len, int dummymode)
 758 {
 759         int err;
 760
 761         spi_bus_lock(spi->master);
 762         err = sif_spi_write_mix_nosync(spi, addr, buf, len, dummymode);
 763         spi_bus_unlock(spi->master);
 764
 765         return err;
 766 }
 767
 768 int sif_spi_epub_write_mix_nosync(struct esp_pub *epub, unsigned int addr, unsigned char *buf,int len, int dummymode)
 769 {
 770         struct esp_spi_ctrl *sctrl = NULL;
 771         struct spi_device *spi = NULL;
 772
 773         if (epub == NULL) {
 774                 ESSERT(0);
 775                 return -EINVAL;
 776         }
 777         sctrl = (struct esp_spi_ctrl *)epub->sif;
 778         spi = sctrl->spi;
 779         if (spi == NULL) {
 780                 ESSERT(0);
 781                 return -EINVAL;
 782         }
 783
 784         return sif_spi_write_mix_nosync(spi, addr, buf, len, dummymode);
 785 }
 786
 787 int sif_spi_epub_write_mix_sync(struct esp_pub *epub, unsigned int addr, unsigned char *buf,int len, int dummymode)
 788 {
 789         struct esp_spi_ctrl *sctrl = NULL;
 790         struct spi_device *spi = NULL;
 791
 792         if (epub == NULL) {
 793                 ESSERT(0);
 794                 return -EINVAL;
 795         }
 796         sctrl = (struct esp_spi_ctrl *)epub->sif;
 797         spi = sctrl->spi;
 798         if (spi == NULL) {
 799                 ESSERT(0);
 800                 return -EINVAL;
 801         }
 802
 803         return sif_spi_write_mix_sync(spi, addr, buf, len, dummymode);
 804 }
 805
 806 int sif_spi_read_bytes(struct spi_device *spi, unsigned int addr,unsigned char *dst, int count, int dummymode)
 807 {
 808     int pos,total_num,len;
 809     int i;
 810     unsigned char *rx_data = (unsigned char *)dst;
 811     int err_ret = 0;
 812     unsigned short crc = 0;
 813     char test_crc[2];
 814     int unexp_byte = 0;
 815
 816     u32 timeout = 200;
 817     int find_start_token = 0;
 818     spi_resp.data_resp_size_r = ((((((count>>2)+1) *25)>>5)*21+16)>>3) +1  ;
 819
 820     if (spi == NULL) {
 821         ESSERT(0);
 822         err_ret = -EINVAL;
 823         goto goto_err;
 824     }
 825
 826     rx_cmd[0]=0x75;
 827
 828     if(count > 512 )
 829     {
 830         err_ret = -1;
 831         goto goto_err;
 832     }
 833
 834     if( addr >= (1<<17) )
 835     {
 836         err_ret = -2;
 837         goto goto_err;
 838     }
 839     else
 840     {
 841         rx_cmd[1]=0x10|0x04|(addr>>15);    //0x94;
 842         rx_cmd[2]=addr>>7;
 843
 844         if(count == 512 )
 845         {
 846             rx_cmd[3]=( addr<<1|0x0 );
 847             rx_cmd[4]= 0x00;     //0x08;
 848         }
 849         else
 850         {
 851             rx_cmd[3]=( addr<<1|(count>>8 & 0x01) );
 852             rx_cmd[4]= count & 0xff;     //0x08;
 853         }
 854     }
 855
 856     rx_cmd[5]=0x01;
 857
 858     total_num = CMD_RESP_SIZE+spi_resp.data_resp_size_r+count+2;
 859     memset(rx_cmd+6 , 0xFF ,total_num);
 860
 861     if(6+total_num <128)
 862     {
 863         len =128 -6 -total_num;
 864         memset(rx_cmd+6+total_num,0xff,len);
 865     }
 866     else
 867     {
 868
 869         if( (6+total_num)%8 )
 870         {
 871             len = (8 - (6+total_num)%8);
 872             memset(rx_cmd+6+total_num,0xff,len);
 873         }
 874         else
 875             len = 0;
 876
 877     }
 878
 879     sif_spi_write_async_read(spi, rx_cmd,rx_cmd,6+total_num+len);
 880
 881     pos = 5+1;
 882     for(i=0;i<CMD_RESP_SIZE;i++)
 883     {
 884         if(rx_cmd[pos+i] == 0x00 && rx_cmd[pos+i-1] == 0xff)
 885         {
 886             if(rx_cmd[pos+i+1] == 0x00 && rx_cmd[pos+i+2] == 0xff)
 887                 break;
 888         }
 889     }
 890
 891     if(i>spi_resp.max_cmd_resp_size)
 892     {
 893         spi_resp.max_cmd_resp_size = i;
 894         //printk(KERN_ERR "new cmd write MAX 0xFF pos:%d",spi_resp.max_cmd_resp_size);
 895     }
 896
 897
 898     if(i>=CMD_RESP_SIZE)
 899     {
 900         esp_dbg(ESP_DBG_ERROR, "spierr byte read cmd resp 0x00 no recv\n");
 901         /***********error info************************/
 902         /*
 903            char t = pos;
 904            while ( t < pos+32) {
 905            printk(KERN_ERR "rx:[0x%02x] ", rx_cmd[t]);
 906            t++;
 907            if ((t-pos)%8 == 0)
 908            printk(KERN_ERR "\n");
 909            }
 910            */
 911         err_ret = -3;
 912         goto goto_err;
 913     }
 914     //esp_dbg(ESP_DBG_ERROR, "0x00 pos:%d",pos+i);
 915     pos = pos+i+2;
 916
 917     for(i=0;i<spi_resp.data_resp_size_r;i++)
 918     {
 919         if(rx_cmd[pos+i]==0xFE)
 920         {
 921
 922             find_start_token = 1;
 923             if(i>spi_resp.max_dataR_resp_size)
 924             {
 925                 spi_resp.max_dataR_resp_size = i;
 926                 //printk(KERN_ERR "new data read MAX 0xFE pos:%d",spi_resp.max_dataR_resp_size);
 927             }
 928             break;
 929         }
 930         else if(rx_cmd[pos+i] != 0xff)
 931         {
 932             unexp_byte ++;
 933             if(unexp_byte == 1)
 934                 esp_dbg(ESP_DBG, " 1 normal byte read not 0xFF or 0xFE  at the first time,count = %d,addr =%x \n",count,addr);
 935         }
 936     }
 937
 938     if(find_start_token == 0)
 939     {
 940         if(dummymode == 0)
 941             esp_dbg(ESP_DBG, " normal byte read start token 0xFE  not recv at the first time,count = %d,addr =%x \n",count,addr);
 942
 943         pos = pos +spi_resp.data_resp_size_r;
 944
 945         for(i=0;i< 6+total_num+len-pos;i++)
 946         {
 947             if(rx_cmd[pos+i]==0xFE)
 948             {
 949                 sif_spi_read_raw(spi,rx_cmd,((count+4)>256)?(count+4):256);
 950                // sif_spi_read_raw(spi, check_buf, 256);
 951                 find_start_token = 1;
 952                 err_ret = -4;
 953                 goto goto_err;
 954             }
 955             else if(rx_cmd[pos+i] !=0xff)
 956             {
 957                 unexp_byte ++;
 958                 if(unexp_byte == 1)
 959                     esp_dbg(ESP_DBG, "2 normal byte read not 0xFF or 0xFE  at the first time,count = %d,addr =%x \n",count,addr);
 960             }
 961
 962         }
 963
 964         timeout = 200;
 965         do {
 966             timeout --;
 967
 968             sif_spi_read_raw(spi, check_buf, 256);
 969             for(i=0;i<256;i++)
 970             {
 971                 if(check_buf[i] ==0xFE)
 972                 {
 973                     find_start_token = 1;
 974                     sif_spi_read_raw(spi,rx_cmd,((count+4)>256)?(count+4):256);
 975
 976                     break;
 977                 }
 978             }
 979         } while( find_start_token != 1 && timeout >0 ) ;
 980
 981         if(timeout == 0)
 982         {
 983             esp_dbg(ESP_DBG_ERROR, "spierr byte read start token 0xFE no recv ,count = %d,addr =%x \n",count,addr);
 984         }
 985         err_ret = -5;
 986
 987         goto goto_err;
 988     }
 989
 990     //esp_dbg(ESP_DBG_ERROR, "0xFE pos:%d",pos+i);
 991     pos = pos+i+1;
 992     memcpy(rx_data,rx_cmd+pos,count);
 993
 994     crc = crc_cal_by_byte(rx_data,count);
 995
 996     test_crc[0] = crc & 0xff;
 997     test_crc[1] = (crc >>8) &0xff ;
 998
 999     if(test_crc[1] != rx_cmd[pos+count] || test_crc[0] != rx_cmd[pos+count+1] )
1000     {
1001         esp_dbg(ESP_DBG, "crc test_crc0  %x\n",test_crc[0]);
1002         esp_dbg(ESP_DBG, "crc test_crc1  %x\n",test_crc[1]);
1003         esp_dbg(ESP_DBG, "crc rx_data-2  %x\n",rx_cmd[pos+count]);
1004         esp_dbg(ESP_DBG, "crc rx_data-1  %x\n",rx_cmd[pos+count+1] );
1005
1006         esp_dbg(ESP_DBG, "crc err\n");
1007
1008         esp_dbg(ESP_DBG_ERROR, "spierr crc count = %d,addr =%x \n",count,addr);
1009
1010         err_ret = -6;
1011         goto goto_err;
1012
1013     }
1014
1015 goto_err:
1016
1017     return err_ret;
1018 }
1019
1020 int sif_spi_read_blocks(struct spi_device *spi, unsigned int addr, unsigned char *dst, int count)
1021 {
1022     int err_ret = 0;
1023     int pos,len;
1024     int i,j;
1025     unsigned char *rx_data = (unsigned char *)dst;
1026     int total_num;
1027     u32 timeout = 200;
1028     int find_start_token = 0;
1029     unsigned short crc = 0;
1030     char test_crc[2];
1031
1032     if (spi == NULL) {
1033         ESSERT(0);
1034         err_ret = -EINVAL;
1035         goto goto_err;
1036     }
1037
1038     rx_cmd[0]=0x75;
1039
1040     if( count <=0 )
1041     {
1042         err_ret = -1;
1043         goto goto_err;
1044     }
1045     if( addr >= (1<<17) )
1046     {
1047         err_ret = -2;
1048         goto goto_err;
1049     }
1050     else
1051     {
1052         rx_cmd[1]=0x10|0x0C|(addr>>15);
1053         rx_cmd[2]=addr>>7;
1054
1055         if(count >= 512 )
1056         {
1057             rx_cmd[3]=( addr<<1|0x0 );
1058             rx_cmd[4]= 0x00;
1059         }
1060         else
1061         {
1062             rx_cmd[3]=( addr<<1|(count>>8 & 0x01) );
1063             rx_cmd[4]= count & 0xff;
1064         }
1065     }
1066     rx_cmd[5]=0x01;
1067     total_num = CMD_RESP_SIZE+spi_resp.block_r_data_resp_size_final+SPI_BLOCK_SIZE+ 2 + (count-1)*(BLOCK_R_DATA_RESP_SIZE_EACH+SPI_BLOCK_SIZE+2);
1068     memset(rx_cmd+6, 0xFF ,total_num);
1069
1070     if( (6+total_num)%8 )
1071     {
1072         len = (8 - (6+total_num)%8);
1073         memset(rx_cmd+6+total_num,0xff,len);
1074     }
1075     else
1076         len = 0;
1077
1078     sif_spi_write_async_read(spi, rx_cmd,rx_cmd,6+total_num+len );
1079
1080     pos = 5+1;
1081     for(i=0;i<CMD_RESP_SIZE;i++)
1082     {
1083         if(rx_cmd[pos+i] == 0x00 && rx_cmd[pos+i-1] == 0xff)
1084         {
1085             if(rx_cmd[pos+i+1] == 0x00 && rx_cmd[pos+i+2] == 0xff)
1086                 break;
1087         }
1088     }
1089
1090     if(i>spi_resp.max_cmd_resp_size)
1091     {
1092         spi_resp.max_cmd_resp_size = i;
1093         //printk(KERN_ERR "new cmd write MAX 0xFF pos:%d",spi_resp.max_cmd_resp_size);
1094     }
1095
1096     if(i>=CMD_RESP_SIZE)
1097     {
1098         esp_dbg(ESP_DBG_ERROR, "spierr block read cmd resp 0x00 no recv\n");
1099
1100         err_ret = -3;
1101         goto goto_err;
1102     }
1103
1104     pos = pos+i+2;
1105
1106     for(i=0;i<spi_resp.block_r_data_resp_size_final;i++)
1107     {
1108         if(rx_cmd[pos+i]==0xFE)
1109         {
1110             //esp_dbg(ESP_DBG_ERROR, "0xFE pos:%d",i);
1111             find_start_token = 1;
1112             if(i>spi_resp.max_block_dataR_resp_size)
1113             {
1114                 spi_resp.max_block_dataR_resp_size = i;
1115                 //printk(KERN_ERR "new block data read MAX 0xFE pos:%d\n",spi_resp.max_block_dataR_resp_size);
1116             }
1117
1118             break;
1119         }
1120     }
1121
1122     if( find_start_token == 0)
1123     {
1124         esp_dbg(ESP_DBG, "1st block read data resp 0xFE no recv,count = %d\n",count);
1125         pos = pos +spi_resp.block_r_data_resp_size_final;
1126         for(i=0;i< 6+total_num+len-pos;i++)
1127         {
1128             if(rx_cmd[pos+i]==0xFE)
1129             {
1130                 sif_spi_read_raw(spi, check_buf, total_num+len);
1131                 find_start_token = 1;
1132                 err_ret = -4;
1133                 goto goto_err;
1134             }
1135         }
1136
1137         timeout = 200;
1138         do {
1139             esp_dbg(ESP_DBG_ERROR, "block read  sleep ,count = %d\n",count);
1140             timeout --;
1141             sif_spi_read_raw(spi, check_buf, 256);
1142             for(i=0;i<256;i++)
1143             {
1144                 if(check_buf[i] ==0xFE)
1145                 {
1146                     find_start_token= 1;
1147                     sif_spi_read_raw(spi, rx_cmd, total_num+len);
1148                     break;
1149                 }
1150             }
1151         } while( find_start_token != 1 && timeout >0 ) ;
1152         if(timeout == 0)
1153         {
1154             err_ret = -8;
1155             esp_dbg(ESP_DBG_ERROR, "spierr block read start token 0xFE no recv\n");
1156         }else
1157         {
1158             err_ret = -5;
1159         }
1160         goto goto_err;
1161     }
1162
1163     pos = pos+i+1;
1164
1165     memcpy(rx_data,rx_cmd+pos,SPI_BLOCK_SIZE);
1166
1167     crc = crc_cal_by_byte(rx_data,512);
1168
1169     test_crc[0] = crc & 0xff;
1170     test_crc[1] = (crc >>8) &0xff ;
1171
1172     if(test_crc[1] != rx_cmd[pos+SPI_BLOCK_SIZE] || test_crc[0] != rx_cmd[pos+SPI_BLOCK_SIZE+1] )
1173     {
1174         esp_dbg(ESP_DBG, "crc test_crc0  %x\n",test_crc[0]);
1175         esp_dbg(ESP_DBG, "crc test_crc1  %x\n",test_crc[1]);
1176         esp_dbg(ESP_DBG, "crc rx_data-2  %x\n",rx_cmd[pos+SPI_BLOCK_SIZE]);
1177         esp_dbg(ESP_DBG, "crc rx_data-1  %x\n",rx_cmd[pos+SPI_BLOCK_SIZE+1] );
1178
1179         esp_dbg(ESP_DBG_ERROR, "spierr crc err block = 1,count = %d\n",count);
1180
1181         err_ret = -6;
1182         goto goto_err;
1183
1184     }
1185
1186     pos = pos +SPI_BLOCK_SIZE + 2;
1187
1188     for(j=1;j<count;j++)
1189     {
1190
1191         for(i=0;i<BLOCK_R_DATA_RESP_SIZE_EACH;i++)
1192         {
1193             if(rx_cmd[pos+i]==0xFE)
1194             {
1195                 //esp_dbg(ESP_DBG_ERROR, "0xFE pos:%d",i);
1196                 if(i>spi_resp.max_block_dataR_resp_size)
1197                 {
1198                     spi_resp.max_block_dataR_resp_size = i;
1199                     //printk(KERN_ERR "new block data read MAX 0xFE pos:%d",spi_resp.max_block_dataR_resp_size);
1200                 }
1201
1202                 break;
1203             }
1204         }
1205         if(i>=BLOCK_R_DATA_RESP_SIZE_EACH)
1206         {
1207             esp_dbg(ESP_DBG_ERROR, "spierr block%d read data token 0xFE no recv,total:%d\n",j+1,count);
1208             err_ret = -7;
1209             goto goto_err;
1210         }
1211
1212         pos = pos+i+1;
1213
1214         memcpy(rx_data+j*SPI_BLOCK_SIZE,rx_cmd+pos,SPI_BLOCK_SIZE);
1215
1216         crc = crc_cal_by_byte(rx_data+j*SPI_BLOCK_SIZE ,512);
1217
1218         test_crc[0] = crc & 0xff;
1219         test_crc[1] = (crc >>8) &0xff ;
1220
1221         if(test_crc[1] != rx_cmd[pos+SPI_BLOCK_SIZE] || test_crc[0] != rx_cmd[pos+SPI_BLOCK_SIZE+1] )
1222         {
1223             esp_dbg(ESP_DBG, "crc test_crc0  %x\n",test_crc[0]);
1224             esp_dbg(ESP_DBG, "crc test_crc1  %x\n",test_crc[1]);
1225             esp_dbg(ESP_DBG, "crc rx_data-2  %x\n",rx_cmd[pos+SPI_BLOCK_SIZE]);
1226             esp_dbg(ESP_DBG, "crc rx_data-1  %x\n",rx_cmd[pos+SPI_BLOCK_SIZE+1] );
1227
1228             esp_dbg(ESP_DBG_ERROR, "spierr crc err,count = %d,block =%d\n",count,j+1);
1229
1230             err_ret = -6;
1231             goto goto_err;
1232         }
1233
1234         pos = pos +SPI_BLOCK_SIZE + 2;
1235     }
1236
1237 goto_err:
1238
1239     return err_ret;
1240 }
1241
1242 int sif_spi_read_mix_nosync(struct spi_device *spi, unsigned int addr, unsigned char *buf, int len, int dummymode)
1243 {
1244         int blk_cnt;
1245         int remain_len;
1246         int err = 0;
1247         int retry = 20;
1248
1249         do{
1250                 blk_cnt = len/SPI_BLOCK_SIZE;
1251                 remain_len = len%SPI_BLOCK_SIZE;
1252
1253                 if (blk_cnt > 0) {
1254
1255                         retry = 20;
1256                         do {
1257                                 if(retry < 20)
1258                                         mdelay(10);
1259                                 retry--;
1260                                 check_buf[0] = 1<<2;
1261                                 err  = sif_spi_read_blocks(spi, addr, buf, blk_cnt);
1262                                 if(err == 0)
1263                                 {
1264                                         sif_spi_write_bytes(spi,SLC_HOST_CONF_W4 + 2,check_buf,1,0);
1265                                 } else if(err == -4 ||err == -5 ||err == -6||err == -7 ||err == -8)
1266                                 {
1267                                         struct esp_spi_ctrl *sctrl = spi_get_drvdata(spi);
1268                                         if(sctrl != NULL) {
1269                                                 sif_ack_target_read_err(sctrl->epub);
1270                                         }
1271                                 } else if(err == -3)
1272                                 {
1273                                         continue;
1274                                 } else
1275                                 {
1276                                         break;
1277                                 }
1278
1279                         }while(retry > 0 && err != 0);
1280                         if(err != 0 && retry == 0)
1281                                 esp_dbg(ESP_DBG_ERROR, "spierr 20 times retry block read fail\n");
1282
1283                         if(err)
1284                                 return err;
1285                 }
1286
1287                 if (remain_len > 0) {
1288                         if(dummymode == 0 )
1289                         {
1290                                 retry = 20;
1291                                 do{
1292                                         if(retry <20)
1293                                                 mdelay(10);
1294                                         retry--;
1295                                         err = sif_spi_read_bytes(spi, addr, (buf + (blk_cnt*SPI_BLOCK_SIZE)), remain_len, dummymode);
1296                                 }while(retry >0 && err != 0);
1297
1298                                 if(err != 0 &&  retry == 0)
1299                                         esp_dbg(ESP_DBG_ERROR, "spierr 20 times retry byte read fail\n");
1300                         }
1301                         else
1302                         {
1303                                 err = sif_spi_read_bytes(spi, addr, (buf + (blk_cnt*SPI_BLOCK_SIZE)), remain_len, dummymode);
1304                         }
1305                         if (err)
1306                                 return err;
1307                 }
1308         } while(0);
1309         return 0;
1310 }
1311
1312 int sif_spi_read_mix_sync(struct spi_device *spi, unsigned int addr, unsigned char *buf, int len, int dummymode)
1313 {
1314         int err;
1315
1316         spi_bus_lock(spi->master);
1317         err = sif_spi_read_mix_nosync(spi, addr, buf, len, dummymode);
1318         spi_bus_unlock(spi->master);
1319
1320         return err;
1321 }
1322
1323 int sif_spi_epub_read_mix_nosync(struct esp_pub *epub, unsigned int addr, unsigned char *buf,int len, int dummymode)
1324 {
1325         struct esp_spi_ctrl *sctrl = NULL;
1326         struct spi_device *spi = NULL;
1327
1328         if (epub == NULL) {
1329                 ESSERT(0);
1330                 return -EINVAL;
1331         }
1332         sctrl = (struct esp_spi_ctrl *)epub->sif;
1333         spi = sctrl->spi;
1334         if (spi == NULL) {
1335                 ESSERT(0);
1336                 return -EINVAL;
1337         }
1338
1339         return sif_spi_read_mix_nosync(spi, addr, buf, len, dummymode);
1340 }
1341
1342 int sif_spi_epub_read_mix_sync(struct esp_pub *epub, unsigned int addr, unsigned char *buf,int len, int dummymode)
1343 {
1344         struct esp_spi_ctrl *sctrl = NULL;
1345         struct spi_device *spi = NULL;
1346
1347         if (epub == NULL) {
1348                 ESSERT(0);
1349                 return -EINVAL;
1350         }
1351         sctrl = (struct esp_spi_ctrl *)epub->sif;
1352         spi = sctrl->spi;
1353         if (spi == NULL) {
1354                 ESSERT(0);
1355                 return -EINVAL;
1356         }
1357
1358         return sif_spi_read_mix_sync(spi, addr, buf, len, dummymode);
1359 }
1360
1361 int sif_spi_read_sync(struct esp_pub *epub, unsigned char *buf, int len, int dummymode)
1362 {
1363         struct esp_spi_ctrl *sctrl = NULL;
1364         struct spi_device *spi = NULL;
1365         u32 read_len;
1366
1367         if (epub == NULL || buf == NULL) {
1368                 ESSERT(0);
1369                 return -EINVAL;
1370         }
1371         sctrl = (struct esp_spi_ctrl *)epub->sif;
1372         spi = sctrl->spi;
1373         if (spi == NULL) {
1374                 ESSERT(0);
1375                 return -EINVAL;
1376         }
1377
1378         switch(sctrl->target_id) {
1379         case 0x100:
1380                 read_len = len;
1381                 break;
1382         case 0x600:
1383                 read_len = roundup(len, sctrl->slc_blk_sz);
1384                 break;
1385         default:
1386                 read_len = len;
1387                 break;
1388         }
1389
1390         return sif_spi_read_mix_sync(spi, sctrl->slc_window_end_addr - 2 - (len), buf, read_len, dummymode);
1391 }
1392
1393 int sif_spi_write_sync(struct esp_pub *epub, unsigned char *buf, int len, int dummymode)
1394 {
1395         struct esp_spi_ctrl *sctrl = NULL;
1396         struct spi_device *spi = NULL;
1397         u32 write_len;
1398
1399         if (epub == NULL || buf == NULL) {
1400                 ESSERT(0);
1401                 return -EINVAL;
1402         }
1403         sctrl = (struct esp_spi_ctrl *)epub->sif;
1404         spi = sctrl->spi;
1405         if (spi == NULL) {
1406                 ESSERT(0);
1407                 return -EINVAL;
1408         }
1409
1410         switch(sctrl->target_id) {
1411         case 0x100:
1412                 write_len = len;
1413                 break;
1414         case 0x600:
1415                 write_len = roundup(len, sctrl->slc_blk_sz);
1416                 break;
1417         default:
1418                 write_len = len;
1419                 break;
1420         }
1421         return sif_spi_write_mix_sync(spi, sctrl->slc_window_end_addr - (len), buf, write_len, dummymode);
1422 }
1423
1424 int sif_spi_read_nosync(struct esp_pub *epub, unsigned char *buf, int len, int dummymode, bool noround)
1425 {
1426         struct esp_spi_ctrl *sctrl = NULL;
1427         struct spi_device *spi = NULL;
1428         u32 read_len;
1429
1430         if (epub == NULL || buf == NULL) {
1431                 ESSERT(0);
1432                 return -EINVAL;
1433         }
1434         sctrl = (struct esp_spi_ctrl *)epub->sif;
1435         spi = sctrl->spi;
1436         if (spi == NULL) {
1437                 ESSERT(0);
1438                 return -EINVAL;
1439         }
1440
1441         switch(sctrl->target_id) {
1442         case 0x100:
1443                 read_len = len;
1444                 break;
1445         case 0x600:
1446                 if (!noround)
1447                         read_len = roundup(len, sctrl->slc_blk_sz);
1448                 else
1449                         read_len = len;
1450                 break;
1451         default:
1452                 read_len = len;
1453                 break;
1454         }
1455
1456         return sif_spi_read_mix_nosync(spi, sctrl->slc_window_end_addr - 2 - (len), buf, read_len, dummymode);
1457 }
1458
1459 int sif_spi_write_nosync(struct esp_pub *epub, unsigned char *buf, int len, int dummymode)
1460 {
1461         struct esp_spi_ctrl *sctrl = NULL;
1462         struct spi_device *spi = NULL;
1463         u32 write_len;
1464
1465         if (epub == NULL || buf == NULL) {
1466                 ESSERT(0);
1467                 return -EINVAL;
1468         }
1469         sctrl = (struct esp_spi_ctrl *)epub->sif;
1470         spi = sctrl->spi;
1471         if (spi == NULL) {
1472                 ESSERT(0);
1473                 return -EINVAL;
1474         }
1475
1476         switch(sctrl->target_id) {
1477         case 0x100:
1478                 write_len = len;
1479                 break;
1480         case 0x600:
1481                 write_len = roundup(len, sctrl->slc_blk_sz);
1482                 break;
1483         default:
1484                 write_len = len;
1485                 break;
1486         }
1487         return sif_spi_write_mix_nosync(spi, sctrl->slc_window_end_addr - (len), buf, write_len, dummymode);
1488 }
1489
1490 int sif_spi_protocol_init(struct spi_device *spi)
1491 {
1492         unsigned char spi_proto_ini_status = 0;
1493         unsigned char rx_buf1[10];
1494         unsigned char tx_buf1[10];
1495         unsigned char dummy_tx_buf[10];
1496         memset(dummy_tx_buf,0xff,sizeof(dummy_tx_buf));
1497         do
1498         {
1499                  if( spi_proto_ini_status == 0 )
1500                  {
1501                         int fail_count = 0;
1502                         do
1503                         {
1504                                 tx_buf1[0]=0x40;
1505                                 tx_buf1[1]=0x00;
1506                                 tx_buf1[2]=0x00;
1507                                 tx_buf1[3]=0x00;
1508                                 tx_buf1[4]=0x00;
1509                                 tx_buf1[5]=0x95;
1510                                 //printf("CMD0 \n");
1511                                 sif_spi_write_raw(spi, tx_buf1, 6);
1512                                 sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1513                                           //  esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1514              //   ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1515                                 mdelay(100);
1516                                 if(fail_count++ > 10)
1517                                         return -ETIMEDOUT;
1518                         }while( rx_buf1[2] != 0x01 );
1519                         //  }while(1);
1520                  }
1521                 else if( spi_proto_ini_status == 1 )
1522                 {
1523                         tx_buf1[0]=0x45;
1524                         tx_buf1[1]=0x00;
1525                         tx_buf1[2]=0x20;               //0x04;
1526                         tx_buf1[3]=0x00;
1527                         tx_buf1[4]=0x00;
1528                         tx_buf1[5]=0x01;
1529                         //spi_err("CMD 5 1st\n");
1530                         sif_spi_write_raw(spi, tx_buf1, 6);
1531                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1532                                      //  esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1533               //  ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1534                  }
1535                 else if( spi_proto_ini_status == 2 )
1536                 {
1537                         tx_buf1[0]=0x45;
1538                         tx_buf1[1]=0x00;
1539                         tx_buf1[2]=0x20;
1540                         tx_buf1[3]=0x00;
1541                         tx_buf1[4]=0x00;
1542                         tx_buf1[5]=0x01;
1543                         //spi_err("CMD5 2nd\n");
1544                         sif_spi_write_raw(spi, tx_buf1, 6);
1545                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1546                                      //  esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1547              //   ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1548                }
1549                else if( spi_proto_ini_status == 3 )                  //CMD 52   addr 0x2,   data 0x02;
1550                 {
1551                         tx_buf1[0]=0x74;
1552                         tx_buf1[1]=0x80;
1553                         tx_buf1[2]=0x00;
1554                         tx_buf1[3]=0x04;
1555                         tx_buf1[4]=0x02;
1556                         tx_buf1[5]=0x01;
1557                         //spi_err("CMD52 Write  addr 02 \n");
1558                         sif_spi_write_raw(spi, tx_buf1, 6);
1559                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1560                                     //   esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1561              //   ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1562                  }
1563                 else if( spi_proto_ini_status == 4 )
1564                 {
1565                         tx_buf1[0]=0x74;
1566                         tx_buf1[1]=0x80;
1567                         tx_buf1[2]=0x00;
1568                         tx_buf1[3]=0x08;
1569                         tx_buf1[4]=0x03;
1570                         tx_buf1[5]=0x01;
1571                         //spi_err("CMD52 Write  addr 04 \n");
1572                         sif_spi_write_raw(spi, tx_buf1, 6);
1573                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1574                                     //   esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1575               //  ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1576                  }
1577                 else if( spi_proto_ini_status == 5 )
1578                 {
1579                         tx_buf1[0]=0x74;
1580                         tx_buf1[1]=0x00;
1581                         tx_buf1[2]=0x00;
1582                         tx_buf1[3]=0x04;
1583                         tx_buf1[4]=0x00;
1584                         tx_buf1[5]=0x01;
1585                         //spi_err("CMD52 Read  addr 0x2 \n");
1586                         sif_spi_write_raw(spi, tx_buf1, 6);
1587                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1588                                     //   esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1589              //   ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1590
1591                  }
1592                  else if( spi_proto_ini_status == 6 )
1593                 {
1594                         tx_buf1[0]=0x74;
1595                         tx_buf1[1]=0x00;
1596                         tx_buf1[2]=0x00;
1597                         tx_buf1[3]=0x08;
1598                         tx_buf1[4]=0x00;
1599                         tx_buf1[5]=0x01;
1600                         //spi_err("CMD52 Read addr 0x4 \n");
1601                         sif_spi_write_raw(spi, tx_buf1, 6);
1602                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1603                                      //  esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1604               //  ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1605                  }
1606                  else if (spi_proto_ini_status>6 && spi_proto_ini_status<15)
1607                 {
1608                         tx_buf1[0]=0x74;
1609                         tx_buf1[1]=0x10;
1610                         tx_buf1[2]=0x00;
1611                         tx_buf1[3]=0xF0+2*(spi_proto_ini_status-7);
1612                         tx_buf1[4]=0x00;
1613                         tx_buf1[5]=0x01;
1614                         sif_spi_write_raw(spi, tx_buf1, 6);
1615                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1616                                     //   esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1617             //    ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1618                  }
1619                 else if (spi_proto_ini_status==15)
1620                 {
1621                         //spi_err("CMD52 Write  Reg addr 0x110 \n");
1622                         tx_buf1[0]=0x74;
1623                         tx_buf1[1]=0x80;              //func0 should be
1624                         tx_buf1[2]=0x02;
1625                         tx_buf1[3]=0x20;
1626                         tx_buf1[4]=(unsigned char)(SPI_BLOCK_SIZE & 0xff);                       //0x02;
1627                         tx_buf1[5]=0x01;
1628                         sif_spi_write_raw(spi, tx_buf1, 6);
1629                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1630                                     //   esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1631               //  ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1632
1633                         //spi_err("CMD52 Write Reg addr 0x111 \n");
1634                         tx_buf1[0]=0x74;
1635                         tx_buf1[1]=0x80;
1636                         tx_buf1[2]=0x02;
1637                         tx_buf1[3]=0x22;
1638                         tx_buf1[4]=(unsigned char)(SPI_BLOCK_SIZE>>8);                      //0x00;
1639                         tx_buf1[5]=0x01;
1640                         sif_spi_write_raw(spi, tx_buf1, 6);
1641                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1642                                     //   esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1643               //  ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1644
1645                         //spi_err("CMD52 Write Reg addr 0x111 \n");   /* set boot mode */
1646                         tx_buf1[0]=0x74;
1647                         tx_buf1[1]=0x80;
1648                         tx_buf1[2]=0x41;
1649                         tx_buf1[3]=0xe0;
1650                         tx_buf1[4]=0x01;          //0x00;
1651                         tx_buf1[5]=0x01;
1652                         sif_spi_write_raw(spi, tx_buf1, 6);
1653                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1654                                        esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1655                 ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1656
1657                 }
1658                 else if (spi_proto_ini_status==16)
1659                 {
1660 #if 0
1661                         //printf("CMD52 Write  Reg addr 0x40 \n");
1662                         tx_buf1[0]=0x74;
1663                         tx_buf1[1]=0x90;
1664                         tx_buf1[2]=0x00;
1665                         tx_buf1[3]=0x80;
1666                         tx_buf1[4]=0x91;                       //0x02;
1667                         tx_buf1[5]=0x01;
1668                         sif_spi_write_raw(spi, tx_buf1, 6);
1669                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1670                 esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1671                 ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1672
1673                         //sif_spi_read_bytes( 0x0c,rx_buf1, 4);
1674
1675                         //printf("CMD52 Write  Reg addr 0x3c \n");
1676                         tx_buf1[0]=0x74;
1677                         tx_buf1[1]=0x90;
1678                         tx_buf1[2]=0x00;
1679                         tx_buf1[3]=0x78;
1680                         tx_buf1[4]=0x3f;
1681                         tx_buf1[5]=0x01;
1682                         sif_spi_write_raw(spi, tx_buf1, 6);
1683                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1684                         esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1685                 ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1686
1687                                                                 //printf("CMD52 Write  Reg addr 0x3d \n");
1688                         tx_buf1[0]=0x74;
1689                         tx_buf1[1]=0x90;
1690                         tx_buf1[2]=0x00;
1691                         tx_buf1[3]=0x7a;
1692                         tx_buf1[4]=0x34;                        //0x02;
1693                         tx_buf1[5]=0x01;
1694                         sif_spi_write_raw(spi, tx_buf1, 6);
1695                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1696                         esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1697                 ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1698
1699                                                                // printf("CMD52 Write  Reg addr 0x3e \n");
1700                         tx_buf1[0]=0x74;
1701                         tx_buf1[1]=0x90;
1702                         tx_buf1[2]=0x00;
1703                         tx_buf1[3]=0x7c;
1704                         tx_buf1[4]=0xfe;                       //0x02;
1705                         tx_buf1[5]=0x01;
1706                         sif_spi_write_raw(spi, tx_buf1, 6);
1707                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1708                         esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1709                 ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1710
1711                                                                 //printf("CMD52 Write  Reg addr 0x3f \n");
1712                         tx_buf1[0]=0x74;
1713                         tx_buf1[1]=0x90;
1714                         tx_buf1[2]=0x00;
1715                         tx_buf1[3]=0x7e;
1716                         tx_buf1[4]=0x00;                       //0x02;
1717                         tx_buf1[5]=0x01;
1718                         sif_spi_write_raw(spi, tx_buf1, 6);
1719                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1720                         esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1721                 ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1722
1723                                                                 //printf("CMD52 Write  Reg addr 0x40 \n");
1724                         tx_buf1[0]=0x74;
1725                         tx_buf1[1]=0x90;
1726                         tx_buf1[2]=0x00;
1727                         tx_buf1[3]=0x80;
1728                         tx_buf1[4]=0xd1;                      //0x02;
1729                         tx_buf1[5]=0x01;
1730                         sif_spi_write_raw(spi, tx_buf1, 6);
1731                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1732                         esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1733                 ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1734
1735                         tx_buf1[0]=0x74;
1736                         tx_buf1[1]=0x90;
1737                         tx_buf1[2]=0x00;
1738                         tx_buf1[3]=0x52;
1739                         tx_buf1[4]=0x30;                      //0x02;
1740                         tx_buf1[5]=0x01;
1741                         sif_spi_write_raw(spi, tx_buf1, 6);
1742                         sif_spi_write_async_read(spi,dummy_tx_buf, rx_buf1,10);
1743                         esp_dbg(ESP_DBG_ERROR, "rx:[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x],[0x%02x]\n", rx_buf1[0],rx_buf1[1]
1744                 ,rx_buf1[2],rx_buf1[3],rx_buf1[4],rx_buf1[5],rx_buf1[6],rx_buf1[7],rx_buf1[8],rx_buf1[9]);
1745
1746 #endif
1747                 }
1748                 else
1749                 {
1750                         break;
1751                }
1752                                             //  mdelay(500);
1753                    spi_proto_ini_status++;
1754         } while (1);
1755         return 0;
1756 }
1757
1758 static int spi_irq_thread(void *data)
1759 {
1760         struct spi_device *spi = (struct spi_device *)data;
1761
1762         do {
1763                 sif_dsr(spi);
1764
1765                 set_current_state(TASK_INTERRUPTIBLE);
1766                 sif_platform_irq_mask(0);
1767
1768                 if (!kthread_should_stop())
1769                         schedule();
1770
1771                 set_current_state(TASK_RUNNING);
1772
1773         } while (!kthread_should_stop());
1774         return 0;
1775 }
1776
1777 int sif_setup_irq_thread(struct spi_device *spi)
1778 {
1779         sif_irq_thread = kthread_run(spi_irq_thread, spi, "kspiirqd/eagle");
1780         if (IS_ERR(sif_irq_thread)) {
1781                 esp_dbg(ESP_DBG_ERROR, "setup irq thread error!\n");
1782                 return -1;
1783         }
1784         return 0;
1785 }
1786
1787 static irqreturn_t sif_irq_handler(int irq, void *dev_id)
1788 {
1789         sif_platform_irq_mask(1);
1790
1791         if (sif_platform_is_irq_occur()) {
1792                 wake_up_process(sif_irq_thread);
1793         } else {
1794                 sif_platform_irq_mask(0);
1795                 return IRQ_NONE;
1796         }
1797
1798         return IRQ_HANDLED;
1799 }
1800
1801 void sif_enable_irq(struct esp_pub *epub)
1802 {
1803         int err;
1804         struct esp_spi_ctrl *sctrl = NULL;
1805         struct spi_device *spi = NULL;
1806
1807         if (epub == NULL) {
1808                 ESSERT(0);
1809                 return;
1810         }
1811         sctrl = (struct esp_spi_ctrl *)epub->sif;
1812         spi = sctrl->spi;
1813         if (spi == NULL) {
1814                 ESSERT(0);
1815                 return;
1816         }
1817
1818         mdelay(100);
1819
1820         sif_platform_irq_init();
1821         err = sif_setup_irq_thread(spi);
1822         if (err) {
1823                 esp_dbg(ESP_DBG_ERROR, "%s setup sif irq failed\n", __func__);
1824                 return;
1825         }
1826
1827 /******************compat with other device in some shared irq system ********************/
1828
1829 #ifdef  REQUEST_IRQ_SHARED
1830 #if   defined(REQUEST_IRQ_RISING)
1831         err = request_irq(sif_platform_get_irq_no(), sif_irq_handler, IRQF_TRIGGER_RISING | IRQF_SHARED, "esp_spi_irq", spi);
1832 #elif defined(REQUEST_IRQ_FALLING)
1833         err = request_irq(sif_platform_get_irq_no(), sif_irq_handler, IRQF_TRIGGER_FALLING | IRQF_SHARED, "esp_spi_irq", spi);
1834 #elif defined(REQUEST_IRQ_LOWLEVEL)
1835         err = request_irq(sif_platform_get_irq_no(), sif_irq_handler, IRQF_TRIGGER_LOW | IRQF_SHARED, "esp_spi_irq", spi);
1836 #elif defined(REQUEST_IRQ_HIGHLEVEL)
1837         err = request_irq(sif_platform_get_irq_no(), sif_irq_handler, IRQF_TRIGGER_HIGH | IRQF_SHARED, "esp_spi_irq", spi);
1838 #else   /* default */
1839         err = request_irq(sif_platform_get_irq_no(), sif_irq_handler, IRQF_TRIGGER_LOW | IRQF_SHARED, "esp_spi_irq", spi);
1840 #endif /* TRIGGER MODE */
1841 #else
1842         err = request_irq(sif_platform_get_irq_no(), sif_irq_handler, IRQF_TRIGGER_LOW, "esp_spi_irq", spi);
1843 #endif /* ESP_IRQ_SHARED */
1844
1845         if (err) {
1846                 esp_dbg(ESP_DBG_ERROR, "sif %s failed\n", __func__);
1847                 return ;
1848         }
1849 #ifdef IRQ_WAKE_HOST
1850         enable_irq_wake(sif_platform_get_irq_no());
1851 #endif
1852         atomic_set(&sctrl->irq_installed, 1);
1853 }
1854
1855 void sif_disable_irq(struct esp_pub *epub)
1856 {
1857         int i = 0;
1858         struct esp_spi_ctrl *sctrl = NULL;
1859         struct spi_device *spi = NULL;
1860
1861         if (epub == NULL) {
1862                 ESSERT(0);
1863                 return;
1864         }
1865         sctrl = (struct esp_spi_ctrl *)epub->sif;
1866         spi = sctrl->spi;
1867         if (spi == NULL) {
1868                 ESSERT(0);
1869                 return;
1870         }
1871
1872         if (atomic_read(&sctrl->irq_installed) == 0)
1873                 return;
1874
1875         while (atomic_read(&sctrl->irq_handling)) {
1876                 schedule_timeout(HZ / 100);
1877                 if (i++ >= 400) {
1878                         esp_dbg(ESP_DBG_ERROR, "%s force to stop irq\n", __func__);
1879                         break;
1880                 }
1881         }
1882
1883         free_irq(sif_platform_get_irq_no(), spi);
1884         kthread_stop(sif_irq_thread);
1885
1886         sif_platform_irq_deinit();
1887
1888         atomic_set(&sctrl->irq_installed, 0);
1889 }
1890
1891
1892 int esp_setup_spi(struct spi_device *spi)
1893 {
1894 #ifndef ESP_PREALLOC
1895         int retry = 10;
1896 #endif
1897         /**** alloc buffer for spi io */
1898         if (sif_sdio_state == ESP_SDIO_STATE_FIRST_INIT) {
1899 #ifdef ESP_PREALLOC
1900                 if ((buf_addr = esp_get_lspi_buf()) == NULL)
1901                         goto _err_buf_addr;
1902 #else
1903                 while ((buf_addr = (unsigned char *)kmalloc (MAX_BUF_SIZE, GFP_KERNEL)) == NULL) {
1904                                 if (--retry < 0)
1905                                         goto _err_buf_addr;
1906                 }
1907 #endif
1908                 if ((check_buf = (unsigned char *)kmalloc (256, GFP_KERNEL)) == NULL)
1909                                         goto _err_check_buf;
1910
1911                 if ((ff_buf = (unsigned char *)kmalloc (256, GFP_KERNEL)) == NULL)
1912                                         goto _err_ff_buf;
1913
1914                 memset(ff_buf,0xff,256);
1915
1916                 tx_cmd = buf_addr;
1917                 rx_cmd = buf_addr;
1918         }
1919         spi_resp.max_dataW_resp_size = 0;
1920         spi_resp.max_dataR_resp_size = 0;
1921         spi_resp.max_block_dataW_resp_size = 0;
1922         spi_resp.max_block_dataR_resp_size = 0;
1923         spi_resp.max_cmd_resp_size = 0;
1924         if( sif_get_ate_config() != 5)
1925         {
1926                 spi_resp.data_resp_size_w = DATA_RESP_SIZE_W;
1927                 spi_resp.data_resp_size_r = DATA_RESP_SIZE_R;
1928                 spi_resp.block_w_data_resp_size_final = BLOCK_W_DATA_RESP_SIZE_FINAL;
1929                 spi_resp.block_r_data_resp_size_final = BLOCK_R_DATA_RESP_SIZE_1ST;
1930         } else {
1931                 spi_resp.data_resp_size_w = 1000;
1932                 spi_resp.data_resp_size_r = 1000;
1933                 spi_resp.block_w_data_resp_size_final = 1000;
1934                 spi_resp.block_r_data_resp_size_final = 1000;
1935         }
1936
1937         return 0;
1938
1939 _err_ff_buf:
1940         if (check_buf) {
1941                 kfree(check_buf);
1942                 check_buf = NULL;
1943         }
1944 _err_check_buf:
1945         if (buf_addr) {
1946 #ifdef ESP_PREALLOC
1947                 esp_put_lspi_buf(&buf_addr);
1948 #else
1949                 kfree(buf_addr);
1950 #endif
1951                 buf_addr = NULL;
1952         }
1953 _err_buf_addr:
1954         return -ENOMEM;
1955 }
1956
1957
1958 static int esp_spi_probe(struct spi_device *spi);
1959 static int esp_spi_remove(struct spi_device *spi);
1960
1961 static int esp_spi_probe(struct spi_device *spi)
1962 {
1963         int err;
1964         struct esp_pub *epub;
1965         struct esp_spi_ctrl *sctrl;
1966
1967         esp_dbg(ESP_DBG_ERROR, "%s enter\n", __func__);
1968
1969         err = esp_setup_spi(spi);
1970         if (err) {
1971                 esp_dbg(ESP_DBG_ERROR, "%s setup_spi error[%d]\n", __func__, err);
1972                 if(sif_sdio_state == ESP_SDIO_STATE_FIRST_INIT)
1973                         goto _err_spi;
1974                 else
1975                         goto _err_second_init;
1976         }
1977         esp_dbg(ESP_DBG_ERROR, "%s init_protocol\n", __func__);
1978         err = sif_spi_protocol_init(spi);
1979         if(err){
1980                 if(sif_sdio_state == ESP_SDIO_STATE_FIRST_INIT)
1981                         goto _err_spi;
1982                 else
1983                         goto _err_second_init;
1984         }
1985
1986         if(sif_sdio_state == ESP_SDIO_STATE_FIRST_INIT){
1987                 sctrl = kzalloc(sizeof(struct esp_spi_ctrl), GFP_KERNEL);
1988
1989                 if (sctrl == NULL) {
1990                         err = -ENOMEM;
1991                         goto _err_spi;
1992                 }
1993
1994                 /* temp buffer reserved for un-dma-able request */
1995                 sctrl->dma_buffer = kzalloc(ESP_DMA_IBUFSZ, GFP_KERNEL);
1996
1997                 if (sctrl->dma_buffer == NULL) {
1998                         err = -ENOMEM;
1999                         goto _err_last;
2000                 }
2001                 sif_sctrl = sctrl;
2002                 sctrl->slc_blk_sz = SIF_SLC_BLOCK_SIZE;
2003
2004                 epub = esp_pub_alloc_mac80211(&spi->dev);
2005
2006                 if (epub == NULL) {
2007                         esp_dbg(ESP_DBG_ERROR, "no mem for epub \n");
2008                         err = -ENOMEM;
2009                         goto _err_dma;
2010                 }
2011                 epub->sif = (void *)sctrl;
2012                 sctrl->epub = epub;
2013
2014 #ifdef USE_EXT_GPIO
2015                 if (sif_get_ate_config() == 0) {
2016                         err = ext_gpio_init(epub);
2017                         if (err) {
2018                                 esp_dbg(ESP_DBG_ERROR, "ext_irq_work_init failed %d\n", err);
2019                                 goto _err_epub;
2020                         }
2021                 }
2022 #endif
2023         } else {
2024                 sctrl = sif_sctrl;
2025                 sif_sctrl = NULL;
2026                 epub = sctrl->epub;
2027                 SET_IEEE80211_DEV(epub->hw, &spi->dev);
2028                 epub->dev = &spi->dev;
2029         }
2030
2031         epub->sdio_state = sif_sdio_state;
2032
2033         sctrl->spi = spi;
2034         spi_set_drvdata(spi, sctrl);
2035
2036         if (err){
2037                 if(sif_sdio_state == ESP_SDIO_STATE_FIRST_INIT)
2038                         goto _err_ext_gpio;
2039                 else
2040                         goto _err_second_init;
2041         }
2042         check_target_id(epub);
2043
2044         err = esp_pub_init_all(epub);
2045
2046         if (err) {
2047                 esp_dbg(ESP_DBG_ERROR, "esp_init_all failed: %d\n", err);
2048                 if(sif_sdio_state == ESP_SDIO_STATE_FIRST_INIT){
2049                         err = 0;
2050                         goto _err_first_init;
2051                 }
2052                 if(sif_sdio_state == ESP_SDIO_STATE_SECOND_INIT)
2053                         goto _err_second_init;
2054         }
2055
2056         esp_dbg(ESP_DBG_TRACE, " %s return  %d\n", __func__, err);
2057         if(sif_sdio_state == ESP_SDIO_STATE_FIRST_INIT){
2058                 esp_dbg(ESP_DBG_ERROR, "first normal exit\n");
2059                 sif_sdio_state = ESP_SDIO_STATE_FIRST_NORMAL_EXIT;
2060                 up(&esp_powerup_sem);
2061         }
2062
2063         return err;
2064 _err_ext_gpio:
2065 #ifdef USE_EXT_GPIO
2066         if (sif_get_ate_config() == 0)
2067                 ext_gpio_deinit();
2068 _err_epub:
2069 #endif
2070         esp_pub_dealloc_mac80211(epub);
2071 _err_dma:
2072         kfree(sctrl->dma_buffer);
2073 _err_last:
2074         kfree(sctrl);
2075 _err_spi:
2076         if (buf_addr) {
2077 #ifdef ESP_PREALLOC
2078                 esp_put_lspi_buf(&buf_addr);
2079 #else
2080                 kfree(buf_addr);
2081 #endif
2082                 buf_addr = NULL;
2083                 tx_cmd = NULL;
2084                 rx_cmd = NULL;
2085         }
2086         if (check_buf) {
2087                 kfree(check_buf);
2088                 check_buf = NULL;
2089         }
2090         if (ff_buf) {
2091                 kfree(ff_buf);
2092                 ff_buf = NULL;
2093         }
2094
2095 _err_first_init:
2096         if(sif_sdio_state == ESP_SDIO_STATE_FIRST_INIT){
2097                 esp_dbg(ESP_DBG_ERROR, "first error exit\n");
2098                 sif_sdio_state = ESP_SDIO_STATE_FIRST_ERROR_EXIT;
2099                 up(&esp_powerup_sem);
2100         }
2101         return err;
2102 _err_second_init:
2103         sif_sdio_state = ESP_SDIO_STATE_SECOND_ERROR_EXIT;
2104         esp_spi_remove(spi);
2105         return err;
2106 }
2107
2108 static int esp_spi_remove(struct spi_device *spi)
2109 {
2110         struct esp_spi_ctrl *sctrl = NULL;
2111
2112         esp_dbg(ESP_SHOW, "%s \n", __func__);
2113
2114         sctrl = spi_get_drvdata(spi);
2115
2116         if (sctrl == NULL) {
2117                 esp_dbg(ESP_DBG_ERROR, "%s no sctrl\n", __func__);
2118                 return -EINVAL;
2119         }
2120
2121         do {
2122                 if (sctrl->epub == NULL) {
2123                         esp_dbg(ESP_DBG_ERROR, "%s epub null\n", __func__);
2124                         break;
2125                 }
2126                 sctrl->epub->sdio_state = sif_sdio_state;
2127                 if(sif_sdio_state != ESP_SDIO_STATE_FIRST_NORMAL_EXIT){
2128                         if (sctrl->epub->sip) {
2129                                 sip_detach(sctrl->epub->sip);
2130                                 sctrl->epub->sip = NULL;
2131                                 esp_dbg(ESP_DBG_TRACE, "%s sip detached \n", __func__);
2132                         }
2133 #ifdef USE_EXT_GPIO
2134                         if (sif_get_ate_config() == 0)
2135                                 ext_gpio_deinit();
2136 #endif
2137                 } else {
2138                         //sif_disable_target_interrupt(sctrl->epub);
2139                         atomic_set(&sctrl->epub->sip->state, SIP_STOP);
2140                         sif_disable_irq(sctrl->epub);
2141                 }
2142
2143 #ifdef TEST_MODE
2144                 test_exit_netlink();
2145 #endif /* TEST_MODE */
2146                 if(sif_sdio_state != ESP_SDIO_STATE_FIRST_NORMAL_EXIT){
2147                         esp_pub_dealloc_mac80211(sctrl->epub);
2148                         esp_dbg(ESP_DBG_TRACE, "%s dealloc mac80211 \n", __func__);
2149
2150                         if (sctrl->dma_buffer) {
2151                                 kfree(sctrl->dma_buffer);
2152                                 sctrl->dma_buffer = NULL;
2153                                 esp_dbg(ESP_DBG_TRACE, "%s free dma_buffer \n", __func__);
2154                         }
2155
2156                         kfree(sctrl);
2157
2158                         if (buf_addr) {
2159 #ifdef ESP_PREALLOC
2160                                 esp_put_lspi_buf(&buf_addr);
2161 #else
2162                                 kfree(buf_addr);
2163 #endif
2164                                 buf_addr = NULL;
2165                                 rx_cmd = NULL;
2166                                 tx_cmd = NULL;
2167                         }
2168
2169                         if (check_buf) {
2170                                 kfree(check_buf);
2171                                 check_buf = NULL;
2172                         }
2173
2174                         if (ff_buf) {
2175                                 kfree(ff_buf);
2176                                 ff_buf = NULL;
2177                         }
2178
2179                 }
2180
2181         } while (0);
2182
2183         spi_set_drvdata(spi,NULL);
2184
2185         esp_dbg(ESP_DBG_TRACE, "eagle spi remove complete\n");
2186
2187         return 0;
2188 }
2189
2190 static int esp_spi_suspend(struct device *dev)
2191 {
2192         struct spi_device *spi = to_spi_device(dev);
2193         struct esp_spi_ctrl *sctrl = spi_get_drvdata(spi);
2194         struct esp_pub *epub = sctrl->epub;
2195
2196         printk("%s", __func__);
2197 #if 0
2198         sip_send_suspend_config(epub, 1);
2199 #endif
2200         atomic_set(&epub->ps.state, ESP_PM_ON);
2201         return 0;
2202 }
2203
2204 static int esp_spi_resume(struct device *dev)
2205 {
2206         esp_dbg(ESP_DBG_ERROR, "%s", __func__);
2207
2208         return 0;
2209 }
2210
2211 static const struct dev_pm_ops esp_spi_pm_ops = {
2212         .suspend= esp_spi_suspend,
2213         .resume= esp_spi_resume,
2214 };
2215
2216 extern struct spi_device_id esp_spi_id[];
2217
2218 struct spi_driver esp_spi_driver = {
2219         .id_table = esp_spi_id,
2220         .driver = {
2221                 .name   = "eagle",
2222                 .bus    = &spi_bus_type,
2223                 .owner  = THIS_MODULE,
2224                 .pm = &esp_spi_pm_ops,
2225         },
2226         .probe  = esp_spi_probe,
2227         .remove = esp_spi_remove,
2228 };
2229
2230 static int esp_spi_dummy_probe(struct spi_device *spi)
2231 {
2232         esp_dbg(ESP_DBG_ERROR, "%s enter\n", __func__);
2233
2234         up(&esp_powerup_sem);
2235
2236         return 0;
2237 }
2238
2239 static int esp_spi_dummy_remove(struct spi_device *spi)
2240 {
2241         return 0;
2242 }
2243
2244 struct spi_driver esp_spi_dummy_driver = {
2245         .id_table = esp_spi_id,
2246         .driver = {
2247                 .name   = "eagle_dummy",
2248                 .bus    = &spi_bus_type,
2249                 .owner  = THIS_MODULE,
2250         },
2251         .probe  = esp_spi_dummy_probe,
2252         .remove = esp_spi_dummy_remove,
2253 };
2254
2255 static int __init esp_spi_init(void)
2256 {
2257 #define ESP_WAIT_UP_TIME_MS 11000
2258         int err;
2259         u64 ver;
2260         int retry = 3;
2261         bool powerup = false;
2262         int edf_ret = 0;
2263
2264         esp_dbg(ESP_DBG_TRACE, "%s \n", __func__);
2265
2266 #ifdef REGISTER_SPI_BOARD_INFO
2267         sif_platform_register_board_info();
2268 #endif
2269
2270 #ifdef DRIVER_VER
2271         ver = DRIVER_VER;
2272         esp_dbg(ESP_SHOW, "\n*****%s %s EAGLE DRIVER VER:%llx*****\n\n", __DATE__, __TIME__, ver);
2273 #endif
2274         edf_ret = esp_debugfs_init();
2275
2276         request_init_conf();
2277
2278         esp_wakelock_init();
2279         esp_wake_lock();
2280
2281         do {
2282                 sema_init(&esp_powerup_sem, 0);
2283
2284                 sif_platform_target_poweron();
2285
2286                 err = spi_register_driver(&esp_spi_dummy_driver);
2287                 if (err) {
2288                         esp_dbg(ESP_DBG_ERROR, "eagle spi driver registration failed, error code: %d\n", err);
2289                         goto _fail;
2290                 }
2291
2292                 if (down_timeout(&esp_powerup_sem,
2293                                  msecs_to_jiffies(ESP_WAIT_UP_TIME_MS)) == 0)
2294                 {
2295
2296                         powerup = true;
2297                         msleep(200);
2298                         break;
2299                 }
2300
2301                 esp_dbg(ESP_SHOW, "%s ------ RETRY ------ \n", __func__);
2302
2303                 sif_record_retry_config();
2304
2305                 spi_unregister_driver(&esp_spi_dummy_driver);
2306
2307                 sif_platform_target_poweroff();
2308
2309         } while (retry--);
2310
2311         if (!powerup) {
2312                 esp_dbg(ESP_DBG_ERROR, "eagle spi can not power up!\n");
2313
2314                 err = -ENODEV;
2315                 goto _fail;
2316         }
2317
2318         esp_dbg(ESP_SHOW, "%s power up OK\n", __func__);
2319
2320         spi_unregister_driver(&esp_spi_dummy_driver);
2321
2322         sif_sdio_state = ESP_SDIO_STATE_FIRST_INIT;
2323         sema_init(&esp_powerup_sem, 0);
2324
2325         spi_register_driver(&esp_spi_driver);
2326
2327         if (down_timeout(&esp_powerup_sem,
2328                                  msecs_to_jiffies(ESP_WAIT_UP_TIME_MS)) == 0 && sif_get_ate_config() == 0) {
2329                 if(sif_sdio_state == ESP_SDIO_STATE_FIRST_NORMAL_EXIT){
2330                         spi_unregister_driver(&esp_spi_driver);
2331
2332                         msleep(100);
2333
2334                         sif_sdio_state = ESP_SDIO_STATE_SECOND_INIT;
2335
2336                         spi_register_driver(&esp_spi_driver);
2337                 }
2338
2339         }
2340
2341         esp_register_early_suspend();
2342         esp_wake_unlock();
2343 #ifdef REQUEST_RTC_IRQ
2344         request_rtc_irq();
2345 #endif
2346         return err;
2347
2348 _fail:
2349         esp_wake_unlock();
2350         esp_wakelock_destroy();
2351
2352         return err;
2353 }
2354
2355 static void __exit esp_spi_exit(void)
2356 {
2357         esp_dbg(ESP_SHOW, "%s \n", __func__);
2358
2359         esp_debugfs_exit();
2360
2361         esp_unregister_early_suspend();
2362
2363         spi_unregister_driver(&esp_spi_driver);
2364
2365 #ifndef FPGA_DEBUG
2366         sif_platform_target_poweroff();
2367 #endif /* !FPGA_DEBUG */
2368
2369         esp_wakelock_destroy();
2370 }
2371
2372 MODULE_AUTHOR("Espressif System");
2373 MODULE_DESCRIPTION("Driver for SPI interconnected eagle low-power WLAN devices");
2374 MODULE_LICENSE("GPL");
2375 #endif /* ESP_USE_SPI */