2 ** $Id: //Department/DaVinci/TRUNK/MT6620_5931_WiFi_Driver/include/nic/mt6628_reg.h#2 $
5 /*! \file "mt6628_reg.h"
6 \brief The common register definition of mt5931
14 ** $Log: mt6628_reg.h $
16 ** 09 12 2012 wcpadmin
17 ** [ALPS00276400] Remove MTK copyright and legal header on GPL/LGPL related packages
21 * [WCXRP00000851] [MT6628 Wi-Fi][Driver] Add HIFSYS related definition to driver source tree
22 * add MT6628-specific definitions.
25 * [WCXRP00000851] [MT6628 Wi-Fi][Driver] Add HIFSYS related definition to driver source tree
26 * add initial version for MT6628 driver support.
33 /*******************************************************************************
34 * C O M P I L E R F L A G S
35 ********************************************************************************
38 /*******************************************************************************
39 * E X T E R N A L R E F E R E N C E S
40 ********************************************************************************
43 /*******************************************************************************
45 ********************************************************************************
48 /*******************************************************************************
50 ********************************************************************************
54 /*******************************************************************************
56 ********************************************************************************
59 /*******************************************************************************
60 * P R I V A T E D A T A
61 ********************************************************************************
64 /*******************************************************************************
66 ********************************************************************************
69 /*******************************************************************************
70 * F U N C T I O N D E C L A R A T I O N S
71 ********************************************************************************
74 /*******************************************************************************
76 ********************************************************************************
79 //1 MT6628 MCR Definition
84 #define MCR_WCIR 0x0000
86 //4 HIF Low Power Control Register
87 #define MCR_WHLPCR 0x0004
89 //4 Control Status Register
90 #define MCR_WSDIOCSR 0x0008
91 #define MCR_WSPICSR 0x0008
93 //4 HIF Control Register
94 #define MCR_WHCR 0x000C
96 //4 HIF Interrupt Status Register
97 #define MCR_WHISR 0x0010
99 //4 HIF Interrupt Enable Register
100 #define MCR_WHIER 0x0014
102 //4 Abnormal Status Register
103 #define MCR_WASR 0x0018
105 //4 WLAN Software Interrupt Control Register
106 #define MCR_WSICR 0x001C
108 //4 WLAN TX Status Register
109 #define MCR_WTSR0 0x0020
111 //4 WLAN TX Status Register
112 #define MCR_WTSR1 0x0024
114 //4 WLAN TX Data Register 0
115 #define MCR_WTDR0 0x0028
117 //4 WLAN TX Data Register 1
118 #define MCR_WTDR1 0x002C
120 //4 WLAN RX Data Register 0
121 #define MCR_WRDR0 0x0030
123 //4 WLAN RX Data Register 1
124 #define MCR_WRDR1 0x0034
126 //4 Host to Device Send Mailbox 0 Register
127 #define MCR_H2DSM0R 0x0038
129 //4 Host to Device Send Mailbox 1 Register
130 #define MCR_H2DSM1R 0x003c
132 //4 Device to Host Receive Mailbox 0 Register
133 #define MCR_D2HRM0R 0x0040
135 //4 Device to Host Receive Mailbox 1 Register
136 #define MCR_D2HRM1R 0x0044
138 //4 Device to Host Receive Mailbox 2 Register
139 #define MCR_D2HRM2R 0x0048
141 //4 WLAN RX Packet Length Register
142 #define MCR_WRPLR 0x0050
145 //#if CFG_SDIO_INTR_ENHANCE
146 typedef struct _ENHANCE_MODE_DATA_STRUCT_T {
162 UINT_16 u2NumValidRx0Len;
163 UINT_16 u2NumValidRx1Len;
164 UINT_16 au2Rx0Len[16];
165 UINT_16 au2Rx1Len[16];
167 UINT_32 au4RxStatusRaw[17];
169 UINT_32 u4RcvMailbox0;
170 UINT_32 u4RcvMailbox1;
171 } ENHANCE_MODE_DATA_STRUCT_T, *P_ENHANCE_MODE_DATA_STRUCT_T;
172 // #endif /* ENHANCE_MODE_DATA_STRUCT_T */
175 //2 Definition in each register
177 #define WCIR_WLAN_READY BIT(21)
178 #define WCIR_POR_INDICATOR BIT(20)
179 #define WCIR_REVISION_ID BITS(16,19)
180 #define WCIR_CHIP_ID BITS(0,15)
182 #define MTK_CHIP_REV 0x00006628
183 #define MTK_CHIP_MP_REVERSION_ID 0x0
186 #define WHLPCR_FW_OWN_REQ_CLR BIT(9)
187 #define WHLPCR_FW_OWN_REQ_SET BIT(8)
188 #define WHLPCR_IS_DRIVER_OWN BIT(8)
189 #define WHLPCR_INT_EN_CLR BIT(1)
190 #define WHLPCR_INT_EN_SET BIT(0)
193 #define WSDIOCSR_SDIO_RE_INIT_EN BIT(0)
196 #define WCSR_SPI_MODE_SEL BITS(3,4)
197 #define WCSR_SPI_ENDIAN_BIG BIT(2)
198 #define WCSR_SPI_INT_OUT_MODE BIT(1)
199 #define WCSR_SPI_DATA_OUT_MODE BIT(0)
202 #define WHCR_RX_ENHANCE_MODE_EN BIT(16)
203 #define WHCR_MAX_HIF_RX_LEN_NUM BITS(4,7)
204 #define WHCR_W_MAILBOX_RD_CLR_EN BIT(2)
205 #define WHCR_W_INT_CLR_CTRL BIT(1)
206 #define WHCR_MCU_DBG_EN BIT(0)
207 #define WHCR_OFFSET_MAX_HIF_RX_LEN_NUM 4
210 #define WHISR_D2H_SW_INT BITS(8,31)
211 #define WHISR_D2H_SW_ASSERT_INFO_INT BIT(31)
212 #define WHISR_FW_OWN_BACK_INT BIT(4)
213 #define WHISR_ABNORMAL_INT BIT(3)
214 #define WHISR_RX1_DONE_INT BIT(2)
215 #define WHISR_RX0_DONE_INT BIT(1)
216 #define WHISR_TX_DONE_INT BIT(0)
220 #define WHIER_D2H_SW_INT BITS(8,31)
221 #define WHIER_FW_OWN_BACK_INT_EN BIT(4)
222 #define WHIER_ABNORMAL_INT_EN BIT(3)
223 #define WHIER_RX1_DONE_INT_EN BIT(2)
224 #define WHIER_RX0_DONE_INT_EN BIT(1)
225 #define WHIER_TX_DONE_INT_EN BIT(0)
226 #define WHIER_DEFAULT (WHIER_RX0_DONE_INT_EN | \
227 WHIER_RX1_DONE_INT_EN | \
228 WHIER_TX_DONE_INT_EN | \
229 WHIER_ABNORMAL_INT_EN | \
235 #define WASR_FW_OWN_INVALID_ACCESS BIT(4)
236 #define WASR_RX1_UNDER_FLOW BIT(3)
237 #define WASR_RX0_UNDER_FLOW BIT(2)
238 #define WASR_TX1_OVER_FLOW BIT(1)
239 #define WASR_TX0_OVER_FLOW BIT(0)
243 #define WSICR_H2D_SW_INT_SET BITS(16,31)
247 #define WRPLR_RX1_PACKET_LENGTH BITS(16,31)
248 #define WRPLR_RX0_PACKET_LENGTH BITS(0,15)
251 #endif /* _MT6628_REG_H */