drivers/net/wireless/rkwifi/bcmdhd/include/sbconfig.h

   1 /*
   2  * Broadcom SiliconBackplane hardware register definitions.
   3  *
   4  * $Copyright Open Broadcom Corporation$
   5  *
   6  * $Id: sbconfig.h 241182 2011-02-17 21:50:03Z $
   7  */
   8
   9 #ifndef _SBCONFIG_H
  10 #define _SBCONFIG_H
  11
  12
  13 #ifndef PAD
  14 #define _PADLINE(line)  pad ## line
  15 #define _XSTR(line)     _PADLINE(line)
  16 #define PAD             _XSTR(__LINE__)
  17 #endif
  18
  19
  20 #define SB_BUS_SIZE             0x10000
  21 #define SB_BUS_BASE(b)          (SI_ENUM_BASE + (b) * SB_BUS_SIZE)
  22 #define SB_BUS_MAXCORES         (SB_BUS_SIZE / SI_CORE_SIZE)
  23
  24
  25 #define SBCONFIGOFF             0xf00
  26 #define SBCONFIGSIZE            256
  27
  28 #define SBIPSFLAG               0x08
  29 #define SBTPSFLAG               0x18
  30 #define SBTMERRLOGA             0x48
  31 #define SBTMERRLOG              0x50
  32 #define SBADMATCH3              0x60
  33 #define SBADMATCH2              0x68
  34 #define SBADMATCH1              0x70
  35 #define SBIMSTATE               0x90
  36 #define SBINTVEC                0x94
  37 #define SBTMSTATELOW            0x98
  38 #define SBTMSTATEHIGH           0x9c
  39 #define SBBWA0                  0xa0
  40 #define SBIMCONFIGLOW           0xa8
  41 #define SBIMCONFIGHIGH          0xac
  42 #define SBADMATCH0              0xb0
  43 #define SBTMCONFIGLOW           0xb8
  44 #define SBTMCONFIGHIGH          0xbc
  45 #define SBBCONFIG               0xc0
  46 #define SBBSTATE                0xc8
  47 #define SBACTCNFG               0xd8
  48 #define SBFLAGST                0xe8
  49 #define SBIDLOW                 0xf8
  50 #define SBIDHIGH                0xfc
  51
  52
  53
  54 #define SBIMERRLOGA             0xea8
  55 #define SBIMERRLOG              0xeb0
  56 #define SBTMPORTCONNID0         0xed8
  57 #define SBTMPORTLOCK0           0xef8
  58
  59 #ifndef _LANGUAGE_ASSEMBLY
  60
  61 typedef volatile struct _sbconfig {
  62         uint32  PAD[2];
  63         uint32  sbipsflag;
  64         uint32  PAD[3];
  65         uint32  sbtpsflag;
  66         uint32  PAD[11];
  67         uint32  sbtmerrloga;
  68         uint32  PAD;
  69         uint32  sbtmerrlog;
  70         uint32  PAD[3];
  71         uint32  sbadmatch3;
  72         uint32  PAD;
  73         uint32  sbadmatch2;
  74         uint32  PAD;
  75         uint32  sbadmatch1;
  76         uint32  PAD[7];
  77         uint32  sbimstate;
  78         uint32  sbintvec;
  79         uint32  sbtmstatelow;
  80         uint32  sbtmstatehigh;
  81         uint32  sbbwa0;
  82         uint32  PAD;
  83         uint32  sbimconfiglow;
  84         uint32  sbimconfighigh;
  85         uint32  sbadmatch0;
  86         uint32  PAD;
  87         uint32  sbtmconfiglow;
  88         uint32  sbtmconfighigh;
  89         uint32  sbbconfig;
  90         uint32  PAD;
  91         uint32  sbbstate;
  92         uint32  PAD[3];
  93         uint32  sbactcnfg;
  94         uint32  PAD[3];
  95         uint32  sbflagst;
  96         uint32  PAD[3];
  97         uint32  sbidlow;
  98         uint32  sbidhigh;
  99 } sbconfig_t;
 100
 101 #endif
 102
 103
 104 #define SBIPS_INT1_MASK         0x3f
 105 #define SBIPS_INT1_SHIFT        0
 106 #define SBIPS_INT2_MASK         0x3f00
 107 #define SBIPS_INT2_SHIFT        8
 108 #define SBIPS_INT3_MASK         0x3f0000
 109 #define SBIPS_INT3_SHIFT        16
 110 #define SBIPS_INT4_MASK         0x3f000000
 111 #define SBIPS_INT4_SHIFT        24
 112
 113
 114 #define SBTPS_NUM0_MASK         0x3f
 115 #define SBTPS_F0EN0             0x40
 116
 117
 118 #define SBTMEL_CM               0x00000007
 119 #define SBTMEL_CI               0x0000ff00
 120 #define SBTMEL_EC               0x0f000000
 121 #define SBTMEL_ME               0x80000000
 122
 123
 124 #define SBIM_PC                 0xf
 125 #define SBIM_AP_MASK            0x30
 126 #define SBIM_AP_BOTH            0x00
 127 #define SBIM_AP_TS              0x10
 128 #define SBIM_AP_TK              0x20
 129 #define SBIM_AP_RSV             0x30
 130 #define SBIM_IBE                0x20000
 131 #define SBIM_TO                 0x40000
 132 #define SBIM_BY                 0x01800000
 133 #define SBIM_RJ                 0x02000000
 134
 135
 136 #define SBTML_RESET             0x0001
 137 #define SBTML_REJ_MASK          0x0006
 138 #define SBTML_REJ               0x0002
 139 #define SBTML_TMPREJ            0x0004
 140
 141 #define SBTML_SICF_SHIFT        16
 142
 143
 144 #define SBTMH_SERR              0x0001
 145 #define SBTMH_INT               0x0002
 146 #define SBTMH_BUSY              0x0004
 147 #define SBTMH_TO                0x0020
 148
 149 #define SBTMH_SISF_SHIFT        16
 150
 151
 152 #define SBBWA_TAB0_MASK         0xffff
 153 #define SBBWA_TAB1_MASK         0xffff
 154 #define SBBWA_TAB1_SHIFT        16
 155
 156
 157 #define SBIMCL_STO_MASK         0x7
 158 #define SBIMCL_RTO_MASK         0x70
 159 #define SBIMCL_RTO_SHIFT        4
 160 #define SBIMCL_CID_MASK         0xff0000
 161 #define SBIMCL_CID_SHIFT        16
 162
 163
 164 #define SBIMCH_IEM_MASK         0xc
 165 #define SBIMCH_TEM_MASK         0x30
 166 #define SBIMCH_TEM_SHIFT        4
 167 #define SBIMCH_BEM_MASK         0xc0
 168 #define SBIMCH_BEM_SHIFT        6
 169
 170
 171 #define SBAM_TYPE_MASK          0x3
 172 #define SBAM_AD64               0x4
 173 #define SBAM_ADINT0_MASK        0xf8
 174 #define SBAM_ADINT0_SHIFT       3
 175 #define SBAM_ADINT1_MASK        0x1f8
 176 #define SBAM_ADINT1_SHIFT       3
 177 #define SBAM_ADINT2_MASK        0x1f8
 178 #define SBAM_ADINT2_SHIFT       3
 179 #define SBAM_ADEN               0x400
 180 #define SBAM_ADNEG              0x800
 181 #define SBAM_BASE0_MASK         0xffffff00
 182 #define SBAM_BASE0_SHIFT        8
 183 #define SBAM_BASE1_MASK         0xfffff000
 184 #define SBAM_BASE1_SHIFT        12
 185 #define SBAM_BASE2_MASK         0xffff0000
 186 #define SBAM_BASE2_SHIFT        16
 187
 188
 189 #define SBTMCL_CD_MASK          0xff
 190 #define SBTMCL_CO_MASK          0xf800
 191 #define SBTMCL_CO_SHIFT         11
 192 #define SBTMCL_IF_MASK          0xfc0000
 193 #define SBTMCL_IF_SHIFT         18
 194 #define SBTMCL_IM_MASK          0x3000000
 195 #define SBTMCL_IM_SHIFT         24
 196
 197
 198 #define SBTMCH_BM_MASK          0x3
 199 #define SBTMCH_RM_MASK          0x3
 200 #define SBTMCH_RM_SHIFT         2
 201 #define SBTMCH_SM_MASK          0x30
 202 #define SBTMCH_SM_SHIFT         4
 203 #define SBTMCH_EM_MASK          0x300
 204 #define SBTMCH_EM_SHIFT         8
 205 #define SBTMCH_IM_MASK          0xc00
 206 #define SBTMCH_IM_SHIFT         10
 207
 208
 209 #define SBBC_LAT_MASK           0x3
 210 #define SBBC_MAX0_MASK          0xf0000
 211 #define SBBC_MAX0_SHIFT         16
 212 #define SBBC_MAX1_MASK          0xf00000
 213 #define SBBC_MAX1_SHIFT         20
 214
 215
 216 #define SBBS_SRD                0x1
 217 #define SBBS_HRD                0x2
 218
 219
 220 #define SBIDL_CS_MASK           0x3
 221 #define SBIDL_AR_MASK           0x38
 222 #define SBIDL_AR_SHIFT          3
 223 #define SBIDL_SYNCH             0x40
 224 #define SBIDL_INIT              0x80
 225 #define SBIDL_MINLAT_MASK       0xf00
 226 #define SBIDL_MINLAT_SHIFT      8
 227 #define SBIDL_MAXLAT            0xf000
 228 #define SBIDL_MAXLAT_SHIFT      12
 229 #define SBIDL_FIRST             0x10000
 230 #define SBIDL_CW_MASK           0xc0000
 231 #define SBIDL_CW_SHIFT          18
 232 #define SBIDL_TP_MASK           0xf00000
 233 #define SBIDL_TP_SHIFT          20
 234 #define SBIDL_IP_MASK           0xf000000
 235 #define SBIDL_IP_SHIFT          24
 236 #define SBIDL_RV_MASK           0xf0000000
 237 #define SBIDL_RV_SHIFT          28
 238 #define SBIDL_RV_2_2            0x00000000
 239 #define SBIDL_RV_2_3            0x10000000
 240
 241
 242 #define SBIDH_RC_MASK           0x000f
 243 #define SBIDH_RCE_MASK          0x7000
 244 #define SBIDH_RCE_SHIFT         8
 245 #define SBCOREREV(sbidh) \
 246         ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
 247 #define SBIDH_CC_MASK           0x8ff0
 248 #define SBIDH_CC_SHIFT          4
 249 #define SBIDH_VC_MASK           0xffff0000
 250 #define SBIDH_VC_SHIFT          16
 251
 252 #define SB_COMMIT               0xfd8
 253
 254
 255 #define SB_VEND_BCM             0x4243
 256
 257 #endif