drivers/net/wireless/rkwifi/bcmdhd/include/sbchipc.h

   1 /*
   2  * SiliconBackplane Chipcommon core hardware definitions.
   3  *
   4  * The chipcommon core provides chip identification, SB control,
   5  * JTAG, 0/1/2 UARTs, clock frequency control, a watchdog interrupt timer,
   6  * GPIO interface, extbus, and support for serial and parallel flashes.
   7  *
   8  * $Id: sbchipc.h 385540 2013-02-15 23:14:50Z $
   9  *
  10  * $Copyright Open Broadcom Corporation$
  11  */
  12
  13 #ifndef _SBCHIPC_H
  14 #define _SBCHIPC_H
  15
  16 #ifndef _LANGUAGE_ASSEMBLY
  17
  18
  19 #ifndef PAD
  20 #define _PADLINE(line)  pad ## line
  21 #define _XSTR(line)     _PADLINE(line)
  22 #define PAD             _XSTR(__LINE__)
  23 #endif
  24
  25 typedef struct eci_prerev35 {
  26         uint32  eci_output;
  27         uint32  eci_control;
  28         uint32  eci_inputlo;
  29         uint32  eci_inputmi;
  30         uint32  eci_inputhi;
  31         uint32  eci_inputintpolaritylo;
  32         uint32  eci_inputintpolaritymi;
  33         uint32  eci_inputintpolarityhi;
  34         uint32  eci_intmasklo;
  35         uint32  eci_intmaskmi;
  36         uint32  eci_intmaskhi;
  37         uint32  eci_eventlo;
  38         uint32  eci_eventmi;
  39         uint32  eci_eventhi;
  40         uint32  eci_eventmasklo;
  41         uint32  eci_eventmaskmi;
  42         uint32  eci_eventmaskhi;
  43         uint32  PAD[3];
  44 } eci_prerev35_t;
  45
  46 typedef struct eci_rev35 {
  47         uint32  eci_outputlo;
  48         uint32  eci_outputhi;
  49         uint32  eci_controllo;
  50         uint32  eci_controlhi;
  51         uint32  eci_inputlo;
  52         uint32  eci_inputhi;
  53         uint32  eci_inputintpolaritylo;
  54         uint32  eci_inputintpolarityhi;
  55         uint32  eci_intmasklo;
  56         uint32  eci_intmaskhi;
  57         uint32  eci_eventlo;
  58         uint32  eci_eventhi;
  59         uint32  eci_eventmasklo;
  60         uint32  eci_eventmaskhi;
  61         uint32  eci_auxtx;
  62         uint32  eci_auxrx;
  63         uint32  eci_datatag;
  64         uint32  eci_uartescvalue;
  65         uint32  eci_autobaudctr;
  66         uint32  eci_uartfifolevel;
  67 } eci_rev35_t;
  68
  69 typedef struct flash_config {
  70         uint32  PAD[19];
  71
  72         uint32 flashstrconfig;
  73 } flash_config_t;
  74
  75 typedef volatile struct {
  76         uint32  chipid;
  77         uint32  capabilities;
  78         uint32  corecontrol;
  79         uint32  bist;
  80
  81
  82         uint32  otpstatus;
  83         uint32  otpcontrol;
  84         uint32  otpprog;
  85         uint32  otplayout;
  86
  87
  88         uint32  intstatus;
  89         uint32  intmask;
  90
  91
  92         uint32  chipcontrol;
  93         uint32  chipstatus;
  94
  95
  96         uint32  jtagcmd;
  97         uint32  jtagir;
  98         uint32  jtagdr;
  99         uint32  jtagctrl;
 100
 101
 102         uint32  flashcontrol;
 103         uint32  flashaddress;
 104         uint32  flashdata;
 105         uint32  otplayoutextension;
 106
 107
 108         uint32  broadcastaddress;
 109         uint32  broadcastdata;
 110
 111
 112         uint32  gpiopullup;
 113         uint32  gpiopulldown;
 114         uint32  gpioin;
 115         uint32  gpioout;
 116         uint32  gpioouten;
 117         uint32  gpiocontrol;
 118         uint32  gpiointpolarity;
 119         uint32  gpiointmask;
 120
 121
 122         uint32  gpioevent;
 123         uint32  gpioeventintmask;
 124
 125
 126         uint32  watchdog;
 127
 128
 129         uint32  gpioeventintpolarity;
 130
 131
 132         uint32  gpiotimerval;
 133         uint32  gpiotimeroutmask;
 134
 135
 136         uint32  clockcontrol_n;
 137         uint32  clockcontrol_sb;
 138         uint32  clockcontrol_pci;
 139         uint32  clockcontrol_m2;
 140         uint32  clockcontrol_m3;
 141         uint32  clkdiv;
 142         uint32  gpiodebugsel;
 143         uint32  capabilities_ext;
 144
 145
 146         uint32  pll_on_delay;
 147         uint32  fref_sel_delay;
 148         uint32  slow_clk_ctl;
 149         uint32  PAD;
 150
 151
 152         uint32  system_clk_ctl;
 153         uint32  clkstatestretch;
 154         uint32  PAD[2];
 155
 156
 157         uint32  bp_addrlow;
 158         uint32  bp_addrhigh;
 159         uint32  bp_data;
 160         uint32  PAD;
 161         uint32  bp_indaccess;
 162
 163         uint32  gsioctrl;
 164         uint32  gsioaddress;
 165         uint32  gsiodata;
 166
 167
 168         uint32  clkdiv2;
 169
 170         uint32  otpcontrol1;
 171         uint32  fabid;
 172
 173
 174         uint32  eromptr;
 175
 176
 177         uint32  pcmcia_config;
 178         uint32  pcmcia_memwait;
 179         uint32  pcmcia_attrwait;
 180         uint32  pcmcia_iowait;
 181         uint32  ide_config;
 182         uint32  ide_memwait;
 183         uint32  ide_attrwait;
 184         uint32  ide_iowait;
 185         uint32  prog_config;
 186         uint32  prog_waitcount;
 187         uint32  flash_config;
 188         uint32  flash_waitcount;
 189         uint32  SECI_config;
 190         uint32  SECI_status;
 191         uint32  SECI_statusmask;
 192         uint32  SECI_rxnibchanged;
 193
 194         uint32  PAD[20];
 195
 196
 197         uint32  sromcontrol;
 198         uint32  sromaddress;
 199         uint32  sromdata;
 200         uint32  PAD[1];
 201
 202     uint32  nflashctrl;
 203     uint32  nflashconf;
 204     uint32  nflashcoladdr;
 205     uint32  nflashrowaddr;
 206     uint32  nflashdata;
 207     uint32  nflashwaitcnt0;
 208     uint32  PAD[2];
 209
 210         uint32  seci_uart_data;
 211         uint32  seci_uart_bauddiv;
 212         uint32  seci_uart_fcr;
 213         uint32  seci_uart_lcr;
 214         uint32  seci_uart_mcr;
 215         uint32  seci_uart_lsr;
 216         uint32  seci_uart_msr;
 217         uint32  seci_uart_baudadj;
 218
 219         uint32  clk_ctl_st;
 220         uint32  hw_war;
 221         uint32  PAD[70];
 222
 223
 224         uint8   uart0data;
 225         uint8   uart0imr;
 226         uint8   uart0fcr;
 227         uint8   uart0lcr;
 228         uint8   uart0mcr;
 229         uint8   uart0lsr;
 230         uint8   uart0msr;
 231         uint8   uart0scratch;
 232         uint8   PAD[248];
 233
 234         uint8   uart1data;
 235         uint8   uart1imr;
 236         uint8   uart1fcr;
 237         uint8   uart1lcr;
 238         uint8   uart1mcr;
 239         uint8   uart1lsr;
 240         uint8   uart1msr;
 241         uint8   uart1scratch;
 242         uint32  PAD[126];
 243
 244
 245
 246         uint32  pmucontrol;
 247         uint32  pmucapabilities;
 248         uint32  pmustatus;
 249         uint32  res_state;
 250         uint32  res_pending;
 251         uint32  pmutimer;
 252         uint32  min_res_mask;
 253         uint32  max_res_mask;
 254         uint32  res_table_sel;
 255         uint32  res_dep_mask;
 256         uint32  res_updn_timer;
 257         uint32  res_timer;
 258         uint32  clkstretch;
 259         uint32  pmuwatchdog;
 260         uint32  gpiosel;
 261         uint32  gpioenable;
 262         uint32  res_req_timer_sel;
 263         uint32  res_req_timer;
 264         uint32  res_req_mask;
 265         uint32  PAD;
 266         uint32  chipcontrol_addr;
 267         uint32  chipcontrol_data;
 268         uint32  regcontrol_addr;
 269         uint32  regcontrol_data;
 270         uint32  pllcontrol_addr;
 271         uint32  pllcontrol_data;
 272         uint32  pmustrapopt;
 273         uint32  pmu_xtalfreq;
 274         uint32  retention_ctl;
 275         uint32  PAD[3];
 276         uint32  retention_grpidx;
 277         uint32  retention_grpctl;
 278         uint32  PAD[94];
 279         uint16  sromotp[512];
 280 #ifdef NFLASH_SUPPORT
 281
 282         uint32  nand_revision;
 283         uint32  nand_cmd_start;
 284         uint32  nand_cmd_addr_x;
 285         uint32  nand_cmd_addr;
 286         uint32  nand_cmd_end_addr;
 287         uint32  nand_cs_nand_select;
 288         uint32  nand_cs_nand_xor;
 289         uint32  PAD;
 290         uint32  nand_spare_rd0;
 291         uint32  nand_spare_rd4;
 292         uint32  nand_spare_rd8;
 293         uint32  nand_spare_rd12;
 294         uint32  nand_spare_wr0;
 295         uint32  nand_spare_wr4;
 296         uint32  nand_spare_wr8;
 297         uint32  nand_spare_wr12;
 298         uint32  nand_acc_control;
 299         uint32  PAD;
 300         uint32  nand_config;
 301         uint32  PAD;
 302         uint32  nand_timing_1;
 303         uint32  nand_timing_2;
 304         uint32  nand_semaphore;
 305         uint32  PAD;
 306         uint32  nand_devid;
 307         uint32  nand_devid_x;
 308         uint32  nand_block_lock_status;
 309         uint32  nand_intfc_status;
 310         uint32  nand_ecc_corr_addr_x;
 311         uint32  nand_ecc_corr_addr;
 312         uint32  nand_ecc_unc_addr_x;
 313         uint32  nand_ecc_unc_addr;
 314         uint32  nand_read_error_count;
 315         uint32  nand_corr_stat_threshold;
 316         uint32  PAD[2];
 317         uint32  nand_read_addr_x;
 318         uint32  nand_read_addr;
 319         uint32  nand_page_program_addr_x;
 320         uint32  nand_page_program_addr;
 321         uint32  nand_copy_back_addr_x;
 322         uint32  nand_copy_back_addr;
 323         uint32  nand_block_erase_addr_x;
 324         uint32  nand_block_erase_addr;
 325         uint32  nand_inv_read_addr_x;
 326         uint32  nand_inv_read_addr;
 327         uint32  PAD[2];
 328         uint32  nand_blk_wr_protect;
 329         uint32  PAD[3];
 330         uint32  nand_acc_control_cs1;
 331         uint32  nand_config_cs1;
 332         uint32  nand_timing_1_cs1;
 333         uint32  nand_timing_2_cs1;
 334         uint32  PAD[20];
 335         uint32  nand_spare_rd16;
 336         uint32  nand_spare_rd20;
 337         uint32  nand_spare_rd24;
 338         uint32  nand_spare_rd28;
 339         uint32  nand_cache_addr;
 340         uint32  nand_cache_data;
 341         uint32  nand_ctrl_config;
 342         uint32  nand_ctrl_status;
 343 #endif
 344         uint32  gci_corecaps0;
 345         uint32  gci_corecaps1;
 346         uint32  gci_corecaps2;
 347         uint32  gci_corectrl;
 348         uint32  gci_corestat;
 349         uint32  gci_intstat;
 350         uint32  gci_intmask;
 351         uint32  gci_wakemask;
 352         uint32  gci_levelintstat;
 353         uint32  gci_eventintstat;
 354         uint32  PAD[6];
 355         uint32  gci_indirect_addr;
 356         uint32  gci_gpioctl;
 357         uint32  PAD;
 358         uint32  gci_gpiomask;
 359         uint32  PAD;
 360         uint32  gci_miscctl;
 361         uint32  PAD[2];
 362         uint32  gci_input[32];
 363         uint32  gci_event[32];
 364         uint32  gci_output[4];
 365         uint32  gci_control_0;
 366         uint32  gci_control_1;
 367         uint32  gci_level_polreg;
 368         uint32  gci_levelintmask;
 369         uint32  gci_eventintmask;
 370         uint32  PAD[3];
 371         uint32  gci_inbandlevelintmask;
 372         uint32  gci_inbandeventintmask;
 373         uint32  PAD[2];
 374         uint32  gci_seciauxtx;
 375         uint32  gci_seciauxrx;
 376         uint32  gci_secitx_datatag;
 377         uint32  gci_secirx_datatag;
 378         uint32  gci_secitx_datamask;
 379         uint32  gci_seciusef0tx_reg;
 380         uint32  gci_secif0tx_offset;
 381         uint32  gci_secif0rx_offset;
 382         uint32  gci_secif1tx_offset;
 383         uint32  PAD[3];
 384         uint32  gci_uartescval;
 385         uint32  PAD[3];
 386         uint32  gci_secibauddiv;
 387         uint32  gci_secifcr;
 388         uint32  gci_secilcr;
 389         uint32  gci_secimcr;
 390         uint32  PAD[2];
 391         uint32  gci_baudadj;
 392         uint32  PAD;
 393         uint32  gci_chipctrl;
 394         uint32  gci_chipsts;
 395 } chipcregs_t;
 396
 397 #endif
 398
 399
 400 #define CC_CHIPID               0
 401 #define CC_CAPABILITIES         4
 402 #define CC_CHIPST               0x2c
 403 #define CC_EROMPTR              0xfc
 404
 405 #define CC_OTPST                0x10
 406 #define CC_JTAGCMD              0x30
 407 #define CC_JTAGIR               0x34
 408 #define CC_JTAGDR               0x38
 409 #define CC_JTAGCTRL             0x3c
 410 #define CC_GPIOPU               0x58
 411 #define CC_GPIOPD               0x5c
 412 #define CC_GPIOIN               0x60
 413 #define CC_GPIOOUT              0x64
 414 #define CC_GPIOOUTEN            0x68
 415 #define CC_GPIOCTRL             0x6c
 416 #define CC_GPIOPOL              0x70
 417 #define CC_GPIOINTM             0x74
 418 #define CC_WATCHDOG             0x80
 419 #define CC_CLKC_N               0x90
 420 #define CC_CLKC_M0              0x94
 421 #define CC_CLKC_M1              0x98
 422 #define CC_CLKC_M2              0x9c
 423 #define CC_CLKC_M3              0xa0
 424 #define CC_CLKDIV               0xa4
 425 #define CC_SYS_CLK_CTL          0xc0
 426 #define CC_CLK_CTL_ST           SI_CLK_CTL_ST
 427 #define PMU_CTL                 0x600
 428 #define PMU_CAP                 0x604
 429 #define PMU_ST                  0x608
 430 #define PMU_RES_STATE           0x60c
 431 #define PMU_TIMER               0x614
 432 #define PMU_MIN_RES_MASK        0x618
 433 #define PMU_MAX_RES_MASK        0x61c
 434 #define CC_CHIPCTL_ADDR         0x650
 435 #define CC_CHIPCTL_DATA         0x654
 436 #define PMU_REG_CONTROL_ADDR    0x658
 437 #define PMU_REG_CONTROL_DATA    0x65C
 438 #define PMU_PLL_CONTROL_ADDR    0x660
 439 #define PMU_PLL_CONTROL_DATA    0x664
 440 #define CC_SROM_OTP             0x800
 441 #define CC_GCI_INDIRECT_ADDR_REG        0xC40
 442 #define CC_GCI_CHIP_CTRL_REG    0xE00
 443 #define CC_GCI_CC_OFFSET_2      2
 444 #define CC_GCI_CC_OFFSET_5      5
 445
 446 #ifdef NFLASH_SUPPORT
 447
 448 #define CC_NAND_REVISION        0xC00
 449 #define CC_NAND_CMD_START       0xC04
 450 #define CC_NAND_CMD_ADDR        0xC0C
 451 #define CC_NAND_SPARE_RD_0      0xC20
 452 #define CC_NAND_SPARE_RD_4      0xC24
 453 #define CC_NAND_SPARE_RD_8      0xC28
 454 #define CC_NAND_SPARE_RD_C      0xC2C
 455 #define CC_NAND_CONFIG          0xC48
 456 #define CC_NAND_DEVID           0xC60
 457 #define CC_NAND_DEVID_EXT       0xC64
 458 #define CC_NAND_INTFC_STATUS    0xC6C
 459 #endif
 460
 461
 462 #define CID_ID_MASK             0x0000ffff
 463 #define CID_REV_MASK            0x000f0000
 464 #define CID_REV_SHIFT           16
 465 #define CID_PKG_MASK            0x00f00000
 466 #define CID_PKG_SHIFT           20
 467 #define CID_CC_MASK             0x0f000000
 468 #define CID_CC_SHIFT            24
 469 #define CID_TYPE_MASK           0xf0000000
 470 #define CID_TYPE_SHIFT          28
 471
 472
 473 #define CC_CAP_UARTS_MASK       0x00000003
 474 #define CC_CAP_MIPSEB           0x00000004
 475 #define CC_CAP_UCLKSEL          0x00000018
 476 #define CC_CAP_UINTCLK          0x00000008
 477 #define CC_CAP_UARTGPIO         0x00000020
 478 #define CC_CAP_EXTBUS_MASK      0x000000c0
 479 #define CC_CAP_EXTBUS_NONE      0x00000000
 480 #define CC_CAP_EXTBUS_FULL      0x00000040
 481 #define CC_CAP_EXTBUS_PROG      0x00000080
 482 #define CC_CAP_FLASH_MASK       0x00000700
 483 #define CC_CAP_PLL_MASK         0x00038000
 484 #define CC_CAP_PWR_CTL          0x00040000
 485 #define CC_CAP_OTPSIZE          0x00380000
 486 #define CC_CAP_OTPSIZE_SHIFT    19
 487 #define CC_CAP_OTPSIZE_BASE     5
 488 #define CC_CAP_JTAGP            0x00400000
 489 #define CC_CAP_ROM              0x00800000
 490 #define CC_CAP_BKPLN64          0x08000000
 491 #define CC_CAP_PMU              0x10000000
 492 #define CC_CAP_ECI              0x20000000
 493 #define CC_CAP_SROM             0x40000000
 494 #define CC_CAP_NFLASH           0x80000000
 495
 496 #define CC_CAP2_SECI            0x00000001
 497 #define CC_CAP2_GSIO            0x00000002
 498
 499
 500 #define CC_CAP_EXT_SECI_PRESENT 0x00000001
 501 #define CC_CAP_EXT_GCI_PRESENT  0x00000004
 502
 503
 504 #define GCI_WL_CHN_INFO_MASK    (0xFF00)
 505
 506 #define PLL_NONE                0x00000000
 507 #define PLL_TYPE1               0x00010000
 508 #define PLL_TYPE2               0x00020000
 509 #define PLL_TYPE3               0x00030000
 510 #define PLL_TYPE4               0x00008000
 511 #define PLL_TYPE5               0x00018000
 512 #define PLL_TYPE6               0x00028000
 513 #define PLL_TYPE7               0x00038000
 514
 515
 516 #define ILP_CLOCK               32000
 517
 518
 519 #define ALP_CLOCK               20000000
 520
 521 #ifdef CFG_SIM
 522 #define NS_ALP_CLOCK            84922
 523 #define NS_SLOW_ALP_CLOCK       84922
 524 #define NS_CPU_CLOCK            534500
 525 #define NS_SLOW_CPU_CLOCK       534500
 526 #define NS_SI_CLOCK             271750
 527 #define NS_SLOW_SI_CLOCK        271750
 528 #define NS_FAST_MEM_CLOCK       271750
 529 #define NS_MEM_CLOCK            271750
 530 #define NS_SLOW_MEM_CLOCK       271750
 531 #else
 532 #define NS_ALP_CLOCK            125000000
 533 #define NS_SLOW_ALP_CLOCK       100000000
 534 #define NS_CPU_CLOCK            1000000000
 535 #define NS_SLOW_CPU_CLOCK       800000000
 536 #define NS_SI_CLOCK             250000000
 537 #define NS_SLOW_SI_CLOCK        200000000
 538 #define NS_FAST_MEM_CLOCK       800000000
 539 #define NS_MEM_CLOCK            533000000
 540 #define NS_SLOW_MEM_CLOCK       400000000
 541 #endif
 542
 543
 544 #define HT_CLOCK                80000000
 545
 546
 547 #define CC_UARTCLKO             0x00000001
 548 #define CC_SE                   0x00000002
 549 #define CC_ASYNCGPIO    0x00000004
 550 #define CC_UARTCLKEN            0x00000008
 551
 552
 553 #define CHIPCTRL_4321A0_DEFAULT 0x3a4
 554 #define CHIPCTRL_4321A1_DEFAULT 0x0a4
 555 #define CHIPCTRL_4321_PLL_DOWN  0x800000
 556
 557
 558 #define OTPS_OL_MASK            0x000000ff
 559 #define OTPS_OL_MFG             0x00000001
 560 #define OTPS_OL_OR1             0x00000002
 561 #define OTPS_OL_OR2             0x00000004
 562 #define OTPS_OL_GU              0x00000008
 563 #define OTPS_GUP_MASK           0x00000f00
 564 #define OTPS_GUP_SHIFT          8
 565 #define OTPS_GUP_HW             0x00000100
 566 #define OTPS_GUP_SW             0x00000200
 567 #define OTPS_GUP_CI             0x00000400
 568 #define OTPS_GUP_FUSE           0x00000800
 569 #define OTPS_READY              0x00001000
 570 #define OTPS_RV(x)              (1 << (16 + (x)))
 571 #define OTPS_RV_MASK            0x0fff0000
 572 #define OTPS_PROGOK     0x40000000
 573
 574
 575 #define OTPC_PROGSEL            0x00000001
 576 #define OTPC_PCOUNT_MASK        0x0000000e
 577 #define OTPC_PCOUNT_SHIFT       1
 578 #define OTPC_VSEL_MASK          0x000000f0
 579 #define OTPC_VSEL_SHIFT         4
 580 #define OTPC_TMM_MASK           0x00000700
 581 #define OTPC_TMM_SHIFT          8
 582 #define OTPC_ODM                0x00000800
 583 #define OTPC_PROGEN             0x80000000
 584
 585
 586 #define OTPC_40NM_PROGSEL_SHIFT 0
 587 #define OTPC_40NM_PCOUNT_SHIFT  1
 588 #define OTPC_40NM_PCOUNT_WR     0xA
 589 #define OTPC_40NM_PCOUNT_V1X    0xB
 590 #define OTPC_40NM_REGCSEL_SHIFT 5
 591 #define OTPC_40NM_REGCSEL_DEF   0x4
 592 #define OTPC_40NM_PROGIN_SHIFT  8
 593 #define OTPC_40NM_R2X_SHIFT     10
 594 #define OTPC_40NM_ODM_SHIFT     11
 595 #define OTPC_40NM_DF_SHIFT      15
 596 #define OTPC_40NM_VSEL_SHIFT    16
 597 #define OTPC_40NM_VSEL_WR       0xA
 598 #define OTPC_40NM_VSEL_V1X      0xA
 599 #define OTPC_40NM_VSEL_R1X      0x5
 600 #define OTPC_40NM_COFAIL_SHIFT  30
 601
 602 #define OTPC1_CPCSEL_SHIFT      0
 603 #define OTPC1_CPCSEL_DEF        6
 604 #define OTPC1_TM_SHIFT          8
 605 #define OTPC1_TM_WR             0x84
 606 #define OTPC1_TM_V1X            0x84
 607 #define OTPC1_TM_R1X            0x4
 608
 609
 610 #define OTPP_COL_MASK           0x000000ff
 611 #define OTPP_COL_SHIFT          0
 612 #define OTPP_ROW_MASK           0x0000ff00
 613 #define OTPP_ROW_SHIFT          8
 614 #define OTPP_OC_MASK            0x0f000000
 615 #define OTPP_OC_SHIFT           24
 616 #define OTPP_READERR            0x10000000
 617 #define OTPP_VALUE_MASK         0x20000000
 618 #define OTPP_VALUE_SHIFT        29
 619 #define OTPP_START_BUSY         0x80000000
 620 #define OTPP_READ               0x40000000
 621
 622
 623 #define OTPL_HWRGN_OFF_MASK     0x00000FFF
 624 #define OTPL_HWRGN_OFF_SHIFT    0
 625 #define OTPL_WRAP_REVID_MASK    0x00F80000
 626 #define OTPL_WRAP_REVID_SHIFT   19
 627 #define OTPL_WRAP_TYPE_MASK     0x00070000
 628 #define OTPL_WRAP_TYPE_SHIFT    16
 629 #define OTPL_WRAP_TYPE_65NM     0
 630 #define OTPL_WRAP_TYPE_40NM     1
 631
 632
 633 #define OTP_CISFORMAT_NEW       0x80000000
 634
 635
 636 #define OTPPOC_READ             0
 637 #define OTPPOC_BIT_PROG         1
 638 #define OTPPOC_VERIFY           3
 639 #define OTPPOC_INIT             4
 640 #define OTPPOC_SET              5
 641 #define OTPPOC_RESET            6
 642 #define OTPPOC_OCST             7
 643 #define OTPPOC_ROW_LOCK         8
 644 #define OTPPOC_PRESCN_TEST      9
 645
 646
 647 #define OTPPOC_READ_40NM        0
 648 #define OTPPOC_PROG_ENABLE_40NM 1
 649 #define OTPPOC_PROG_DISABLE_40NM        2
 650 #define OTPPOC_VERIFY_40NM      3
 651 #define OTPPOC_WORD_VERIFY_1_40NM       4
 652 #define OTPPOC_ROW_LOCK_40NM    5
 653 #define OTPPOC_STBY_40NM        6
 654 #define OTPPOC_WAKEUP_40NM      7
 655 #define OTPPOC_WORD_VERIFY_0_40NM       8
 656 #define OTPPOC_PRESCN_TEST_40NM 9
 657 #define OTPPOC_BIT_PROG_40NM    10
 658 #define OTPPOC_WORDPROG_40NM    11
 659 #define OTPPOC_BURNIN_40NM      12
 660 #define OTPPOC_AUTORELOAD_40NM  13
 661 #define OTPPOC_OVST_READ_40NM   14
 662 #define OTPPOC_OVST_PROG_40NM   15
 663
 664
 665 #define OTPLAYOUTEXT_FUSE_MASK  0x3FF
 666
 667
 668
 669 #define JTAGM_CREV_OLD          10
 670 #define JTAGM_CREV_IRP          22
 671 #define JTAGM_CREV_RTI          28
 672
 673
 674 #define JCMD_START              0x80000000
 675 #define JCMD_BUSY               0x80000000
 676 #define JCMD_STATE_MASK         0x60000000
 677 #define JCMD_STATE_TLR          0x00000000
 678 #define JCMD_STATE_PIR          0x20000000
 679 #define JCMD_STATE_PDR          0x40000000
 680 #define JCMD_STATE_RTI          0x60000000
 681 #define JCMD0_ACC_MASK          0x0000f000
 682 #define JCMD0_ACC_IRDR          0x00000000
 683 #define JCMD0_ACC_DR            0x00001000
 684 #define JCMD0_ACC_IR            0x00002000
 685 #define JCMD0_ACC_RESET         0x00003000
 686 #define JCMD0_ACC_IRPDR         0x00004000
 687 #define JCMD0_ACC_PDR           0x00005000
 688 #define JCMD0_IRW_MASK          0x00000f00
 689 #define JCMD_ACC_MASK           0x000f0000
 690 #define JCMD_ACC_IRDR           0x00000000
 691 #define JCMD_ACC_DR             0x00010000
 692 #define JCMD_ACC_IR             0x00020000
 693 #define JCMD_ACC_RESET          0x00030000
 694 #define JCMD_ACC_IRPDR          0x00040000
 695 #define JCMD_ACC_PDR            0x00050000
 696 #define JCMD_ACC_PIR            0x00060000
 697 #define JCMD_ACC_IRDR_I         0x00070000
 698 #define JCMD_ACC_DR_I           0x00080000
 699 #define JCMD_IRW_MASK           0x00001f00
 700 #define JCMD_IRW_SHIFT          8
 701 #define JCMD_DRW_MASK           0x0000003f
 702
 703
 704 #define JCTRL_FORCE_CLK         4
 705 #define JCTRL_EXT_EN            2
 706 #define JCTRL_EN                1
 707
 708
 709 #define CLKD_SFLASH             0x0f000000
 710 #define CLKD_SFLASH_SHIFT       24
 711 #define CLKD_OTP                0x000f0000
 712 #define CLKD_OTP_SHIFT          16
 713 #define CLKD_JTAG               0x00000f00
 714 #define CLKD_JTAG_SHIFT         8
 715 #define CLKD_UART               0x000000ff
 716
 717 #define CLKD2_SROM              0x00000003
 718
 719
 720 #define CI_GPIO                 0x00000001
 721 #define CI_EI                   0x00000002
 722 #define CI_TEMP                 0x00000004
 723 #define CI_SIRQ                 0x00000008
 724 #define CI_ECI                  0x00000010
 725 #define CI_PMU                  0x00000020
 726 #define CI_UART                 0x00000040
 727 #define CI_WDRESET              0x80000000
 728
 729
 730 #define SCC_SS_MASK             0x00000007
 731 #define SCC_SS_LPO              0x00000000
 732 #define SCC_SS_XTAL             0x00000001
 733 #define SCC_SS_PCI              0x00000002
 734 #define SCC_LF                  0x00000200
 735 #define SCC_LP                  0x00000400
 736 #define SCC_FS                  0x00000800
 737 #define SCC_IP                  0x00001000
 738 #define SCC_XC                  0x00002000
 739 #define SCC_XP                  0x00004000
 740 #define SCC_CD_MASK             0xffff0000
 741 #define SCC_CD_SHIFT            16
 742
 743
 744 #define SYCC_IE                 0x00000001
 745 #define SYCC_AE                 0x00000002
 746 #define SYCC_FP                 0x00000004
 747 #define SYCC_AR                 0x00000008
 748 #define SYCC_HR                 0x00000010
 749 #define SYCC_CD_MASK            0xffff0000
 750 #define SYCC_CD_SHIFT           16
 751
 752
 753 #define BPIA_BYTEEN             0x0000000f
 754 #define BPIA_SZ1                0x00000001
 755 #define BPIA_SZ2                0x00000003
 756 #define BPIA_SZ4                0x00000007
 757 #define BPIA_SZ8                0x0000000f
 758 #define BPIA_WRITE              0x00000100
 759 #define BPIA_START              0x00000200
 760 #define BPIA_BUSY               0x00000200
 761 #define BPIA_ERROR              0x00000400
 762
 763
 764 #define CF_EN                   0x00000001
 765 #define CF_EM_MASK              0x0000000e
 766 #define CF_EM_SHIFT             1
 767 #define CF_EM_FLASH             0
 768 #define CF_EM_SYNC              2
 769 #define CF_EM_PCMCIA            4
 770 #define CF_DS                   0x00000010
 771 #define CF_BS                   0x00000020
 772 #define CF_CD_MASK              0x000000c0
 773 #define CF_CD_SHIFT             6
 774 #define CF_CD_DIV2              0x00000000
 775 #define CF_CD_DIV3              0x00000040
 776 #define CF_CD_DIV4              0x00000080
 777 #define CF_CE                   0x00000100
 778 #define CF_SB                   0x00000200
 779
 780
 781 #define PM_W0_MASK              0x0000003f
 782 #define PM_W1_MASK              0x00001f00
 783 #define PM_W1_SHIFT             8
 784 #define PM_W2_MASK              0x001f0000
 785 #define PM_W2_SHIFT             16
 786 #define PM_W3_MASK              0x1f000000
 787 #define PM_W3_SHIFT             24
 788
 789
 790 #define PA_W0_MASK              0x0000003f
 791 #define PA_W1_MASK              0x00001f00
 792 #define PA_W1_SHIFT             8
 793 #define PA_W2_MASK              0x001f0000
 794 #define PA_W2_SHIFT             16
 795 #define PA_W3_MASK              0x1f000000
 796 #define PA_W3_SHIFT             24
 797
 798
 799 #define PI_W0_MASK              0x0000003f
 800 #define PI_W1_MASK              0x00001f00
 801 #define PI_W1_SHIFT             8
 802 #define PI_W2_MASK              0x001f0000
 803 #define PI_W2_SHIFT             16
 804 #define PI_W3_MASK              0x1f000000
 805 #define PI_W3_SHIFT             24
 806
 807
 808 #define PW_W0_MASK              0x0000001f
 809 #define PW_W1_MASK              0x00001f00
 810 #define PW_W1_SHIFT             8
 811 #define PW_W2_MASK              0x001f0000
 812 #define PW_W2_SHIFT             16
 813 #define PW_W3_MASK              0x1f000000
 814 #define PW_W3_SHIFT             24
 815
 816 #define PW_W0                   0x0000000c
 817 #define PW_W1                   0x00000a00
 818 #define PW_W2                   0x00020000
 819 #define PW_W3                   0x01000000
 820
 821
 822 #define FW_W0_MASK              0x0000003f
 823 #define FW_W1_MASK              0x00001f00
 824 #define FW_W1_SHIFT             8
 825 #define FW_W2_MASK              0x001f0000
 826 #define FW_W2_SHIFT             16
 827 #define FW_W3_MASK              0x1f000000
 828 #define FW_W3_SHIFT             24
 829
 830
 831 #define SRC_START               0x80000000
 832 #define SRC_BUSY                0x80000000
 833 #define SRC_OPCODE              0x60000000
 834 #define SRC_OP_READ             0x00000000
 835 #define SRC_OP_WRITE            0x20000000
 836 #define SRC_OP_WRDIS            0x40000000
 837 #define SRC_OP_WREN             0x60000000
 838 #define SRC_OTPSEL              0x00000010
 839 #define SRC_LOCK                0x00000008
 840 #define SRC_SIZE_MASK           0x00000006
 841 #define SRC_SIZE_1K             0x00000000
 842 #define SRC_SIZE_4K             0x00000002
 843 #define SRC_SIZE_16K            0x00000004
 844 #define SRC_SIZE_SHIFT          1
 845 #define SRC_PRESENT             0x00000001
 846
 847
 848 #define PCTL_ILP_DIV_MASK       0xffff0000
 849 #define PCTL_ILP_DIV_SHIFT      16
 850 #define PCTL_PLL_PLLCTL_UPD     0x00000400
 851 #define PCTL_NOILP_ON_WAIT      0x00000200
 852 #define PCTL_HT_REQ_EN          0x00000100
 853 #define PCTL_ALP_REQ_EN         0x00000080
 854 #define PCTL_XTALFREQ_MASK      0x0000007c
 855 #define PCTL_XTALFREQ_SHIFT     2
 856 #define PCTL_ILP_DIV_EN         0x00000002
 857 #define PCTL_LPO_SEL            0x00000001
 858
 859
 860 #define PMU_RCTL_CLK_DIV_SHIFT          0
 861 #define PMU_RCTL_CHAIN_LEN_SHIFT        12
 862 #define PMU_RCTL_MACPHY_DISABLE_SHIFT   26
 863 #define PMU_RCTL_MACPHY_DISABLE_MASK    (1 << 26)
 864 #define PMU_RCTL_LOGIC_DISABLE_SHIFT    27
 865 #define PMU_RCTL_LOGIC_DISABLE_MASK     (1 << 27)
 866 #define PMU_RCTL_MEMSLP_LOG_SHIFT       28
 867 #define PMU_RCTL_MEMSLP_LOG_MASK        (1 << 28)
 868 #define PMU_RCTL_MEMRETSLP_LOG_SHIFT    29
 869 #define PMU_RCTL_MEMRETSLP_LOG_MASK     (1 << 29)
 870
 871
 872 #define PMU_RCTLGRP_CHAIN_LEN_SHIFT     0
 873 #define PMU_RCTLGRP_RMODE_ENABLE_SHIFT  14
 874 #define PMU_RCTLGRP_RMODE_ENABLE_MASK   (1 << 14)
 875 #define PMU_RCTLGRP_DFT_ENABLE_SHIFT    15
 876 #define PMU_RCTLGRP_DFT_ENABLE_MASK     (1 << 15)
 877 #define PMU_RCTLGRP_NSRST_DISABLE_SHIFT 16
 878 #define PMU_RCTLGRP_NSRST_DISABLE_MASK  (1 << 16)
 879
 880 #define PMU4334_RCTLGRP_CHAIN_LEN_GRP0  338
 881 #define PMU4334_RCTLGRP_CHAIN_LEN_GRP1  315
 882
 883 #define PMU43341_RCTLGRP_CHAIN_LEN_GRP0 366
 884 #define PMU43341_RCTLGRP_CHAIN_LEN_GRP1 330
 885
 886
 887 #define CSTRETCH_HT             0xffff0000
 888 #define CSTRETCH_ALP            0x0000ffff
 889
 890
 891 #define GPIO_ONTIME_SHIFT       16
 892
 893
 894 #define CN_N1_MASK              0x3f
 895 #define CN_N2_MASK              0x3f00
 896 #define CN_N2_SHIFT             8
 897 #define CN_PLLC_MASK            0xf0000
 898 #define CN_PLLC_SHIFT           16
 899
 900
 901 #define CC_M1_MASK              0x3f
 902 #define CC_M2_MASK              0x3f00
 903 #define CC_M2_SHIFT             8
 904 #define CC_M3_MASK              0x3f0000
 905 #define CC_M3_SHIFT             16
 906 #define CC_MC_MASK              0x1f000000
 907 #define CC_MC_SHIFT             24
 908
 909
 910 #define CC_F6_2                 0x02
 911 #define CC_F6_3                 0x03
 912 #define CC_F6_4                 0x05
 913 #define CC_F6_5                 0x09
 914 #define CC_F6_6                 0x11
 915 #define CC_F6_7                 0x21
 916
 917 #define CC_F5_BIAS              5
 918
 919 #define CC_MC_BYPASS            0x08
 920 #define CC_MC_M1                0x04
 921 #define CC_MC_M1M2              0x02
 922 #define CC_MC_M1M2M3            0x01
 923 #define CC_MC_M1M3              0x11
 924
 925
 926 #define CC_T2_BIAS              2
 927 #define CC_T2M2_BIAS            3
 928
 929 #define CC_T2MC_M1BYP           1
 930 #define CC_T2MC_M2BYP           2
 931 #define CC_T2MC_M3BYP           4
 932
 933
 934 #define CC_T6_MMASK             1
 935 #define CC_T6_M0                120000000
 936 #define CC_T6_M1                100000000
 937 #define SB2MIPS_T6(sb)          (2 * (sb))
 938
 939
 940 #define CC_CLOCK_BASE1          24000000
 941 #define CC_CLOCK_BASE2          12500000
 942
 943
 944 #define CLKC_5350_N             0x0311
 945 #define CLKC_5350_M             0x04020009
 946
 947
 948 #define FLASH_NONE              0x000
 949 #define SFLASH_ST               0x100
 950 #define SFLASH_AT               0x200
 951 #define NFLASH                  0x300
 952 #define PFLASH                  0x700
 953 #define QSPIFLASH_ST            0x800
 954 #define QSPIFLASH_AT            0x900
 955
 956
 957 #define CC_CFG_EN               0x0001
 958 #define CC_CFG_EM_MASK          0x000e
 959 #define CC_CFG_EM_ASYNC         0x0000
 960 #define CC_CFG_EM_SYNC          0x0002
 961 #define CC_CFG_EM_PCMCIA        0x0004
 962 #define CC_CFG_EM_IDE           0x0006
 963 #define CC_CFG_DS               0x0010
 964 #define CC_CFG_CD_MASK          0x00e0
 965 #define CC_CFG_CE               0x0100
 966 #define CC_CFG_SB               0x0200
 967 #define CC_CFG_IS               0x0400
 968
 969
 970 #define CC_EB_BASE              0x1a000000
 971 #define CC_EB_PCMCIA_MEM        0x1a000000
 972 #define CC_EB_PCMCIA_IO         0x1a200000
 973 #define CC_EB_PCMCIA_CFG        0x1a400000
 974 #define CC_EB_IDE               0x1a800000
 975 #define CC_EB_PCMCIA1_MEM       0x1a800000
 976 #define CC_EB_PCMCIA1_IO        0x1aa00000
 977 #define CC_EB_PCMCIA1_CFG       0x1ac00000
 978 #define CC_EB_PROGIF            0x1b000000
 979
 980
 981
 982 #define SFLASH_OPCODE           0x000000ff
 983 #define SFLASH_ACTION           0x00000700
 984 #define SFLASH_CS_ACTIVE        0x00001000
 985 #define SFLASH_START            0x80000000
 986 #define SFLASH_BUSY             SFLASH_START
 987
 988
 989 #define SFLASH_ACT_OPONLY       0x0000
 990 #define SFLASH_ACT_OP1D         0x0100
 991 #define SFLASH_ACT_OP3A         0x0200
 992 #define SFLASH_ACT_OP3A1D       0x0300
 993 #define SFLASH_ACT_OP3A4D       0x0400
 994 #define SFLASH_ACT_OP3A4X4D     0x0500
 995 #define SFLASH_ACT_OP3A1X4D     0x0700
 996
 997
 998 #define SFLASH_ST_WREN          0x0006
 999 #define SFLASH_ST_WRDIS         0x0004
1000 #define SFLASH_ST_RDSR          0x0105
1001 #define SFLASH_ST_WRSR          0x0101
1002 #define SFLASH_ST_READ          0x0303
1003 #define SFLASH_ST_PP            0x0302
1004 #define SFLASH_ST_SE            0x02d8
1005 #define SFLASH_ST_BE            0x00c7
1006 #define SFLASH_ST_DP            0x00b9
1007 #define SFLASH_ST_RES           0x03ab
1008 #define SFLASH_ST_CSA           0x1000
1009 #define SFLASH_ST_SSE           0x0220
1010
1011 #define SFLASH_MXIC_RDID        0x0390
1012 #define SFLASH_MXIC_MFID        0xc2
1013
1014
1015 #define SFLASH_ST_WIP           0x01
1016 #define SFLASH_ST_WEL           0x02
1017 #define SFLASH_ST_BP_MASK       0x1c
1018 #define SFLASH_ST_BP_SHIFT      2
1019 #define SFLASH_ST_SRWD          0x80
1020
1021
1022 #define SFLASH_AT_READ                          0x07e8
1023 #define SFLASH_AT_PAGE_READ                     0x07d2
1024 #define SFLASH_AT_BUF1_READ
1025 #define SFLASH_AT_BUF2_READ
1026 #define SFLASH_AT_STATUS                        0x01d7
1027 #define SFLASH_AT_BUF1_WRITE                    0x0384
1028 #define SFLASH_AT_BUF2_WRITE                    0x0387
1029 #define SFLASH_AT_BUF1_ERASE_PROGRAM            0x0283
1030 #define SFLASH_AT_BUF2_ERASE_PROGRAM            0x0286
1031 #define SFLASH_AT_BUF1_PROGRAM                  0x0288
1032 #define SFLASH_AT_BUF2_PROGRAM                  0x0289
1033 #define SFLASH_AT_PAGE_ERASE                    0x0281
1034 #define SFLASH_AT_BLOCK_ERASE                   0x0250
1035 #define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM      0x0382
1036 #define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM      0x0385
1037 #define SFLASH_AT_BUF1_LOAD                     0x0253
1038 #define SFLASH_AT_BUF2_LOAD                     0x0255
1039 #define SFLASH_AT_BUF1_COMPARE                  0x0260
1040 #define SFLASH_AT_BUF2_COMPARE                  0x0261
1041 #define SFLASH_AT_BUF1_REPROGRAM                0x0258
1042 #define SFLASH_AT_BUF2_REPROGRAM                0x0259
1043
1044
1045 #define SFLASH_AT_READY                         0x80
1046 #define SFLASH_AT_MISMATCH                      0x40
1047 #define SFLASH_AT_ID_MASK                       0x38
1048 #define SFLASH_AT_ID_SHIFT                      3
1049
1050
1051 #define GSIO_START                      0x80000000
1052 #define GSIO_BUSY                       GSIO_START
1053
1054
1055
1056 #define UART_RX         0
1057 #define UART_TX         0
1058 #define UART_DLL        0
1059 #define UART_IER        1
1060 #define UART_DLM        1
1061 #define UART_IIR        2
1062 #define UART_FCR        2
1063 #define UART_LCR        3
1064 #define UART_MCR        4
1065 #define UART_LSR        5
1066 #define UART_MSR        6
1067 #define UART_SCR        7
1068 #define UART_LCR_DLAB   0x80
1069 #define UART_LCR_WLEN8  0x03
1070 #define UART_MCR_OUT2   0x08
1071 #define UART_MCR_LOOP   0x10
1072 #define UART_LSR_RX_FIFO        0x80
1073 #define UART_LSR_TDHR           0x40
1074 #define UART_LSR_THRE           0x20
1075 #define UART_LSR_BREAK          0x10
1076 #define UART_LSR_FRAMING        0x08
1077 #define UART_LSR_PARITY         0x04
1078 #define UART_LSR_OVERRUN        0x02
1079 #define UART_LSR_RXRDY          0x01
1080 #define UART_FCR_FIFO_ENABLE 1
1081
1082
1083 #define UART_IIR_FIFO_MASK      0xc0
1084 #define UART_IIR_INT_MASK       0xf
1085 #define UART_IIR_MDM_CHG        0x0
1086 #define UART_IIR_NOINT          0x1
1087 #define UART_IIR_THRE           0x2
1088 #define UART_IIR_RCVD_DATA      0x4
1089 #define UART_IIR_RCVR_STATUS    0x6
1090 #define UART_IIR_CHAR_TIME      0xc
1091
1092
1093 #define UART_IER_EDSSI  8
1094 #define UART_IER_ELSI   4
1095 #define UART_IER_ETBEI  2
1096 #define UART_IER_ERBFI  1
1097
1098
1099 #define PST_EXTLPOAVAIL 0x0100
1100 #define PST_WDRESET     0x0080
1101 #define PST_INTPEND     0x0040
1102 #define PST_SBCLKST     0x0030
1103 #define PST_SBCLKST_ILP 0x0010
1104 #define PST_SBCLKST_ALP 0x0020
1105 #define PST_SBCLKST_HT  0x0030
1106 #define PST_ALPAVAIL    0x0008
1107 #define PST_HTAVAIL     0x0004
1108 #define PST_RESINIT     0x0003
1109
1110
1111 #define PCAP_REV_MASK   0x000000ff
1112 #define PCAP_RC_MASK    0x00001f00
1113 #define PCAP_RC_SHIFT   8
1114 #define PCAP_TC_MASK    0x0001e000
1115 #define PCAP_TC_SHIFT   13
1116 #define PCAP_PC_MASK    0x001e0000
1117 #define PCAP_PC_SHIFT   17
1118 #define PCAP_VC_MASK    0x01e00000
1119 #define PCAP_VC_SHIFT   21
1120 #define PCAP_CC_MASK    0x1e000000
1121 #define PCAP_CC_SHIFT   25
1122 #define PCAP5_PC_MASK   0x003e0000
1123 #define PCAP5_PC_SHIFT  17
1124 #define PCAP5_VC_MASK   0x07c00000
1125 #define PCAP5_VC_SHIFT  22
1126 #define PCAP5_CC_MASK   0xf8000000
1127 #define PCAP5_CC_SHIFT  27
1128
1129
1130
1131 #define PRRT_TIME_MASK  0x03ff
1132 #define PRRT_INTEN      0x0400
1133 #define PRRT_REQ_ACTIVE 0x0800
1134 #define PRRT_ALP_REQ    0x1000
1135 #define PRRT_HT_REQ     0x2000
1136 #define PRRT_HQ_REQ 0x4000
1137
1138
1139 #define PMURES_BIT(bit) (1 << (bit))
1140
1141
1142 #define PMURES_MAX_RESNUM       30
1143
1144
1145 #define PMU_CHIPCTL0            0
1146 #define PMU43143_CC0_SDIO_DRSTR_OVR     (1 << 31)
1147
1148
1149 #define PMU_CC1_CLKREQ_TYPE_SHIFT       19
1150 #define PMU_CC1_CLKREQ_TYPE_MASK        (1 << PMU_CC1_CLKREQ_TYPE_SHIFT)
1151
1152 #define CLKREQ_TYPE_CONFIG_OPENDRAIN            0
1153 #define CLKREQ_TYPE_CONFIG_PUSHPULL             1
1154
1155
1156 #define PMU_CHIPCTL1                    1
1157 #define PMU_CC1_RXC_DLL_BYPASS          0x00010000
1158
1159 #define PMU_CC1_IF_TYPE_MASK            0x00000030
1160 #define PMU_CC1_IF_TYPE_RMII            0x00000000
1161 #define PMU_CC1_IF_TYPE_MII             0x00000010
1162 #define PMU_CC1_IF_TYPE_RGMII           0x00000020
1163
1164 #define PMU_CC1_SW_TYPE_MASK            0x000000c0
1165 #define PMU_CC1_SW_TYPE_EPHY            0x00000000
1166 #define PMU_CC1_SW_TYPE_EPHYMII         0x00000040
1167 #define PMU_CC1_SW_TYPE_EPHYRMII        0x00000080
1168 #define PMU_CC1_SW_TYPE_RGMII           0x000000c0
1169
1170
1171 #define PMU_CHIPCTL2            2
1172
1173
1174 #define PMU_CHIPCTL3            3
1175
1176 #define PMU_CC3_ENABLE_SDIO_WAKEUP_SHIFT  19
1177 #define PMU_CC3_ENABLE_RF_SHIFT           22
1178 #define PMU_CC3_RF_DISABLE_IVALUE_SHIFT   23
1179
1180
1181 #define PMU_CHIPCTL5                    5
1182
1183
1184
1185
1186
1187 #define PMU0_PLL0_PLLCTL0               0
1188 #define PMU0_PLL0_PC0_PDIV_MASK         1
1189 #define PMU0_PLL0_PC0_PDIV_FREQ         25000
1190 #define PMU0_PLL0_PC0_DIV_ARM_MASK      0x00000038
1191 #define PMU0_PLL0_PC0_DIV_ARM_SHIFT     3
1192 #define PMU0_PLL0_PC0_DIV_ARM_BASE      8
1193
1194
1195 #define PMU0_PLL0_PC0_DIV_ARM_110MHZ    0
1196 #define PMU0_PLL0_PC0_DIV_ARM_97_7MHZ   1
1197 #define PMU0_PLL0_PC0_DIV_ARM_88MHZ     2
1198 #define PMU0_PLL0_PC0_DIV_ARM_80MHZ     3
1199 #define PMU0_PLL0_PC0_DIV_ARM_73_3MHZ   4
1200 #define PMU0_PLL0_PC0_DIV_ARM_67_7MHZ   5
1201 #define PMU0_PLL0_PC0_DIV_ARM_62_9MHZ   6
1202 #define PMU0_PLL0_PC0_DIV_ARM_58_6MHZ   7
1203
1204
1205 #define PMU0_PLL0_PLLCTL1               1
1206 #define PMU0_PLL0_PC1_WILD_INT_MASK     0xf0000000
1207 #define PMU0_PLL0_PC1_WILD_INT_SHIFT    28
1208 #define PMU0_PLL0_PC1_WILD_FRAC_MASK    0x0fffff00
1209 #define PMU0_PLL0_PC1_WILD_FRAC_SHIFT   8
1210 #define PMU0_PLL0_PC1_STOP_MOD          0x00000040
1211
1212
1213 #define PMU0_PLL0_PLLCTL2               2
1214 #define PMU0_PLL0_PC2_WILD_INT_MASK     0xf
1215 #define PMU0_PLL0_PC2_WILD_INT_SHIFT    4
1216
1217
1218
1219 #define PMU1_PLL0_PLLCTL0               0
1220 #define PMU1_PLL0_PC0_P1DIV_MASK        0x00f00000
1221 #define PMU1_PLL0_PC0_P1DIV_SHIFT       20
1222 #define PMU1_PLL0_PC0_P2DIV_MASK        0x0f000000
1223 #define PMU1_PLL0_PC0_P2DIV_SHIFT       24
1224
1225
1226 #define PMU1_PLL0_PLLCTL1               1
1227 #define PMU1_PLL0_PC1_M1DIV_MASK        0x000000ff
1228 #define PMU1_PLL0_PC1_M1DIV_SHIFT       0
1229 #define PMU1_PLL0_PC1_M2DIV_MASK        0x0000ff00
1230 #define PMU1_PLL0_PC1_M2DIV_SHIFT       8
1231 #define PMU1_PLL0_PC1_M3DIV_MASK        0x00ff0000
1232 #define PMU1_PLL0_PC1_M3DIV_SHIFT       16
1233 #define PMU1_PLL0_PC1_M4DIV_MASK        0xff000000
1234 #define PMU1_PLL0_PC1_M4DIV_SHIFT       24
1235 #define PMU1_PLL0_PC1_M4DIV_BY_9        9
1236 #define PMU1_PLL0_PC1_M4DIV_BY_18       0x12
1237 #define PMU1_PLL0_PC1_M4DIV_BY_36       0x24
1238
1239 #define DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT 8
1240 #define DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT)
1241 #define DOT11MAC_880MHZ_CLK_DIVISOR_VAL  (0xE << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT)
1242
1243
1244 #define PMU1_PLL0_PLLCTL2               2
1245 #define PMU1_PLL0_PC2_M5DIV_MASK        0x000000ff
1246 #define PMU1_PLL0_PC2_M5DIV_SHIFT       0
1247 #define PMU1_PLL0_PC2_M5DIV_BY_12       0xc
1248 #define PMU1_PLL0_PC2_M5DIV_BY_18       0x12
1249 #define PMU1_PLL0_PC2_M5DIV_BY_36       0x24
1250 #define PMU1_PLL0_PC2_M6DIV_MASK        0x0000ff00
1251 #define PMU1_PLL0_PC2_M6DIV_SHIFT       8
1252 #define PMU1_PLL0_PC2_M6DIV_BY_18       0x12
1253 #define PMU1_PLL0_PC2_M6DIV_BY_36       0x24
1254 #define PMU1_PLL0_PC2_NDIV_MODE_MASK    0x000e0000
1255 #define PMU1_PLL0_PC2_NDIV_MODE_SHIFT   17
1256 #define PMU1_PLL0_PC2_NDIV_MODE_MASH    1
1257 #define PMU1_PLL0_PC2_NDIV_MODE_MFB     2
1258 #define PMU1_PLL0_PC2_NDIV_INT_MASK     0x1ff00000
1259 #define PMU1_PLL0_PC2_NDIV_INT_SHIFT    20
1260
1261
1262 #define PMU1_PLL0_PLLCTL3               3
1263 #define PMU1_PLL0_PC3_NDIV_FRAC_MASK    0x00ffffff
1264 #define PMU1_PLL0_PC3_NDIV_FRAC_SHIFT   0
1265
1266
1267 #define PMU1_PLL0_PLLCTL4               4
1268
1269
1270 #define PMU1_PLL0_PLLCTL5               5
1271 #define PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00
1272 #define PMU1_PLL0_PC5_CLK_DRV_SHIFT 8
1273
1274
1275 #define PMU2_PHY_PLL_PLLCTL             4
1276 #define PMU2_SI_PLL_PLLCTL              10
1277
1278
1279
1280
1281 #define PMU2_PLL_PLLCTL0                0
1282 #define PMU2_PLL_PC0_P1DIV_MASK         0x00f00000
1283 #define PMU2_PLL_PC0_P1DIV_SHIFT        20
1284 #define PMU2_PLL_PC0_P2DIV_MASK         0x0f000000
1285 #define PMU2_PLL_PC0_P2DIV_SHIFT        24
1286
1287
1288 #define PMU2_PLL_PLLCTL1                1
1289 #define PMU2_PLL_PC1_M1DIV_MASK         0x000000ff
1290 #define PMU2_PLL_PC1_M1DIV_SHIFT        0
1291 #define PMU2_PLL_PC1_M2DIV_MASK         0x0000ff00
1292 #define PMU2_PLL_PC1_M2DIV_SHIFT        8
1293 #define PMU2_PLL_PC1_M3DIV_MASK         0x00ff0000
1294 #define PMU2_PLL_PC1_M3DIV_SHIFT        16
1295 #define PMU2_PLL_PC1_M4DIV_MASK         0xff000000
1296 #define PMU2_PLL_PC1_M4DIV_SHIFT        24
1297
1298
1299 #define PMU2_PLL_PLLCTL2                2
1300 #define PMU2_PLL_PC2_M5DIV_MASK         0x000000ff
1301 #define PMU2_PLL_PC2_M5DIV_SHIFT        0
1302 #define PMU2_PLL_PC2_M6DIV_MASK         0x0000ff00
1303 #define PMU2_PLL_PC2_M6DIV_SHIFT        8
1304 #define PMU2_PLL_PC2_NDIV_MODE_MASK     0x000e0000
1305 #define PMU2_PLL_PC2_NDIV_MODE_SHIFT    17
1306 #define PMU2_PLL_PC2_NDIV_INT_MASK      0x1ff00000
1307 #define PMU2_PLL_PC2_NDIV_INT_SHIFT     20
1308
1309
1310 #define PMU2_PLL_PLLCTL3                3
1311 #define PMU2_PLL_PC3_NDIV_FRAC_MASK     0x00ffffff
1312 #define PMU2_PLL_PC3_NDIV_FRAC_SHIFT    0
1313
1314
1315 #define PMU2_PLL_PLLCTL4                4
1316
1317
1318 #define PMU2_PLL_PLLCTL5                5
1319 #define PMU2_PLL_PC5_CLKDRIVE_CH1_MASK  0x00000f00
1320 #define PMU2_PLL_PC5_CLKDRIVE_CH1_SHIFT 8
1321 #define PMU2_PLL_PC5_CLKDRIVE_CH2_MASK  0x0000f000
1322 #define PMU2_PLL_PC5_CLKDRIVE_CH2_SHIFT 12
1323 #define PMU2_PLL_PC5_CLKDRIVE_CH3_MASK  0x000f0000
1324 #define PMU2_PLL_PC5_CLKDRIVE_CH3_SHIFT 16
1325 #define PMU2_PLL_PC5_CLKDRIVE_CH4_MASK  0x00f00000
1326 #define PMU2_PLL_PC5_CLKDRIVE_CH4_SHIFT 20
1327 #define PMU2_PLL_PC5_CLKDRIVE_CH5_MASK  0x0f000000
1328 #define PMU2_PLL_PC5_CLKDRIVE_CH5_SHIFT 24
1329 #define PMU2_PLL_PC5_CLKDRIVE_CH6_MASK  0xf0000000
1330 #define PMU2_PLL_PC5_CLKDRIVE_CH6_SHIFT 28
1331
1332
1333 #define PMU5_PLL_P1P2_OFF               0
1334 #define PMU5_PLL_P1_MASK                0x0f000000
1335 #define PMU5_PLL_P1_SHIFT               24
1336 #define PMU5_PLL_P2_MASK                0x00f00000
1337 #define PMU5_PLL_P2_SHIFT               20
1338 #define PMU5_PLL_M14_OFF                1
1339 #define PMU5_PLL_MDIV_MASK              0x000000ff
1340 #define PMU5_PLL_MDIV_WIDTH             8
1341 #define PMU5_PLL_NM5_OFF                2
1342 #define PMU5_PLL_NDIV_MASK              0xfff00000
1343 #define PMU5_PLL_NDIV_SHIFT             20
1344 #define PMU5_PLL_NDIV_MODE_MASK         0x000e0000
1345 #define PMU5_PLL_NDIV_MODE_SHIFT        17
1346 #define PMU5_PLL_FMAB_OFF               3
1347 #define PMU5_PLL_MRAT_MASK              0xf0000000
1348 #define PMU5_PLL_MRAT_SHIFT             28
1349 #define PMU5_PLL_ABRAT_MASK             0x08000000
1350 #define PMU5_PLL_ABRAT_SHIFT            27
1351 #define PMU5_PLL_FDIV_MASK              0x07ffffff
1352 #define PMU5_PLL_PLLCTL_OFF             4
1353 #define PMU5_PLL_PCHI_OFF               5
1354 #define PMU5_PLL_PCHI_MASK              0x0000003f
1355
1356
1357 #define PMU_XTALFREQ_REG_ILPCTR_MASK    0x00001FFF
1358 #define PMU_XTALFREQ_REG_MEASURE_MASK   0x80000000
1359 #define PMU_XTALFREQ_REG_MEASURE_SHIFT  31
1360
1361
1362 #define PMU5_MAINPLL_CPU                1
1363 #define PMU5_MAINPLL_MEM                2
1364 #define PMU5_MAINPLL_SI                 3
1365
1366
1367 #define PMU4706_MAINPLL_PLL0    0
1368 #define PMU6_4706_PROCPLL_OFF   4
1369 #define PMU6_4706_PROC_P2DIV_MASK               0x000f0000
1370 #define PMU6_4706_PROC_P2DIV_SHIFT      16
1371 #define PMU6_4706_PROC_P1DIV_MASK               0x0000f000
1372 #define PMU6_4706_PROC_P1DIV_SHIFT      12
1373 #define PMU6_4706_PROC_NDIV_INT_MASK    0x00000ff8
1374 #define PMU6_4706_PROC_NDIV_INT_SHIFT   3
1375 #define PMU6_4706_PROC_NDIV_MODE_MASK           0x00000007
1376 #define PMU6_4706_PROC_NDIV_MODE_SHIFT  0
1377
1378 #define PMU7_PLL_PLLCTL7                7
1379 #define PMU7_PLL_CTL7_M4DIV_MASK        0xff000000
1380 #define PMU7_PLL_CTL7_M4DIV_SHIFT       24
1381 #define PMU7_PLL_CTL7_M4DIV_BY_6        6
1382 #define PMU7_PLL_CTL7_M4DIV_BY_12       0xc
1383 #define PMU7_PLL_CTL7_M4DIV_BY_24       0x18
1384 #define PMU7_PLL_PLLCTL8                8
1385 #define PMU7_PLL_CTL8_M5DIV_MASK        0x000000ff
1386 #define PMU7_PLL_CTL8_M5DIV_SHIFT       0
1387 #define PMU7_PLL_CTL8_M5DIV_BY_8        8
1388 #define PMU7_PLL_CTL8_M5DIV_BY_12       0xc
1389 #define PMU7_PLL_CTL8_M5DIV_BY_24       0x18
1390 #define PMU7_PLL_CTL8_M6DIV_MASK        0x0000ff00
1391 #define PMU7_PLL_CTL8_M6DIV_SHIFT       8
1392 #define PMU7_PLL_CTL8_M6DIV_BY_12       0xc
1393 #define PMU7_PLL_CTL8_M6DIV_BY_24       0x18
1394 #define PMU7_PLL_PLLCTL11               11
1395 #define PMU7_PLL_PLLCTL11_MASK          0xffffff00
1396 #define PMU7_PLL_PLLCTL11_VAL           0x22222200
1397
1398
1399 #define PMU15_PLL_PLLCTL0               0
1400 #define PMU15_PLL_PC0_CLKSEL_MASK       0x00000003
1401 #define PMU15_PLL_PC0_CLKSEL_SHIFT      0
1402 #define PMU15_PLL_PC0_FREQTGT_MASK      0x003FFFFC
1403 #define PMU15_PLL_PC0_FREQTGT_SHIFT     2
1404 #define PMU15_PLL_PC0_PRESCALE_MASK     0x00C00000
1405 #define PMU15_PLL_PC0_PRESCALE_SHIFT    22
1406 #define PMU15_PLL_PC0_KPCTRL_MASK       0x07000000
1407 #define PMU15_PLL_PC0_KPCTRL_SHIFT      24
1408 #define PMU15_PLL_PC0_FCNTCTRL_MASK     0x38000000
1409 #define PMU15_PLL_PC0_FCNTCTRL_SHIFT    27
1410 #define PMU15_PLL_PC0_FDCMODE_MASK      0x40000000
1411 #define PMU15_PLL_PC0_FDCMODE_SHIFT     30
1412 #define PMU15_PLL_PC0_CTRLBIAS_MASK     0x80000000
1413 #define PMU15_PLL_PC0_CTRLBIAS_SHIFT    31
1414
1415 #define PMU15_PLL_PLLCTL1                       1
1416 #define PMU15_PLL_PC1_BIAS_CTLM_MASK            0x00000060
1417 #define PMU15_PLL_PC1_BIAS_CTLM_SHIFT           5
1418 #define PMU15_PLL_PC1_BIAS_CTLM_RST_MASK        0x00000040
1419 #define PMU15_PLL_PC1_BIAS_CTLM_RST_SHIFT       6
1420 #define PMU15_PLL_PC1_BIAS_SS_DIVR_MASK         0x0001FF80
1421 #define PMU15_PLL_PC1_BIAS_SS_DIVR_SHIFT        7
1422 #define PMU15_PLL_PC1_BIAS_SS_RSTVAL_MASK       0x03FE0000
1423 #define PMU15_PLL_PC1_BIAS_SS_RSTVAL_SHIFT      17
1424 #define PMU15_PLL_PC1_BIAS_INTG_BW_MASK         0x0C000000
1425 #define PMU15_PLL_PC1_BIAS_INTG_BW_SHIFT        26
1426 #define PMU15_PLL_PC1_BIAS_INTG_BYP_MASK        0x10000000
1427 #define PMU15_PLL_PC1_BIAS_INTG_BYP_SHIFT       28
1428 #define PMU15_PLL_PC1_OPENLP_EN_MASK            0x40000000
1429 #define PMU15_PLL_PC1_OPENLP_EN_SHIFT           30
1430
1431 #define PMU15_PLL_PLLCTL2                       2
1432 #define PMU15_PLL_PC2_CTEN_MASK                 0x00000001
1433 #define PMU15_PLL_PC2_CTEN_SHIFT                0
1434
1435 #define PMU15_PLL_PLLCTL3                       3
1436 #define PMU15_PLL_PC3_DITHER_EN_MASK            0x00000001
1437 #define PMU15_PLL_PC3_DITHER_EN_SHIFT           0
1438 #define PMU15_PLL_PC3_DCOCTLSP_MASK             0xFE000000
1439 #define PMU15_PLL_PC3_DCOCTLSP_SHIFT            25
1440 #define PMU15_PLL_PC3_DCOCTLSP_DIV2EN_MASK      0x01
1441 #define PMU15_PLL_PC3_DCOCTLSP_DIV2EN_SHIFT     0
1442 #define PMU15_PLL_PC3_DCOCTLSP_CH0EN_MASK       0x02
1443 #define PMU15_PLL_PC3_DCOCTLSP_CH0EN_SHIFT      1
1444 #define PMU15_PLL_PC3_DCOCTLSP_CH1EN_MASK       0x04
1445 #define PMU15_PLL_PC3_DCOCTLSP_CH1EN_SHIFT      2
1446 #define PMU15_PLL_PC3_DCOCTLSP_CH0SEL_MASK      0x18
1447 #define PMU15_PLL_PC3_DCOCTLSP_CH0SEL_SHIFT     3
1448 #define PMU15_PLL_PC3_DCOCTLSP_CH1SEL_MASK      0x60
1449 #define PMU15_PLL_PC3_DCOCTLSP_CH1SEL_SHIFT     5
1450 #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV1  0
1451 #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV2  1
1452 #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV3  2
1453 #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV5  3
1454
1455 #define PMU15_PLL_PLLCTL4                       4
1456 #define PMU15_PLL_PC4_FLLCLK1_DIV_MASK          0x00000007
1457 #define PMU15_PLL_PC4_FLLCLK1_DIV_SHIFT         0
1458 #define PMU15_PLL_PC4_FLLCLK2_DIV_MASK          0x00000038
1459 #define PMU15_PLL_PC4_FLLCLK2_DIV_SHIFT         3
1460 #define PMU15_PLL_PC4_FLLCLK3_DIV_MASK          0x000001C0
1461 #define PMU15_PLL_PC4_FLLCLK3_DIV_SHIFT         6
1462 #define PMU15_PLL_PC4_DBGMODE_MASK              0x00000E00
1463 #define PMU15_PLL_PC4_DBGMODE_SHIFT             9
1464 #define PMU15_PLL_PC4_FLL480_CTLSP_LK_MASK      0x00001000
1465 #define PMU15_PLL_PC4_FLL480_CTLSP_LK_SHIFT     12
1466 #define PMU15_PLL_PC4_FLL480_CTLSP_MASK         0x000FE000
1467 #define PMU15_PLL_PC4_FLL480_CTLSP_SHIFT        13
1468 #define PMU15_PLL_PC4_DINPOL_MASK               0x00100000
1469 #define PMU15_PLL_PC4_DINPOL_SHIFT              20
1470 #define PMU15_PLL_PC4_CLKOUT_PD_MASK            0x00200000
1471 #define PMU15_PLL_PC4_CLKOUT_PD_SHIFT           21
1472 #define PMU15_PLL_PC4_CLKDIV2_PD_MASK           0x00400000
1473 #define PMU15_PLL_PC4_CLKDIV2_PD_SHIFT          22
1474 #define PMU15_PLL_PC4_CLKDIV4_PD_MASK           0x00800000
1475 #define PMU15_PLL_PC4_CLKDIV4_PD_SHIFT          23
1476 #define PMU15_PLL_PC4_CLKDIV8_PD_MASK           0x01000000
1477 #define PMU15_PLL_PC4_CLKDIV8_PD_SHIFT          24
1478 #define PMU15_PLL_PC4_CLKDIV16_PD_MASK          0x02000000
1479 #define PMU15_PLL_PC4_CLKDIV16_PD_SHIFT         25
1480 #define PMU15_PLL_PC4_TEST_EN_MASK              0x04000000
1481 #define PMU15_PLL_PC4_TEST_EN_SHIFT             26
1482
1483 #define PMU15_PLL_PLLCTL5                       5
1484 #define PMU15_PLL_PC5_FREQTGT_MASK              0x000FFFFF
1485 #define PMU15_PLL_PC5_FREQTGT_SHIFT             0
1486 #define PMU15_PLL_PC5_DCOCTLSP_MASK             0x07F00000
1487 #define PMU15_PLL_PC5_DCOCTLSP_SHIFT            20
1488 #define PMU15_PLL_PC5_PRESCALE_MASK             0x18000000
1489 #define PMU15_PLL_PC5_PRESCALE_SHIFT            27
1490
1491 #define PMU15_PLL_PLLCTL6               6
1492 #define PMU15_PLL_PC6_FREQTGT_MASK      0x000FFFFF
1493 #define PMU15_PLL_PC6_FREQTGT_SHIFT     0
1494 #define PMU15_PLL_PC6_DCOCTLSP_MASK     0x07F00000
1495 #define PMU15_PLL_PC6_DCOCTLSP_SHIFT    20
1496 #define PMU15_PLL_PC6_PRESCALE_MASK     0x18000000
1497 #define PMU15_PLL_PC6_PRESCALE_SHIFT    27
1498
1499 #define PMU15_FREQTGT_480_DEFAULT       0x19AB1
1500 #define PMU15_FREQTGT_492_DEFAULT       0x1A4F5
1501 #define PMU15_ARM_96MHZ                 96000000
1502 #define PMU15_ARM_98MHZ                 98400000
1503 #define PMU15_ARM_97MHZ                 97000000
1504
1505
1506 #define PMU17_PLLCTL2_NDIVTYPE_MASK             0x00000070
1507 #define PMU17_PLLCTL2_NDIVTYPE_SHIFT            4
1508
1509 #define PMU17_PLLCTL2_NDIV_MODE_INT             0
1510 #define PMU17_PLLCTL2_NDIV_MODE_INT1B8          1
1511 #define PMU17_PLLCTL2_NDIV_MODE_MASH111         2
1512 #define PMU17_PLLCTL2_NDIV_MODE_MASH111B8       3
1513
1514 #define PMU17_PLLCTL0_BBPLL_PWRDWN              0
1515 #define PMU17_PLLCTL0_BBPLL_DRST                3
1516 #define PMU17_PLLCTL0_BBPLL_DISBL_CLK           8
1517
1518
1519 #define PMU4716_MAINPLL_PLL0            12
1520
1521
1522 #define PMU5356_MAINPLL_PLL0            0
1523 #define PMU5357_MAINPLL_PLL0            0
1524
1525
1526 #define RES4716_PROC_PLL_ON             0x00000040
1527 #define RES4716_PROC_HT_AVAIL           0x00000080
1528
1529
1530 #define CCTRL_471X_I2S_PINS_ENABLE      0x0080
1531
1532
1533
1534 #define CCTRL_5357_I2S_PINS_ENABLE      0x00040000
1535 #define CCTRL_5357_I2CSPI_PINS_ENABLE   0x00080000
1536
1537
1538 #define RES5354_EXT_SWITCHER_PWM        0
1539 #define RES5354_BB_SWITCHER_PWM         1
1540 #define RES5354_BB_SWITCHER_BURST       2
1541 #define RES5354_BB_EXT_SWITCHER_BURST   3
1542 #define RES5354_ILP_REQUEST             4
1543 #define RES5354_RADIO_SWITCHER_PWM      5
1544 #define RES5354_RADIO_SWITCHER_BURST    6
1545 #define RES5354_ROM_SWITCH              7
1546 #define RES5354_PA_REF_LDO              8
1547 #define RES5354_RADIO_LDO               9
1548 #define RES5354_AFE_LDO                 10
1549 #define RES5354_PLL_LDO                 11
1550 #define RES5354_BG_FILTBYP              12
1551 #define RES5354_TX_FILTBYP              13
1552 #define RES5354_RX_FILTBYP              14
1553 #define RES5354_XTAL_PU                 15
1554 #define RES5354_XTAL_EN                 16
1555 #define RES5354_BB_PLL_FILTBYP          17
1556 #define RES5354_RF_PLL_FILTBYP          18
1557 #define RES5354_BB_PLL_PU               19
1558
1559
1560 #define CCTRL5357_EXTPA                 (1<<14)
1561 #define CCTRL5357_ANT_MUX_2o3           (1<<15)
1562 #define CCTRL5357_NFLASH                (1<<16)
1563
1564
1565 #define CCTRL43217_EXTPA_C0             (1<<13)
1566 #define CCTRL43217_EXTPA_C1             (1<<8)
1567
1568
1569 #define CCTRL43228_EXTPA_C0             (1<<14)
1570 #define CCTRL43228_EXTPA_C1             (1<<9)
1571
1572
1573 #define RES4328_EXT_SWITCHER_PWM        0
1574 #define RES4328_BB_SWITCHER_PWM         1
1575 #define RES4328_BB_SWITCHER_BURST       2
1576 #define RES4328_BB_EXT_SWITCHER_BURST   3
1577 #define RES4328_ILP_REQUEST             4
1578 #define RES4328_RADIO_SWITCHER_PWM      5
1579 #define RES4328_RADIO_SWITCHER_BURST    6
1580 #define RES4328_ROM_SWITCH              7
1581 #define RES4328_PA_REF_LDO              8
1582 #define RES4328_RADIO_LDO               9
1583 #define RES4328_AFE_LDO                 10
1584 #define RES4328_PLL_LDO                 11
1585 #define RES4328_BG_FILTBYP              12
1586 #define RES4328_TX_FILTBYP              13
1587 #define RES4328_RX_FILTBYP              14
1588 #define RES4328_XTAL_PU                 15
1589 #define RES4328_XTAL_EN                 16
1590 #define RES4328_BB_PLL_FILTBYP          17
1591 #define RES4328_RF_PLL_FILTBYP          18
1592 #define RES4328_BB_PLL_PU               19
1593
1594
1595 #define RES4325_BUCK_BOOST_BURST        0
1596 #define RES4325_CBUCK_BURST             1
1597 #define RES4325_CBUCK_PWM               2
1598 #define RES4325_CLDO_CBUCK_BURST        3
1599 #define RES4325_CLDO_CBUCK_PWM          4
1600 #define RES4325_BUCK_BOOST_PWM          5
1601 #define RES4325_ILP_REQUEST             6
1602 #define RES4325_ABUCK_BURST             7
1603 #define RES4325_ABUCK_PWM               8
1604 #define RES4325_LNLDO1_PU               9
1605 #define RES4325_OTP_PU                  10
1606 #define RES4325_LNLDO3_PU               11
1607 #define RES4325_LNLDO4_PU               12
1608 #define RES4325_XTAL_PU                 13
1609 #define RES4325_ALP_AVAIL               14
1610 #define RES4325_RX_PWRSW_PU             15
1611 #define RES4325_TX_PWRSW_PU             16
1612 #define RES4325_RFPLL_PWRSW_PU          17
1613 #define RES4325_LOGEN_PWRSW_PU          18
1614 #define RES4325_AFE_PWRSW_PU            19
1615 #define RES4325_BBPLL_PWRSW_PU          20
1616 #define RES4325_HT_AVAIL                21
1617
1618
1619 #define RES4325B0_CBUCK_LPOM            1
1620 #define RES4325B0_CBUCK_BURST           2
1621 #define RES4325B0_CBUCK_PWM             3
1622 #define RES4325B0_CLDO_PU               4
1623
1624
1625 #define RES4325C1_LNLDO2_PU             12
1626
1627
1628 #define CST4325_SPROM_OTP_SEL_MASK      0x00000003
1629 #define CST4325_DEFCIS_SEL              0
1630 #define CST4325_SPROM_SEL               1
1631 #define CST4325_OTP_SEL                 2
1632 #define CST4325_OTP_PWRDN               3
1633 #define CST4325_SDIO_USB_MODE_MASK      0x00000004
1634 #define CST4325_SDIO_USB_MODE_SHIFT     2
1635 #define CST4325_RCAL_VALID_MASK         0x00000008
1636 #define CST4325_RCAL_VALID_SHIFT        3
1637 #define CST4325_RCAL_VALUE_MASK         0x000001f0
1638 #define CST4325_RCAL_VALUE_SHIFT        4
1639 #define CST4325_PMUTOP_2B_MASK          0x00000200
1640 #define CST4325_PMUTOP_2B_SHIFT         9
1641
1642 #define RES4329_RESERVED0               0
1643 #define RES4329_CBUCK_LPOM              1
1644 #define RES4329_CBUCK_BURST             2
1645 #define RES4329_CBUCK_PWM               3
1646 #define RES4329_CLDO_PU                 4
1647 #define RES4329_PALDO_PU                5
1648 #define RES4329_ILP_REQUEST             6
1649 #define RES4329_RESERVED7               7
1650 #define RES4329_RESERVED8               8
1651 #define RES4329_LNLDO1_PU               9
1652 #define RES4329_OTP_PU                  10
1653 #define RES4329_RESERVED11              11
1654 #define RES4329_LNLDO2_PU               12
1655 #define RES4329_XTAL_PU                 13
1656 #define RES4329_ALP_AVAIL               14
1657 #define RES4329_RX_PWRSW_PU             15
1658 #define RES4329_TX_PWRSW_PU             16
1659 #define RES4329_RFPLL_PWRSW_PU          17
1660 #define RES4329_LOGEN_PWRSW_PU          18
1661 #define RES4329_AFE_PWRSW_PU            19
1662 #define RES4329_BBPLL_PWRSW_PU          20
1663 #define RES4329_HT_AVAIL                21
1664
1665 #define CST4329_SPROM_OTP_SEL_MASK      0x00000003
1666 #define CST4329_DEFCIS_SEL              0
1667 #define CST4329_SPROM_SEL               1
1668 #define CST4329_OTP_SEL                 2
1669 #define CST4329_OTP_PWRDN               3
1670 #define CST4329_SPI_SDIO_MODE_MASK      0x00000004
1671 #define CST4329_SPI_SDIO_MODE_SHIFT     2
1672
1673
1674 #define CST4312_SPROM_OTP_SEL_MASK      0x00000003
1675 #define CST4312_DEFCIS_SEL              0
1676 #define CST4312_SPROM_SEL               1
1677 #define CST4312_OTP_SEL                 2
1678 #define CST4312_OTP_BAD                 3
1679
1680
1681 #define RES4312_SWITCHER_BURST          0
1682 #define RES4312_SWITCHER_PWM            1
1683 #define RES4312_PA_REF_LDO              2
1684 #define RES4312_CORE_LDO_BURST          3
1685 #define RES4312_CORE_LDO_PWM            4
1686 #define RES4312_RADIO_LDO               5
1687 #define RES4312_ILP_REQUEST             6
1688 #define RES4312_BG_FILTBYP              7
1689 #define RES4312_TX_FILTBYP              8
1690 #define RES4312_RX_FILTBYP              9
1691 #define RES4312_XTAL_PU                 10
1692 #define RES4312_ALP_AVAIL               11
1693 #define RES4312_BB_PLL_FILTBYP          12
1694 #define RES4312_RF_PLL_FILTBYP          13
1695 #define RES4312_HT_AVAIL                14
1696
1697
1698 #define RES4322_RF_LDO                  0
1699 #define RES4322_ILP_REQUEST             1
1700 #define RES4322_XTAL_PU                 2
1701 #define RES4322_ALP_AVAIL               3
1702 #define RES4322_SI_PLL_ON               4
1703 #define RES4322_HT_SI_AVAIL             5
1704 #define RES4322_PHY_PLL_ON              6
1705 #define RES4322_HT_PHY_AVAIL            7
1706 #define RES4322_OTP_PU                  8
1707
1708
1709 #define CST4322_XTAL_FREQ_20_40MHZ      0x00000020
1710 #define CST4322_SPROM_OTP_SEL_MASK      0x000000c0
1711 #define CST4322_SPROM_OTP_SEL_SHIFT     6
1712 #define CST4322_NO_SPROM_OTP            0
1713 #define CST4322_SPROM_PRESENT           1
1714 #define CST4322_OTP_PRESENT             2
1715 #define CST4322_PCI_OR_USB              0x00000100
1716 #define CST4322_BOOT_MASK               0x00000600
1717 #define CST4322_BOOT_SHIFT              9
1718 #define CST4322_BOOT_FROM_SRAM          0
1719 #define CST4322_BOOT_FROM_ROM           1
1720 #define CST4322_BOOT_FROM_FLASH         2
1721 #define CST4322_BOOT_FROM_INVALID       3
1722 #define CST4322_ILP_DIV_EN              0x00000800
1723 #define CST4322_FLASH_TYPE_MASK         0x00001000
1724 #define CST4322_FLASH_TYPE_SHIFT        12
1725 #define CST4322_FLASH_TYPE_SHIFT_ST     0
1726 #define CST4322_FLASH_TYPE_SHIFT_ATMEL  1
1727 #define CST4322_ARM_TAP_SEL             0x00002000
1728 #define CST4322_RES_INIT_MODE_MASK      0x0000c000
1729 #define CST4322_RES_INIT_MODE_SHIFT     14
1730 #define CST4322_RES_INIT_MODE_ILPAVAIL  0
1731 #define CST4322_RES_INIT_MODE_ILPREQ    1
1732 #define CST4322_RES_INIT_MODE_ALPAVAIL  2
1733 #define CST4322_RES_INIT_MODE_HTAVAIL   3
1734 #define CST4322_PCIPLLCLK_GATING        0x00010000
1735 #define CST4322_CLK_SWITCH_PCI_TO_ALP   0x00020000
1736 #define CST4322_PCI_CARDBUS_MODE        0x00040000
1737
1738
1739 #define CCTRL43224_GPIO_TOGGLE          0x8000
1740 #define CCTRL_43224A0_12MA_LED_DRIVE    0x00F000F0
1741 #define CCTRL_43224B0_12MA_LED_DRIVE    0xF0
1742
1743
1744 #define RES43236_REGULATOR              0
1745 #define RES43236_ILP_REQUEST            1
1746 #define RES43236_XTAL_PU                2
1747 #define RES43236_ALP_AVAIL              3
1748 #define RES43236_SI_PLL_ON              4
1749 #define RES43236_HT_SI_AVAIL            5
1750
1751
1752 #define CCTRL43236_BT_COEXIST           (1<<0)
1753 #define CCTRL43236_SECI                 (1<<1)
1754 #define CCTRL43236_EXT_LNA              (1<<2)
1755 #define CCTRL43236_ANT_MUX_2o3          (1<<3)
1756 #define CCTRL43236_GSIO                 (1<<4)
1757
1758
1759 #define CST43236_SFLASH_MASK            0x00000040
1760 #define CST43236_OTP_SEL_MASK           0x00000080
1761 #define CST43236_OTP_SEL_SHIFT          7
1762 #define CST43236_HSIC_MASK              0x00000100
1763 #define CST43236_BP_CLK                 0x00000200
1764 #define CST43236_BOOT_MASK              0x00001800
1765 #define CST43236_BOOT_SHIFT             11
1766 #define CST43236_BOOT_FROM_SRAM         0
1767 #define CST43236_BOOT_FROM_ROM          1
1768 #define CST43236_BOOT_FROM_FLASH        2
1769 #define CST43236_BOOT_FROM_INVALID      3
1770
1771
1772 #define RES43237_REGULATOR              0
1773 #define RES43237_ILP_REQUEST            1
1774 #define RES43237_XTAL_PU                2
1775 #define RES43237_ALP_AVAIL              3
1776 #define RES43237_SI_PLL_ON              4
1777 #define RES43237_HT_SI_AVAIL            5
1778
1779
1780 #define CCTRL43237_BT_COEXIST           (1<<0)
1781 #define CCTRL43237_SECI                 (1<<1)
1782 #define CCTRL43237_EXT_LNA              (1<<2)
1783 #define CCTRL43237_ANT_MUX_2o3          (1<<3)
1784 #define CCTRL43237_GSIO                 (1<<4)
1785
1786
1787 #define CST43237_SFLASH_MASK            0x00000040
1788 #define CST43237_OTP_SEL_MASK           0x00000080
1789 #define CST43237_OTP_SEL_SHIFT          7
1790 #define CST43237_HSIC_MASK              0x00000100
1791 #define CST43237_BP_CLK                 0x00000200
1792 #define CST43237_BOOT_MASK              0x00001800
1793 #define CST43237_BOOT_SHIFT             11
1794 #define CST43237_BOOT_FROM_SRAM         0
1795 #define CST43237_BOOT_FROM_ROM          1
1796 #define CST43237_BOOT_FROM_FLASH        2
1797 #define CST43237_BOOT_FROM_INVALID      3
1798
1799
1800 #define RES43239_OTP_PU                 9
1801 #define RES43239_MACPHY_CLKAVAIL        23
1802 #define RES43239_HT_AVAIL               24
1803
1804
1805 #define CST43239_SPROM_MASK                     0x00000002
1806 #define CST43239_SFLASH_MASK            0x00000004
1807 #define CST43239_RES_INIT_MODE_SHIFT    7
1808 #define CST43239_RES_INIT_MODE_MASK             0x000001f0
1809 #define CST43239_CHIPMODE_SDIOD(cs)     ((cs) & (1 << 15))
1810 #define CST43239_CHIPMODE_USB20D(cs)    (~(cs) & (1 << 15))
1811 #define CST43239_CHIPMODE_SDIO(cs)      (((cs) & (1 << 0)) == 0)
1812 #define CST43239_CHIPMODE_GSPI(cs)      (((cs) & (1 << 0)) == (1 << 0))
1813
1814
1815
1816 #define RES4324_LPLDO_PU                        0
1817 #define RES4324_RESET_PULLDN_DIS                1
1818 #define RES4324_PMU_BG_PU                       2
1819 #define RES4324_HSIC_LDO_PU                     3
1820 #define RES4324_CBUCK_LPOM_PU                   4
1821 #define RES4324_CBUCK_PFM_PU                    5
1822 #define RES4324_CLDO_PU                         6
1823 #define RES4324_LPLDO2_LVM                      7
1824 #define RES4324_LNLDO1_PU                       8
1825 #define RES4324_LNLDO2_PU                       9
1826 #define RES4324_LDO3P3_PU                       10
1827 #define RES4324_OTP_PU                          11
1828 #define RES4324_XTAL_PU                         12
1829 #define RES4324_BBPLL_PU                        13
1830 #define RES4324_LQ_AVAIL                        14
1831 #define RES4324_WL_CORE_READY                   17
1832 #define RES4324_ILP_REQ                         18
1833 #define RES4324_ALP_AVAIL                       19
1834 #define RES4324_PALDO_PU                        20
1835 #define RES4324_RADIO_PU                        21
1836 #define RES4324_SR_CLK_STABLE                   22
1837 #define RES4324_SR_SAVE_RESTORE                 23
1838 #define RES4324_SR_PHY_PWRSW                    24
1839 #define RES4324_SR_PHY_PIC                      25
1840 #define RES4324_SR_SUBCORE_PWRSW                26
1841 #define RES4324_SR_SUBCORE_PIC                  27
1842 #define RES4324_SR_MEM_PM0                      28
1843 #define RES4324_HT_AVAIL                        29
1844 #define RES4324_MACPHY_CLKAVAIL                 30
1845
1846
1847 #define CST4324_SPROM_MASK                      0x00000080
1848 #define CST4324_SFLASH_MASK                     0x00400000
1849 #define CST4324_RES_INIT_MODE_SHIFT     10
1850 #define CST4324_RES_INIT_MODE_MASK      0x00000c00
1851 #define CST4324_CHIPMODE_MASK           0x7
1852 #define CST4324_CHIPMODE_SDIOD(cs)      ((~(cs)) & (1 << 2))
1853 #define CST4324_CHIPMODE_USB20D(cs)     (((cs) & CST4324_CHIPMODE_MASK) == 0x6)
1854
1855
1856 #define CST43242_SFLASH_MASK                    0x00000008
1857
1858
1859 #define RES4331_REGULATOR               0
1860 #define RES4331_ILP_REQUEST             1
1861 #define RES4331_XTAL_PU                 2
1862 #define RES4331_ALP_AVAIL               3
1863 #define RES4331_SI_PLL_ON               4
1864 #define RES4331_HT_SI_AVAIL             5
1865
1866
1867 #define CCTRL4331_BT_COEXIST            (1<<0)
1868 #define CCTRL4331_SECI                  (1<<1)
1869 #define CCTRL4331_EXT_LNA_G             (1<<2)
1870 #define CCTRL4331_SPROM_GPIO13_15       (1<<3)
1871 #define CCTRL4331_EXTPA_EN              (1<<4)
1872 #define CCTRL4331_GPIOCLK_ON_SPROMCS    (1<<5)
1873 #define CCTRL4331_PCIE_MDIO_ON_SPROMCS  (1<<6)
1874 #define CCTRL4331_EXTPA_ON_GPIO2_5      (1<<7)
1875 #define CCTRL4331_OVR_PIPEAUXCLKEN      (1<<8)
1876 #define CCTRL4331_OVR_PIPEAUXPWRDOWN    (1<<9)
1877 #define CCTRL4331_PCIE_AUXCLKEN         (1<<10)
1878 #define CCTRL4331_PCIE_PIPE_PLLDOWN     (1<<11)
1879 #define CCTRL4331_EXTPA_EN2             (1<<12)
1880 #define CCTRL4331_EXT_LNA_A             (1<<13)
1881 #define CCTRL4331_BT_SHD0_ON_GPIO4      (1<<16)
1882 #define CCTRL4331_BT_SHD1_ON_GPIO5      (1<<17)
1883 #define CCTRL4331_EXTPA_ANA_EN          (1<<24)
1884
1885
1886 #define CST4331_XTAL_FREQ               0x00000001
1887 #define CST4331_SPROM_OTP_SEL_MASK      0x00000006
1888 #define CST4331_SPROM_OTP_SEL_SHIFT     1
1889 #define CST4331_SPROM_PRESENT           0x00000002
1890 #define CST4331_OTP_PRESENT             0x00000004
1891 #define CST4331_LDO_RF                  0x00000008
1892 #define CST4331_LDO_PAR                 0x00000010
1893
1894
1895 #define RES4315_CBUCK_LPOM              1
1896 #define RES4315_CBUCK_BURST             2
1897 #define RES4315_CBUCK_PWM               3
1898 #define RES4315_CLDO_PU                 4
1899 #define RES4315_PALDO_PU                5
1900 #define RES4315_ILP_REQUEST             6
1901 #define RES4315_LNLDO1_PU               9
1902 #define RES4315_OTP_PU                  10
1903 #define RES4315_LNLDO2_PU               12
1904 #define RES4315_XTAL_PU                 13
1905 #define RES4315_ALP_AVAIL               14
1906 #define RES4315_RX_PWRSW_PU             15
1907 #define RES4315_TX_PWRSW_PU             16
1908 #define RES4315_RFPLL_PWRSW_PU          17
1909 #define RES4315_LOGEN_PWRSW_PU          18
1910 #define RES4315_AFE_PWRSW_PU            19
1911 #define RES4315_BBPLL_PWRSW_PU          20
1912 #define RES4315_HT_AVAIL                21
1913
1914
1915 #define CST4315_SPROM_OTP_SEL_MASK      0x00000003
1916 #define CST4315_DEFCIS_SEL              0x00000000
1917 #define CST4315_SPROM_SEL               0x00000001
1918 #define CST4315_OTP_SEL                 0x00000002
1919 #define CST4315_OTP_PWRDN               0x00000003
1920 #define CST4315_SDIO_MODE               0x00000004
1921 #define CST4315_RCAL_VALID              0x00000008
1922 #define CST4315_RCAL_VALUE_MASK         0x000001f0
1923 #define CST4315_RCAL_VALUE_SHIFT        4
1924 #define CST4315_PALDO_EXTPNP            0x00000200
1925 #define CST4315_CBUCK_MODE_MASK         0x00000c00
1926 #define CST4315_CBUCK_MODE_BURST        0x00000400
1927 #define CST4315_CBUCK_MODE_LPBURST      0x00000c00
1928
1929
1930 #define RES4319_CBUCK_LPOM              1
1931 #define RES4319_CBUCK_BURST             2
1932 #define RES4319_CBUCK_PWM               3
1933 #define RES4319_CLDO_PU                 4
1934 #define RES4319_PALDO_PU                5
1935 #define RES4319_ILP_REQUEST             6
1936 #define RES4319_LNLDO1_PU               9
1937 #define RES4319_OTP_PU                  10
1938 #define RES4319_LNLDO2_PU               12
1939 #define RES4319_XTAL_PU                 13
1940 #define RES4319_ALP_AVAIL               14
1941 #define RES4319_RX_PWRSW_PU             15
1942 #define RES4319_TX_PWRSW_PU             16
1943 #define RES4319_RFPLL_PWRSW_PU          17
1944 #define RES4319_LOGEN_PWRSW_PU          18
1945 #define RES4319_AFE_PWRSW_PU            19
1946 #define RES4319_BBPLL_PWRSW_PU          20
1947 #define RES4319_HT_AVAIL                21
1948
1949
1950 #define CST4319_SPI_CPULESSUSB          0x00000001
1951 #define CST4319_SPI_CLK_POL             0x00000002
1952 #define CST4319_SPI_CLK_PH              0x00000008
1953 #define CST4319_SPROM_OTP_SEL_MASK      0x000000c0
1954 #define CST4319_SPROM_OTP_SEL_SHIFT     6
1955 #define CST4319_DEFCIS_SEL              0x00000000
1956 #define CST4319_SPROM_SEL               0x00000040
1957 #define CST4319_OTP_SEL                 0x00000080
1958 #define CST4319_OTP_PWRDN               0x000000c0
1959 #define CST4319_SDIO_USB_MODE           0x00000100
1960 #define CST4319_REMAP_SEL_MASK          0x00000600
1961 #define CST4319_ILPDIV_EN               0x00000800
1962 #define CST4319_XTAL_PD_POL             0x00001000
1963 #define CST4319_LPO_SEL                 0x00002000
1964 #define CST4319_RES_INIT_MODE           0x0000c000
1965 #define CST4319_PALDO_EXTPNP            0x00010000
1966 #define CST4319_CBUCK_MODE_MASK         0x00060000
1967 #define CST4319_CBUCK_MODE_BURST        0x00020000
1968 #define CST4319_CBUCK_MODE_LPBURST      0x00060000
1969 #define CST4319_RCAL_VALID              0x01000000
1970 #define CST4319_RCAL_VALUE_MASK         0x3e000000
1971 #define CST4319_RCAL_VALUE_SHIFT        25
1972
1973 #define PMU1_PLL0_CHIPCTL0              0
1974 #define PMU1_PLL0_CHIPCTL1              1
1975 #define PMU1_PLL0_CHIPCTL2              2
1976 #define CCTL_4319USB_XTAL_SEL_MASK      0x00180000
1977 #define CCTL_4319USB_XTAL_SEL_SHIFT     19
1978 #define CCTL_4319USB_48MHZ_PLL_SEL      1
1979 #define CCTL_4319USB_24MHZ_PLL_SEL      2
1980
1981
1982 #define RES4336_CBUCK_LPOM              0
1983 #define RES4336_CBUCK_BURST             1
1984 #define RES4336_CBUCK_LP_PWM            2
1985 #define RES4336_CBUCK_PWM               3
1986 #define RES4336_CLDO_PU                 4
1987 #define RES4336_DIS_INT_RESET_PD        5
1988 #define RES4336_ILP_REQUEST             6
1989 #define RES4336_LNLDO_PU                7
1990 #define RES4336_LDO3P3_PU               8
1991 #define RES4336_OTP_PU                  9
1992 #define RES4336_XTAL_PU                 10
1993 #define RES4336_ALP_AVAIL               11
1994 #define RES4336_RADIO_PU                12
1995 #define RES4336_BG_PU                   13
1996 #define RES4336_VREG1p4_PU_PU           14
1997 #define RES4336_AFE_PWRSW_PU            15
1998 #define RES4336_RX_PWRSW_PU             16
1999 #define RES4336_TX_PWRSW_PU             17
2000 #define RES4336_BB_PWRSW_PU             18
2001 #define RES4336_SYNTH_PWRSW_PU          19
2002 #define RES4336_MISC_PWRSW_PU           20
2003 #define RES4336_LOGEN_PWRSW_PU          21
2004 #define RES4336_BBPLL_PWRSW_PU          22
2005 #define RES4336_MACPHY_CLKAVAIL         23
2006 #define RES4336_HT_AVAIL                24
2007 #define RES4336_RSVD                    25
2008
2009
2010 #define CST4336_SPI_MODE_MASK           0x00000001
2011 #define CST4336_SPROM_PRESENT           0x00000002
2012 #define CST4336_OTP_PRESENT             0x00000004
2013 #define CST4336_ARMREMAP_0              0x00000008
2014 #define CST4336_ILPDIV_EN_MASK          0x00000010
2015 #define CST4336_ILPDIV_EN_SHIFT         4
2016 #define CST4336_XTAL_PD_POL_MASK        0x00000020
2017 #define CST4336_XTAL_PD_POL_SHIFT       5
2018 #define CST4336_LPO_SEL_MASK            0x00000040
2019 #define CST4336_LPO_SEL_SHIFT           6
2020 #define CST4336_RES_INIT_MODE_MASK      0x00000180
2021 #define CST4336_RES_INIT_MODE_SHIFT     7
2022 #define CST4336_CBUCK_MODE_MASK         0x00000600
2023 #define CST4336_CBUCK_MODE_SHIFT        9
2024
2025
2026 #define PCTL_4336_SERIAL_ENAB   (1  << 24)
2027
2028
2029 #define RES4330_CBUCK_LPOM              0
2030 #define RES4330_CBUCK_BURST             1
2031 #define RES4330_CBUCK_LP_PWM            2
2032 #define RES4330_CBUCK_PWM               3
2033 #define RES4330_CLDO_PU                 4
2034 #define RES4330_DIS_INT_RESET_PD        5
2035 #define RES4330_ILP_REQUEST             6
2036 #define RES4330_LNLDO_PU                7
2037 #define RES4330_LDO3P3_PU               8
2038 #define RES4330_OTP_PU                  9
2039 #define RES4330_XTAL_PU                 10
2040 #define RES4330_ALP_AVAIL               11
2041 #define RES4330_RADIO_PU                12
2042 #define RES4330_BG_PU                   13
2043 #define RES4330_VREG1p4_PU_PU           14
2044 #define RES4330_AFE_PWRSW_PU            15
2045 #define RES4330_RX_PWRSW_PU             16
2046 #define RES4330_TX_PWRSW_PU             17
2047 #define RES4330_BB_PWRSW_PU             18
2048 #define RES4330_SYNTH_PWRSW_PU          19
2049 #define RES4330_MISC_PWRSW_PU           20
2050 #define RES4330_LOGEN_PWRSW_PU          21
2051 #define RES4330_BBPLL_PWRSW_PU          22
2052 #define RES4330_MACPHY_CLKAVAIL         23
2053 #define RES4330_HT_AVAIL                24
2054 #define RES4330_5gRX_PWRSW_PU           25
2055 #define RES4330_5gTX_PWRSW_PU           26
2056 #define RES4330_5g_LOGEN_PWRSW_PU       27
2057
2058
2059 #define CST4330_CHIPMODE_SDIOD(cs)      (((cs) & 0x7) < 6)
2060 #define CST4330_CHIPMODE_USB20D(cs)     (((cs) & 0x7) >= 6)
2061 #define CST4330_CHIPMODE_SDIO(cs)       (((cs) & 0x4) == 0)
2062 #define CST4330_CHIPMODE_GSPI(cs)       (((cs) & 0x6) == 4)
2063 #define CST4330_CHIPMODE_USB(cs)        (((cs) & 0x7) == 6)
2064 #define CST4330_CHIPMODE_USBDA(cs)      (((cs) & 0x7) == 7)
2065 #define CST4330_OTP_PRESENT             0x00000010
2066 #define CST4330_LPO_AUTODET_EN          0x00000020
2067 #define CST4330_ARMREMAP_0              0x00000040
2068 #define CST4330_SPROM_PRESENT           0x00000080
2069 #define CST4330_ILPDIV_EN               0x00000100
2070 #define CST4330_LPO_SEL                 0x00000200
2071 #define CST4330_RES_INIT_MODE_SHIFT     10
2072 #define CST4330_RES_INIT_MODE_MASK      0x00000c00
2073 #define CST4330_CBUCK_MODE_SHIFT        12
2074 #define CST4330_CBUCK_MODE_MASK         0x00003000
2075 #define CST4330_CBUCK_POWER_OK          0x00004000
2076 #define CST4330_BB_PLL_LOCKED           0x00008000
2077 #define SOCDEVRAM_BP_ADDR               0x1E000000
2078 #define SOCDEVRAM_ARM_ADDR              0x00800000
2079
2080
2081 #define PCTL_4330_SERIAL_ENAB   (1  << 24)
2082
2083
2084 #define CCTRL_4330_GPIO_SEL             0x00000001
2085 #define CCTRL_4330_ERCX_SEL             0x00000002
2086 #define CCTRL_4330_SDIO_HOST_WAKE       0x00000004
2087 #define CCTRL_4330_JTAG_DISABLE 0x00000008
2088
2089 #define PMU_VREG0_ADDR                          0
2090 #define PMU_VREG0_DISABLE_PULLD_BT_SHIFT        2
2091 #define PMU_VREG0_DISABLE_PULLD_WL_SHIFT        3
2092
2093 #define PMU_VREG4_ADDR                  4
2094
2095 #define PMU_VREG4_CLDO_PWM_SHIFT        4
2096 #define PMU_VREG4_CLDO_PWM_MASK         0x7
2097
2098 #define PMU_VREG4_LPLDO1_SHIFT          15
2099 #define PMU_VREG4_LPLDO1_MASK           0x7
2100 #define PMU_VREG4_LPLDO1_1p20V          0
2101 #define PMU_VREG4_LPLDO1_1p15V          1
2102 #define PMU_VREG4_LPLDO1_1p10V          2
2103 #define PMU_VREG4_LPLDO1_1p25V          3
2104 #define PMU_VREG4_LPLDO1_1p05V          4
2105 #define PMU_VREG4_LPLDO1_1p00V          5
2106 #define PMU_VREG4_LPLDO1_0p95V          6
2107 #define PMU_VREG4_LPLDO1_0p90V          7
2108
2109 #define PMU_VREG4_LPLDO2_LVM_SHIFT      18
2110 #define PMU_VREG4_LPLDO2_LVM_MASK       0x7
2111 #define PMU_VREG4_LPLDO2_HVM_SHIFT      21
2112 #define PMU_VREG4_LPLDO2_HVM_MASK       0x7
2113 #define PMU_VREG4_LPLDO2_LVM_HVM_MASK   0x3f
2114 #define PMU_VREG4_LPLDO2_1p00V          0
2115 #define PMU_VREG4_LPLDO2_1p15V          1
2116 #define PMU_VREG4_LPLDO2_1p20V          2
2117 #define PMU_VREG4_LPLDO2_1p10V          3
2118 #define PMU_VREG4_LPLDO2_0p90V          4
2119
2120 #define PMU_VREG4_HSICLDO_BYPASS_SHIFT  27
2121 #define PMU_VREG4_HSICLDO_BYPASS_MASK   0x1
2122
2123 #define PMU_VREG5_ADDR                  5
2124 #define PMU_VREG5_HSICAVDD_PD_SHIFT     6
2125 #define PMU_VREG5_HSICAVDD_PD_MASK      0x1
2126 #define PMU_VREG5_HSICDVDD_PD_SHIFT     11
2127 #define PMU_VREG5_HSICDVDD_PD_MASK      0x1
2128
2129
2130 #define RES4334_LPLDO_PU                0
2131 #define RES4334_RESET_PULLDN_DIS        1
2132 #define RES4334_PMU_BG_PU               2
2133 #define RES4334_HSIC_LDO_PU             3
2134 #define RES4334_CBUCK_LPOM_PU           4
2135 #define RES4334_CBUCK_PFM_PU            5
2136 #define RES4334_CLDO_PU                 6
2137 #define RES4334_LPLDO2_LVM              7
2138 #define RES4334_LNLDO_PU                8
2139 #define RES4334_LDO3P3_PU               9
2140 #define RES4334_OTP_PU                  10
2141 #define RES4334_XTAL_PU                 11
2142 #define RES4334_WL_PWRSW_PU             12
2143 #define RES4334_LQ_AVAIL                13
2144 #define RES4334_LOGIC_RET               14
2145 #define RES4334_MEM_SLEEP               15
2146 #define RES4334_MACPHY_RET              16
2147 #define RES4334_WL_CORE_READY           17
2148 #define RES4334_ILP_REQ                 18
2149 #define RES4334_ALP_AVAIL               19
2150 #define RES4334_MISC_PWRSW_PU           20
2151 #define RES4334_SYNTH_PWRSW_PU          21
2152 #define RES4334_RX_PWRSW_PU             22
2153 #define RES4334_RADIO_PU                23
2154 #define RES4334_WL_PMU_PU               24
2155 #define RES4334_VCO_LDO_PU              25
2156 #define RES4334_AFE_LDO_PU              26
2157 #define RES4334_RX_LDO_PU               27
2158 #define RES4334_TX_LDO_PU               28
2159 #define RES4334_HT_AVAIL                29
2160 #define RES4334_MACPHY_CLK_AVAIL        30
2161
2162
2163 #define CST4334_CHIPMODE_MASK           7
2164 #define CST4334_SDIO_MODE               0x00000000
2165 #define CST4334_SPI_MODE                0x00000004
2166 #define CST4334_HSIC_MODE               0x00000006
2167 #define CST4334_BLUSB_MODE              0x00000007
2168 #define CST4334_CHIPMODE_HSIC(cs)       (((cs) & CST4334_CHIPMODE_MASK) == CST4334_HSIC_MODE)
2169 #define CST4334_OTP_PRESENT             0x00000010
2170 #define CST4334_LPO_AUTODET_EN          0x00000020
2171 #define CST4334_ARMREMAP_0              0x00000040
2172 #define CST4334_SPROM_PRESENT           0x00000080
2173 #define CST4334_ILPDIV_EN_MASK          0x00000100
2174 #define CST4334_ILPDIV_EN_SHIFT         8
2175 #define CST4334_LPO_SEL_MASK            0x00000200
2176 #define CST4334_LPO_SEL_SHIFT           9
2177 #define CST4334_RES_INIT_MODE_MASK      0x00000C00
2178 #define CST4334_RES_INIT_MODE_SHIFT     10
2179
2180
2181 #define PCTL_4334_GPIO3_ENAB    (1  << 3)
2182
2183
2184 #define CCTRL4334_PMU_WAKEUP_GPIO1      (1  << 0)
2185 #define CCTRL4334_PMU_WAKEUP_HSIC       (1  << 1)
2186 #define CCTRL4334_PMU_WAKEUP_AOS        (1  << 2)
2187 #define CCTRL4334_HSIC_WAKE_MODE        (1  << 3)
2188 #define CCTRL4334_HSIC_INBAND_GPIO1     (1  << 4)
2189 #define CCTRL4334_HSIC_LDO_PU           (1  << 23)
2190
2191
2192 #define CCTRL4334_BLOCK_EXTRNL_WAKE             (1  << 4)
2193 #define CCTRL4334_SAVERESTORE_FIX               (1  << 5)
2194
2195
2196 #define CCTRL43341_BLOCK_EXTRNL_WAKE            (1  << 13)
2197 #define CCTRL43341_SAVERESTORE_FIX              (1  << 14)
2198 #define CCTRL43341_BT_ISO_SEL                   (1  << 16)
2199
2200
2201 #define CCTRL1_4334_GPIO_SEL            (1 << 0)
2202 #define CCTRL1_4334_ERCX_SEL            (1 << 1)
2203 #define CCTRL1_4334_SDIO_HOST_WAKE (1 << 2)
2204 #define CCTRL1_4334_JTAG_DISABLE        (1 << 3)
2205 #define CCTRL1_4334_UART_ON_4_5 (1 << 28)
2206
2207
2208 #define CCTRL1_4324_GPIO_SEL            (1 << 0)
2209 #define CCTRL1_4324_SDIO_HOST_WAKE (1 << 2)
2210
2211
2212
2213 #define CST43143_REMAP_TO_ROM    (3 << 0)
2214 #define CST43143_SDIO_EN         (1 << 2)
2215 #define CST43143_SDIO_ISO        (1 << 3)
2216 #define CST43143_USB_CPU_LESS    (1 << 4)
2217 #define CST43143_CBUCK_MODE      (3 << 6)
2218 #define CST43143_POK_CBUCK       (1 << 8)
2219 #define CST43143_PMU_OVRSPIKE    (1 << 9)
2220 #define CST43143_PMU_OVRTEMP     (0xF << 10)
2221 #define CST43143_SR_FLL_CAL_DONE (1 << 14)
2222 #define CST43143_USB_PLL_LOCKDET (1 << 15)
2223 #define CST43143_PMU_PLL_LOCKDET (1 << 16)
2224 #define CST43143_CHIPMODE_SDIOD(cs)     (((cs) & CST43143_SDIO_EN) != 0)
2225
2226
2227
2228 #define CCTRL_43143_SECI                (1<<0)
2229 #define CCTRL_43143_BT_LEGACY           (1<<1)
2230 #define CCTRL_43143_I2S_MODE            (1<<2)
2231 #define CCTRL_43143_I2S_MASTER          (1<<3)
2232 #define CCTRL_43143_I2S_FULL            (1<<4)
2233 #define CCTRL_43143_GSIO                (1<<5)
2234 #define CCTRL_43143_RF_SWCTRL_MASK      (7<<6)
2235 #define CCTRL_43143_RF_SWCTRL_0         (1<<6)
2236 #define CCTRL_43143_RF_SWCTRL_1         (2<<6)
2237 #define CCTRL_43143_RF_SWCTRL_2         (4<<6)
2238 #define CCTRL_43143_RF_XSWCTRL          (1<<9)
2239 #define CCTRL_43143_HOST_WAKE0          (1<<11)
2240 #define CCTRL_43143_HOST_WAKE1          (1<<12)
2241
2242
2243 #define RES43143_EXT_SWITCHER_PWM       0
2244 #define RES43143_XTAL_PU                1
2245 #define RES43143_ILP_REQUEST            2
2246 #define RES43143_ALP_AVAIL              3
2247 #define RES43143_WL_CORE_READY          4
2248 #define RES43143_BBPLL_PWRSW_PU         5
2249 #define RES43143_HT_AVAIL               6
2250 #define RES43143_RADIO_PU               7
2251 #define RES43143_MACPHY_CLK_AVAIL       8
2252 #define RES43143_OTP_PU                 9
2253 #define RES43143_LQ_AVAIL               10
2254
2255 #define PMU43143_XTAL_CORE_SIZE_MASK    0x3F
2256
2257
2258 #define RES4313_BB_PU_RSRC              0
2259 #define RES4313_ILP_REQ_RSRC            1
2260 #define RES4313_XTAL_PU_RSRC            2
2261 #define RES4313_ALP_AVAIL_RSRC          3
2262 #define RES4313_RADIO_PU_RSRC           4
2263 #define RES4313_BG_PU_RSRC              5
2264 #define RES4313_VREG1P4_PU_RSRC         6
2265 #define RES4313_AFE_PWRSW_RSRC          7
2266 #define RES4313_RX_PWRSW_RSRC           8
2267 #define RES4313_TX_PWRSW_RSRC           9
2268 #define RES4313_BB_PWRSW_RSRC           10
2269 #define RES4313_SYNTH_PWRSW_RSRC        11
2270 #define RES4313_MISC_PWRSW_RSRC         12
2271 #define RES4313_BB_PLL_PWRSW_RSRC       13
2272 #define RES4313_HT_AVAIL_RSRC           14
2273 #define RES4313_MACPHY_CLK_AVAIL_RSRC   15
2274
2275
2276 #define CST4313_SPROM_PRESENT                   1
2277 #define CST4313_OTP_PRESENT                     2
2278 #define CST4313_SPROM_OTP_SEL_MASK              0x00000002
2279 #define CST4313_SPROM_OTP_SEL_SHIFT             0
2280
2281
2282 #define CCTRL_4313_12MA_LED_DRIVE    0x00000007
2283
2284
2285 #define RES4314_LPLDO_PU                0
2286 #define RES4314_PMU_SLEEP_DIS           1
2287 #define RES4314_PMU_BG_PU               2
2288 #define RES4314_CBUCK_LPOM_PU           3
2289 #define RES4314_CBUCK_PFM_PU            4
2290 #define RES4314_CLDO_PU                 5
2291 #define RES4314_LPLDO2_LVM              6
2292 #define RES4314_WL_PMU_PU               7
2293 #define RES4314_LNLDO_PU                8
2294 #define RES4314_LDO3P3_PU               9
2295 #define RES4314_OTP_PU                  10
2296 #define RES4314_XTAL_PU                 11
2297 #define RES4314_WL_PWRSW_PU             12
2298 #define RES4314_LQ_AVAIL                13
2299 #define RES4314_LOGIC_RET               14
2300 #define RES4314_MEM_SLEEP               15
2301 #define RES4314_MACPHY_RET              16
2302 #define RES4314_WL_CORE_READY           17
2303 #define RES4314_ILP_REQ                 18
2304 #define RES4314_ALP_AVAIL               19
2305 #define RES4314_MISC_PWRSW_PU           20
2306 #define RES4314_SYNTH_PWRSW_PU          21
2307 #define RES4314_RX_PWRSW_PU             22
2308 #define RES4314_RADIO_PU                23
2309 #define RES4314_VCO_LDO_PU              24
2310 #define RES4314_AFE_LDO_PU              25
2311 #define RES4314_RX_LDO_PU               26
2312 #define RES4314_TX_LDO_PU               27
2313 #define RES4314_HT_AVAIL                28
2314 #define RES4314_MACPHY_CLK_AVAIL        29
2315
2316
2317 #define CST4314_OTP_ENABLED             0x00200000
2318
2319
2320 #define RES43228_NOT_USED               0
2321 #define RES43228_ILP_REQUEST            1
2322 #define RES43228_XTAL_PU                2
2323 #define RES43228_ALP_AVAIL              3
2324 #define RES43228_PLL_EN                 4
2325 #define RES43228_HT_PHY_AVAIL           5
2326
2327
2328 #define CST43228_ILP_DIV_EN             0x1
2329 #define CST43228_OTP_PRESENT            0x2
2330 #define CST43228_SERDES_REFCLK_PADSEL   0x4
2331 #define CST43228_SDIO_MODE              0x8
2332 #define CST43228_SDIO_OTP_PRESENT       0x10
2333 #define CST43228_SDIO_RESET             0x20
2334
2335
2336 #define CST4706_PKG_OPTION              (1<<0)
2337 #define CST4706_SFLASH_PRESENT  (1<<1)
2338 #define CST4706_SFLASH_TYPE             (1<<2)
2339 #define CST4706_MIPS_BENDIAN    (1<<3)
2340 #define CST4706_PCIE1_DISABLE   (1<<5)
2341
2342
2343 #define FLSTRCF4706_MASK                0x000000ff
2344 #define FLSTRCF4706_SF1                 0x00000001
2345 #define FLSTRCF4706_PF1                 0x00000002
2346 #define FLSTRCF4706_SF1_TYPE    0x00000004
2347 #define FLSTRCF4706_NF1                 0x00000008
2348 #define FLSTRCF4706_1ST_MADDR_SEG_MASK          0x000000f0
2349 #define FLSTRCF4706_1ST_MADDR_SEG_4MB           0x00000010
2350 #define FLSTRCF4706_1ST_MADDR_SEG_8MB           0x00000020
2351 #define FLSTRCF4706_1ST_MADDR_SEG_16MB          0x00000030
2352 #define FLSTRCF4706_1ST_MADDR_SEG_32MB          0x00000040
2353 #define FLSTRCF4706_1ST_MADDR_SEG_64MB          0x00000050
2354 #define FLSTRCF4706_1ST_MADDR_SEG_128MB         0x00000060
2355 #define FLSTRCF4706_1ST_MADDR_SEG_256MB         0x00000070
2356
2357
2358 #define CCTRL4360_I2C_MODE                      (1 << 0)
2359 #define CCTRL4360_UART_MODE                     (1 << 1)
2360 #define CCTRL4360_SECI_MODE                     (1 << 2)
2361 #define CCTRL4360_BTSWCTRL_MODE                 (1 << 3)
2362 #define CCTRL4360_DISCRETE_FEMCTRL_MODE         (1 << 4)
2363 #define CCTRL4360_DIGITAL_PACTRL_MODE           (1 << 5)
2364 #define CCTRL4360_BTSWCTRL_AND_DIGPA_PRESENT    (1 << 6)
2365 #define CCTRL4360_EXTRA_GPIO_MODE               (1 << 7)
2366 #define CCTRL4360_EXTRA_FEMCTRL_MODE            (1 << 8)
2367 #define CCTRL4360_BT_LGCY_MODE                  (1 << 9)
2368 #define CCTRL4360_CORE2FEMCTRL4_ON              (1 << 21)
2369 #define CCTRL4360_SECI_ON_GPIO01                (1 << 24)
2370
2371
2372
2373 #define RES4360_REGULATOR          0
2374 #define RES4360_ILP_AVAIL          1
2375 #define RES4360_ILP_REQ            2
2376 #define RES4360_XTAL_LDO_PU        3
2377 #define RES4360_XTAL_PU            4
2378 #define RES4360_ALP_AVAIL          5
2379 #define RES4360_BBPLLPWRSW_PU      6
2380 #define RES4360_HT_AVAIL           7
2381 #define RES4360_OTP_PU             8
2382
2383 #define CST4360_XTAL_40MZ                  0x00000001
2384 #define CST4360_SFLASH                     0x00000002
2385 #define CST4360_SPROM_PRESENT              0x00000004
2386 #define CST4360_SFLASH_TYPE                0x00000004
2387 #define CST4360_OTP_ENABLED                0x00000008
2388 #define CST4360_REMAP_ROM                  0x00000010
2389 #define CST4360_RSRC_INIT_MODE_MASK        0x00000060
2390 #define CST4360_RSRC_INIT_MODE_SHIFT       5
2391 #define CST4360_ILP_DIVEN                  0x00000080
2392 #define CST4360_MODE_USB                   0x00000100
2393 #define CST4360_SPROM_SIZE_MASK            0x00000600
2394 #define CST4360_SPROM_SIZE_SHIFT           9
2395 #define CST4360_BBPLL_LOCK                 0x00000800
2396 #define CST4360_AVBBPLL_LOCK               0x00001000
2397 #define CST4360_USBBBPLL_LOCK              0x00002000
2398
2399 #define CCTRL_4360_UART_SEL     0x2
2400
2401
2402 #define CHIP_HOSTIF_PCIEMODE    0x1
2403 #define CHIP_HOSTIF_USBMODE     0x2
2404 #define CHIP_HOSTIF_SDIOMODE    0x4
2405 #define CHIP_HOSTIF_PCIE(sih)   (si_chip_hostif(sih) == CHIP_HOSTIF_PCIEMODE)
2406 #define CHIP_HOSTIF_SDIO(sih)   (si_chip_hostif(sih) == CHIP_HOSTIF_SDIOMODE)
2407
2408
2409 #define RES4335_LPLDO_PO           0
2410 #define RES4335_PMU_BG_PU          1
2411 #define RES4335_PMU_SLEEP          2
2412 #define RES4335_RSVD_3             3
2413 #define RES4335_CBUCK_LPOM_PU           4
2414 #define RES4335_CBUCK_PFM_PU            5
2415 #define RES4335_RSVD_6             6
2416 #define RES4335_RSVD_7             7
2417 #define RES4335_LNLDO_PU           8
2418 #define RES4335_XTALLDO_PU         9
2419 #define RES4335_LDO3P3_PU                       10
2420 #define RES4335_OTP_PU                          11
2421 #define RES4335_XTAL_PU                         12
2422 #define RES4335_SR_CLK_START       13
2423 #define RES4335_LQ_AVAIL                        14
2424 #define RES4335_LQ_START           15
2425 #define RES4335_RSVD_16            16
2426 #define RES4335_WL_CORE_RDY        17
2427 #define RES4335_ILP_REQ                         18
2428 #define RES4335_ALP_AVAIL                       19
2429 #define RES4335_MINI_PMU           20
2430 #define RES4335_RADIO_PU                        21
2431 #define RES4335_SR_CLK_STABLE           22
2432 #define RES4335_SR_SAVE_RESTORE         23
2433 #define RES4335_SR_PHY_PWRSW            24
2434 #define RES4335_SR_VDDM_PWRSW      25
2435 #define RES4335_SR_SUBCORE_PWRSW        26
2436 #define RES4335_SR_SLEEP           27
2437 #define RES4335_HT_START           28
2438 #define RES4335_HT_AVAIL                        29
2439 #define RES4335_MACPHY_CLKAVAIL         30
2440
2441
2442 #define CST4335_SPROM_MASK                      0x00000020
2443 #define CST4335_SFLASH_MASK                     0x00000040
2444 #define CST4335_RES_INIT_MODE_SHIFT     7
2445 #define CST4335_RES_INIT_MODE_MASK      0x00000180
2446 #define CST4335_CHIPMODE_MASK           0xF
2447 #define CST4335_CHIPMODE_SDIOD(cs)      (((cs) & (1 << 0)) != 0)
2448 #define CST4335_CHIPMODE_GSPI(cs)       (((cs) & (1 << 1)) != 0)
2449 #define CST4335_CHIPMODE_USB20D(cs)     (((cs) & (1 << 2)) != 0)
2450 #define CST4335_CHIPMODE_PCIE(cs)       (((cs) & (1 << 3)) != 0)
2451
2452
2453 #define CCTRL1_4335_GPIO_SEL            (1 << 0)
2454 #define CCTRL1_4335_SDIO_HOST_WAKE (1 << 2)
2455
2456 #define CR4_4335_RAM_BASE                    (0x180000)
2457 #define PATCHTBL_SIZE                   (0x800)
2458 #define CR4_4350_RAM_BASE                    (0x180000)
2459 #define CR4_4360_RAM_BASE                    (0x0)
2460
2461
2462
2463 #define SPROM4335_OTP_SELECT    0x00000010
2464 #define SPROM4335_OTP_PRESENT   0x00000020
2465
2466
2467 #define CC4335_GCI_STRAP_OVERRIDE_SFLASH_PRESENT        (1 << 24)
2468 #define CC4335_GCI_STRAP_OVERRIDE_SFLASH_TYPE   25
2469 #define CC4335_GCI_FUNC_SEL_PAD_SDIO    0x00707770
2470
2471
2472 #define CC4335_SFLASH_CLKDIV_MASK       0x1F000000
2473 #define CC4335_SFLASH_CLKDIV_SHIFT      25
2474
2475
2476 #define CC4335_SROM_OTP_SFLASH  40
2477 #define CC4335_SROM_OTP_SFLASH_PRESENT  0x1
2478 #define CC4335_SROM_OTP_SFLASH_TYPE     0x2
2479 #define CC4335_SROM_OTP_SFLASH_CLKDIV_MASK      0x003C
2480 #define CC4335_SROM_OTP_SFLASH_CLKDIV_SHIFT     2
2481
2482
2483
2484
2485
2486 #define CST4350_SDIO_MODE               0x00000001
2487 #define CST4350_HSIC20D_MODE            0x00000002
2488 #define CST4350_BP_ON_HSIC_CLK          0x00000004
2489 #define CST4350_PCIE_MODE               0x00000008
2490 #define CST4350_USB20D_MODE             0x00000010
2491 #define CST4350_USB30D_MODE             0x00000020
2492 #define CST4350_SPROM_PRESENT           0x00000040
2493 #define CST4350_RSRC_INIT_MODE_0        0x00000080
2494 #define CST4350_RSRC_INIT_MODE_1        0x00000100
2495 #define CST4350_SEL0_SDIO               0x00000200
2496 #define CST4350_SEL1_SDIO               0x00000400
2497 #define CST4350_SDIO_PAD_MODE           0x00000800
2498 #define CST4350_BBPLL_LOCKED            0x00001000
2499 #define CST4350_USBPLL_LOCKED           0x00002000
2500 #define CST4350_LINE_STATE              0x0000C000
2501 #define CST4350_SERDES_PIPE_PLLLOCK     0x00010000
2502 #define CST4350_BT_READY                0x00020000
2503 #define CST4350_SFLASH_PRESENT          0x00040000
2504 #define CST4350_CPULESS_ENABLE          0x00080000
2505 #define CST4350_STRAP_HOST_IFC_1        0x00100000
2506 #define CST4350_STRAP_HOST_IFC_2        0x00200000
2507 #define CST4350_STRAP_HOST_IFC_3        0x00400000
2508 #define CST4350_RAW_SPROM_PRESENT       0x00800000
2509 #define CST4350_APP_CLK_SWITCH_SEL_RDBACK       0x01000000
2510 #define CST4350_RAW_RSRC_INIT_MODE_0    0x02000000
2511 #define CST4350_SDIO_PAD_VDDIO          0x04000000
2512 #define CST4350_GSPI_MODE               0x08000000
2513 #define CST4350_PACKAGE_OPTION          0xF0000000
2514
2515
2516 #define CST4350_HOST_IFC_MASK           0x00700000
2517 #define CST4350_HOST_IFC_SHIFT          20
2518
2519
2520 #define CST4350_IFC_MODE_SDIOD                  0x0
2521 #define CST4350_IFC_MODE_HSIC20D                0x1
2522 #define CST4350_IFC_MODE_HSIC30D                0x2
2523 #define CST4350_IFC_MODE_PCIE                   0x3
2524 #define CST4350_IFC_MODE_USB20D                 0x4
2525 #define CST4350_IFC_MODE_USB30D                 0x5
2526 #define CST4350_IFC_MODE_USB30D_WL              0x6
2527 #define CST4350_IFC_MODE_USB30D_BT              0x7
2528
2529 #define CST4350_IFC_MODE(cs)    ((cs & CST4350_HOST_IFC_MASK) >> CST4350_HOST_IFC_SHIFT)
2530
2531 #define CST4350_CHIPMODE_SDIOD(cs)      (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_SDIOD))
2532 #define CST4350_CHIPMODE_USB20D(cs)     ((CST4350_IFC_MODE(cs)) == (CST4350_IFC_MODE_USB20D))
2533 #define CST4350_CHIPMODE_HSIC20D(cs)    (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_HSIC20D))
2534 #define CST4350_CHIPMODE_HSIC30D(cs)    (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_HSIC30D))
2535 #define CST4350_CHIPMODE_USB30D(cs)     (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_USB30D))
2536 #define CST4350_CHIPMODE_USB30D_WL(cs)  (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_USB30D_WL))
2537 #define CST4350_CHIPMODE_PCIE(cs)       (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_PCIE))
2538
2539
2540 #define RES4350_LPLDO_PU        0
2541 #define RES4350_PMU_BG_PU       1
2542 #define RES4350_PMU_SLEEP       2
2543 #define RES4350_RSVD_3          3
2544 #define RES4350_CBUCK_LPOM_PU   4
2545 #define RES4350_CBUCK_PFM_PU    5
2546 #define RES4350_COLD_START_WAIT 6
2547 #define RES4350_RSVD_7          7
2548 #define RES4350_LNLDO_PU        8
2549 #define RES4350_XTALLDO_PU      9
2550 #define RES4350_LDO3P3_PU       10
2551 #define RES4350_OTP_PU          11
2552 #define RES4350_XTAL_PU         12
2553 #define RES4350_SR_CLK_START    13
2554 #define RES4350_LQ_AVAIL        14
2555 #define RES4350_LQ_START        15
2556 #define RES4350_RSVD_16         16
2557 #define RES4350_WL_CORE_RDY     17
2558 #define RES4350_ILP_REQ         18
2559 #define RES4350_ALP_AVAIL       19
2560 #define RES4350_MINI_PMU        20
2561 #define RES4350_RADIO_PU        21
2562 #define RES4350_SR_CLK_STABLE   22
2563 #define RES4350_SR_SAVE_RESTORE 23
2564 #define RES4350_SR_PHY_PWRSW    24
2565 #define RES4350_SR_VDDM_PWRSW   25
2566 #define RES4350_SR_SUBCORE_PWRSW        26
2567 #define RES4350_SR_SLEEP        27
2568 #define RES4350_HT_START        28
2569 #define RES4350_HT_AVAIL        29
2570 #define RES4350_MACPHY_CLKAVAIL 30
2571
2572 #define MUXENAB4350_UART_MASK           (0x0000000f)
2573
2574
2575 #define CC4350_FNSEL_HWDEF              (0)
2576 #define CC4350_FNSEL_SAMEASPIN          (1)
2577 #define CC4350_FNSEL_UART               (2)
2578 #define CC4350_FNSEL_SFLASH             (3)
2579 #define CC4350_FNSEL_SPROM              (4)
2580 #define CC4350_FNSEL_I2C                (5)
2581 #define CC4350_FNSEL_MISC0              (6)
2582 #define CC4350_FNSEL_GCI                (7)
2583 #define CC4350_FNSEL_MISC1              (8)
2584 #define CC4350_FNSEL_MISC2              (9)
2585 #define CC4350_FNSEL_PWDOG              (10)
2586 #define CC4350_FNSEL_IND                (12)
2587 #define CC4350_FNSEL_PDN                (13)
2588 #define CC4350_FNSEL_PUP                (14)
2589 #define CC4350_FNSEL_TRISTATE           (15)
2590
2591
2592 #define CC4350_PIN_GPIO_00              (0)
2593 #define CC4350_PIN_GPIO_01              (1)
2594 #define CC4350_PIN_GPIO_02              (2)
2595 #define CC4350_PIN_GPIO_03              (3)
2596 #define CC4350_PIN_GPIO_04              (4)
2597 #define CC4350_PIN_GPIO_05              (5)
2598 #define CC4350_PIN_GPIO_06              (6)
2599 #define CC4350_PIN_GPIO_07              (7)
2600 #define CC4350_PIN_GPIO_08              (8)
2601 #define CC4350_PIN_GPIO_09              (9)
2602 #define CC4350_PIN_GPIO_10              (10)
2603 #define CC4350_PIN_GPIO_11              (11)
2604 #define CC4350_PIN_GPIO_12              (12)
2605 #define CC4350_PIN_GPIO_13              (13)
2606 #define CC4350_PIN_GPIO_14              (14)
2607 #define CC4350_PIN_GPIO_15              (15)
2608
2609 #define CC2_4350_MEMLPLDO_PWRSW_EN_MASK         (1 << 21)
2610 #define CC2_4350_MEMLPLDO_PWRSW_EN_SHIFT        (21)
2611 #define CC2_4350_SDIO_AOS_WAKEUP_MASK           (1 << 24)
2612 #define CC2_4350_SDIO_AOS_WAKEUP_SHIFT          (24)
2613
2614
2615 #define CC3_SR_CLK_SR_MEM_MASK                  (1 << 0)
2616 #define CC3_SR_CLK_SR_MEM_SHIFT                 (0)
2617 #define CC3_SR_BIT1_TBD_MASK                    (1 << 1)
2618 #define CC3_SR_BIT1_TBD_SHIFT                   (1)
2619 #define CC3_SR_ENGINE_ENABLE_MASK               (1 << 2)
2620 #define CC3_SR_ENGINE_ENABLE_SHIFT              (2)
2621 #define CC3_SR_BIT3_TBD_MASK                    (1 << 3)
2622 #define CC3_SR_BIT3_TBD_SHIFT                   (3)
2623 #define CC3_SR_MINDIV_FAST_CLK_MASK             (0xF << 4)
2624 #define CC3_SR_MINDIV_FAST_CLK_SHIFT            (4)
2625 #define CC3_SR_R23_SR2_RISE_EDGE_TRIG_MASK      (1 << 8)
2626 #define CC3_SR_R23_SR2_RISE_EDGE_TRIG_SHIFT     (8)
2627 #define CC3_SR_R23_SR2_FALL_EDGE_TRIG_MASK      (1 << 9)
2628 #define CC3_SR_R23_SR2_FALL_EDGE_TRIG_SHIFT     (9)
2629 #define CC3_SR_R23_SR_RISE_EDGE_TRIG_MASK       (1 << 10)
2630 #define CC3_SR_R23_SR_RISE_EDGE_TRIG_SHIFT      (10)
2631 #define CC3_SR_R23_SR_FALL_EDGE_TRIG_MASK       (1 << 11)
2632 #define CC3_SR_R23_SR_FALL_EDGE_TRIG_SHIFT      (11)
2633 #define CC3_SR_NUM_CLK_HIGH_MASK                (0x7 << 12)
2634 #define CC3_SR_NUM_CLK_HIGH_SHIFT               (12)
2635 #define CC3_SR_BIT15_TBD_MASK                   (1 << 15)
2636 #define CC3_SR_BIT15_TBD_SHIFT                  (15)
2637 #define CC3_SR_PHY_FUNC_PIC_MASK                (1 << 16)
2638 #define CC3_SR_PHY_FUNC_PIC_SHIFT               (16)
2639 #define CC3_SR_BIT17_19_TBD_MASK                (0x7 << 17)
2640 #define CC3_SR_BIT17_19_TBD_SHIFT               (17)
2641 #define CC3_SR_CHIP_TRIGGER_1_MASK              (1 << 20)
2642 #define CC3_SR_CHIP_TRIGGER_1_SHIFT             (20)
2643 #define CC3_SR_CHIP_TRIGGER_2_MASK              (1 << 21)
2644 #define CC3_SR_CHIP_TRIGGER_2_SHIFT             (21)
2645 #define CC3_SR_CHIP_TRIGGER_3_MASK              (1 << 22)
2646 #define CC3_SR_CHIP_TRIGGER_3_SHIFT             (22)
2647 #define CC3_SR_CHIP_TRIGGER_4_MASK              (1 << 23)
2648 #define CC3_SR_CHIP_TRIGGER_4_SHIFT             (23)
2649 #define CC3_SR_ALLOW_SBC_FUNC_PIC_MASK          (1 << 24)
2650 #define CC3_SR_ALLOW_SBC_FUNC_PIC_SHIFT         (24)
2651 #define CC3_SR_BIT25_26_TBD_MASK                (0x3 << 25)
2652 #define CC3_SR_BIT25_26_TBD_SHIFT               (25)
2653 #define CC3_SR_ALLOW_SBC_STBY_MASK              (1 << 27)
2654 #define CC3_SR_ALLOW_SBC_STBY_SHIFT             (27)
2655 #define CC3_SR_GPIO_MUX_MASK                    (0xF << 28)
2656 #define CC3_SR_GPIO_MUX_SHIFT                   (28)
2657
2658
2659 #define CC4_SR_INIT_ADDR_MASK           (0x3FF0000)
2660 #define         CC4_4350_SR_ASM_ADDR    (0x30)
2661 #define         CC4_4335_SR_ASM_ADDR    (0x48)
2662 #define CC4_SR_INIT_ADDR_SHIFT          (16)
2663
2664 #define CC4_4350_EN_SR_CLK_ALP_MASK     (1 << 30)
2665 #define CC4_4350_EN_SR_CLK_ALP_SHIFT    (30)
2666 #define CC4_4350_EN_SR_CLK_HT_MASK      (1 << 31)
2667 #define CC4_4350_EN_SR_CLK_HT_SHIFT     (31)
2668
2669 #define VREG4_4350_MEMLPDO_PU_MASK      (1 << 31)
2670 #define VREG4_4350_MEMLPDO_PU_SHIFT     31
2671
2672 #define CC6_4350_PCIE_CLKREQ_WAKEUP_MASK        (1 << 4)
2673 #define CC6_4350_PCIE_CLKREQ_WAKEUP_SHIFT       (4)
2674 #define CC6_4350_PMU_WAKEUP_ALPAVAIL_MASK       (1 << 6)
2675 #define CC6_4350_PMU_WAKEUP_ALPAVAIL_SHIFT      (6)
2676
2677
2678 #define CC_GCI_CHIPCTRL_00      (0)
2679 #define CC_GCI_CHIPCTRL_01      (1)
2680 #define CC_GCI_CHIPCTRL_02      (2)
2681 #define CC_GCI_CHIPCTRL_03      (3)
2682 #define CC_GCI_CHIPCTRL_04      (4)
2683 #define CC_GCI_CHIPCTRL_05      (5)
2684 #define CC_GCI_CHIPCTRL_06      (6)
2685 #define CC_GCI_CHIPCTRL_07      (7)
2686 #define CC_GCI_CHIPCTRL_08      (8)
2687
2688 #define CC_GCI_06_JTAG_SEL_SHIFT        4
2689 #define CC_GCI_06_JTAG_SEL_MASK         (1 << 4)
2690
2691 #define CC_GCI_NUMCHIPCTRLREGS(cap1)    ((cap1 & 0xF00) >> 8)
2692
2693
2694 #define CC4335_PIN_GPIO_00              (0)
2695 #define CC4335_PIN_GPIO_01              (1)
2696 #define CC4335_PIN_GPIO_02              (2)
2697 #define CC4335_PIN_GPIO_03              (3)
2698 #define CC4335_PIN_GPIO_04              (4)
2699 #define CC4335_PIN_GPIO_05              (5)
2700 #define CC4335_PIN_GPIO_06              (6)
2701 #define CC4335_PIN_GPIO_07              (7)
2702 #define CC4335_PIN_GPIO_08              (8)
2703 #define CC4335_PIN_GPIO_09              (9)
2704 #define CC4335_PIN_GPIO_10              (10)
2705 #define CC4335_PIN_GPIO_11              (11)
2706 #define CC4335_PIN_GPIO_12              (12)
2707 #define CC4335_PIN_GPIO_13              (13)
2708 #define CC4335_PIN_GPIO_14              (14)
2709 #define CC4335_PIN_GPIO_15              (15)
2710 #define CC4335_PIN_SDIO_CLK             (16)
2711 #define CC4335_PIN_SDIO_CMD             (17)
2712 #define CC4335_PIN_SDIO_DATA0   (18)
2713 #define CC4335_PIN_SDIO_DATA1   (19)
2714 #define CC4335_PIN_SDIO_DATA2   (20)
2715 #define CC4335_PIN_SDIO_DATA3   (21)
2716 #define CC4335_PIN_RF_SW_CTRL_0 (22)
2717 #define CC4335_PIN_RF_SW_CTRL_1 (23)
2718 #define CC4335_PIN_RF_SW_CTRL_2 (24)
2719 #define CC4335_PIN_RF_SW_CTRL_3 (25)
2720 #define CC4335_PIN_RF_SW_CTRL_4 (26)
2721 #define CC4335_PIN_RF_SW_CTRL_5 (27)
2722 #define CC4335_PIN_RF_SW_CTRL_6 (28)
2723 #define CC4335_PIN_RF_SW_CTRL_7 (29)
2724 #define CC4335_PIN_RF_SW_CTRL_8 (30)
2725 #define CC4335_PIN_RF_SW_CTRL_9 (31)
2726
2727
2728 #define CC4335_FNSEL_HWDEF              (0)
2729 #define CC4335_FNSEL_SAMEASPIN  (1)
2730 #define CC4335_FNSEL_GPIO0              (2)
2731 #define CC4335_FNSEL_GPIO1              (3)
2732 #define CC4335_FNSEL_GCI0               (4)
2733 #define CC4335_FNSEL_GCI1               (5)
2734 #define CC4335_FNSEL_UART               (6)
2735 #define CC4335_FNSEL_SFLASH             (7)
2736 #define CC4335_FNSEL_SPROM              (8)
2737 #define CC4335_FNSEL_MISC0              (9)
2738 #define CC4335_FNSEL_MISC1              (10)
2739 #define CC4335_FNSEL_MISC2              (11)
2740 #define CC4335_FNSEL_IND                (12)
2741 #define CC4335_FNSEL_PDN                (13)
2742 #define CC4335_FNSEL_PUP                (14)
2743 #define CC4335_FNSEL_TRI                (15)
2744
2745
2746 #define GCIMASK(pos)  (((uint32)0xF) << pos)
2747
2748
2749 #define GCIPOSVAL(val, pos)  ((((uint32)val) << pos) & GCIMASK(pos))
2750
2751
2752 #define MUXENAB4335_UART_MASK           (0x0000000f)
2753
2754 #define MUXENAB4335_UART_SHIFT          0
2755 #define MUXENAB4335_HOSTWAKE_MASK       (0x000000f0)
2756 #define MUXENAB4335_HOSTWAKE_SHIFT      4
2757 #define MUXENAB4335_GETIX(val, name) \
2758         ((((val) & MUXENAB4335_ ## name ## _MASK) >> MUXENAB4335_ ## name ## _SHIFT) - 1)
2759
2760
2761 #define CHIP_HOSTIF_USB(sih)    (si_chip_hostif(sih) & CST4360_MODE_USB)
2762
2763
2764 #define PMU_MAX_TRANSITION_DLY  15000
2765
2766
2767 #define PMURES_UP_TRANSITION    2
2768
2769
2770
2771 #define SECI_MODE_UART                  0x0
2772 #define SECI_MODE_SECI                  0x1
2773 #define SECI_MODE_LEGACY_3WIRE_BT       0x2
2774 #define SECI_MODE_LEGACY_3WIRE_WLAN     0x3
2775 #define SECI_MODE_HALF_SECI             0x4
2776
2777 #define SECI_RESET              (1 << 0)
2778 #define SECI_RESET_BAR_UART     (1 << 1)
2779 #define SECI_ENAB_SECI_ECI      (1 << 2)
2780 #define SECI_ENAB_SECIOUT_DIS   (1 << 3)
2781 #define SECI_MODE_MASK          0x7
2782 #define SECI_MODE_SHIFT         4
2783 #define SECI_UPD_SECI           (1 << 7)
2784
2785 #define SECI_SIGNOFF_0     0xDB
2786 #define SECI_SIGNOFF_1     0
2787
2788
2789 #define CLKCTL_STS_SECI_CLK_REQ         (1 << 8)
2790 #define CLKCTL_STS_SECI_CLK_AVAIL       (1 << 24)
2791
2792 #define SECI_UART_MSR_CTS_STATE         (1 << 0)
2793 #define SECI_UART_MSR_RTS_STATE         (1 << 1)
2794 #define SECI_UART_SECI_IN_STATE         (1 << 2)
2795 #define SECI_UART_SECI_IN2_STATE        (1 << 3)
2796
2797
2798 #define SECI_UART_LCR_STOP_BITS         (1 << 0)
2799 #define SECI_UART_LCR_PARITY_EN         (1 << 1)
2800 #define SECI_UART_LCR_PARITY            (1 << 2)
2801 #define SECI_UART_LCR_RX_EN             (1 << 3)
2802 #define SECI_UART_LCR_LBRK_CTRL         (1 << 4)
2803 #define SECI_UART_LCR_TXO_EN            (1 << 5)
2804 #define SECI_UART_LCR_RTSO_EN           (1 << 6)
2805 #define SECI_UART_LCR_SLIPMODE_EN       (1 << 7)
2806 #define SECI_UART_LCR_RXCRC_CHK         (1 << 8)
2807 #define SECI_UART_LCR_TXCRC_INV         (1 << 9)
2808 #define SECI_UART_LCR_TXCRC_LSBF        (1 << 10)
2809 #define SECI_UART_LCR_TXCRC_EN          (1 << 11)
2810
2811 #define SECI_UART_MCR_TX_EN             (1 << 0)
2812 #define SECI_UART_MCR_PRTS              (1 << 1)
2813 #define SECI_UART_MCR_SWFLCTRL_EN       (1 << 2)
2814 #define SECI_UART_MCR_HIGHRATE_EN       (1 << 3)
2815 #define SECI_UART_MCR_LOOPBK_EN         (1 << 4)
2816 #define SECI_UART_MCR_AUTO_RTS          (1 << 5)
2817 #define SECI_UART_MCR_AUTO_TX_DIS       (1 << 6)
2818 #define SECI_UART_MCR_BAUD_ADJ_EN       (1 << 7)
2819 #define SECI_UART_MCR_XONOFF_RPT        (1 << 9)
2820
2821
2822
2823
2824 #define ECI_BW_20   0x0
2825 #define ECI_BW_25   0x1
2826 #define ECI_BW_30   0x2
2827 #define ECI_BW_35   0x3
2828 #define ECI_BW_40   0x4
2829 #define ECI_BW_45   0x5
2830 #define ECI_BW_50   0x6
2831 #define ECI_BW_ALL  0x7
2832
2833
2834 #define WLAN_NUM_ANT1 TXANT_0
2835 #define WLAN_NUM_ANT2 TXANT_1
2836
2837 #endif