1 /******************************************************************************
3 * Copyright(c) 2009-2010 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
40 #include "../pwrseqcmd.h"
42 #include "../btcoexist/rtl_btc.h"
46 static void _rtl8821ae_return_beacon_queue_skb(struct ieee80211_hw *hw)
48 struct rtl_priv *rtlpriv = rtl_priv(hw);
49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
50 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
53 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
54 while (skb_queue_len(&ring->queue)) {
55 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
56 struct sk_buff *skb = __skb_dequeue(&ring->queue);
58 pci_unmap_single(rtlpci->pdev,
59 rtlpriv->cfg->ops->get_desc(
60 (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
61 skb->len, PCI_DMA_TODEVICE);
63 ring->idx = (ring->idx + 1) % ring->entries;
65 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
68 static void _rtl8821ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
69 u8 set_bits, u8 clear_bits)
71 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
72 struct rtl_priv *rtlpriv = rtl_priv(hw);
74 rtlpci->reg_bcn_ctrl_val |= set_bits;
75 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
77 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
80 void _rtl8821ae_stop_tx_beacon(struct ieee80211_hw *hw)
82 struct rtl_priv *rtlpriv = rtl_priv(hw);
85 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
86 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
87 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
88 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
89 tmp1byte &= ~(BIT(0));
90 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
93 void _rtl8821ae_resume_tx_beacon(struct ieee80211_hw *hw)
95 struct rtl_priv *rtlpriv = rtl_priv(hw);
98 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
99 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
100 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
101 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
103 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
106 static void _rtl8821ae_enable_bcn_sub_func(struct ieee80211_hw *hw)
108 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(1));
111 static void _rtl8821ae_disable_bcn_sub_func(struct ieee80211_hw *hw)
113 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(1), 0);
116 static void _rtl8821ae_set_fw_clock_on(struct ieee80211_hw *hw,
117 u8 rpwm_val, bool b_need_turn_off_ckk)
119 struct rtl_priv *rtlpriv = rtl_priv(hw);
120 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
121 bool b_support_remote_wake_up;
122 u32 count = 0, isr_regaddr, content;
123 bool b_schedule_timer = b_need_turn_off_ckk;
125 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
126 (u8 *)(&b_support_remote_wake_up));
128 if (!rtlhal->fw_ready)
130 if (!rtlpriv->psc.fw_current_inpsmode)
134 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
135 if (rtlhal->fw_clk_change_in_progress) {
136 while (rtlhal->fw_clk_change_in_progress) {
137 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
142 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
144 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
146 rtlhal->fw_clk_change_in_progress = false;
147 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
152 if (IS_IN_LOW_POWER_STATE_8821AE(rtlhal->fw_ps_state)) {
153 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
155 if (FW_PS_IS_ACK(rpwm_val)) {
156 isr_regaddr = REG_HISR;
157 content = rtl_read_dword(rtlpriv, isr_regaddr);
158 while (!(content & IMR_CPWM) && (count < 500)) {
161 content = rtl_read_dword(rtlpriv, isr_regaddr);
164 if (content & IMR_CPWM) {
165 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
166 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_8821AE;
167 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
168 "Receive CPWM INT!!! Set rtlhal->FwPSState = %X\n",
169 rtlhal->fw_ps_state);
173 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
174 rtlhal->fw_clk_change_in_progress = false;
175 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
176 if (b_schedule_timer)
177 mod_timer(&rtlpriv->works.fw_clockoff_timer,
178 jiffies + MSECS(10));
180 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
181 rtlhal->fw_clk_change_in_progress = false;
182 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
186 static void _rtl8821ae_set_fw_clock_off(struct ieee80211_hw *hw,
189 struct rtl_priv *rtlpriv = rtl_priv(hw);
190 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
191 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
192 struct rtl8192_tx_ring *ring;
193 enum rf_pwrstate rtstate;
194 bool b_schedule_timer = false;
197 if (!rtlhal->fw_ready)
199 if (!rtlpriv->psc.fw_current_inpsmode)
201 if (!rtlhal->allow_sw_to_change_hwclc)
203 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
204 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
207 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
208 ring = &rtlpci->tx_ring[queue];
209 if (skb_queue_len(&ring->queue)) {
210 b_schedule_timer = true;
215 if (b_schedule_timer) {
216 mod_timer(&rtlpriv->works.fw_clockoff_timer,
217 jiffies + MSECS(10));
221 if (FW_PS_STATE(rtlhal->fw_ps_state) !=
222 FW_PS_STATE_RF_OFF_LOW_PWR_8821AE) {
223 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
224 if (!rtlhal->fw_clk_change_in_progress) {
225 rtlhal->fw_clk_change_in_progress = true;
226 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
227 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
228 rtl_write_word(rtlpriv, REG_HISR, 0x0100);
229 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
231 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
232 rtlhal->fw_clk_change_in_progress = false;
233 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
235 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
236 mod_timer(&rtlpriv->works.fw_clockoff_timer,
237 jiffies + MSECS(10));
242 static void _rtl8821ae_set_fw_ps_rf_on(struct ieee80211_hw *hw)
246 rpwm_val |= (FW_PS_STATE_RF_OFF_8821AE | FW_PS_ACK);
247 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, true);
250 static void _rtl8821ae_fwlps_leave(struct ieee80211_hw *hw)
252 struct rtl_priv *rtlpriv = rtl_priv(hw);
253 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
254 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
255 bool fw_current_inps = false;
256 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
258 if (ppsc->low_power_enable) {
259 rpwm_val = (FW_PS_STATE_ALL_ON_8821AE|FW_PS_ACK);/* RF on */
260 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, false);
261 rtlhal->allow_sw_to_change_hwclc = false;
262 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
263 (u8 *)(&fw_pwrmode));
264 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
265 (u8 *)(&fw_current_inps));
267 rpwm_val = FW_PS_STATE_ALL_ON_8821AE; /* RF on */
268 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
270 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
271 (u8 *)(&fw_pwrmode));
272 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
273 (u8 *)(&fw_current_inps));
277 static void _rtl8821ae_fwlps_enter(struct ieee80211_hw *hw)
279 struct rtl_priv *rtlpriv = rtl_priv(hw);
280 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
281 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
282 bool fw_current_inps = true;
285 if (ppsc->low_power_enable) {
286 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_8821AE; /* RF off */
287 rtlpriv->cfg->ops->set_hw_reg(hw,
288 HW_VAR_FW_PSMODE_STATUS,
289 (u8 *)(&fw_current_inps));
290 rtlpriv->cfg->ops->set_hw_reg(hw,
291 HW_VAR_H2C_FW_PWRMODE,
292 (u8 *)(&ppsc->fwctrl_psmode));
293 rtlhal->allow_sw_to_change_hwclc = true;
294 _rtl8821ae_set_fw_clock_off(hw, rpwm_val);
296 rpwm_val = FW_PS_STATE_RF_OFF_8821AE; /* RF off */
297 rtlpriv->cfg->ops->set_hw_reg(hw,
298 HW_VAR_FW_PSMODE_STATUS,
299 (u8 *)(&fw_current_inps));
300 rtlpriv->cfg->ops->set_hw_reg(hw,
301 HW_VAR_H2C_FW_PWRMODE,
302 (u8 *)(&ppsc->fwctrl_psmode));
303 rtlpriv->cfg->ops->set_hw_reg(hw,
309 static void _rtl8821ae_download_rsvd_page(struct ieee80211_hw *hw,
310 bool dl_whole_packets)
312 struct rtl_priv *rtlpriv = rtl_priv(hw);
313 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
314 u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
315 u8 count = 0, dlbcn_count = 0;
316 bool send_beacon = false;
318 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
319 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr | BIT(0)));
321 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
322 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
324 tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
325 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
326 tmp_reg422 & (~BIT(6)));
327 if (tmp_reg422 & BIT(6))
331 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
332 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
333 (bcnvalid_reg | BIT(0)));
334 _rtl8821ae_return_beacon_queue_skb(hw);
336 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
337 rtl8812ae_set_fw_rsvdpagepkt(hw, false,
340 rtl8821ae_set_fw_rsvdpagepkt(hw, false,
343 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
345 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
348 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
351 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
353 if (!(bcnvalid_reg & BIT(0)))
354 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
355 "Download RSVD page failed!\n");
356 if (bcnvalid_reg & BIT(0) && rtlhal->enter_pnp_sleep) {
357 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, bcnvalid_reg | BIT(0));
358 _rtl8821ae_return_beacon_queue_skb(hw);
362 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
363 bcnvalid_reg | BIT(0));
365 _rtl8821ae_return_beacon_queue_skb(hw);
367 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
368 rtl8812ae_set_fw_rsvdpagepkt(hw, true,
371 rtl8821ae_set_fw_rsvdpagepkt(hw, true,
374 /* check rsvd page download OK. */
375 bcnvalid_reg = rtl_read_byte(rtlpriv,
378 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
382 rtl_read_byte(rtlpriv,
386 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
388 if (!(bcnvalid_reg & BIT(0)))
389 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
390 "2 Download RSVD page failed!\n");
394 if (bcnvalid_reg & BIT(0))
395 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0));
397 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
398 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
401 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
403 if (!rtlhal->enter_pnp_sleep) {
404 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
405 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0))));
409 void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
411 struct rtl_priv *rtlpriv = rtl_priv(hw);
412 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
413 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
414 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
417 case HW_VAR_ETHER_ADDR:
418 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_MACID);
419 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_MACID + 4);
422 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_BSSID);
423 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_BSSID+4);
425 case HW_VAR_MEDIA_STATUS:
426 val[0] = rtl_read_byte(rtlpriv, MSR) & 0x3;
428 case HW_VAR_SLOT_TIME:
429 *((u8 *)(val)) = mac->slot_time;
431 case HW_VAR_BEACON_INTERVAL:
432 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_BCN_INTERVAL);
434 case HW_VAR_ATIM_WINDOW:
435 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_ATIMWND);
438 *((u32 *)(val)) = rtlpci->receive_config;
440 case HW_VAR_RF_STATE:
441 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
443 case HW_VAR_FWLPS_RF_ON:{
444 enum rf_pwrstate rfstate;
447 rtlpriv->cfg->ops->get_hw_reg(hw,
450 if (rfstate == ERFOFF) {
451 *((bool *)(val)) = true;
453 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
454 val_rcr &= 0x00070000;
456 *((bool *)(val)) = false;
458 *((bool *)(val)) = true;
461 case HW_VAR_FW_PSMODE_STATUS:
462 *((bool *)(val)) = ppsc->fw_current_inpsmode;
464 case HW_VAR_CORRECT_TSF:{
466 u32 *ptsf_low = (u32 *)&tsf;
467 u32 *ptsf_high = ((u32 *)&tsf) + 1;
469 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
470 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
472 *((u64 *)(val)) = tsf;
476 if (ppsc->wo_wlan_mode)
477 *((bool *)(val)) = true;
479 *((bool *)(val)) = false;
482 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
483 "switch case not process %x\n", variable);
488 void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
490 struct rtl_priv *rtlpriv = rtl_priv(hw);
491 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
492 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
493 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
494 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
495 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
499 case HW_VAR_ETHER_ADDR:{
500 for (idx = 0; idx < ETH_ALEN; idx++) {
501 rtl_write_byte(rtlpriv, (REG_MACID + idx),
506 case HW_VAR_BASIC_RATE:{
507 u16 b_rate_cfg = ((u16 *)val)[0];
508 b_rate_cfg = b_rate_cfg & 0x15f;
509 rtl_write_word(rtlpriv, REG_RRSR, b_rate_cfg);
513 for (idx = 0; idx < ETH_ALEN; idx++) {
514 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
520 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
521 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[0]);
523 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
524 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
526 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]);
527 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM, val[0]);
529 case HW_VAR_R2T_SIFS:
530 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]);
532 case HW_VAR_SLOT_TIME:{
535 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
536 "HW_VAR_SLOT_TIME %x\n", val[0]);
538 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
540 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
541 rtlpriv->cfg->ops->set_hw_reg(hw,
546 case HW_VAR_ACK_PREAMBLE:{
548 u8 short_preamble = (bool)(*(u8 *)val);
550 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
551 if (short_preamble) {
553 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2,
556 reg_tmp &= (~BIT(1));
557 rtl_write_byte(rtlpriv,
562 case HW_VAR_WPA_CONFIG:
563 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
565 case HW_VAR_AMPDU_MIN_SPACE:{
566 u8 min_spacing_to_set;
569 min_spacing_to_set = *((u8 *)val);
570 if (min_spacing_to_set <= 7) {
573 if (min_spacing_to_set < sec_min_space)
574 min_spacing_to_set = sec_min_space;
576 mac->min_space_cfg = ((mac->min_space_cfg &
580 *val = min_spacing_to_set;
582 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
583 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
586 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
590 case HW_VAR_SHORTGI_DENSITY:{
593 density_to_set = *((u8 *)val);
594 mac->min_space_cfg |= (density_to_set << 3);
596 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
597 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
600 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
604 case HW_VAR_AMPDU_FACTOR:{
605 u32 ampdu_len = (*((u8 *)val));
607 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
608 if (ampdu_len < VHT_AGG_SIZE_128K)
610 (0x2000 << (*((u8 *)val))) - 1;
613 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
614 if (ampdu_len < HT_AGG_SIZE_64K)
616 (0x2000 << (*((u8 *)val))) - 1;
620 ampdu_len |= BIT(31);
622 rtl_write_dword(rtlpriv,
623 REG_AMPDU_MAX_LENGTH_8812, ampdu_len);
625 case HW_VAR_AC_PARAM:{
626 u8 e_aci = *((u8 *)val);
628 rtl8821ae_dm_init_edca_turbo(hw);
629 if (rtlpci->acm_method != EACMWAY2_SW)
630 rtlpriv->cfg->ops->set_hw_reg(hw,
634 case HW_VAR_ACM_CTRL:{
635 u8 e_aci = *((u8 *)val);
636 union aci_aifsn *p_aci_aifsn =
637 (union aci_aifsn *)(&mac->ac[0].aifs);
638 u8 acm = p_aci_aifsn->f.acm;
639 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
642 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
647 acm_ctrl |= ACMHW_BEQEN;
650 acm_ctrl |= ACMHW_VIQEN;
653 acm_ctrl |= ACMHW_VOQEN;
656 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
657 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
664 acm_ctrl &= (~ACMHW_BEQEN);
667 acm_ctrl &= (~ACMHW_VIQEN);
670 acm_ctrl &= (~ACMHW_VOQEN);
673 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
674 "switch case not process\n");
679 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
680 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
682 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
685 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
686 rtlpci->receive_config = ((u32 *)(val))[0];
688 case HW_VAR_RETRY_LIMIT:{
689 u8 retry_limit = ((u8 *)(val))[0];
691 rtl_write_word(rtlpriv, REG_RL,
692 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
693 retry_limit << RETRY_LIMIT_LONG_SHIFT);
695 case HW_VAR_DUAL_TSF_RST:
696 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
698 case HW_VAR_EFUSE_BYTES:
699 rtlefuse->efuse_usedbytes = *((u16 *)val);
701 case HW_VAR_EFUSE_USAGE:
702 rtlefuse->efuse_usedpercentage = *((u8 *)val);
705 rtl8821ae_phy_set_io_cmd(hw, (*(enum io_type *)val));
707 case HW_VAR_SET_RPWM:{
710 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
713 if (rpwm_val & BIT(7)) {
714 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
717 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
718 ((*(u8 *)val) | BIT(7)));
722 case HW_VAR_H2C_FW_PWRMODE:
723 rtl8821ae_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
725 case HW_VAR_FW_PSMODE_STATUS:
726 ppsc->fw_current_inpsmode = *((bool *)val);
728 case HW_VAR_INIT_RTS_RATE:
730 case HW_VAR_RESUME_CLK_ON:
731 _rtl8821ae_set_fw_ps_rf_on(hw);
733 case HW_VAR_FW_LPS_ACTION:{
734 bool b_enter_fwlps = *((bool *)val);
737 _rtl8821ae_fwlps_enter(hw);
739 _rtl8821ae_fwlps_leave(hw);
741 case HW_VAR_H2C_FW_JOINBSSRPT:{
742 u8 mstatus = (*(u8 *)val);
744 if (mstatus == RT_MEDIA_CONNECT) {
745 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
747 _rtl8821ae_download_rsvd_page(hw, false);
749 rtl8821ae_set_fw_media_status_rpt_cmd(hw, mstatus);
752 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
753 rtl8821ae_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
757 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
759 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
762 case HW_VAR_CORRECT_TSF:{
763 u8 btype_ibss = ((u8 *)(val))[0];
766 _rtl8821ae_stop_tx_beacon(hw);
768 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
770 rtl_write_dword(rtlpriv, REG_TSFTR,
771 (u32)(mac->tsf & 0xffffffff));
772 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
773 (u32)((mac->tsf >> 32) & 0xffffffff));
775 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
778 _rtl8821ae_resume_tx_beacon(hw);
780 case HW_VAR_NAV_UPPER: {
781 u32 us_nav_upper = ((u32)*val);
783 if (us_nav_upper > HAL_92C_NAV_UPPER_UNIT * 0xFF) {
784 RT_TRACE(rtlpriv, COMP_INIT , DBG_WARNING,
785 "The setting value (0x%08X us) of NAV_UPPER is larger than (%d * 0xFF)!!!\n",
786 us_nav_upper, HAL_92C_NAV_UPPER_UNIT);
789 rtl_write_byte(rtlpriv, REG_NAV_UPPER,
790 ((u8)((us_nav_upper +
791 HAL_92C_NAV_UPPER_UNIT - 1) /
792 HAL_92C_NAV_UPPER_UNIT)));
794 case HW_VAR_KEEP_ALIVE: {
797 array[1] = *((u8 *)val);
798 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_KEEP_ALIVE_CTRL, 2,
802 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
803 "switch case not process %x\n", variable);
808 static bool _rtl8821ae_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
810 struct rtl_priv *rtlpriv = rtl_priv(hw);
813 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
814 _LLT_OP(_LLT_WRITE_ACCESS);
816 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
819 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
820 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
823 if (count > POLLING_LLT_THRESHOLD) {
824 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
825 "Failed to polling write LLT done at address %d!\n",
835 static bool _rtl8821ae_llt_table_init(struct ieee80211_hw *hw)
837 struct rtl_priv *rtlpriv = rtl_priv(hw);
845 txpktbuf_bndy = 0xF8;
847 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8812AE) {
848 txpktbuf_bndy = 0xFA;
852 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
853 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, MAX_RX_DMA_BUFFER_SIZE - 1);
855 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
857 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
858 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
860 rtl_write_byte(rtlpriv, REG_PBP, 0x31);
861 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
863 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
864 status = _rtl8821ae_llt_write(hw, i, i + 1);
869 status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
873 for (i = txpktbuf_bndy; i < maxpage; i++) {
874 status = _rtl8821ae_llt_write(hw, i, (i + 1));
879 status = _rtl8821ae_llt_write(hw, maxpage, txpktbuf_bndy);
883 rtl_write_dword(rtlpriv, REG_RQPN, rqpn);
885 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00);
890 static void _rtl8821ae_gen_refresh_led_state(struct ieee80211_hw *hw)
892 struct rtl_priv *rtlpriv = rtl_priv(hw);
893 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
894 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
895 struct rtl_led *pled0 = &pcipriv->ledctl.sw_led0;
896 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
898 if (rtlpriv->rtlhal.up_first_time)
901 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
902 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
903 rtl8812ae_sw_led_on(hw, pled0);
905 rtl8821ae_sw_led_on(hw, pled0);
906 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
907 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
908 rtl8812ae_sw_led_on(hw, pled0);
910 rtl8821ae_sw_led_on(hw, pled0);
912 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
913 rtl8812ae_sw_led_off(hw, pled0);
915 rtl8821ae_sw_led_off(hw, pled0);
918 static bool _rtl8821ae_init_mac(struct ieee80211_hw *hw)
920 struct rtl_priv *rtlpriv = rtl_priv(hw);
921 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
922 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
926 bool mac_func_enable = rtlhal->mac_func_enable;
928 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
930 /*Auto Power Down to CHIP-off State*/
931 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
932 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
934 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
935 /* HW Power on sequence*/
936 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
937 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
938 RTL8812_NIC_ENABLE_FLOW)) {
939 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
940 "init 8812 MAC Fail as power on failure\n");
944 /* HW Power on sequence */
945 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_A_MSK,
946 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
947 RTL8821A_NIC_ENABLE_FLOW)){
948 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
949 "init 8821 MAC Fail as power on failure\n");
954 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
955 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
957 bytetmp = rtl_read_byte(rtlpriv, REG_CR);
959 rtl_write_byte(rtlpriv, REG_CR, bytetmp);
963 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
966 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
967 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3);
968 if (bytetmp & BIT(0)) {
969 bytetmp = rtl_read_byte(rtlpriv, 0x7c);
971 rtl_write_byte(rtlpriv, 0x7c, bytetmp);
975 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
977 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp);
979 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
981 if (!mac_func_enable) {
982 if (!_rtl8821ae_llt_table_init(hw))
986 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
987 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
989 /* Enable FW Beamformer Interrupt */
990 bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3);
991 rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6));
993 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
996 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
998 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
999 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1000 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
1002 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
1003 rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
1004 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
1005 rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
1006 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
1007 rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
1008 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
1009 rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
1010 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
1011 rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
1012 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
1013 rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
1014 rtl_write_dword(rtlpriv, REG_HQ_DESA,
1015 rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
1016 rtl_write_dword(rtlpriv, REG_RX_DESA,
1017 rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
1019 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
1021 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
1023 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0);
1025 rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3);
1026 _rtl8821ae_gen_refresh_led_state(hw);
1031 static void _rtl8821ae_hw_configure(struct ieee80211_hw *hw)
1033 struct rtl_priv *rtlpriv = rtl_priv(hw);
1034 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1037 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1039 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
1040 /* ARFB table 9 for 11ac 5G 2SS */
1041 rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000);
1042 /* ARFB table 10 for 11ac 5G 1SS */
1043 rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000);
1044 /* ARFB table 11 for 11ac 24G 1SS */
1045 rtl_write_dword(rtlpriv, REG_ARFR2, 0x00000015);
1046 rtl_write_dword(rtlpriv, REG_ARFR2 + 4, 0x003ff000);
1047 /* ARFB table 12 for 11ac 24G 1SS */
1048 rtl_write_dword(rtlpriv, REG_ARFR3, 0x00000015);
1049 rtl_write_dword(rtlpriv, REG_ARFR3 + 4, 0xffcff000);
1050 /* 0x420[7] = 0 , enable retry AMPDU in new AMPD not singal MPDU. */
1051 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00);
1052 rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70);
1055 rtl_write_word(rtlpriv, REG_RL, 0x0707);
1057 /* Set Data / Response auto rate fallack retry count*/
1058 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
1059 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
1060 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
1061 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
1063 rtlpci->reg_bcn_ctrl_val = 0x1d;
1064 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
1066 /* TBTT prohibit hold time. Suggested by designer TimChen. */
1067 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1069 /* AGGR_BK_TIME Reg51A 0x16 */
1070 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
1072 /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
1073 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
1075 rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80);
1076 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
1077 rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1F1F);
1080 static u16 _rtl8821ae_mdio_read(struct rtl_priv *rtlpriv, u8 addr)
1083 u8 tmp = 0, count = 0;
1085 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6));
1086 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1088 while (tmp && count < 20) {
1090 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1094 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA);
1099 static void _rtl8821ae_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data)
1101 u8 tmp = 0, count = 0;
1103 rtl_write_word(rtlpriv, REG_MDIO_WDATA, data);
1104 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5));
1105 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1107 while (tmp && count < 20) {
1109 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1114 static u8 _rtl8821ae_dbi_read(struct rtl_priv *rtlpriv, u16 addr)
1116 u16 read_addr = addr & 0xfffc;
1117 u8 tmp = 0, count = 0, ret = 0;
1119 rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr);
1120 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2);
1121 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1123 while (tmp && count < 20) {
1125 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1129 read_addr = REG_DBI_RDATA + addr % 4;
1130 ret = rtl_read_word(rtlpriv, read_addr);
1135 static void _rtl8821ae_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data)
1137 u8 tmp = 0, count = 0;
1138 u16 wrtie_addr, remainder = addr % 4;
1140 wrtie_addr = REG_DBI_WDATA + remainder;
1141 rtl_write_byte(rtlpriv, wrtie_addr, data);
1143 wrtie_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12));
1144 rtl_write_word(rtlpriv, REG_DBI_ADDR, wrtie_addr);
1146 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1);
1148 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1150 while (tmp && count < 20) {
1152 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1157 static void _rtl8821ae_enable_aspm_back_door(struct ieee80211_hw *hw)
1159 struct rtl_priv *rtlpriv = rtl_priv(hw);
1160 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1163 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1164 if (_rtl8821ae_mdio_read(rtlpriv, 0x04) != 0x8544)
1165 _rtl8821ae_mdio_write(rtlpriv, 0x04, 0x8544);
1167 if (_rtl8821ae_mdio_read(rtlpriv, 0x0b) != 0x0070)
1168 _rtl8821ae_mdio_write(rtlpriv, 0x0b, 0x0070);
1171 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x70f);
1172 _rtl8821ae_dbi_write(rtlpriv, 0x70f, tmp | BIT(7));
1174 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x719);
1175 _rtl8821ae_dbi_write(rtlpriv, 0x719, tmp | BIT(3) | BIT(4));
1177 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1178 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1179 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp|BIT(4));
1183 void rtl8821ae_enable_hw_security_config(struct ieee80211_hw *hw)
1185 struct rtl_priv *rtlpriv = rtl_priv(hw);
1189 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1190 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1191 rtlpriv->sec.pairwise_enc_algorithm,
1192 rtlpriv->sec.group_enc_algorithm);
1194 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1195 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1196 "not open hw encryption\n");
1200 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1202 if (rtlpriv->sec.use_defaultkey) {
1203 sec_reg_value |= SCR_TXUSEDK;
1204 sec_reg_value |= SCR_RXUSEDK;
1207 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1209 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1210 rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1));
1212 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1213 "The SECR-value %x\n", sec_reg_value);
1215 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1218 /* Static MacID Mapping (cf. Used in MacIdDoStaticMapping) ---------- */
1219 #define MAC_ID_STATIC_FOR_DEFAULT_PORT 0
1220 #define MAC_ID_STATIC_FOR_BROADCAST_MULTICAST 1
1221 #define MAC_ID_STATIC_FOR_BT_CLIENT_START 2
1222 #define MAC_ID_STATIC_FOR_BT_CLIENT_END 3
1223 /* ----------------------------------------------------------- */
1225 static void rtl8821ae_macid_initialize_mediastatus(struct ieee80211_hw *hw)
1227 struct rtl_priv *rtlpriv = rtl_priv(hw);
1228 u8 media_rpt[4] = {RT_MEDIA_CONNECT, 1,
1229 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1230 MAC_ID_STATIC_FOR_BT_CLIENT_END};
1232 rtlpriv->cfg->ops->set_hw_reg(hw,
1233 HW_VAR_H2C_FW_MEDIASTATUSRPT, media_rpt);
1235 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1236 "Initialize MacId media status: from %d to %d\n",
1237 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1238 MAC_ID_STATIC_FOR_BT_CLIENT_END);
1241 static bool _rtl8821ae_check_pcie_dma_hang(struct ieee80211_hw *hw)
1243 struct rtl_priv *rtlpriv = rtl_priv(hw);
1246 /* write reg 0x350 Bit[26]=1. Enable debug port. */
1247 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1248 if (!(tmp & BIT(2))) {
1249 rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2)));
1253 /* read reg 0x350 Bit[25] if 1 : RX hang */
1254 /* read reg 0x350 Bit[24] if 1 : TX hang */
1255 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1256 if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1257 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1258 "CheckPcieDMAHang8821AE(): true! Reset PCIE DMA!\n");
1265 static bool _rtl8821ae_reset_pcie_interface_dma(struct ieee80211_hw *hw,
1269 struct rtl_priv *rtlpriv = rtl_priv(hw);
1270 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1272 bool release_mac_rx_pause;
1273 u8 backup_pcie_dma_pause;
1275 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
1277 /* 1. Disable register write lock. 0x1c[1] = 0 */
1278 tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1280 rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1281 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1282 /* write 0xCC bit[2] = 1'b1 */
1283 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1285 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1288 /* 2. Check and pause TRX DMA */
1289 /* write 0x284 bit[18] = 1'b1 */
1290 /* write 0x301 = 0xFF */
1291 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1293 /* Already pause before the function for another purpose. */
1294 release_mac_rx_pause = false;
1296 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1297 release_mac_rx_pause = true;
1299 backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1);
1300 if (backup_pcie_dma_pause != 0xFF)
1301 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF);
1304 /* 3. reset TRX function */
1305 /* write 0x100 = 0x00 */
1306 rtl_write_byte(rtlpriv, REG_CR, 0);
1309 /* 4. Reset PCIe DMA. 0x3[0] = 0 */
1310 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1312 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1314 /* 5. Enable PCIe DMA. 0x3[0] = 1 */
1315 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1317 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1320 /* 6. enable TRX function */
1321 /* write 0x100 = 0xFF */
1322 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1324 /* We should init LLT & RQPN and
1325 * prepare Tx/Rx descrptor address later
1326 * because MAC function is reset.*/
1329 /* 7. Restore PCIe autoload down bit */
1330 /* 8812AE does not has the defination. */
1331 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1332 /* write 0xF8 bit[17] = 1'b1 */
1333 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2);
1335 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp);
1338 /* In MAC power on state, BB and RF maybe in ON state,
1339 * if we release TRx DMA here.
1340 * it will cause packets to be started to Tx/Rx,
1341 * so we release Tx/Rx DMA later.*/
1342 if (!mac_power_on/* || in_watchdog*/) {
1343 /* 8. release TRX DMA */
1344 /* write 0x284 bit[18] = 1'b0 */
1345 /* write 0x301 = 0x00 */
1346 if (release_mac_rx_pause) {
1347 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1348 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL,
1351 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1,
1352 backup_pcie_dma_pause);
1355 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1356 /* 9. lock system register */
1357 /* write 0xCC bit[2] = 1'b0 */
1358 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1360 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1365 static void _rtl8821ae_get_wakeup_reason(struct ieee80211_hw *hw)
1367 struct rtl_priv *rtlpriv = rtl_priv(hw);
1368 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1369 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
1373 fw_reason = rtl_read_byte(rtlpriv, REG_MCUTST_WOWLAN);
1375 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "WOL Read 0x1c7 = %02X\n",
1378 ppsc->wakeup_reason = 0;
1380 rtlhal->last_suspend_sec = ts.tv_sec;
1382 switch (fw_reason) {
1383 case FW_WOW_V2_PTK_UPDATE_EVENT:
1384 ppsc->wakeup_reason = WOL_REASON_PTK_UPDATE;
1385 do_gettimeofday(&ts);
1386 ppsc->last_wakeup_time = ts.tv_sec*1000 + ts.tv_usec/1000;
1387 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1388 "It's a WOL PTK Key update event!\n");
1390 case FW_WOW_V2_GTK_UPDATE_EVENT:
1391 ppsc->wakeup_reason = WOL_REASON_GTK_UPDATE;
1392 do_gettimeofday(&ts);
1393 ppsc->last_wakeup_time = ts.tv_sec*1000 + ts.tv_usec/1000;
1394 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1395 "It's a WOL GTK Key update event!\n");
1397 case FW_WOW_V2_DISASSOC_EVENT:
1398 ppsc->wakeup_reason = WOL_REASON_DISASSOC;
1399 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1400 "It's a disassociation event!\n");
1402 case FW_WOW_V2_DEAUTH_EVENT:
1403 ppsc->wakeup_reason = WOL_REASON_DEAUTH;
1404 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1405 "It's a deauth event!\n");
1407 case FW_WOW_V2_FW_DISCONNECT_EVENT:
1408 ppsc->wakeup_reason = WOL_REASON_AP_LOST;
1409 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1410 "It's a Fw disconnect decision (AP lost) event!\n");
1412 case FW_WOW_V2_MAGIC_PKT_EVENT:
1413 ppsc->wakeup_reason = WOL_REASON_MAGIC_PKT;
1414 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1415 "It's a magic packet event!\n");
1417 case FW_WOW_V2_UNICAST_PKT_EVENT:
1418 ppsc->wakeup_reason = WOL_REASON_UNICAST_PKT;
1419 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1420 "It's an unicast packet event!\n");
1422 case FW_WOW_V2_PATTERN_PKT_EVENT:
1423 ppsc->wakeup_reason = WOL_REASON_PATTERN_PKT;
1424 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1425 "It's a pattern match event!\n");
1427 case FW_WOW_V2_RTD3_SSID_MATCH_EVENT:
1428 ppsc->wakeup_reason = WOL_REASON_RTD3_SSID_MATCH;
1429 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1430 "It's an RTD3 Ssid match event!\n");
1432 case FW_WOW_V2_REALWOW_V2_WAKEUPPKT:
1433 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_WAKEUPPKT;
1434 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1435 "It's an RealWoW wake packet event!\n");
1437 case FW_WOW_V2_REALWOW_V2_ACKLOST:
1438 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_ACKLOST;
1439 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1440 "It's an RealWoW ack lost event!\n");
1443 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1444 "WOL Read 0x1c7 = %02X, Unknown reason!\n",
1450 static void _rtl8821ae_init_trx_desc_hw_address(struct ieee80211_hw *hw)
1452 struct rtl_priv *rtlpriv = rtl_priv(hw);
1453 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1456 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
1457 rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
1458 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
1459 rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
1460 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
1461 rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
1462 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
1463 rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
1464 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
1465 rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
1466 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
1467 rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
1468 rtl_write_dword(rtlpriv, REG_HQ_DESA,
1469 rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
1470 rtl_write_dword(rtlpriv, REG_RX_DESA,
1471 rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
1474 static bool _rtl8821ae_init_llt_table(struct ieee80211_hw *hw, u32 boundary)
1478 u32 txpktbuf_bndy = boundary;
1479 u32 last_entry_of_txpktbuf = LAST_ENTRY_OF_TX_PKT_BUFFER;
1481 for (i = 0 ; i < (txpktbuf_bndy - 1) ; i++) {
1482 status = _rtl8821ae_llt_write(hw, i , i + 1);
1487 status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
1491 for (i = txpktbuf_bndy ; i < last_entry_of_txpktbuf ; i++) {
1492 status = _rtl8821ae_llt_write(hw, i, (i + 1));
1497 status = _rtl8821ae_llt_write(hw, last_entry_of_txpktbuf,
1505 static bool _rtl8821ae_dynamic_rqpn(struct ieee80211_hw *hw, u32 boundary,
1506 u16 npq_rqpn_value, u32 rqpn_val)
1508 struct rtl_priv *rtlpriv = rtl_priv(hw);
1511 u16 count = 0, tmp16;
1512 bool support_remote_wakeup;
1514 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
1515 (u8 *)(&support_remote_wakeup));
1517 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1518 "boundary=%#X, NPQ_RQPNValue=%#X, RQPNValue=%#X\n",
1519 boundary, npq_rqpn_value, rqpn_val);
1522 * 1. 0x301[7:0] = 0xFE */
1523 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1526 * 2. polling till 0x41A[15:0]=0x07FF */
1527 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
1528 while ((tmp16 & 0x07FF) != 0x07FF) {
1530 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
1532 if ((count % 200) == 0) {
1533 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1534 "Tx queue is not empty for 20ms!\n");
1536 if (count >= 1000) {
1537 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1538 "Wait for Tx FIFO empty timeout!\n");
1544 * 3. reg 0x522=0xFF */
1545 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1547 /* Wait TX State Machine OK
1548 * 4. polling till reg 0x5FB~0x5F8 = 0x00000000 for 50ms */
1550 while (rtl_read_byte(rtlpriv, REG_SCH_TXCMD) != 0) {
1554 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1555 "Wait for TX State Machine ready timeout !!\n");
1562 * 6. wait till 0x284[17] == 1
1563 * wait RX DMA idle */
1565 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1566 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1568 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1571 } while (!(tmp & BIT(1)) && count < 100);
1573 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1574 "Wait until Rx DMA Idle. count=%d REG[0x286]=0x%x\n",
1578 * 7. 0x02 [0] = 0 */
1579 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
1581 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmp);
1586 rtl_write_byte(rtlpriv, REG_CR, 0x00);
1589 /* Disable MAC Security Engine
1590 * 9. 0x100 bit[9]=0 */
1591 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1593 rtl_write_byte(rtlpriv, REG_CR + 1, tmp);
1595 /* To avoid DD-Tim Circuit hang
1596 * 10. 0x553 bit[5]=1 */
1597 tmp = rtl_read_byte(rtlpriv, REG_DUAL_TSF_RST);
1598 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (tmp | BIT(5)));
1600 /* Enable MAC Security Engine
1601 * 11. 0x100 bit[9]=1 */
1602 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1603 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp | BIT(1)));
1608 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1612 * 13. 0x02 [0] = 1 */
1613 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
1614 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, (tmp | BIT(0)));
1617 * 14,15. set beacon head page (reg 0x209 and 0x424) */
1618 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, (u8)boundary);
1619 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, (u8)boundary);
1620 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, (u8)boundary);
1622 /* 16. WMAC_LBK_BF_HD 0x45D[7:0]
1624 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD,
1627 rtl_write_word(rtlpriv, REG_TRXFF_BNDY, boundary);
1631 if (!_rtl8821ae_init_llt_table(hw, boundary)) {
1632 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
1633 "Failed to init LLT table!\n");
1638 * 18. reallocate RQPN and init LLT */
1639 rtl_write_word(rtlpriv, REG_RQPN_NPQ, npq_rqpn_value);
1640 rtl_write_dword(rtlpriv, REG_RQPN, rqpn_val);
1644 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1647 * 20. 0x301[7:0] = 0x00
1648 * 21. 0x284[18] = 0 */
1649 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00);
1650 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1651 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp&~BIT(2)));
1653 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "End.\n");
1657 static void _rtl8821ae_simple_initialize_adapter(struct ieee80211_hw *hw)
1659 struct rtl_priv *rtlpriv = rtl_priv(hw);
1660 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1661 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
1663 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
1664 /* Re-download normal Fw. */
1665 rtl8821ae_set_fw_related_for_wowlan(hw, false);
1668 /* Re-Initialize LLT table. */
1669 if (rtlhal->re_init_llt_table) {
1670 u32 rqpn = 0x80e70808;
1671 u8 rqpn_npq = 0, boundary = 0xF8;
1672 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1676 if (_rtl8821ae_dynamic_rqpn(hw, boundary, rqpn_npq, rqpn))
1677 rtlhal->re_init_llt_table = false;
1680 ppsc->rfpwr_state = ERFON;
1683 static void _rtl8821ae_enable_l1off(struct ieee80211_hw *hw)
1686 struct rtl_priv *rtlpriv = rtl_priv(hw);
1688 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1690 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x160);
1691 if (!(tmp & (BIT(2) | BIT(3)))) {
1692 RT_TRACE(rtlpriv, COMP_POWER | COMP_INIT, DBG_LOUD,
1693 "0x160(%#x)return!!\n", tmp);
1697 tmp = _rtl8821ae_mdio_read(rtlpriv, 0x1b);
1698 _rtl8821ae_mdio_write(rtlpriv, 0x1b, (tmp | BIT(4)));
1700 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1701 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp | BIT(5));
1703 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1706 static void _rtl8821ae_enable_ltr(struct ieee80211_hw *hw)
1709 struct rtl_priv *rtlpriv = rtl_priv(hw);
1711 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1713 /* Check 0x98[10] */
1714 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x99);
1715 if (!(tmp & BIT(2))) {
1716 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1717 "<---0x99(%#x) return!!\n", tmp);
1721 /* LTR idle latency, 0x90 for 144us */
1722 rtl_write_dword(rtlpriv, 0x798, 0x88908890);
1724 /* LTR active latency, 0x3c for 60us */
1725 rtl_write_dword(rtlpriv, 0x79c, 0x883c883c);
1727 tmp = rtl_read_byte(rtlpriv, 0x7a4);
1728 rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(4)));
1730 tmp = rtl_read_byte(rtlpriv, 0x7a4);
1731 rtl_write_byte(rtlpriv, 0x7a4, (tmp & (~BIT(0))));
1732 rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(0)));
1734 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1737 static bool _rtl8821ae_wowlan_initialize_adapter(struct ieee80211_hw *hw)
1739 struct rtl_priv *rtlpriv = rtl_priv(hw);
1740 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1741 bool init_finished = true;
1744 /* Get Fw wake up reason. */
1745 _rtl8821ae_get_wakeup_reason(hw);
1747 /* Patch Pcie Rx DMA hang after S3/S4 several times.
1748 * The root cause has not be found. */
1749 if (_rtl8821ae_check_pcie_dma_hang(hw))
1750 _rtl8821ae_reset_pcie_interface_dma(hw, true, false);
1752 /* Prepare Tx/Rx Desc Hw address. */
1753 _rtl8821ae_init_trx_desc_hw_address(hw);
1755 /* Release Pcie Interface Rx DMA to allow wake packet DMA. */
1756 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1757 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Enable PCIE Rx DMA.\n");
1759 /* Check wake up event.
1760 * We should check wake packet bit before disable wowlan by H2C or
1761 * Fw will clear the bit. */
1762 tmp = rtl_read_byte(rtlpriv, REG_FTISR + 3);
1763 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1764 "Read REG_FTISR 0x13f = %#X\n", tmp);
1766 /* Set the WoWLAN related function control disable. */
1767 rtl8821ae_set_fw_wowlan_mode(hw, false);
1768 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 0);
1770 if (rtlhal->hw_rof_enable) {
1771 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3);
1773 /* Clear GPIO9 ISR */
1774 rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1));
1775 init_finished = false;
1777 init_finished = true;
1781 if (init_finished) {
1782 _rtl8821ae_simple_initialize_adapter(hw);
1784 /* Release Pcie Interface Tx DMA. */
1785 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00);
1786 /* Release Pcie RX DMA */
1787 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, 0x02);
1789 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1790 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp & (~BIT(0))));
1792 _rtl8821ae_enable_l1off(hw);
1793 _rtl8821ae_enable_ltr(hw);
1796 return init_finished;
1799 static void _rtl8812ae_bb8812_config_1t(struct ieee80211_hw *hw)
1801 /* BB OFDM RX Path_A */
1802 rtl_set_bbreg(hw, 0x808, 0xff, 0x11);
1803 /* BB OFDM TX Path_A */
1804 rtl_set_bbreg(hw, 0x80c, MASKLWORD, 0x1111);
1805 /* BB CCK R/Rx Path_A */
1806 rtl_set_bbreg(hw, 0xa04, 0x0c000000, 0x0);
1808 rtl_set_bbreg(hw, 0x8bc, 0xc0000060, 0x4);
1809 /* RF Path_B HSSI OFF */
1810 rtl_set_bbreg(hw, 0xe00, 0xf, 0x4);
1811 /* RF Path_B Power Down */
1812 rtl_set_bbreg(hw, 0xe90, MASKDWORD, 0);
1813 /* ADDA Path_B OFF */
1814 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0);
1815 rtl_set_bbreg(hw, 0xe64, MASKDWORD, 0);
1818 static void _rtl8821ae_poweroff_adapter(struct ieee80211_hw *hw)
1820 struct rtl_priv *rtlpriv = rtl_priv(hw);
1821 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1824 rtlhal->mac_func_enable = false;
1826 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1827 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1828 /* 1. Run LPS WL RFOFF flow */
1829 /* RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1830 "=====>CardDisableRTL8812E,RTL8821A_NIC_LPS_ENTER_FLOW\n");
1832 rtl_hal_pwrseqcmdparsing(rtlpriv,
1833 PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1834 PWR_INTF_PCI_MSK, RTL8821A_NIC_LPS_ENTER_FLOW);
1836 /* 2. 0x1F[7:0] = 0 */
1838 /* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */
1839 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1841 rtl8821ae_firmware_selfreset(hw);
1844 /* Reset MCU. Suggested by Filen. */
1845 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1846 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
1848 /* g. MCUFWDL 0x80[1:0]=0 */
1849 /* reset MCU ready status */
1850 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1852 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1853 /* HW card disable configuration. */
1854 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1855 PWR_INTF_PCI_MSK, RTL8821A_NIC_DISABLE_FLOW);
1857 /* HW card disable configuration. */
1858 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1859 PWR_INTF_PCI_MSK, RTL8812_NIC_DISABLE_FLOW);
1862 /* Reset MCU IO Wrapper */
1863 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1864 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1865 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1866 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1868 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1869 /* lock ISO/CLK/Power control register */
1870 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1873 int rtl8821ae_hw_init(struct ieee80211_hw *hw)
1875 struct rtl_priv *rtlpriv = rtl_priv(hw);
1876 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1877 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1878 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1879 bool rtstatus = true;
1882 bool support_remote_wakeup;
1883 u32 nav_upper = WIFI_NAV_UPPER_US;
1885 rtlhal->being_init_adapter = true;
1886 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
1887 (u8 *)(&support_remote_wakeup));
1888 rtlpriv->intf_ops->disable_aspm(hw);
1890 /*YP wowlan not considered*/
1892 tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
1893 if (tmp_u1b != 0 && tmp_u1b != 0xEA) {
1894 rtlhal->mac_func_enable = true;
1895 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1896 "MAC has already power on.\n");
1898 rtlhal->mac_func_enable = false;
1899 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1902 if (support_remote_wakeup &&
1903 rtlhal->wake_from_pnp_sleep &&
1904 rtlhal->mac_func_enable) {
1905 if (_rtl8821ae_wowlan_initialize_adapter(hw)) {
1906 rtlhal->being_init_adapter = false;
1911 if (_rtl8821ae_check_pcie_dma_hang(hw)) {
1912 _rtl8821ae_reset_pcie_interface_dma(hw,
1913 rtlhal->mac_func_enable,
1915 rtlhal->mac_func_enable = false;
1918 /* Reset MAC/BB/RF status if it is not powered off
1919 * before calling initialize Hw flow to prevent
1920 * from interface and MAC status mismatch.
1921 * 2013.06.21, by tynli. Suggested by SD1 JackieLau. */
1922 if (rtlhal->mac_func_enable) {
1923 _rtl8821ae_poweroff_adapter(hw);
1924 rtlhal->mac_func_enable = false;
1927 rtstatus = _rtl8821ae_init_mac(hw);
1928 if (rtstatus != true) {
1929 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
1934 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG);
1936 rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b);
1938 err = rtl8821ae_download_fw(hw, false);
1940 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1941 "Failed to download FW. Init HW without FW now\n");
1943 rtlhal->fw_ready = false;
1946 rtlhal->fw_ready = true;
1948 ppsc->fw_current_inpsmode = false;
1949 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1950 rtlhal->fw_clk_change_in_progress = false;
1951 rtlhal->allow_sw_to_change_hwclc = false;
1952 rtlhal->last_hmeboxnum = 0;
1954 /*SIC_Init(Adapter);
1955 if(rtlhal->AMPDUBurstMode)
1956 rtl_write_byte(rtlpriv,REG_AMPDU_BURST_MODE_8812, 0x7F);*/
1958 rtl8821ae_phy_mac_config(hw);
1959 /* because last function modify RCR, so we update
1960 * rcr var here, or TP will unstable for receive_config
1961 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1962 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1963 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
1964 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1965 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);*/
1966 rtl8821ae_phy_bb_config(hw);
1968 rtl8821ae_phy_rf_config(hw);
1970 if (rtlpriv->phy.rf_type == RF_1T1R &&
1971 rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1972 _rtl8812ae_bb8812_config_1t(hw);
1974 _rtl8821ae_hw_configure(hw);
1976 rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G);
1978 /*set wireless mode*/
1980 rtlhal->mac_func_enable = true;
1982 rtl_cam_reset_all_entry(hw);
1984 rtl8821ae_enable_hw_security_config(hw);
1986 ppsc->rfpwr_state = ERFON;
1988 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1989 _rtl8821ae_enable_aspm_back_door(hw);
1990 rtlpriv->intf_ops->enable_aspm(hw);
1992 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE &&
1993 (rtlhal->rfe_type == 1 || rtlhal->rfe_type == 5))
1994 rtl_set_bbreg(hw, 0x900, 0x00000303, 0x0302);
1996 rtl8821ae_bt_hw_init(hw);
1997 rtlpriv->rtlhal.being_init_adapter = false;
1999 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_NAV_UPPER, (u8 *)&nav_upper);
2001 /* rtl8821ae_dm_check_txpower_tracking(hw); */
2002 /* rtl8821ae_phy_lc_calibrate(hw); */
2003 if (support_remote_wakeup)
2004 rtl_write_byte(rtlpriv, REG_WOW_CTRL, 0);
2007 tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2008 if (tmp_u1b & BIT(2)) {
2009 /* Release Rx DMA if needed*/
2011 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b);
2014 /* Release Tx/Rx PCIE DMA if*/
2015 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0);
2017 rtl8821ae_dm_init(hw);
2018 rtl8821ae_macid_initialize_mediastatus(hw);
2020 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_hw_init() <====\n");
2024 static enum version_8821ae _rtl8821ae_read_chip_version(struct ieee80211_hw *hw)
2026 struct rtl_priv *rtlpriv = rtl_priv(hw);
2027 struct rtl_phy *rtlphy = &rtlpriv->phy;
2028 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2029 enum version_8821ae version = VERSION_UNKNOWN;
2032 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
2033 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2034 "ReadChipVersion8812A 0xF0 = 0x%x\n", value32);
2036 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
2037 rtlphy->rf_type = RF_2T2R;
2038 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
2039 rtlphy->rf_type = RF_1T1R;
2041 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2042 "RF_Type is %x!!\n", rtlphy->rf_type);
2044 if (value32 & TRP_VAUX_EN) {
2045 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2046 if (rtlphy->rf_type == RF_2T2R)
2047 version = VERSION_TEST_CHIP_2T2R_8812;
2049 version = VERSION_TEST_CHIP_1T1R_8812;
2051 version = VERSION_TEST_CHIP_8821;
2053 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2054 u32 rtl_id = ((value32 & CHIP_VER_RTL_MASK) >> 12) + 1;
2056 if (rtlphy->rf_type == RF_2T2R)
2058 (enum version_8821ae)(CHIP_8812
2062 version = (enum version_8821ae)(CHIP_8812
2065 version = (enum version_8821ae)(version | (rtl_id << 12));
2066 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2067 u32 rtl_id = value32 & CHIP_VER_RTL_MASK;
2069 version = (enum version_8821ae)(CHIP_8821
2070 | NORMAL_CHIP | rtl_id);
2074 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2076 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2077 rtlhal->hw_rof_enable = ((value32 & WL_HWROF_EN) ? 1 : 0);
2081 case VERSION_TEST_CHIP_1T1R_8812:
2082 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2083 "Chip Version ID: VERSION_TEST_CHIP_1T1R_8812\n");
2085 case VERSION_TEST_CHIP_2T2R_8812:
2086 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2087 "Chip Version ID: VERSION_TEST_CHIP_2T2R_8812\n");
2089 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812:
2090 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2091 "Chip Version ID:VERSION_NORMAL_TSMC_CHIP_1T1R_8812\n");
2093 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812:
2094 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2095 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812\n");
2097 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT:
2098 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2099 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812 C CUT\n");
2101 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT:
2102 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2103 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812 C CUT\n");
2105 case VERSION_TEST_CHIP_8821:
2106 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2107 "Chip Version ID: VERSION_TEST_CHIP_8821\n");
2109 case VERSION_NORMAL_TSMC_CHIP_8821:
2110 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2111 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 A CUT\n");
2113 case VERSION_NORMAL_TSMC_CHIP_8821_B_CUT:
2114 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2115 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 B CUT\n");
2118 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2119 "Chip Version ID: Unknow (0x%X)\n", version);
2126 static int _rtl8821ae_set_media_status(struct ieee80211_hw *hw,
2127 enum nl80211_iftype type)
2129 struct rtl_priv *rtlpriv = rtl_priv(hw);
2130 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
2131 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
2134 rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
2135 RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD,
2136 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n");
2138 if (type == NL80211_IFTYPE_UNSPECIFIED ||
2139 type == NL80211_IFTYPE_STATION) {
2140 _rtl8821ae_stop_tx_beacon(hw);
2141 _rtl8821ae_enable_bcn_sub_func(hw);
2142 } else if (type == NL80211_IFTYPE_ADHOC ||
2143 type == NL80211_IFTYPE_AP) {
2144 _rtl8821ae_resume_tx_beacon(hw);
2145 _rtl8821ae_disable_bcn_sub_func(hw);
2147 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2148 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
2153 case NL80211_IFTYPE_UNSPECIFIED:
2154 bt_msr |= MSR_NOLINK;
2155 ledaction = LED_CTL_LINK;
2156 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2157 "Set Network type to NO LINK!\n");
2159 case NL80211_IFTYPE_ADHOC:
2160 bt_msr |= MSR_ADHOC;
2161 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2162 "Set Network type to Ad Hoc!\n");
2164 case NL80211_IFTYPE_STATION:
2165 bt_msr |= MSR_INFRA;
2166 ledaction = LED_CTL_LINK;
2167 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2168 "Set Network type to STA!\n");
2170 case NL80211_IFTYPE_AP:
2172 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2173 "Set Network type to AP!\n");
2176 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2177 "Network type %d not support!\n", type);
2181 rtl_write_byte(rtlpriv, MSR, bt_msr);
2182 rtlpriv->cfg->ops->led_control(hw, ledaction);
2183 if ((bt_msr & MSR_MASK) == MSR_AP)
2184 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
2186 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
2191 void rtl8821ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
2193 struct rtl_priv *rtlpriv = rtl_priv(hw);
2194 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2195 u32 reg_rcr = rtlpci->receive_config;
2197 if (rtlpriv->psc.rfpwr_state != ERFON)
2201 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
2202 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
2204 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
2205 } else if (!check_bssid) {
2206 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
2207 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
2208 rtlpriv->cfg->ops->set_hw_reg(hw,
2209 HW_VAR_RCR, (u8 *)(®_rcr));
2213 int rtl8821ae_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
2215 struct rtl_priv *rtlpriv = rtl_priv(hw);
2217 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_set_network_type!\n");
2219 if (_rtl8821ae_set_media_status(hw, type))
2222 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
2223 if (type != NL80211_IFTYPE_AP)
2224 rtl8821ae_set_check_bssid(hw, true);
2226 rtl8821ae_set_check_bssid(hw, false);
2232 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
2233 void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci)
2235 struct rtl_priv *rtlpriv = rtl_priv(hw);
2236 rtl8821ae_dm_init_edca_turbo(hw);
2239 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
2242 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
2245 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
2248 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
2251 RT_ASSERT(false, "invalid aci: %d !\n", aci);
2256 void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw)
2258 struct rtl_priv *rtlpriv = rtl_priv(hw);
2259 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2261 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
2262 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
2263 rtlpci->irq_enabled = true;
2264 /* there are some C2H CMDs have been sent before
2265 system interrupt is enabled, e.g., C2H, CPWM.
2266 *So we need to clear all C2H events that FW has
2267 notified, otherwise FW won't schedule any commands anymore.
2269 /* rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0); */
2270 /*enable system interrupt*/
2271 rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
2274 void rtl8821ae_disable_interrupt(struct ieee80211_hw *hw)
2276 struct rtl_priv *rtlpriv = rtl_priv(hw);
2277 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2279 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
2280 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
2281 rtlpci->irq_enabled = false;
2282 /*synchronize_irq(rtlpci->pdev->irq);*/
2285 static void _rtl8821ae_clear_pci_pme_status(struct ieee80211_hw *hw)
2287 struct rtl_priv *rtlpriv = rtl_priv(hw);
2288 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2295 /* Get the Capability pointer first,
2296 * the Capability Pointer is located at
2297 * offset 0x34 from the Function Header */
2299 pci_read_config_byte(rtlpci->pdev, 0x34, &cap_pointer);
2300 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2301 "PCI configration 0x34 = 0x%2x\n", cap_pointer);
2304 pci_read_config_word(rtlpci->pdev, cap_pointer, &cap_hdr);
2305 cap_id = cap_hdr & 0xFF;
2307 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2308 "in pci configration, cap_pointer%x = %x\n",
2309 cap_pointer, cap_id);
2311 if (cap_id == 0x01) {
2314 /* point to next Capability */
2315 cap_pointer = (cap_hdr >> 8) & 0xFF;
2316 /* 0: end of pci capability, 0xff: invalid value */
2317 if (cap_pointer == 0x00 || cap_pointer == 0xff) {
2322 } while (cnt++ < 200);
2324 if (cap_id == 0x01) {
2325 /* Get the PM CSR (Control/Status Register),
2326 * The PME_Status is located at PM Capatibility offset 5, bit 7
2328 pci_read_config_byte(rtlpci->pdev, cap_pointer + 5, &pmcs_reg);
2330 if (pmcs_reg & BIT(7)) {
2331 /* PME event occured, clear the PM_Status by write 1 */
2332 pmcs_reg = pmcs_reg | BIT(7);
2334 pci_write_config_byte(rtlpci->pdev, cap_pointer + 5,
2336 /* Read it back to check */
2337 pci_read_config_byte(rtlpci->pdev, cap_pointer + 5,
2339 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2340 "Clear PME status 0x%2x to 0x%2x\n",
2341 cap_pointer + 5, pmcs_reg);
2343 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2344 "PME status(0x%2x) = 0x%2x\n",
2345 cap_pointer + 5, pmcs_reg);
2348 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
2349 "Cannot find PME Capability\n");
2353 void rtl8821ae_card_disable(struct ieee80211_hw *hw)
2355 struct rtl_priv *rtlpriv = rtl_priv(hw);
2356 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2357 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
2358 struct rtl_mac *mac = rtl_mac(rtlpriv);
2359 enum nl80211_iftype opmode;
2360 bool support_remote_wakeup;
2364 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
2365 (u8 *)(&support_remote_wakeup));
2367 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2369 if (!(support_remote_wakeup && mac->opmode == NL80211_IFTYPE_STATION)
2370 || !rtlhal->enter_pnp_sleep) {
2371 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Normal Power off\n");
2372 mac->link_state = MAC80211_NOLINK;
2373 opmode = NL80211_IFTYPE_UNSPECIFIED;
2374 _rtl8821ae_set_media_status(hw, opmode);
2375 _rtl8821ae_poweroff_adapter(hw);
2377 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Wowlan Supported.\n");
2378 /* 3 <1> Prepare for configuring wowlan related infomations */
2379 /* Clear Fw WoWLAN event. */
2380 rtl_write_byte(rtlpriv, REG_MCUTST_WOWLAN, 0x0);
2382 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
2383 rtl8821ae_set_fw_related_for_wowlan(hw, true);
2385 /* Dynamically adjust Tx packet boundary
2386 * for download reserved page packet.
2387 * reserve 30 pages for rsvd page */
2388 if (_rtl8821ae_dynamic_rqpn(hw, 0xE0, 0x3, 0x80c20d0d))
2389 rtlhal->re_init_llt_table = true;
2391 /* 3 <2> Set Fw releted H2C cmd. */
2393 /* Set WoWLAN related security information. */
2394 rtl8821ae_set_fw_global_info_cmd(hw);
2396 _rtl8821ae_download_rsvd_page(hw, true);
2398 /* Just enable AOAC related functions when we connect to AP. */
2399 printk("mac->link_state = %d\n", mac->link_state);
2400 if (mac->link_state >= MAC80211_LINKED &&
2401 mac->opmode == NL80211_IFTYPE_STATION) {
2402 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
2403 rtl8821ae_set_fw_media_status_rpt_cmd(hw,
2406 rtl8821ae_set_fw_wowlan_mode(hw, true);
2407 /* Enable Fw Keep alive mechanism. */
2408 rtl8821ae_set_fw_keep_alive_cmd(hw, true);
2410 /* Enable disconnect decision control. */
2411 rtl8821ae_set_fw_disconnect_decision_ctrl_cmd(hw, true);
2414 /* 3 <3> Hw Configutations */
2416 /* Wait untill Rx DMA Finished before host sleep.
2417 * FW Pause Rx DMA may happens when received packet doing dma.
2419 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, BIT(2));
2421 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2423 while (!(tmp & BIT(1)) && (count++ < 100)) {
2425 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2427 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2428 "Wait Rx DMA Finished before host sleep. count=%d\n",
2431 /* reset trx ring */
2432 rtlpriv->intf_ops->reset_trx_ring(hw);
2434 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x0);
2436 _rtl8821ae_clear_pci_pme_status(hw);
2437 tmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
2438 rtl_write_byte(rtlpriv, REG_SYS_CLKR, tmp | BIT(3));
2439 /* prevent 8051 to be reset by PERST */
2440 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x20);
2441 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x60);
2444 if (rtlpriv->rtlhal.driver_is_goingto_unload ||
2445 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
2446 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
2447 /* For wowlan+LPS+32k. */
2448 if (support_remote_wakeup && rtlhal->enter_pnp_sleep) {
2449 /* Set the WoWLAN related function control enable.
2450 * It should be the last H2C cmd in the WoWLAN flow. */
2451 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 1);
2453 /* Stop Pcie Interface Tx DMA. */
2454 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);
2455 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Stop PCIE Tx DMA.\n");
2457 /* Wait for TxDMA idle. */
2460 tmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG);
2463 } while ((tmp != 0) && (count < 100));
2464 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2465 "Wait Tx DMA Finished before host sleep. count=%d\n",
2468 if (rtlhal->hw_rof_enable) {
2469 printk("hw_rof_enable\n");
2470 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3);
2471 rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1));
2474 /* after power off we should do iqk again */
2475 rtlpriv->phy.iqk_initialized = false;
2478 void rtl8821ae_interrupt_recognized(struct ieee80211_hw *hw,
2479 u32 *p_inta, u32 *p_intb)
2481 struct rtl_priv *rtlpriv = rtl_priv(hw);
2482 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2484 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
2485 rtl_write_dword(rtlpriv, ISR, *p_inta);
2487 *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
2488 rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
2491 void rtl8821ae_set_beacon_related_registers(struct ieee80211_hw *hw)
2493 struct rtl_priv *rtlpriv = rtl_priv(hw);
2494 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2495 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2496 u16 bcn_interval, atim_window;
2498 bcn_interval = mac->beacon_interval;
2499 atim_window = 2; /*FIX MERGE */
2500 rtl8821ae_disable_interrupt(hw);
2501 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
2502 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
2503 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
2504 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
2505 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
2506 rtl_write_byte(rtlpriv, 0x606, 0x30);
2507 rtlpci->reg_bcn_ctrl_val |= BIT(3);
2508 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
2509 rtl8821ae_enable_interrupt(hw);
2512 void rtl8821ae_set_beacon_interval(struct ieee80211_hw *hw)
2514 struct rtl_priv *rtlpriv = rtl_priv(hw);
2515 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2516 u16 bcn_interval = mac->beacon_interval;
2518 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
2519 "beacon_interval:%d\n", bcn_interval);
2520 rtl8821ae_disable_interrupt(hw);
2521 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
2522 rtl8821ae_enable_interrupt(hw);
2525 void rtl8821ae_update_interrupt_mask(struct ieee80211_hw *hw,
2526 u32 add_msr, u32 rm_msr)
2528 struct rtl_priv *rtlpriv = rtl_priv(hw);
2529 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2531 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
2532 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
2535 rtlpci->irq_mask[0] |= add_msr;
2537 rtlpci->irq_mask[0] &= (~rm_msr);
2538 rtl8821ae_disable_interrupt(hw);
2539 rtl8821ae_enable_interrupt(hw);
2542 static u8 _rtl8821ae_get_chnl_group(u8 chnl)
2547 if (1 <= chnl && chnl <= 2)
2549 else if (3 <= chnl && chnl <= 5)
2551 else if (6 <= chnl && chnl <= 8)
2553 else if (9 <= chnl && chnl <= 11)
2555 else /*if (12 <= chnl && chnl <= 14)*/
2558 if (36 <= chnl && chnl <= 42)
2560 else if (44 <= chnl && chnl <= 48)
2562 else if (50 <= chnl && chnl <= 58)
2564 else if (60 <= chnl && chnl <= 64)
2566 else if (100 <= chnl && chnl <= 106)
2568 else if (108 <= chnl && chnl <= 114)
2570 else if (116 <= chnl && chnl <= 122)
2572 else if (124 <= chnl && chnl <= 130)
2574 else if (132 <= chnl && chnl <= 138)
2576 else if (140 <= chnl && chnl <= 144)
2578 else if (149 <= chnl && chnl <= 155)
2580 else if (157 <= chnl && chnl <= 161)
2582 else if (165 <= chnl && chnl <= 171)
2584 else if (173 <= chnl && chnl <= 177)
2587 /*RT_TRACE(rtlpriv, COMP_EFUSE,DBG_LOUD,
2588 "5G, Channel %d in Group not found\n",chnl);*/
2589 RT_ASSERT(!COMP_EFUSE,
2590 "5G, Channel %d in Group not found\n", chnl);
2595 static void _rtl8821ae_read_power_value_fromprom(struct ieee80211_hw *hw,
2596 struct txpower_info_2g *pwrinfo24g,
2597 struct txpower_info_5g *pwrinfo5g,
2601 struct rtl_priv *rtlpriv = rtl_priv(hw);
2602 u32 rfPath, eeAddr = EEPROM_TX_PWR_INX, group, TxCount = 0;
2604 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2605 "hal_ReadPowerValueFromPROM8821ae(): hwinfo[0x%x]=0x%x\n",
2606 (eeAddr+1), hwinfo[eeAddr+1]);
2607 if (0xFF == hwinfo[eeAddr+1]) /*YJ,add,120316*/
2608 autoload_fail = true;
2610 if (autoload_fail) {
2611 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2612 "auto load fail : Use Default value!\n");
2613 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
2614 /*2.4G default value*/
2615 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2616 pwrinfo24g->index_cck_base[rfPath][group] = 0x2D;
2617 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
2619 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2621 pwrinfo24g->bw20_diff[rfPath][0] = 0x02;
2622 pwrinfo24g->ofdm_diff[rfPath][0] = 0x04;
2624 pwrinfo24g->bw20_diff[rfPath][TxCount] = 0xFE;
2625 pwrinfo24g->bw40_diff[rfPath][TxCount] = 0xFE;
2626 pwrinfo24g->cck_diff[rfPath][TxCount] = 0xFE;
2627 pwrinfo24g->ofdm_diff[rfPath][TxCount] = 0xFE;
2630 /*5G default value*/
2631 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++)
2632 pwrinfo5g->index_bw40_base[rfPath][group] = 0x2A;
2634 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2636 pwrinfo5g->ofdm_diff[rfPath][0] = 0x04;
2637 pwrinfo5g->bw20_diff[rfPath][0] = 0x00;
2638 pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
2639 pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
2641 pwrinfo5g->ofdm_diff[rfPath][0] = 0xFE;
2642 pwrinfo5g->bw20_diff[rfPath][0] = 0xFE;
2643 pwrinfo5g->bw40_diff[rfPath][0] = 0xFE;
2644 pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
2645 pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
2652 rtl_priv(hw)->efuse.txpwr_fromeprom = true;
2654 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
2655 /*2.4G default value*/
2656 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2657 pwrinfo24g->index_cck_base[rfPath][group] = hwinfo[eeAddr++];
2658 if (pwrinfo24g->index_cck_base[rfPath][group] == 0xFF)
2659 pwrinfo24g->index_cck_base[rfPath][group] = 0x2D;
2661 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) {
2662 pwrinfo24g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2663 if (pwrinfo24g->index_bw40_base[rfPath][group] == 0xFF)
2664 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
2666 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2668 pwrinfo24g->bw40_diff[rfPath][TxCount] = 0;
2669 /*bit sign number to 8 bit sign number*/
2670 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2671 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2672 pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2673 /*bit sign number to 8 bit sign number*/
2674 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2675 if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2676 pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2678 pwrinfo24g->cck_diff[rfPath][TxCount] = 0;
2681 pwrinfo24g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr]&0xf0) >> 4;
2682 if (pwrinfo24g->bw40_diff[rfPath][TxCount] & BIT(3))
2683 pwrinfo24g->bw40_diff[rfPath][TxCount] |= 0xF0;
2685 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2686 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2687 pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2691 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2692 if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2693 pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2695 pwrinfo24g->cck_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2696 if (pwrinfo24g->cck_diff[rfPath][TxCount] & BIT(3))
2697 pwrinfo24g->cck_diff[rfPath][TxCount] |= 0xF0;
2703 /*5G default value*/
2704 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
2705 pwrinfo5g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2706 if (pwrinfo5g->index_bw40_base[rfPath][group] == 0xFF)
2707 pwrinfo5g->index_bw40_base[rfPath][group] = 0xFE;
2710 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2712 pwrinfo5g->bw40_diff[rfPath][TxCount] = 0;
2714 pwrinfo5g->bw20_diff[rfPath][0] = (hwinfo[eeAddr] & 0xf0) >> 4;
2715 if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2716 pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2718 pwrinfo5g->ofdm_diff[rfPath][0] = (hwinfo[eeAddr] & 0x0f);
2719 if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2720 pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2724 pwrinfo5g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2725 if (pwrinfo5g->bw40_diff[rfPath][TxCount] & BIT(3))
2726 pwrinfo5g->bw40_diff[rfPath][TxCount] |= 0xF0;
2728 pwrinfo5g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2729 if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2730 pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2736 pwrinfo5g->ofdm_diff[rfPath][1] = (hwinfo[eeAddr] & 0xf0) >> 4;
2737 pwrinfo5g->ofdm_diff[rfPath][2] = (hwinfo[eeAddr] & 0x0f);
2741 pwrinfo5g->ofdm_diff[rfPath][3] = (hwinfo[eeAddr] & 0x0f);
2745 for (TxCount = 1; TxCount < MAX_TX_COUNT; TxCount++) {
2746 if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2747 pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2749 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2750 pwrinfo5g->bw80_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2751 /* 4bit sign number to 8 bit sign number */
2752 if (pwrinfo5g->bw80_diff[rfPath][TxCount] & BIT(3))
2753 pwrinfo5g->bw80_diff[rfPath][TxCount] |= 0xF0;
2754 /* 4bit sign number to 8 bit sign number */
2755 pwrinfo5g->bw160_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2756 if (pwrinfo5g->bw160_diff[rfPath][TxCount] & BIT(3))
2757 pwrinfo5g->bw160_diff[rfPath][TxCount] |= 0xF0;
2764 static void _rtl8812ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2768 struct rtl_priv *rtlpriv = rtl_priv(hw);
2769 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2770 struct txpower_info_2g pwrinfo24g;
2771 struct txpower_info_5g pwrinfo5g;
2772 u8 channel5g[CHANNEL_MAX_NUMBER_5G] = {
2773 36, 38, 40, 42, 44, 46, 48, 50, 52, 54,
2774 56, 58, 60, 62, 64, 100, 102, 104, 106,
2775 108, 110, 112, 114, 116, 118, 120, 122,
2776 124, 126, 128, 130, 132, 134, 136, 138,
2777 140, 142, 144, 149, 151, 153, 155, 157,
2778 159, 161, 163, 165, 167, 168, 169, 171, 173, 175, 177};
2779 u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {42, 58, 106, 122, 138, 155, 171};
2783 _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g,
2784 &pwrinfo5g, autoload_fail, hwinfo);
2786 for (rf_path = 0; rf_path < 2; rf_path++) {
2787 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2788 index = _rtl8821ae_get_chnl_group(i + 1);
2790 if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2791 rtlefuse->txpwrlevel_cck[rf_path][i] =
2792 pwrinfo24g.index_cck_base[rf_path][5];
2793 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2794 pwrinfo24g.index_bw40_base[rf_path][index];
2796 rtlefuse->txpwrlevel_cck[rf_path][i] =
2797 pwrinfo24g.index_cck_base[rf_path][index];
2798 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2799 pwrinfo24g.index_bw40_base[rf_path][index];
2803 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2804 index = _rtl8821ae_get_chnl_group(channel5g[i]);
2805 rtlefuse->txpwr_5g_bw40base[rf_path][i] =
2806 pwrinfo5g.index_bw40_base[rf_path][index];
2808 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2810 index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2811 upper = pwrinfo5g.index_bw40_base[rf_path][index];
2812 lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2814 rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2816 for (i = 0; i < MAX_TX_COUNT; i++) {
2817 rtlefuse->txpwr_cckdiff[rf_path][i] =
2818 pwrinfo24g.cck_diff[rf_path][i];
2819 rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2820 pwrinfo24g.ofdm_diff[rf_path][i];
2821 rtlefuse->txpwr_ht20diff[rf_path][i] =
2822 pwrinfo24g.bw20_diff[rf_path][i];
2823 rtlefuse->txpwr_ht40diff[rf_path][i] =
2824 pwrinfo24g.bw40_diff[rf_path][i];
2826 rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] =
2827 pwrinfo5g.ofdm_diff[rf_path][i];
2828 rtlefuse->txpwr_5g_bw20diff[rf_path][i] =
2829 pwrinfo5g.bw20_diff[rf_path][i];
2830 rtlefuse->txpwr_5g_bw40diff[rf_path][i] =
2831 pwrinfo5g.bw40_diff[rf_path][i];
2832 rtlefuse->txpwr_5g_bw80diff[rf_path][i] =
2833 pwrinfo5g.bw80_diff[rf_path][i];
2837 if (!autoload_fail) {
2838 rtlefuse->eeprom_regulatory =
2839 hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;/*bit0~2*/
2840 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2841 rtlefuse->eeprom_regulatory = 0;
2843 rtlefuse->eeprom_regulatory = 0;
2846 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2847 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2850 static void _rtl8821ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2854 struct rtl_priv *rtlpriv = rtl_priv(hw);
2855 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2856 struct txpower_info_2g pwrinfo24g;
2857 struct txpower_info_5g pwrinfo5g;
2858 u8 channel5g[CHANNEL_MAX_NUMBER_5G] = {
2859 36, 38, 40, 42, 44, 46, 48, 50, 52, 54,
2860 56, 58, 60, 62, 64, 100, 102, 104, 106,
2861 108, 110, 112, 114, 116, 118, 120, 122,
2862 124, 126, 128, 130, 132, 134, 136, 138,
2863 140, 142, 144, 149, 151, 153, 155, 157,
2864 159, 161, 163, 165, 167, 168, 169, 171,
2866 u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {
2867 42, 58, 106, 122, 138, 155, 171};
2871 _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g,
2872 &pwrinfo5g, autoload_fail, hwinfo);
2874 for (rf_path = 0; rf_path < 2; rf_path++) {
2875 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2876 index = _rtl8821ae_get_chnl_group(i + 1);
2878 if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2879 rtlefuse->txpwrlevel_cck[rf_path][i] =
2880 pwrinfo24g.index_cck_base[rf_path][5];
2881 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2882 pwrinfo24g.index_bw40_base[rf_path][index];
2884 rtlefuse->txpwrlevel_cck[rf_path][i] =
2885 pwrinfo24g.index_cck_base[rf_path][index];
2886 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2887 pwrinfo24g.index_bw40_base[rf_path][index];
2891 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2892 index = _rtl8821ae_get_chnl_group(channel5g[i]);
2893 rtlefuse->txpwr_5g_bw40base[rf_path][i] =
2894 pwrinfo5g.index_bw40_base[rf_path][index];
2896 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2898 index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2899 upper = pwrinfo5g.index_bw40_base[rf_path][index];
2900 lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2902 rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2904 for (i = 0; i < MAX_TX_COUNT; i++) {
2905 rtlefuse->txpwr_cckdiff[rf_path][i] =
2906 pwrinfo24g.cck_diff[rf_path][i];
2907 rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2908 pwrinfo24g.ofdm_diff[rf_path][i];
2909 rtlefuse->txpwr_ht20diff[rf_path][i] =
2910 pwrinfo24g.bw20_diff[rf_path][i];
2911 rtlefuse->txpwr_ht40diff[rf_path][i] =
2912 pwrinfo24g.bw40_diff[rf_path][i];
2914 rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] =
2915 pwrinfo5g.ofdm_diff[rf_path][i];
2916 rtlefuse->txpwr_5g_bw20diff[rf_path][i] =
2917 pwrinfo5g.bw20_diff[rf_path][i];
2918 rtlefuse->txpwr_5g_bw40diff[rf_path][i] =
2919 pwrinfo5g.bw40_diff[rf_path][i];
2920 rtlefuse->txpwr_5g_bw80diff[rf_path][i] =
2921 pwrinfo5g.bw80_diff[rf_path][i];
2925 if (!autoload_fail) {
2926 rtlefuse->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;
2927 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2928 rtlefuse->eeprom_regulatory = 0;
2930 rtlefuse->eeprom_regulatory = 0;
2933 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2934 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2937 static void _rtl8812ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
2940 struct rtl_priv *rtlpriv = rtl_priv(hw);
2941 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2943 if (!autoload_fail) {
2944 rtlhal->pa_type_2g = hwinfo[0xBC];
2945 rtlhal->lna_type_2g = hwinfo[0xBD];
2946 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
2947 rtlhal->pa_type_2g = 0;
2948 rtlhal->lna_type_2g = 0;
2950 rtlhal->external_pa_2g = ((rtlhal->pa_type_2g & BIT(5)) &&
2951 (rtlhal->pa_type_2g & BIT(4))) ?
2953 rtlhal->external_lna_2g = ((rtlhal->lna_type_2g & BIT(7)) &&
2954 (rtlhal->lna_type_2g & BIT(3))) ?
2957 rtlhal->pa_type_5g = hwinfo[0xBC];
2958 rtlhal->lna_type_5g = hwinfo[0xBF];
2959 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
2960 rtlhal->pa_type_5g = 0;
2961 rtlhal->lna_type_5g = 0;
2963 rtlhal->external_pa_5g = ((rtlhal->pa_type_5g & BIT(1)) &&
2964 (rtlhal->pa_type_5g & BIT(0))) ?
2966 rtlhal->external_lna_5g = ((rtlhal->lna_type_5g & BIT(7)) &&
2967 (rtlhal->lna_type_5g & BIT(3))) ?
2970 rtlhal->external_pa_2g = 0;
2971 rtlhal->external_lna_2g = 0;
2972 rtlhal->external_pa_5g = 0;
2973 rtlhal->external_lna_5g = 0;
2977 static void _rtl8821ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
2980 struct rtl_priv *rtlpriv = rtl_priv(hw);
2981 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2983 if (!autoload_fail) {
2984 rtlhal->pa_type_2g = hwinfo[0xBC];
2985 rtlhal->lna_type_2g = hwinfo[0xBD];
2986 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
2987 rtlhal->pa_type_2g = 0;
2988 rtlhal->lna_type_2g = 0;
2990 rtlhal->external_pa_2g = (rtlhal->pa_type_2g & BIT(5)) ? 1 : 0;
2991 rtlhal->external_lna_2g = (rtlhal->lna_type_2g & BIT(7)) ? 1 : 0;
2993 rtlhal->pa_type_5g = hwinfo[0xBC];
2994 rtlhal->lna_type_5g = hwinfo[0xBF];
2995 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
2996 rtlhal->pa_type_5g = 0;
2997 rtlhal->lna_type_5g = 0;
2999 rtlhal->external_pa_5g = (rtlhal->pa_type_5g & BIT(1)) ? 1 : 0;
3000 rtlhal->external_lna_5g = (rtlhal->lna_type_5g & BIT(7)) ? 1 : 0;
3002 rtlhal->external_pa_2g = 0;
3003 rtlhal->external_lna_2g = 0;
3004 rtlhal->external_pa_5g = 0;
3005 rtlhal->external_lna_5g = 0;
3009 static void _rtl8821ae_read_rfe_type(struct ieee80211_hw *hw, u8 *hwinfo,
3012 struct rtl_priv *rtlpriv = rtl_priv(hw);
3013 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
3015 if (!autoload_fail) {
3016 if (hwinfo[EEPROM_RFE_OPTION] & BIT(7)) {
3017 if (rtlhal->external_lna_5g) {
3018 if (rtlhal->external_pa_5g) {
3019 if (rtlhal->external_lna_2g &&
3020 rtlhal->external_pa_2g)
3021 rtlhal->rfe_type = 3;
3023 rtlhal->rfe_type = 0;
3025 rtlhal->rfe_type = 2;
3028 rtlhal->rfe_type = 4;
3031 rtlhal->rfe_type = hwinfo[EEPROM_RFE_OPTION] & 0x3F;
3033 if (rtlhal->rfe_type == 4 &&
3034 (rtlhal->external_pa_5g ||
3035 rtlhal->external_pa_2g ||
3036 rtlhal->external_lna_5g ||
3037 rtlhal->external_lna_2g)) {
3038 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
3039 rtlhal->rfe_type = 2;
3043 rtlhal->rfe_type = 0x04;
3046 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3047 "RFE Type: 0x%2x\n", rtlhal->rfe_type);
3050 static void _rtl8812ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3051 bool auto_load_fail, u8 *hwinfo)
3053 struct rtl_priv *rtlpriv = rtl_priv(hw);
3056 if (!auto_load_fail) {
3057 value = *(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION];
3058 if (((value & 0xe0) >> 5) == 0x1)
3059 rtlpriv->btcoexist.btc_info.btcoexist = 1;
3061 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3062 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3064 value = hwinfo[EEPROM_RF_BT_SETTING];
3065 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3067 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3068 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3069 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3071 /*move BT_InitHalVars() to init_sw_vars*/
3074 static void _rtl8821ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3075 bool auto_load_fail, u8 *hwinfo)
3077 struct rtl_priv *rtlpriv = rtl_priv(hw);
3081 if (!auto_load_fail) {
3082 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
3083 if (tmpu_32 & BIT(18))
3084 rtlpriv->btcoexist.btc_info.btcoexist = 1;
3086 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3087 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3089 value = hwinfo[EEPROM_RF_BT_SETTING];
3090 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3092 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3093 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3094 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3096 /*move BT_InitHalVars() to init_sw_vars*/
3099 static void _rtl8821ae_read_adapter_info(struct ieee80211_hw *hw, bool b_pseudo_test)
3101 struct rtl_priv *rtlpriv = rtl_priv(hw);
3102 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3103 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3104 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3106 u8 hwinfo[HWSET_MAX_SIZE];
3109 if (b_pseudo_test) {
3113 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
3114 rtl_efuse_shadow_map_update(hw);
3115 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
3117 } else if (rtlefuse->epromtype == EEPROM_93C46) {
3118 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3119 "RTL819X Not boot from eeprom, check it !!");
3122 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP\n",
3123 hwinfo, HWSET_MAX_SIZE);
3125 eeprom_id = *((u16 *)&hwinfo[0]);
3126 if (eeprom_id != RTL_EEPROM_ID) {
3127 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3128 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
3129 rtlefuse->autoload_failflag = true;
3131 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
3132 rtlefuse->autoload_failflag = false;
3135 if (rtlefuse->autoload_failflag) {
3136 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3137 "RTL8812AE autoload_failflag, check it !!");
3141 rtlefuse->eeprom_version = *(u8 *)&hwinfo[EEPROM_VERSION];
3142 if (rtlefuse->eeprom_version == 0xff)
3143 rtlefuse->eeprom_version = 0;
3145 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3146 "EEPROM version: 0x%2x\n", rtlefuse->eeprom_version);
3148 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
3149 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
3150 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
3151 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
3152 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3153 "EEPROMId = 0x%4x\n", eeprom_id);
3154 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3155 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
3156 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3157 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
3158 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3159 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
3160 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3161 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
3164 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
3165 if (rtlefuse->eeprom_oemid == 0xFF)
3166 rtlefuse->eeprom_oemid = 0;
3168 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3169 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
3171 for (i = 0; i < 6; i += 2) {
3172 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
3173 *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue;
3176 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
3177 "dev_addr: %pM\n", rtlefuse->dev_addr);
3179 _rtl8821ae_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
3182 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
3183 _rtl8812ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag);
3184 _rtl8812ae_read_bt_coexist_info_from_hwpg(hw,
3185 rtlefuse->autoload_failflag, hwinfo);
3187 _rtl8821ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag);
3188 _rtl8821ae_read_bt_coexist_info_from_hwpg(hw,
3189 rtlefuse->autoload_failflag, hwinfo);
3192 _rtl8821ae_read_rfe_type(hw, hwinfo, rtlefuse->autoload_failflag);
3194 rtlefuse->board_type = ODM_BOARD_DEFAULT;
3195 if (rtlhal->external_lna_2g != 0)
3196 rtlefuse->board_type |= ODM_BOARD_EXT_LNA;
3197 if (rtlhal->external_lna_5g != 0)
3198 rtlefuse->board_type |= ODM_BOARD_EXT_LNA_5G;
3199 if (rtlhal->external_pa_2g != 0)
3200 rtlefuse->board_type |= ODM_BOARD_EXT_PA;
3201 if (rtlhal->external_pa_5g != 0)
3202 rtlefuse->board_type |= ODM_BOARD_EXT_PA_5G;
3204 if (rtlpriv->btcoexist.btc_info.btcoexist == 1)
3205 rtlefuse->board_type |= ODM_BOARD_BT;
3207 rtlhal->board_type = rtlefuse->board_type;
3208 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3209 "board_type = 0x%x\n", rtlefuse->board_type);
3211 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
3212 if (rtlefuse->eeprom_channelplan == 0xff)
3213 rtlefuse->eeprom_channelplan = 0x7F;
3215 /* set channel plan from efuse */
3216 rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
3219 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8821AE];
3220 if (rtlefuse->crystalcap == 0xFF)
3221 rtlefuse->crystalcap = 0x20;
3223 rtlefuse->eeprom_thermalmeter = *(u8 *)&hwinfo[EEPROM_THERMAL_METER];
3224 if ((rtlefuse->eeprom_thermalmeter == 0xff) ||
3225 rtlefuse->autoload_failflag) {
3226 rtlefuse->apk_thermalmeterignore = true;
3227 rtlefuse->eeprom_thermalmeter = 0xff;
3230 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
3231 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3232 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
3234 if (!rtlefuse->autoload_failflag) {
3235 rtlefuse->antenna_div_cfg =
3236 (hwinfo[EEPROM_RF_BOARD_OPTION] & 0x18) >> 3;
3237 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xff)
3238 rtlefuse->antenna_div_cfg = 0;
3240 if (rtlpriv->btcoexist.btc_info.btcoexist == 1 &&
3241 rtlpriv->btcoexist.btc_info.ant_num == ANT_X1)
3242 rtlefuse->antenna_div_cfg = 0;
3244 rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
3245 if (rtlefuse->antenna_div_type == 0xff)
3246 rtlefuse->antenna_div_type = FIXED_HW_ANTDIV;
3248 rtlefuse->antenna_div_cfg = 0;
3249 rtlefuse->antenna_div_type = 0;
3252 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3253 "SWAS: bHwAntDiv = %x, TRxAntDivType = %x\n",
3254 rtlefuse->antenna_div_cfg, rtlefuse->antenna_div_type);
3256 pcipriv->ledctl.led_opendrain = true;
3258 if (rtlhal->oem_id == RT_CID_DEFAULT) {
3259 switch (rtlefuse->eeprom_oemid) {
3260 case RT_CID_DEFAULT:
3262 case EEPROM_CID_TOSHIBA:
3263 rtlhal->oem_id = RT_CID_TOSHIBA;
3265 case EEPROM_CID_CCX:
3266 rtlhal->oem_id = RT_CID_CCX;
3268 case EEPROM_CID_QMI:
3269 rtlhal->oem_id = RT_CID_819X_QMI;
3271 case EEPROM_CID_WHQL:
3279 /*static void _rtl8821ae_hal_customized_behavior(struct ieee80211_hw *hw)
3281 struct rtl_priv *rtlpriv = rtl_priv(hw);
3282 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3283 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3285 pcipriv->ledctl.led_opendrain = true;
3286 switch (rtlhal->oem_id) {
3287 case RT_CID_819X_HP:
3288 pcipriv->ledctl.led_opendrain = true;
3290 case RT_CID_819X_LENOVO:
3291 case RT_CID_DEFAULT:
3292 case RT_CID_TOSHIBA:
3294 case RT_CID_819X_ACER:
3299 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
3300 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
3303 void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw)
3305 struct rtl_priv *rtlpriv = rtl_priv(hw);
3306 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3307 struct rtl_phy *rtlphy = &rtlpriv->phy;
3308 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3311 rtlhal->version = _rtl8821ae_read_chip_version(hw);
3312 if (get_rf_type(rtlphy) == RF_1T1R)
3313 rtlpriv->dm.rfpath_rxenable[0] = true;
3315 rtlpriv->dm.rfpath_rxenable[0] =
3316 rtlpriv->dm.rfpath_rxenable[1] = true;
3317 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
3320 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
3321 if (tmp_u1b & BIT(4)) {
3322 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
3323 rtlefuse->epromtype = EEPROM_93C46;
3325 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
3326 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
3329 if (tmp_u1b & BIT(5)) {
3330 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
3331 rtlefuse->autoload_failflag = false;
3332 _rtl8821ae_read_adapter_info(hw, false);
3334 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
3336 /*hal_ReadRFType_8812A()*/
3337 /* _rtl8821ae_hal_customized_behavior(hw); */
3340 static void rtl8821ae_update_hal_rate_table(struct ieee80211_hw *hw,
3341 struct ieee80211_sta *sta)
3343 struct rtl_priv *rtlpriv = rtl_priv(hw);
3344 struct rtl_phy *rtlphy = &rtlpriv->phy;
3345 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3346 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3349 u8 b_nmode = mac->ht_enable;
3350 u8 mimo_ps = IEEE80211_SMPS_OFF;
3353 u8 curtxbw_40mhz = mac->bw_40;
3354 u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
3356 u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
3358 enum wireless_mode wirelessmode = mac->mode;
3360 if (rtlhal->current_bandtype == BAND_ON_5G)
3361 ratr_value = sta->supp_rates[1] << 4;
3363 ratr_value = sta->supp_rates[0];
3364 if (mac->opmode == NL80211_IFTYPE_ADHOC)
3366 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
3367 sta->ht_cap.mcs.rx_mask[0] << 12);
3368 switch (wirelessmode) {
3369 case WIRELESS_MODE_B:
3370 if (ratr_value & 0x0000000c)
3371 ratr_value &= 0x0000000d;
3373 ratr_value &= 0x0000000f;
3375 case WIRELESS_MODE_G:
3376 ratr_value &= 0x00000FF5;
3378 case WIRELESS_MODE_N_24G:
3379 case WIRELESS_MODE_N_5G:
3381 if (mimo_ps == IEEE80211_SMPS_STATIC) {
3382 ratr_value &= 0x0007F005;
3386 if (get_rf_type(rtlphy) == RF_1T2R ||
3387 get_rf_type(rtlphy) == RF_1T1R)
3388 ratr_mask = 0x000ff005;
3390 ratr_mask = 0x0f0ff005;
3392 ratr_value &= ratr_mask;
3396 if (rtlphy->rf_type == RF_1T2R)
3397 ratr_value &= 0x000ff0ff;
3399 ratr_value &= 0x0f0ff0ff;
3404 if ((rtlpriv->btcoexist.bt_coexistence) &&
3405 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
3406 (rtlpriv->btcoexist.bt_cur_state) &&
3407 (rtlpriv->btcoexist.bt_ant_isolation) &&
3408 ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
3409 (rtlpriv->btcoexist.bt_service == BT_BUSY)))
3410 ratr_value &= 0x0fffcfc0;
3412 ratr_value &= 0x0FFFFFFF;
3414 if (b_nmode && ((curtxbw_40mhz &&
3415 b_curshortgi_40mhz) || (!curtxbw_40mhz &&
3416 b_curshortgi_20mhz))) {
3417 ratr_value |= 0x10000000;
3418 tmp_ratr_value = (ratr_value >> 12);
3420 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
3421 if ((1 << shortgi_rate) & tmp_ratr_value)
3425 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
3426 (shortgi_rate << 4) | (shortgi_rate);
3429 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
3431 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
3432 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
3435 static u8 _rtl8821ae_mrate_idx_to_arfr_id(
3436 struct ieee80211_hw *hw, u8 rate_index,
3437 enum wireless_mode wirelessmode)
3439 struct rtl_priv *rtlpriv = rtl_priv(hw);
3440 struct rtl_phy *rtlphy = &rtlpriv->phy;
3442 switch (rate_index) {
3443 case RATR_INX_WIRELESS_NGB:
3444 if (rtlphy->rf_type == RF_1T1R)
3449 case RATR_INX_WIRELESS_N:
3450 case RATR_INX_WIRELESS_NG:
3451 if (rtlphy->rf_type == RF_1T1R)
3456 case RATR_INX_WIRELESS_NB:
3457 if (rtlphy->rf_type == RF_1T1R)
3462 case RATR_INX_WIRELESS_GB:
3465 case RATR_INX_WIRELESS_G:
3468 case RATR_INX_WIRELESS_B:
3471 case RATR_INX_WIRELESS_MC:
3472 if ((wirelessmode == WIRELESS_MODE_B)
3473 || (wirelessmode == WIRELESS_MODE_G)
3474 || (wirelessmode == WIRELESS_MODE_N_24G)
3475 || (wirelessmode == WIRELESS_MODE_AC_24G))
3479 case RATR_INX_WIRELESS_AC_5N:
3480 if (rtlphy->rf_type == RF_1T1R)
3485 case RATR_INX_WIRELESS_AC_24N:
3486 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) {
3487 if (rtlphy->rf_type == RF_1T1R)
3492 if (rtlphy->rf_type == RF_1T1R)
3504 static u32 _rtl8821ae_rate_to_bitmap_2ssvht(__le16 vht_rate)
3507 u32 rate_bitmap = 0;
3509 for (i = j = 0; i < 4; i += 2, j += 10) {
3510 tmp_rate = (le16_to_cpu(vht_rate) >> i) & 3;
3514 rate_bitmap = rate_bitmap | (0x03ff << j);
3517 rate_bitmap = rate_bitmap | (0x01ff << j);
3520 rate_bitmap = rate_bitmap | (0x00ff << j);
3530 static u32 _rtl8821ae_set_ra_vht_ratr_bitmap(struct ieee80211_hw *hw,
3531 enum wireless_mode wirelessmode,
3534 struct rtl_priv *rtlpriv = rtl_priv(hw);
3535 struct rtl_phy *rtlphy = &rtlpriv->phy;
3536 u32 ret_bitmap = ratr_bitmap;
3538 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40
3539 || rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
3540 ret_bitmap = ratr_bitmap;
3541 else if (wirelessmode == WIRELESS_MODE_AC_5G
3542 || wirelessmode == WIRELESS_MODE_AC_24G) {
3543 if (rtlphy->rf_type == RF_1T1R)
3544 ret_bitmap = ratr_bitmap & (~BIT21);
3546 ret_bitmap = ratr_bitmap & (~(BIT31|BIT21));
3552 static u8 _rtl8821ae_get_vht_eni(enum wireless_mode wirelessmode,
3556 if (wirelessmode < WIRELESS_MODE_N_24G)
3558 else if (wirelessmode == WIRELESS_MODE_AC_24G) {
3559 if (ratr_bitmap & 0xfff00000) /* Mix , 2SS */
3563 } else if (wirelessmode == WIRELESS_MODE_AC_5G) {
3570 static u8 _rtl8821ae_get_ra_ldpc(struct ieee80211_hw *hw,
3571 u8 mac_id, struct rtl_sta_info *sta_entry,
3572 enum wireless_mode wirelessmode)
3575 /*not support ldpc, do not open*/
3579 static u8 _rtl8821ae_get_ra_rftype(struct ieee80211_hw *hw,
3580 enum wireless_mode wirelessmode,
3583 struct rtl_priv *rtlpriv = rtl_priv(hw);
3584 struct rtl_phy *rtlphy = &rtlpriv->phy;
3585 u8 rf_type = RF_1T1R;
3587 if (rtlphy->rf_type == RF_1T1R)
3589 else if (wirelessmode == WIRELESS_MODE_AC_5G
3590 || wirelessmode == WIRELESS_MODE_AC_24G
3591 || wirelessmode == WIRELESS_MODE_AC_ONLY) {
3592 if (ratr_bitmap & 0xffc00000)
3594 } else if (wirelessmode == WIRELESS_MODE_N_5G
3595 || wirelessmode == WIRELESS_MODE_N_24G) {
3596 if (ratr_bitmap & 0xfff00000)
3603 static bool _rtl8821ae_get_ra_shortgi(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
3606 bool b_short_gi = false;
3607 u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
3609 u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
3611 u8 b_curshortgi_80mhz = 0;
3612 b_curshortgi_80mhz = (sta->vht_cap.cap &
3613 IEEE80211_VHT_CAP_SHORT_GI_80) ? 1 : 0;
3615 if (mac_id == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST)
3618 if (b_curshortgi_40mhz || b_curshortgi_80mhz
3619 || b_curshortgi_20mhz)
3625 static void rtl8821ae_update_hal_rate_mask(struct ieee80211_hw *hw,
3626 struct ieee80211_sta *sta, u8 rssi_level)
3628 struct rtl_priv *rtlpriv = rtl_priv(hw);
3629 struct rtl_phy *rtlphy = &rtlpriv->phy;
3630 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3631 struct rtl_sta_info *sta_entry = NULL;
3634 enum wireless_mode wirelessmode = 0;
3635 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
3637 bool b_shortgi = false;
3640 u8 mimo_ps = IEEE80211_SMPS_OFF;
3643 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
3644 wirelessmode = sta_entry->wireless_mode;
3646 RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD,
3647 "wireless mode = 0x%x\n", wirelessmode);
3648 if (mac->opmode == NL80211_IFTYPE_STATION ||
3649 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
3650 curtxbw_40mhz = mac->bw_40;
3651 } else if (mac->opmode == NL80211_IFTYPE_AP ||
3652 mac->opmode == NL80211_IFTYPE_ADHOC)
3653 macid = sta->aid + 1;
3654 if (wirelessmode == WIRELESS_MODE_N_5G ||
3655 wirelessmode == WIRELESS_MODE_AC_5G ||
3656 wirelessmode == WIRELESS_MODE_A)
3657 ratr_bitmap = sta->supp_rates[NL80211_BAND_5GHZ] << 4;
3659 ratr_bitmap = sta->supp_rates[NL80211_BAND_2GHZ];
3661 if (mac->opmode == NL80211_IFTYPE_ADHOC)
3662 ratr_bitmap = 0xfff;
3664 if (wirelessmode == WIRELESS_MODE_N_24G
3665 || wirelessmode == WIRELESS_MODE_N_5G)
3666 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
3667 sta->ht_cap.mcs.rx_mask[0] << 12);
3668 else if (wirelessmode == WIRELESS_MODE_AC_24G
3669 || wirelessmode == WIRELESS_MODE_AC_5G
3670 || wirelessmode == WIRELESS_MODE_AC_ONLY)
3671 ratr_bitmap |= _rtl8821ae_rate_to_bitmap_2ssvht(
3672 sta->vht_cap.vht_mcs.rx_mcs_map) << 12;
3674 b_shortgi = _rtl8821ae_get_ra_shortgi(hw, sta, macid);
3675 rf_type = _rtl8821ae_get_ra_rftype(hw, wirelessmode, ratr_bitmap);
3678 switch (wirelessmode) {
3679 case WIRELESS_MODE_B:
3680 ratr_index = RATR_INX_WIRELESS_B;
3681 if (ratr_bitmap & 0x0000000c)
3682 ratr_bitmap &= 0x0000000d;
3684 ratr_bitmap &= 0x0000000f;
3686 case WIRELESS_MODE_G:
3687 ratr_index = RATR_INX_WIRELESS_GB;
3689 if (rssi_level == 1)
3690 ratr_bitmap &= 0x00000f00;
3691 else if (rssi_level == 2)
3692 ratr_bitmap &= 0x00000ff0;
3694 ratr_bitmap &= 0x00000ff5;
3696 case WIRELESS_MODE_A:
3697 ratr_index = RATR_INX_WIRELESS_G;
3698 ratr_bitmap &= 0x00000ff0;
3700 case WIRELESS_MODE_N_24G:
3701 case WIRELESS_MODE_N_5G:
3702 if (wirelessmode == WIRELESS_MODE_N_24G)
3703 ratr_index = RATR_INX_WIRELESS_NGB;
3705 ratr_index = RATR_INX_WIRELESS_NG;
3707 if (mimo_ps == IEEE80211_SMPS_STATIC
3708 || mimo_ps == IEEE80211_SMPS_DYNAMIC) {
3709 if (rssi_level == 1)
3710 ratr_bitmap &= 0x000f0000;
3711 else if (rssi_level == 2)
3712 ratr_bitmap &= 0x000ff000;
3714 ratr_bitmap &= 0x000ff005;
3716 if (rf_type == RF_1T1R) {
3717 if (curtxbw_40mhz) {
3718 if (rssi_level == 1)
3719 ratr_bitmap &= 0x000f0000;
3720 else if (rssi_level == 2)
3721 ratr_bitmap &= 0x000ff000;
3723 ratr_bitmap &= 0x000ff015;
3725 if (rssi_level == 1)
3726 ratr_bitmap &= 0x000f0000;
3727 else if (rssi_level == 2)
3728 ratr_bitmap &= 0x000ff000;
3730 ratr_bitmap &= 0x000ff005;
3733 if (curtxbw_40mhz) {
3734 if (rssi_level == 1)
3735 ratr_bitmap &= 0x0fff0000;
3736 else if (rssi_level == 2)
3737 ratr_bitmap &= 0x0ffff000;
3739 ratr_bitmap &= 0x0ffff015;
3741 if (rssi_level == 1)
3742 ratr_bitmap &= 0x0fff0000;
3743 else if (rssi_level == 2)
3744 ratr_bitmap &= 0x0ffff000;
3746 ratr_bitmap &= 0x0ffff005;
3752 case WIRELESS_MODE_AC_24G:
3753 ratr_index = RATR_INX_WIRELESS_AC_24N;
3754 if (rssi_level == 1)
3755 ratr_bitmap &= 0xfc3f0000;
3756 else if (rssi_level == 2)
3757 ratr_bitmap &= 0xfffff000;
3759 ratr_bitmap &= 0xffffffff;
3762 case WIRELESS_MODE_AC_5G:
3763 ratr_index = RATR_INX_WIRELESS_AC_5N;
3765 if (rf_type == RF_1T1R) {
3766 if (rssi_level == 1) /*add by Gary for ac-series*/
3767 ratr_bitmap &= 0x003f8000;
3768 else if (rssi_level == 2)
3769 ratr_bitmap &= 0x003ff000;
3771 ratr_bitmap &= 0x003ff010;
3773 if (rssi_level == 1)
3774 ratr_bitmap &= 0xfe3f8000;
3775 else if (rssi_level == 2)
3776 ratr_bitmap &= 0xfffff000;
3778 ratr_bitmap &= 0xfffff010;
3783 ratr_index = RATR_INX_WIRELESS_NGB;
3785 if (rf_type == RF_1T2R)
3786 ratr_bitmap &= 0x000ff0ff;
3788 ratr_bitmap &= 0x0f8ff0ff;
3792 ratr_index = _rtl8821ae_mrate_idx_to_arfr_id(hw, ratr_index, wirelessmode);
3793 sta_entry->ratr_index = ratr_index;
3794 ratr_bitmap = _rtl8821ae_set_ra_vht_ratr_bitmap(hw, wirelessmode,
3797 RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD,
3798 "ratr_bitmap :%x\n", ratr_bitmap);
3800 /* *(u32 *)& rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
3801 (ratr_index << 28)); */
3803 rate_mask[0] = macid;
3804 rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00);
3805 rate_mask[2] = rtlphy->current_chan_bw
3806 | _rtl8821ae_get_vht_eni(wirelessmode, ratr_bitmap)
3807 | _rtl8821ae_get_ra_ldpc(hw, macid, sta_entry, wirelessmode);
3809 rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
3810 rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
3811 rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
3812 rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
3814 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
3815 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
3816 ratr_index, ratr_bitmap,
3817 rate_mask[0], rate_mask[1],
3818 rate_mask[2], rate_mask[3],
3819 rate_mask[4], rate_mask[5],
3821 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_RA_MASK, 7, rate_mask);
3822 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
3825 void rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw *hw,
3826 struct ieee80211_sta *sta, u8 rssi_level)
3828 struct rtl_priv *rtlpriv = rtl_priv(hw);
3829 if (rtlpriv->dm.useramask)
3830 rtl8821ae_update_hal_rate_mask(hw, sta, rssi_level);
3832 /*RT_TRACE(rtlpriv, COMP_RATR,DBG_LOUD,
3833 "rtl8821ae_update_hal_rate_tbl() Error! 8821ae FW RA Only");*/
3834 rtl8821ae_update_hal_rate_table(hw, sta);
3837 void rtl8821ae_update_channel_access_setting(struct ieee80211_hw *hw)
3839 struct rtl_priv *rtlpriv = rtl_priv(hw);
3840 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3841 u8 wireless_mode = mac->mode;
3842 u8 sifs_timer, r2t_sifs;
3844 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
3845 (u8 *)&mac->slot_time);
3846 if (wireless_mode == WIRELESS_MODE_G)
3850 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
3854 if (wireless_mode == WIRELESS_MODE_AC_5G &&
3855 (mac->vht_ldpc_cap & LDPC_VHT_ENABLE_RX) &&
3856 (mac->vht_stbc_cap & STBC_VHT_ENABLE_RX)) {
3857 if (mac->vendor == PEER_ATH)
3861 } else if (wireless_mode == WIRELESS_MODE_AC_5G) {
3865 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_R2T_SIFS, (u8 *)&r2t_sifs);
3868 bool rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
3870 struct rtl_priv *rtlpriv = rtl_priv(hw);
3871 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3872 struct rtl_phy *rtlphy = &rtlpriv->phy;
3873 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
3875 bool b_actuallyset = false;
3877 if (rtlpriv->rtlhal.being_init_adapter)
3880 if (ppsc->swrf_processing)
3883 spin_lock(&rtlpriv->locks.rf_ps_lock);
3884 if (ppsc->rfchange_inprogress) {
3885 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3888 ppsc->rfchange_inprogress = true;
3889 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3892 cur_rfstate = ppsc->rfpwr_state;
3894 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
3895 rtl_read_byte(rtlpriv,
3896 REG_GPIO_IO_SEL_2) & ~(BIT(1)));
3898 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
3900 if (rtlphy->polarity_ctl)
3901 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
3903 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
3905 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
3906 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3907 "GPIOChangeRF - HW Radio ON, RF ON\n");
3909 e_rfpowerstate_toset = ERFON;
3910 ppsc->hwradiooff = false;
3911 b_actuallyset = true;
3912 } else if ((!ppsc->hwradiooff)
3913 && (e_rfpowerstate_toset == ERFOFF)) {
3914 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3915 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
3917 e_rfpowerstate_toset = ERFOFF;
3918 ppsc->hwradiooff = true;
3919 b_actuallyset = true;
3922 if (b_actuallyset) {
3923 spin_lock(&rtlpriv->locks.rf_ps_lock);
3924 ppsc->rfchange_inprogress = false;
3925 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3927 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
3928 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3930 spin_lock(&rtlpriv->locks.rf_ps_lock);
3931 ppsc->rfchange_inprogress = false;
3932 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3936 return !ppsc->hwradiooff;
3939 void rtl8821ae_set_key(struct ieee80211_hw *hw, u32 key_index,
3940 u8 *p_macaddr, bool is_group, u8 enc_algo,
3941 bool is_wepkey, bool clear_all)
3943 struct rtl_priv *rtlpriv = rtl_priv(hw);
3944 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3945 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3946 u8 *macaddr = p_macaddr;
3948 bool is_pairwise = false;
3950 static u8 cam_const_addr[4][6] = {
3951 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
3952 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
3953 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
3954 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
3956 static u8 cam_const_broad[] = {
3957 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
3963 u8 clear_number = 5;
3965 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
3967 for (idx = 0; idx < clear_number; idx++) {
3968 rtl_cam_mark_invalid(hw, cam_offset + idx);
3969 rtl_cam_empty_entry(hw, cam_offset + idx);
3972 memset(rtlpriv->sec.key_buf[idx], 0,
3974 rtlpriv->sec.key_len[idx] = 0;
3979 case WEP40_ENCRYPTION:
3980 enc_algo = CAM_WEP40;
3982 case WEP104_ENCRYPTION:
3983 enc_algo = CAM_WEP104;
3985 case TKIP_ENCRYPTION:
3986 enc_algo = CAM_TKIP;
3988 case AESCCMP_ENCRYPTION:
3992 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
3993 "switch case not process\n");
3994 enc_algo = CAM_TKIP;
3998 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
3999 macaddr = cam_const_addr[key_index];
4000 entry_id = key_index;
4003 macaddr = cam_const_broad;
4004 entry_id = key_index;
4006 if (mac->opmode == NL80211_IFTYPE_AP) {
4007 entry_id = rtl_cam_get_free_entry(hw, p_macaddr);
4008 if (entry_id >= TOTAL_CAM_ENTRY) {
4009 RT_TRACE(rtlpriv, COMP_SEC, DBG_EMERG,
4010 "Can not find free hwsecurity cam entry\n");
4014 entry_id = CAM_PAIRWISE_KEY_POSITION;
4017 key_index = PAIRWISE_KEYIDX;
4022 if (rtlpriv->sec.key_len[key_index] == 0) {
4023 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
4024 "delete one entry, entry_id is %d\n",
4026 if (mac->opmode == NL80211_IFTYPE_AP)
4027 rtl_cam_del_entry(hw, p_macaddr);
4028 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
4030 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
4033 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
4034 "set Pairwise key\n");
4036 rtl_cam_add_one_entry(hw, macaddr, key_index,
4038 CAM_CONFIG_NO_USEDK,
4039 rtlpriv->sec.key_buf[key_index]);
4041 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
4044 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
4045 rtl_cam_add_one_entry(hw,
4048 CAM_PAIRWISE_KEY_POSITION,
4050 CAM_CONFIG_NO_USEDK,
4051 rtlpriv->sec.key_buf
4055 rtl_cam_add_one_entry(hw, macaddr, key_index,
4057 CAM_CONFIG_NO_USEDK,
4058 rtlpriv->sec.key_buf[entry_id]);
4064 void rtl8821ae_bt_reg_init(struct ieee80211_hw *hw)
4066 struct rtl_priv *rtlpriv = rtl_priv(hw);
4068 /* 0:Low, 1:High, 2:From Efuse. */
4069 rtlpriv->btcoexist.reg_bt_iso = 2;
4070 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
4071 rtlpriv->btcoexist.reg_bt_sco = 3;
4072 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
4073 rtlpriv->btcoexist.reg_bt_sco = 0;
4076 void rtl8821ae_bt_hw_init(struct ieee80211_hw *hw)
4078 struct rtl_priv *rtlpriv = rtl_priv(hw);
4080 if (rtlpriv->cfg->ops->get_btc_status())
4081 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
4084 void rtl8821ae_suspend(struct ieee80211_hw *hw)
4088 void rtl8821ae_resume(struct ieee80211_hw *hw)
4092 /* Turn on AAP (RCR:bit 0) for promicuous mode. */
4093 void rtl8821ae_allow_all_destaddr(struct ieee80211_hw *hw,
4094 bool allow_all_da, bool write_into_reg)
4096 struct rtl_priv *rtlpriv = rtl_priv(hw);
4097 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
4099 if (allow_all_da) /* Set BIT0 */
4100 rtlpci->receive_config |= RCR_AAP;
4101 else /* Clear BIT0 */
4102 rtlpci->receive_config &= ~RCR_AAP;
4105 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
4107 RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
4108 "receive_config=0x%08X, write_into_reg=%d\n",
4109 rtlpci->receive_config, write_into_reg);
4112 /* WKFMCAMAddAllEntry8812 */
4113 void rtl8821ae_add_wowlan_pattern(struct ieee80211_hw *hw,
4114 struct rtl_wow_pattern *rtl_pattern,
4117 struct rtl_priv *rtlpriv = rtl_priv(hw);
4125 /* Count the WFCAM entry start offset. */
4127 /* RX page size = 128 byte */
4128 offset = MAX_RX_DMA_BUFFER_SIZE_8812 / 128;
4129 /* We should start from the boundry */
4130 cam_start = offset * 128;
4132 /* Enable Rx packet buffer access. */
4133 rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
4134 for (addr = 0; addr < WKFMCAM_ADDR_NUM; addr++) {
4135 /* Set Rx packet buffer offset.
4136 * RxBufer pointer increases 1,
4137 * we can access 8 bytes in Rx packet buffer.
4138 * CAM start offset (unit: 1 byte) = index*WKFMCAM_SIZE
4139 * RxBufer addr = (CAM start offset +
4140 * per entry offset of a WKFM CAM)/8
4141 * * index: The index of the wake up frame mask
4142 * * WKFMCAM_SIZE: the total size of one WKFM CAM
4143 * * per entry offset of a WKFM CAM: Addr*4 bytes
4145 rxbuf_addr = (cam_start + index * WKFMCAM_SIZE + addr * 4) >> 3;
4146 /* Set R/W start offset */
4147 rtl_write_word(rtlpriv, REG_PKTBUF_DBG_CTRL, rxbuf_addr);
4150 cam = BIT(31) | rtl_pattern->crc;
4152 if (rtl_pattern->type == UNICAST_PATTERN)
4154 else if (rtl_pattern->type == MULTICAST_PATTERN)
4156 else if (rtl_pattern->type == BROADCAST_PATTERN)
4159 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4160 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4161 "WRITE entry[%d] 0x%x: %x\n", addr,
4162 REG_PKTBUF_DBG_DATA_L, cam);
4164 /* Write to Rx packet buffer. */
4165 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
4166 } else if (addr == 2 || addr == 4) {/* WKFM[127:0] */
4167 cam = rtl_pattern->mask[addr - 2];
4169 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4170 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4171 "WRITE entry[%d] 0x%x: %x\n", addr,
4172 REG_PKTBUF_DBG_DATA_L, cam);
4174 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
4175 } else if (addr == 3 || addr == 5) {/* WKFM[127:0] */
4176 cam = rtl_pattern->mask[addr - 2];
4178 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_H, cam);
4179 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4180 "WRITE entry[%d] 0x%x: %x\n", addr,
4181 REG_PKTBUF_DBG_DATA_H, cam);
4183 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0xf001);
4188 tmp = rtl_read_byte(rtlpriv, REG_RXPKTBUF_CTRL);
4191 } while (tmp && count < 100);
4193 RT_ASSERT((count < 100),
4194 "Write wake up frame mask FAIL %d value!\n", tmp);
4196 /* Disable Rx packet buffer access. */
4197 rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL,
4198 DISABLE_TRXPKT_BUF_ACCESS);