2 * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
3 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
19 MT_TXQ_VO = IEEE80211_AC_VO,
20 MT_TXQ_VI = IEEE80211_AC_VI,
21 MT_TXQ_BE = IEEE80211_AC_BE,
22 MT_TXQ_BK = IEEE80211_AC_BK,
28 /* Hardware uses mirrored order of queues with Q0 having the highest priority */
34 /* Take mac80211 Q id from the skb and translate it to hardware Q id */
35 static u8 skb2q(struct sk_buff *skb)
37 int qid = skb_get_queue_mapping(skb);
39 if (WARN_ON(qid >= MT_TXQ_PSD)) {
41 skb_set_queue_mapping(skb, qid);
47 /* Note: TX retry reporting is a bit broken.
48 * Retries are reported only once per AMPDU and often come a frame early
49 * i.e. they are reported in the last status preceding the AMPDU. Apart
50 * from the fact that it's hard to know the length of the AMPDU (which is
51 * required to know to how many consecutive frames retries should be
52 * applied), if status comes early on full FIFO it gets lost and retries
53 * of the whole AMPDU become invisible.
54 * As a work-around encode the desired rate in PKT_ID of TX descriptor
55 * and based on that guess the retries (every rate is tried once).
56 * Only downside here is that for MCS0 we have to rely solely on
57 * transmission failures as no retries can ever be reported.
58 * Not having to read EXT_FIFO has a nice effect of doubling the number
59 * of reports which can be fetched.
60 * Also the vendor driver never uses the EXT_FIFO register so it may be
63 static u8 mt7601u_tx_pktid_enc(struct mt7601u_dev *dev, u8 rate, bool is_probe)
65 u8 encoded = (rate + 1) + is_probe * 8;
67 /* Because PKT_ID 0 disables status reporting only 15 values are
68 * available but 16 are needed (8 MCS * 2 for encoding is_probe)
69 * - we need to cram together two rates. MCS0 and MCS7 with is_probe
72 if (is_probe && rate == 7)
79 mt7601u_tx_pktid_dec(struct mt7601u_dev *dev, struct mt76_tx_status *stat)
81 u8 req_rate = stat->pktid;
82 u8 eff_rate = stat->rate & 0x7;
87 stat->is_probe = true;
90 /* Decide between MCS0 and MCS7 which share pktid 9 */
91 if (!req_rate && eff_rate)
95 stat->retry = req_rate - eff_rate;
98 static void mt7601u_tx_skb_remove_dma_overhead(struct sk_buff *skb,
99 struct ieee80211_tx_info *info)
101 int pkt_len = (unsigned long)info->status.status_driver_data[0];
103 skb_pull(skb, sizeof(struct mt76_txwi) + 4);
104 if (ieee80211_get_hdrlen_from_skb(skb) % 4)
105 mt76_remove_hdr_pad(skb);
107 skb_trim(skb, pkt_len);
110 void mt7601u_tx_status(struct mt7601u_dev *dev, struct sk_buff *skb)
112 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
114 mt7601u_tx_skb_remove_dma_overhead(skb, info);
116 ieee80211_tx_info_clear_status(info);
117 info->status.rates[0].idx = -1;
118 info->flags |= IEEE80211_TX_STAT_ACK;
119 ieee80211_tx_status(dev->hw, skb);
122 static int mt7601u_skb_rooms(struct mt7601u_dev *dev, struct sk_buff *skb)
124 int hdr_len = ieee80211_get_hdrlen_from_skb(skb);
127 need_head = sizeof(struct mt76_txwi) + 4;
131 return skb_cow(skb, need_head);
134 static struct mt76_txwi *
135 mt7601u_push_txwi(struct mt7601u_dev *dev, struct sk_buff *skb,
136 struct ieee80211_sta *sta, struct mt76_wcid *wcid,
139 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
140 struct ieee80211_tx_rate *rate = &info->control.rates[0];
141 struct mt76_txwi *txwi;
148 txwi = (struct mt76_txwi *)skb_push(skb, sizeof(struct mt76_txwi));
149 memset(txwi, 0, sizeof(*txwi));
151 if (!wcid->tx_rate_set)
152 ieee80211_get_tx_rates(info->control.vif, sta, skb,
153 info->control.rates, 1);
155 spin_lock_irqsave(&dev->lock, flags);
156 if (rate->idx < 0 || !rate->count)
157 rate_ctl = wcid->tx_rate;
159 rate_ctl = mt76_mac_tx_rate_val(dev, rate, &nss);
160 spin_unlock_irqrestore(&dev->lock, flags);
161 txwi->rate_ctl = cpu_to_le16(rate_ctl);
163 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK))
164 txwi->ack_ctl |= MT_TXWI_ACK_CTL_REQ;
165 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)
166 txwi->ack_ctl |= MT_TXWI_ACK_CTL_NSEQ;
168 if ((info->flags & IEEE80211_TX_CTL_AMPDU) && sta) {
169 u8 ba_size = IEEE80211_MIN_AMPDU_BUF;
171 ba_size <<= sta->ht_cap.ampdu_factor;
172 ba_size = min_t(int, 63, ba_size);
173 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)
175 txwi->ack_ctl |= MT76_SET(MT_TXWI_ACK_CTL_BA_WINDOW, ba_size);
177 txwi->flags = cpu_to_le16(MT_TXWI_FLAGS_AMPDU |
178 MT76_SET(MT_TXWI_FLAGS_MPDU_DENSITY,
179 sta->ht_cap.ampdu_density));
180 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)
184 txwi->wcid = wcid->idx;
186 is_probe = !!(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
187 pkt_id = mt7601u_tx_pktid_enc(dev, rate_ctl & 0x7, is_probe);
188 pkt_len |= MT76_SET(MT_TXWI_LEN_PKTID, pkt_id);
189 txwi->len_ctl = cpu_to_le16(pkt_len);
194 void mt7601u_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
197 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
198 struct mt7601u_dev *dev = hw->priv;
199 struct ieee80211_vif *vif = info->control.vif;
200 struct ieee80211_sta *sta = control->sta;
201 struct mt76_sta *msta = NULL;
202 struct mt76_wcid *wcid = dev->mon_wcid;
203 struct mt76_txwi *txwi;
204 int pkt_len = skb->len;
205 int hw_q = skb2q(skb);
207 BUILD_BUG_ON(ARRAY_SIZE(info->status.status_driver_data) < 1);
208 info->status.status_driver_data[0] = (void *)(unsigned long)pkt_len;
210 if (mt7601u_skb_rooms(dev, skb) || mt76_insert_hdr_pad(skb)) {
211 ieee80211_free_txskb(dev->hw, skb);
216 msta = (struct mt76_sta *) sta->drv_priv;
219 struct mt76_vif *mvif = (struct mt76_vif *)vif->drv_priv;
221 wcid = &mvif->group_wcid;
224 txwi = mt7601u_push_txwi(dev, skb, sta, wcid, pkt_len);
226 if (mt7601u_dma_enqueue_tx(dev, skb, wcid, hw_q))
229 trace_mt_tx(dev, skb, msta, txwi);
232 void mt7601u_tx_stat(struct work_struct *work)
234 struct mt7601u_dev *dev = container_of(work, struct mt7601u_dev,
236 struct mt76_tx_status stat;
240 while (!test_bit(MT7601U_STATE_REMOVED, &dev->state)) {
241 stat = mt7601u_mac_fetch_tx_status(dev);
245 mt7601u_tx_pktid_dec(dev, &stat);
246 mt76_send_tx_status(dev, &stat);
250 trace_mt_tx_status_cleaned(dev, cleaned);
252 spin_lock_irqsave(&dev->tx_lock, flags);
254 queue_delayed_work(dev->stat_wq, &dev->stat_work,
255 msecs_to_jiffies(10));
256 else if (test_and_clear_bit(MT7601U_STATE_MORE_STATS, &dev->state))
257 queue_delayed_work(dev->stat_wq, &dev->stat_work,
258 msecs_to_jiffies(20));
260 clear_bit(MT7601U_STATE_READING_STATS, &dev->state);
261 spin_unlock_irqrestore(&dev->tx_lock, flags);
264 int mt7601u_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
265 u16 queue, const struct ieee80211_tx_queue_params *params)
267 struct mt7601u_dev *dev = hw->priv;
268 u8 cw_min = 5, cw_max = 10, hw_q = q2hwq(queue);
271 /* TODO: should we do funny things with the parameters?
272 * See what mt7601u_set_default_edca() used to do in init.c.
276 cw_min = fls(params->cw_min);
278 cw_max = fls(params->cw_max);
280 WARN_ON(params->txop > 0xff);
281 WARN_ON(params->aifs > 0xf);
282 WARN_ON(cw_min > 0xf);
283 WARN_ON(cw_max > 0xf);
285 val = MT76_SET(MT_EDCA_CFG_AIFSN, params->aifs) |
286 MT76_SET(MT_EDCA_CFG_CWMIN, cw_min) |
287 MT76_SET(MT_EDCA_CFG_CWMAX, cw_max);
288 /* TODO: based on user-controlled EnableTxBurst var vendor drv sets
289 * a really long txop on AC0 (see connect.c:2009) but only on
290 * connect? When not connected should be 0.
295 val |= MT76_SET(MT_EDCA_CFG_TXOP, params->txop);
296 mt76_wr(dev, MT_EDCA_CFG_AC(hw_q), val);
298 val = mt76_rr(dev, MT_WMM_TXOP(hw_q));
299 val &= ~(MT_WMM_TXOP_MASK << MT_WMM_TXOP_SHIFT(hw_q));
300 val |= params->txop << MT_WMM_TXOP_SHIFT(hw_q);
301 mt76_wr(dev, MT_WMM_TXOP(hw_q), val);
303 val = mt76_rr(dev, MT_WMM_AIFSN);
304 val &= ~(MT_WMM_AIFSN_MASK << MT_WMM_AIFSN_SHIFT(hw_q));
305 val |= params->aifs << MT_WMM_AIFSN_SHIFT(hw_q);
306 mt76_wr(dev, MT_WMM_AIFSN, val);
308 val = mt76_rr(dev, MT_WMM_CWMIN);
309 val &= ~(MT_WMM_CWMIN_MASK << MT_WMM_CWMIN_SHIFT(hw_q));
310 val |= cw_min << MT_WMM_CWMIN_SHIFT(hw_q);
311 mt76_wr(dev, MT_WMM_CWMIN, val);
313 val = mt76_rr(dev, MT_WMM_CWMAX);
314 val &= ~(MT_WMM_CWMAX_MASK << MT_WMM_CWMAX_SHIFT(hw_q));
315 val |= cw_max << MT_WMM_CWMAX_SHIFT(hw_q);
316 mt76_wr(dev, MT_WMM_CWMAX, val);