drivers/net/wireless/iwlwifi/pcie/rx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/sched.h>
  30 #include <linux/wait.h>
  31 #include <linux/gfp.h>
  32
  33 #include "iwl-prph.h"
  34 #include "iwl-io.h"
  35 #include "internal.h"
  36 #include "iwl-op-mode.h"
  37
  38 /******************************************************************************
  39  *
  40  * RX path functions
  41  *
  42  ******************************************************************************/
  43
  44 /*
  45  * Rx theory of operation
  46  *
  47  * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  48  * each of which point to Receive Buffers to be filled by the NIC.  These get
  49  * used not only for Rx frames, but for any command response or notification
  50  * from the NIC.  The driver and NIC manage the Rx buffers by means
  51  * of indexes into the circular buffer.
  52  *
  53  * Rx Queue Indexes
  54  * The host/firmware share two index registers for managing the Rx buffers.
  55  *
  56  * The READ index maps to the first position that the firmware may be writing
  57  * to -- the driver can read up to (but not including) this position and get
  58  * good data.
  59  * The READ index is managed by the firmware once the card is enabled.
  60  *
  61  * The WRITE index maps to the last position the driver has read from -- the
  62  * position preceding WRITE is the last slot the firmware can place a packet.
  63  *
  64  * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  65  * WRITE = READ.
  66  *
  67  * During initialization, the host sets up the READ queue position to the first
  68  * INDEX position, and WRITE to the last (READ - 1 wrapped)
  69  *
  70  * When the firmware places a packet in a buffer, it will advance the READ index
  71  * and fire the RX interrupt.  The driver can then query the READ index and
  72  * process as many packets as possible, moving the WRITE index forward as it
  73  * resets the Rx queue buffers with new memory.
  74  *
  75  * The management in the driver is as follows:
  76  * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free.  When
  77  *   iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  78  *   to replenish the iwl->rxq->rx_free.
  79  * + In iwl_pcie_rx_replenish (scheduled) if 'processed' != 'read' then the
  80  *   iwl->rxq is replenished and the READ INDEX is updated (updating the
  81  *   'processed' and 'read' driver indexes as well)
  82  * + A received packet is processed and handed to the kernel network stack,
  83  *   detached from the iwl->rxq.  The driver 'processed' index is updated.
  84  * + The Host/Firmware iwl->rxq is replenished at irq thread time from the
  85  *   rx_free list. If there are no allocated buffers in iwl->rxq->rx_free,
  86  *   the READ INDEX is not incremented and iwl->status(RX_STALLED) is set.
  87  *   If there were enough free buffers and RX_STALLED is set it is cleared.
  88  *
  89  *
  90  * Driver sequence:
  91  *
  92  * iwl_rxq_alloc()            Allocates rx_free
  93  * iwl_pcie_rx_replenish()    Replenishes rx_free list from rx_used, and calls
  94  *                            iwl_pcie_rxq_restock
  95  * iwl_pcie_rxq_restock()     Moves available buffers from rx_free into Rx
  96  *                            queue, updates firmware pointers, and updates
  97  *                            the WRITE index.  If insufficient rx_free buffers
  98  *                            are available, schedules iwl_pcie_rx_replenish
  99  *
 100  * -- enable interrupts --
 101  * ISR - iwl_rx()             Detach iwl_rx_mem_buffers from pool up to the
 102  *                            READ INDEX, detaching the SKB from the pool.
 103  *                            Moves the packet buffer from queue to rx_used.
 104  *                            Calls iwl_pcie_rxq_restock to refill any empty
 105  *                            slots.
 106  * ...
 107  *
 108  */
 109
 110 /*
 111  * iwl_rxq_space - Return number of free slots available in queue.
 112  */
 113 static int iwl_rxq_space(const struct iwl_rxq *q)
 114 {
 115         int s = q->read - q->write;
 116         if (s <= 0)
 117                 s += RX_QUEUE_SIZE;
 118         /* keep some buffer to not confuse full and empty queue */
 119         s -= 2;
 120         if (s < 0)
 121                 s = 0;
 122         return s;
 123 }
 124
 125 /*
 126  * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 127  */
 128 static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr)
 129 {
 130         return cpu_to_le32((u32)(dma_addr >> 8));
 131 }
 132
 133 /*
 134  * iwl_pcie_rx_stop - stops the Rx DMA
 135  */
 136 int iwl_pcie_rx_stop(struct iwl_trans *trans)
 137 {
 138         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 139         return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
 140                                    FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 141 }
 142
 143 /*
 144  * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue
 145  */
 146 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_rxq *q)
 147 {
 148         unsigned long flags;
 149         u32 reg;
 150
 151         spin_lock_irqsave(&q->lock, flags);
 152
 153         if (q->need_update == 0)
 154                 goto exit_unlock;
 155
 156         if (trans->cfg->base_params->shadow_reg_enable) {
 157                 /* shadow register enabled */
 158                 /* Device expects a multiple of 8 */
 159                 q->write_actual = (q->write & ~0x7);
 160                 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, q->write_actual);
 161         } else {
 162                 struct iwl_trans_pcie *trans_pcie =
 163                         IWL_TRANS_GET_PCIE_TRANS(trans);
 164
 165                 /* If power-saving is in use, make sure device is awake */
 166                 if (test_bit(STATUS_TPOWER_PMI, &trans_pcie->status)) {
 167                         reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 168
 169                         if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 170                                 IWL_DEBUG_INFO(trans,
 171                                         "Rx queue requesting wakeup,"
 172                                         " GP1 = 0x%x\n", reg);
 173                                 iwl_set_bit(trans, CSR_GP_CNTRL,
 174                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 175                                 goto exit_unlock;
 176                         }
 177
 178                         q->write_actual = (q->write & ~0x7);
 179                         iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
 180                                         q->write_actual);
 181
 182                 /* Else device is assumed to be awake */
 183                 } else {
 184                         /* Device expects a multiple of 8 */
 185                         q->write_actual = (q->write & ~0x7);
 186                         iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
 187                                 q->write_actual);
 188                 }
 189         }
 190         q->need_update = 0;
 191
 192  exit_unlock:
 193         spin_unlock_irqrestore(&q->lock, flags);
 194 }
 195
 196 /*
 197  * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool
 198  *
 199  * If there are slots in the RX queue that need to be restocked,
 200  * and we have free pre-allocated buffers, fill the ranks as much
 201  * as we can, pulling from rx_free.
 202  *
 203  * This moves the 'write' index forward to catch up with 'processed', and
 204  * also updates the memory address in the firmware to reference the new
 205  * target buffer.
 206  */
 207 static void iwl_pcie_rxq_restock(struct iwl_trans *trans)
 208 {
 209         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 210         struct iwl_rxq *rxq = &trans_pcie->rxq;
 211         struct iwl_rx_mem_buffer *rxb;
 212         unsigned long flags;
 213
 214         /*
 215          * If the device isn't enabled - not need to try to add buffers...
 216          * This can happen when we stop the device and still have an interrupt
 217          * pending. We stop the APM before we sync the interrupts because we
 218          * have to (see comment there). On the other hand, since the APM is
 219          * stopped, we cannot access the HW (in particular not prph).
 220          * So don't try to restock if the APM has been already stopped.
 221          */
 222         if (!test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status))
 223                 return;
 224
 225         spin_lock_irqsave(&rxq->lock, flags);
 226         while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) {
 227                 /* The overwritten rxb must be a used one */
 228                 rxb = rxq->queue[rxq->write];
 229                 BUG_ON(rxb && rxb->page);
 230
 231                 /* Get next free Rx buffer, remove from free list */
 232                 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
 233                                        list);
 234                 list_del(&rxb->list);
 235
 236                 /* Point to Rx buffer via next RBD in circular buffer */
 237                 rxq->bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma);
 238                 rxq->queue[rxq->write] = rxb;
 239                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 240                 rxq->free_count--;
 241         }
 242         spin_unlock_irqrestore(&rxq->lock, flags);
 243         /* If the pre-allocated buffer pool is dropping low, schedule to
 244          * refill it */
 245         if (rxq->free_count <= RX_LOW_WATERMARK)
 246                 schedule_work(&trans_pcie->rx_replenish);
 247
 248         /* If we've added more space for the firmware to place data, tell it.
 249          * Increment device's write pointer in multiples of 8. */
 250         if (rxq->write_actual != (rxq->write & ~0x7)) {
 251                 spin_lock_irqsave(&rxq->lock, flags);
 252                 rxq->need_update = 1;
 253                 spin_unlock_irqrestore(&rxq->lock, flags);
 254                 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
 255         }
 256 }
 257
 258 /*
 259  * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD
 260  *
 261  * A used RBD is an Rx buffer that has been given to the stack. To use it again
 262  * a page must be allocated and the RBD must point to the page. This function
 263  * doesn't change the HW pointer but handles the list of pages that is used by
 264  * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly
 265  * allocated buffers.
 266  */
 267 static void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority)
 268 {
 269         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 270         struct iwl_rxq *rxq = &trans_pcie->rxq;
 271         struct iwl_rx_mem_buffer *rxb;
 272         struct page *page;
 273         unsigned long flags;
 274         gfp_t gfp_mask = priority;
 275
 276         while (1) {
 277                 spin_lock_irqsave(&rxq->lock, flags);
 278                 if (list_empty(&rxq->rx_used)) {
 279                         spin_unlock_irqrestore(&rxq->lock, flags);
 280                         return;
 281                 }
 282                 spin_unlock_irqrestore(&rxq->lock, flags);
 283
 284                 if (rxq->free_count > RX_LOW_WATERMARK)
 285                         gfp_mask |= __GFP_NOWARN;
 286
 287                 if (trans_pcie->rx_page_order > 0)
 288                         gfp_mask |= __GFP_COMP;
 289
 290                 /* Alloc a new receive buffer */
 291                 page = alloc_pages(gfp_mask, trans_pcie->rx_page_order);
 292                 if (!page) {
 293                         if (net_ratelimit())
 294                                 IWL_DEBUG_INFO(trans, "alloc_pages failed, "
 295                                            "order: %d\n",
 296                                            trans_pcie->rx_page_order);
 297
 298                         if ((rxq->free_count <= RX_LOW_WATERMARK) &&
 299                             net_ratelimit())
 300                                 IWL_CRIT(trans, "Failed to alloc_pages with %s."
 301                                          "Only %u free buffers remaining.\n",
 302                                          priority == GFP_ATOMIC ?
 303                                          "GFP_ATOMIC" : "GFP_KERNEL",
 304                                          rxq->free_count);
 305                         /* We don't reschedule replenish work here -- we will
 306                          * call the restock method and if it still needs
 307                          * more buffers it will schedule replenish */
 308                         return;
 309                 }
 310
 311                 spin_lock_irqsave(&rxq->lock, flags);
 312
 313                 if (list_empty(&rxq->rx_used)) {
 314                         spin_unlock_irqrestore(&rxq->lock, flags);
 315                         __free_pages(page, trans_pcie->rx_page_order);
 316                         return;
 317                 }
 318                 rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer,
 319                                        list);
 320                 list_del(&rxb->list);
 321                 spin_unlock_irqrestore(&rxq->lock, flags);
 322
 323                 BUG_ON(rxb->page);
 324                 rxb->page = page;
 325                 /* Get physical address of the RB */
 326                 rxb->page_dma =
 327                         dma_map_page(trans->dev, page, 0,
 328                                      PAGE_SIZE << trans_pcie->rx_page_order,
 329                                      DMA_FROM_DEVICE);
 330                 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
 331                         rxb->page = NULL;
 332                         spin_lock_irqsave(&rxq->lock, flags);
 333                         list_add(&rxb->list, &rxq->rx_used);
 334                         spin_unlock_irqrestore(&rxq->lock, flags);
 335                         __free_pages(page, trans_pcie->rx_page_order);
 336                         return;
 337                 }
 338                 /* dma address must be no more than 36 bits */
 339                 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
 340                 /* and also 256 byte aligned! */
 341                 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
 342
 343                 spin_lock_irqsave(&rxq->lock, flags);
 344
 345                 list_add_tail(&rxb->list, &rxq->rx_free);
 346                 rxq->free_count++;
 347
 348                 spin_unlock_irqrestore(&rxq->lock, flags);
 349         }
 350 }
 351
 352 static void iwl_pcie_rxq_free_rbs(struct iwl_trans *trans)
 353 {
 354         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 355         struct iwl_rxq *rxq = &trans_pcie->rxq;
 356         int i;
 357
 358         /* Fill the rx_used queue with _all_ of the Rx buffers */
 359         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 360                 /* In the reset function, these buffers may have been allocated
 361                  * to an SKB, so we need to unmap and free potential storage */
 362                 if (rxq->pool[i].page != NULL) {
 363                         dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
 364                                        PAGE_SIZE << trans_pcie->rx_page_order,
 365                                        DMA_FROM_DEVICE);
 366                         __free_pages(rxq->pool[i].page,
 367                                      trans_pcie->rx_page_order);
 368                         rxq->pool[i].page = NULL;
 369                 }
 370                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 371         }
 372 }
 373
 374 /*
 375  * iwl_pcie_rx_replenish - Move all used buffers from rx_used to rx_free
 376  *
 377  * When moving to rx_free an page is allocated for the slot.
 378  *
 379  * Also restock the Rx queue via iwl_pcie_rxq_restock.
 380  * This is called as a scheduled work item (except for during initialization)
 381  */
 382 static void iwl_pcie_rx_replenish(struct iwl_trans *trans)
 383 {
 384         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 385         unsigned long flags;
 386
 387         iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL);
 388
 389         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 390         iwl_pcie_rxq_restock(trans);
 391         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 392 }
 393
 394 static void iwl_pcie_rx_replenish_now(struct iwl_trans *trans)
 395 {
 396         iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC);
 397
 398         iwl_pcie_rxq_restock(trans);
 399 }
 400
 401 static void iwl_pcie_rx_replenish_work(struct work_struct *data)
 402 {
 403         struct iwl_trans_pcie *trans_pcie =
 404             container_of(data, struct iwl_trans_pcie, rx_replenish);
 405
 406         iwl_pcie_rx_replenish(trans_pcie->trans);
 407 }
 408
 409 static int iwl_pcie_rx_alloc(struct iwl_trans *trans)
 410 {
 411         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 412         struct iwl_rxq *rxq = &trans_pcie->rxq;
 413         struct device *dev = trans->dev;
 414
 415         memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
 416
 417         spin_lock_init(&rxq->lock);
 418
 419         if (WARN_ON(rxq->bd || rxq->rb_stts))
 420                 return -EINVAL;
 421
 422         /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
 423         rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 424                                       &rxq->bd_dma, GFP_KERNEL);
 425         if (!rxq->bd)
 426                 goto err_bd;
 427
 428         /*Allocate the driver's pointer to receive buffer status */
 429         rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
 430                                            &rxq->rb_stts_dma, GFP_KERNEL);
 431         if (!rxq->rb_stts)
 432                 goto err_rb_stts;
 433
 434         return 0;
 435
 436 err_rb_stts:
 437         dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 438                           rxq->bd, rxq->bd_dma);
 439         rxq->bd_dma = 0;
 440         rxq->bd = NULL;
 441 err_bd:
 442         return -ENOMEM;
 443 }
 444
 445 static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
 446 {
 447         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 448         u32 rb_size;
 449         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 450
 451         if (trans_pcie->rx_buf_size_8k)
 452                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 453         else
 454                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 455
 456         /* Stop Rx DMA */
 457         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 458         /* reset and flush pointers */
 459         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);
 460         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);
 461         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RDPTR, 0);
 462
 463         /* Reset driver's Rx queue write index */
 464         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 465
 466         /* Tell device where to find RBD circular buffer in DRAM */
 467         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 468                            (u32)(rxq->bd_dma >> 8));
 469
 470         /* Tell device where in DRAM to update its Rx status */
 471         iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 472                            rxq->rb_stts_dma >> 4);
 473
 474         /* Enable Rx DMA
 475          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 476          *      the credit mechanism in 5000 HW RX FIFO
 477          * Direct rx interrupts to hosts
 478          * Rx buffer size 4 or 8k
 479          * RB timeout 0x10
 480          * 256 RBDs
 481          */
 482         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 483                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 484                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 485                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 486                            rb_size|
 487                            (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 488                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 489
 490         /* Set interrupt coalescing timer to default (2048 usecs) */
 491         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 492
 493         /* W/A for interrupt coalescing bug in 7260 and 3160 */
 494         if (trans->cfg->host_interrupt_operation_mode)
 495                 iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE);
 496 }
 497
 498 int iwl_pcie_rx_init(struct iwl_trans *trans)
 499 {
 500         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 501         struct iwl_rxq *rxq = &trans_pcie->rxq;
 502         int i, err;
 503         unsigned long flags;
 504
 505         if (!rxq->bd) {
 506                 err = iwl_pcie_rx_alloc(trans);
 507                 if (err)
 508                         return err;
 509         }
 510
 511         spin_lock_irqsave(&rxq->lock, flags);
 512         INIT_LIST_HEAD(&rxq->rx_free);
 513         INIT_LIST_HEAD(&rxq->rx_used);
 514
 515         INIT_WORK(&trans_pcie->rx_replenish,
 516                   iwl_pcie_rx_replenish_work);
 517
 518         iwl_pcie_rxq_free_rbs(trans);
 519
 520         for (i = 0; i < RX_QUEUE_SIZE; i++)
 521                 rxq->queue[i] = NULL;
 522
 523         /* Set us so that we have processed and used all buffers, but have
 524          * not restocked the Rx queue with fresh buffers */
 525         rxq->read = rxq->write = 0;
 526         rxq->write_actual = 0;
 527         rxq->free_count = 0;
 528         memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
 529         spin_unlock_irqrestore(&rxq->lock, flags);
 530
 531         iwl_pcie_rx_replenish(trans);
 532
 533         iwl_pcie_rx_hw_init(trans, rxq);
 534
 535         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 536         rxq->need_update = 1;
 537         iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
 538         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 539
 540         return 0;
 541 }
 542
 543 void iwl_pcie_rx_free(struct iwl_trans *trans)
 544 {
 545         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 546         struct iwl_rxq *rxq = &trans_pcie->rxq;
 547         unsigned long flags;
 548
 549         /*if rxq->bd is NULL, it means that nothing has been allocated,
 550          * exit now */
 551         if (!rxq->bd) {
 552                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
 553                 return;
 554         }
 555
 556         cancel_work_sync(&trans_pcie->rx_replenish);
 557
 558         spin_lock_irqsave(&rxq->lock, flags);
 559         iwl_pcie_rxq_free_rbs(trans);
 560         spin_unlock_irqrestore(&rxq->lock, flags);
 561
 562         dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
 563                           rxq->bd, rxq->bd_dma);
 564         rxq->bd_dma = 0;
 565         rxq->bd = NULL;
 566
 567         if (rxq->rb_stts)
 568                 dma_free_coherent(trans->dev,
 569                                   sizeof(struct iwl_rb_status),
 570                                   rxq->rb_stts, rxq->rb_stts_dma);
 571         else
 572                 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
 573         rxq->rb_stts_dma = 0;
 574         rxq->rb_stts = NULL;
 575 }
 576
 577 static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans,
 578                                 struct iwl_rx_mem_buffer *rxb)
 579 {
 580         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 581         struct iwl_rxq *rxq = &trans_pcie->rxq;
 582         struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
 583         unsigned long flags;
 584         bool page_stolen = false;
 585         int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
 586         u32 offset = 0;
 587
 588         if (WARN_ON(!rxb))
 589                 return;
 590
 591         dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE);
 592
 593         while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) {
 594                 struct iwl_rx_packet *pkt;
 595                 struct iwl_device_cmd *cmd;
 596                 u16 sequence;
 597                 bool reclaim;
 598                 int index, cmd_index, err, len;
 599                 struct iwl_rx_cmd_buffer rxcb = {
 600                         ._offset = offset,
 601                         ._rx_page_order = trans_pcie->rx_page_order,
 602                         ._page = rxb->page,
 603                         ._page_stolen = false,
 604                         .truesize = max_len,
 605                 };
 606
 607                 pkt = rxb_addr(&rxcb);
 608
 609                 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID))
 610                         break;
 611
 612                 IWL_DEBUG_RX(trans, "cmd at offset %d: %s (0x%.2x)\n",
 613                         rxcb._offset, get_cmd_string(trans_pcie, pkt->hdr.cmd),
 614                         pkt->hdr.cmd);
 615
 616                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 617                 len += sizeof(u32); /* account for status word */
 618                 trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len);
 619                 trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len);
 620
 621                 /* Reclaim a command buffer only if this packet is a response
 622                  *   to a (driver-originated) command.
 623                  * If the packet (e.g. Rx frame) originated from uCode,
 624                  *   there is no command buffer to reclaim.
 625                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 626                  *   but apparently a few don't get set; catch them here. */
 627                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME);
 628                 if (reclaim) {
 629                         int i;
 630
 631                         for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) {
 632                                 if (trans_pcie->no_reclaim_cmds[i] ==
 633                                                         pkt->hdr.cmd) {
 634                                         reclaim = false;
 635                                         break;
 636                                 }
 637                         }
 638                 }
 639
 640                 sequence = le16_to_cpu(pkt->hdr.sequence);
 641                 index = SEQ_TO_INDEX(sequence);
 642                 cmd_index = get_cmd_index(&txq->q, index);
 643
 644                 if (reclaim)
 645                         cmd = txq->entries[cmd_index].cmd;
 646                 else
 647                         cmd = NULL;
 648
 649                 err = iwl_op_mode_rx(trans->op_mode, &rxcb, cmd);
 650
 651                 if (reclaim) {
 652                         kfree(txq->entries[cmd_index].free_buf);
 653                         txq->entries[cmd_index].free_buf = NULL;
 654                 }
 655
 656                 /*
 657                  * After here, we should always check rxcb._page_stolen,
 658                  * if it is true then one of the handlers took the page.
 659                  */
 660
 661                 if (reclaim) {
 662                         /* Invoke any callbacks, transfer the buffer to caller,
 663                          * and fire off the (possibly) blocking
 664                          * iwl_trans_send_cmd()
 665                          * as we reclaim the driver command queue */
 666                         if (!rxcb._page_stolen)
 667                                 iwl_pcie_hcmd_complete(trans, &rxcb, err);
 668                         else
 669                                 IWL_WARN(trans, "Claim null rxb?\n");
 670                 }
 671
 672                 page_stolen |= rxcb._page_stolen;
 673                 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN);
 674         }
 675
 676         /* page was stolen from us -- free our reference */
 677         if (page_stolen) {
 678                 __free_pages(rxb->page, trans_pcie->rx_page_order);
 679                 rxb->page = NULL;
 680         }
 681
 682         /* Reuse the page if possible. For notification packets and
 683          * SKBs that fail to Rx correctly, add them back into the
 684          * rx_free list for reuse later. */
 685         spin_lock_irqsave(&rxq->lock, flags);
 686         if (rxb->page != NULL) {
 687                 rxb->page_dma =
 688                         dma_map_page(trans->dev, rxb->page, 0,
 689                                      PAGE_SIZE << trans_pcie->rx_page_order,
 690                                      DMA_FROM_DEVICE);
 691                 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
 692                         /*
 693                          * free the page(s) as well to not break
 694                          * the invariant that the items on the used
 695                          * list have no page(s)
 696                          */
 697                         __free_pages(rxb->page, trans_pcie->rx_page_order);
 698                         rxb->page = NULL;
 699                         list_add_tail(&rxb->list, &rxq->rx_used);
 700                 } else {
 701                         list_add_tail(&rxb->list, &rxq->rx_free);
 702                         rxq->free_count++;
 703                 }
 704         } else
 705                 list_add_tail(&rxb->list, &rxq->rx_used);
 706         spin_unlock_irqrestore(&rxq->lock, flags);
 707 }
 708
 709 /*
 710  * iwl_pcie_rx_handle - Main entry function for receiving responses from fw
 711  */
 712 static void iwl_pcie_rx_handle(struct iwl_trans *trans)
 713 {
 714         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 715         struct iwl_rxq *rxq = &trans_pcie->rxq;
 716         u32 r, i;
 717         u8 fill_rx = 0;
 718         u32 count = 8;
 719         int total_empty;
 720
 721         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 722          * buffer that the driver may process (last buffer filled by ucode). */
 723         r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
 724         i = rxq->read;
 725
 726         /* Rx interrupt, but nothing sent from uCode */
 727         if (i == r)
 728                 IWL_DEBUG_RX(trans, "HW = SW = %d\n", r);
 729
 730         /* calculate total frames need to be restock after handling RX */
 731         total_empty = r - rxq->write_actual;
 732         if (total_empty < 0)
 733                 total_empty += RX_QUEUE_SIZE;
 734
 735         if (total_empty > (RX_QUEUE_SIZE / 2))
 736                 fill_rx = 1;
 737
 738         while (i != r) {
 739                 struct iwl_rx_mem_buffer *rxb;
 740
 741                 rxb = rxq->queue[i];
 742                 rxq->queue[i] = NULL;
 743
 744                 IWL_DEBUG_RX(trans, "rxbuf: HW = %d, SW = %d (%p)\n",
 745                              r, i, rxb);
 746                 iwl_pcie_rx_handle_rb(trans, rxb);
 747
 748                 i = (i + 1) & RX_QUEUE_MASK;
 749                 /* If there are a lot of unused frames,
 750                  * restock the Rx queue so ucode wont assert. */
 751                 if (fill_rx) {
 752                         count++;
 753                         if (count >= 8) {
 754                                 rxq->read = i;
 755                                 iwl_pcie_rx_replenish_now(trans);
 756                                 count = 0;
 757                         }
 758                 }
 759         }
 760
 761         /* Backtrack one entry */
 762         rxq->read = i;
 763         if (fill_rx)
 764                 iwl_pcie_rx_replenish_now(trans);
 765         else
 766                 iwl_pcie_rxq_restock(trans);
 767 }
 768
 769 /*
 770  * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card
 771  */
 772 static void iwl_pcie_irq_handle_error(struct iwl_trans *trans)
 773 {
 774         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 775
 776         /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
 777         if (trans->cfg->internal_wimax_coex &&
 778             (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
 779                              APMS_CLK_VAL_MRB_FUNC_MODE) ||
 780              (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
 781                             APMG_PS_CTRL_VAL_RESET_REQ))) {
 782                 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
 783                 iwl_op_mode_wimax_active(trans->op_mode);
 784                 wake_up(&trans_pcie->wait_command_queue);
 785                 return;
 786         }
 787
 788         iwl_pcie_dump_csr(trans);
 789         iwl_pcie_dump_fh(trans, NULL);
 790
 791         set_bit(STATUS_FW_ERROR, &trans_pcie->status);
 792         clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
 793         wake_up(&trans_pcie->wait_command_queue);
 794
 795         local_bh_disable();
 796         iwl_op_mode_nic_error(trans->op_mode);
 797         local_bh_enable();
 798 }
 799
 800 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
 801 {
 802         struct iwl_trans *trans = dev_id;
 803         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 804         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
 805         u32 inta = 0;
 806         u32 handled = 0;
 807         unsigned long flags;
 808         u32 i;
 809 #ifdef CONFIG_IWLWIFI_DEBUG
 810         u32 inta_mask;
 811 #endif
 812
 813         lock_map_acquire(&trans->sync_cmd_lockdep_map);
 814
 815         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 816
 817         /* Ack/clear/reset pending uCode interrupts.
 818          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
 819          */
 820         /* There is a hardware bug in the interrupt mask function that some
 821          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
 822          * they are disabled in the CSR_INT_MASK register. Furthermore the
 823          * ICT interrupt handling mechanism has another bug that might cause
 824          * these unmasked interrupts fail to be detected. We workaround the
 825          * hardware bugs here by ACKing all the possible interrupts so that
 826          * interrupt coalescing can still be achieved.
 827          */
 828         iwl_write32(trans, CSR_INT,
 829                     trans_pcie->inta | ~trans_pcie->inta_mask);
 830
 831         inta = trans_pcie->inta;
 832
 833 #ifdef CONFIG_IWLWIFI_DEBUG
 834         if (iwl_have_debug_level(IWL_DL_ISR)) {
 835                 /* just for debug */
 836                 inta_mask = iwl_read32(trans, CSR_INT_MASK);
 837                 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
 838                               inta, inta_mask);
 839         }
 840 #endif
 841
 842         /* saved interrupt in inta variable now we can reset trans_pcie->inta */
 843         trans_pcie->inta = 0;
 844
 845         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 846
 847         /* Now service all interrupt bits discovered above. */
 848         if (inta & CSR_INT_BIT_HW_ERR) {
 849                 IWL_ERR(trans, "Hardware error detected.  Restarting.\n");
 850
 851                 /* Tell the device to stop sending interrupts */
 852                 iwl_disable_interrupts(trans);
 853
 854                 isr_stats->hw++;
 855                 iwl_pcie_irq_handle_error(trans);
 856
 857                 handled |= CSR_INT_BIT_HW_ERR;
 858
 859                 goto out;
 860         }
 861
 862 #ifdef CONFIG_IWLWIFI_DEBUG
 863         if (iwl_have_debug_level(IWL_DL_ISR)) {
 864                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
 865                 if (inta & CSR_INT_BIT_SCD) {
 866                         IWL_DEBUG_ISR(trans, "Scheduler finished to transmit "
 867                                       "the frame/frames.\n");
 868                         isr_stats->sch++;
 869                 }
 870
 871                 /* Alive notification via Rx interrupt will do the real work */
 872                 if (inta & CSR_INT_BIT_ALIVE) {
 873                         IWL_DEBUG_ISR(trans, "Alive interrupt\n");
 874                         isr_stats->alive++;
 875                 }
 876         }
 877 #endif
 878         /* Safely ignore these bits for debug checks below */
 879         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
 880
 881         /* HW RF KILL switch toggled */
 882         if (inta & CSR_INT_BIT_RF_KILL) {
 883                 bool hw_rfkill;
 884
 885                 hw_rfkill = iwl_is_rfkill_set(trans);
 886                 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
 887                          hw_rfkill ? "disable radio" : "enable radio");
 888
 889                 isr_stats->rfkill++;
 890
 891                 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 892                 if (hw_rfkill) {
 893                         set_bit(STATUS_RFKILL, &trans_pcie->status);
 894                         if (test_and_clear_bit(STATUS_HCMD_ACTIVE,
 895                                                &trans_pcie->status))
 896                                 IWL_DEBUG_RF_KILL(trans,
 897                                                   "Rfkill while SYNC HCMD in flight\n");
 898                         wake_up(&trans_pcie->wait_command_queue);
 899                 } else {
 900                         clear_bit(STATUS_RFKILL, &trans_pcie->status);
 901                 }
 902
 903                 handled |= CSR_INT_BIT_RF_KILL;
 904         }
 905
 906         /* Chip got too hot and stopped itself */
 907         if (inta & CSR_INT_BIT_CT_KILL) {
 908                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
 909                 isr_stats->ctkill++;
 910                 handled |= CSR_INT_BIT_CT_KILL;
 911         }
 912
 913         /* Error detected by uCode */
 914         if (inta & CSR_INT_BIT_SW_ERR) {
 915                 IWL_ERR(trans, "Microcode SW error detected. "
 916                         " Restarting 0x%X.\n", inta);
 917                 isr_stats->sw++;
 918                 iwl_pcie_irq_handle_error(trans);
 919                 handled |= CSR_INT_BIT_SW_ERR;
 920         }
 921
 922         /* uCode wakes up after power-down sleep */
 923         if (inta & CSR_INT_BIT_WAKEUP) {
 924                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
 925                 iwl_pcie_rxq_inc_wr_ptr(trans, &trans_pcie->rxq);
 926                 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++)
 927                         iwl_pcie_txq_inc_wr_ptr(trans, &trans_pcie->txq[i]);
 928
 929                 isr_stats->wakeup++;
 930
 931                 handled |= CSR_INT_BIT_WAKEUP;
 932         }
 933
 934         /* All uCode command responses, including Tx command responses,
 935          * Rx "responses" (frame-received notification), and other
 936          * notifications from uCode come through here*/
 937         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
 938                     CSR_INT_BIT_RX_PERIODIC)) {
 939                 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
 940                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
 941                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
 942                         iwl_write32(trans, CSR_FH_INT_STATUS,
 943                                         CSR_FH_INT_RX_MASK);
 944                 }
 945                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
 946                         handled |= CSR_INT_BIT_RX_PERIODIC;
 947                         iwl_write32(trans,
 948                                 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
 949                 }
 950                 /* Sending RX interrupt require many steps to be done in the
 951                  * the device:
 952                  * 1- write interrupt to current index in ICT table.
 953                  * 2- dma RX frame.
 954                  * 3- update RX shared data to indicate last write index.
 955                  * 4- send interrupt.
 956                  * This could lead to RX race, driver could receive RX interrupt
 957                  * but the shared data changes does not reflect this;
 958                  * periodic interrupt will detect any dangling Rx activity.
 959                  */
 960
 961                 /* Disable periodic interrupt; we use it as just a one-shot. */
 962                 iwl_write8(trans, CSR_INT_PERIODIC_REG,
 963                             CSR_INT_PERIODIC_DIS);
 964
 965                 iwl_pcie_rx_handle(trans);
 966
 967                 /*
 968                  * Enable periodic interrupt in 8 msec only if we received
 969                  * real RX interrupt (instead of just periodic int), to catch
 970                  * any dangling Rx interrupt.  If it was just the periodic
 971                  * interrupt, there was no dangling Rx activity, and no need
 972                  * to extend the periodic interrupt; one-shot is enough.
 973                  */
 974                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
 975                         iwl_write8(trans, CSR_INT_PERIODIC_REG,
 976                                    CSR_INT_PERIODIC_ENA);
 977
 978                 isr_stats->rx++;
 979         }
 980
 981         /* This "Tx" DMA channel is used only for loading uCode */
 982         if (inta & CSR_INT_BIT_FH_TX) {
 983                 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
 984                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
 985                 isr_stats->tx++;
 986                 handled |= CSR_INT_BIT_FH_TX;
 987                 /* Wake up uCode load routine, now that load is complete */
 988                 trans_pcie->ucode_write_complete = true;
 989                 wake_up(&trans_pcie->ucode_write_waitq);
 990         }
 991
 992         if (inta & ~handled) {
 993                 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
 994                 isr_stats->unhandled++;
 995         }
 996
 997         if (inta & ~(trans_pcie->inta_mask)) {
 998                 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
 999                          inta & ~trans_pcie->inta_mask);
1000         }
1001
1002         /* Re-enable all interrupts */
1003         /* only Re-enable if disabled by irq */
1004         if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status))
1005                 iwl_enable_interrupts(trans);
1006         /* Re-enable RF_KILL if it occurred */
1007         else if (handled & CSR_INT_BIT_RF_KILL)
1008                 iwl_enable_rfkill_int(trans);
1009
1010 out:
1011         lock_map_release(&trans->sync_cmd_lockdep_map);
1012         return IRQ_HANDLED;
1013 }
1014
1015 /******************************************************************************
1016  *
1017  * ICT functions
1018  *
1019  ******************************************************************************/
1020
1021 /* a device (PCI-E) page is 4096 bytes long */
1022 #define ICT_SHIFT       12
1023 #define ICT_SIZE        (1 << ICT_SHIFT)
1024 #define ICT_COUNT       (ICT_SIZE / sizeof(u32))
1025
1026 /* Free dram table */
1027 void iwl_pcie_free_ict(struct iwl_trans *trans)
1028 {
1029         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1030
1031         if (trans_pcie->ict_tbl) {
1032                 dma_free_coherent(trans->dev, ICT_SIZE,
1033                                   trans_pcie->ict_tbl,
1034                                   trans_pcie->ict_tbl_dma);
1035                 trans_pcie->ict_tbl = NULL;
1036                 trans_pcie->ict_tbl_dma = 0;
1037         }
1038 }
1039
1040 /*
1041  * allocate dram shared table, it is an aligned memory
1042  * block of ICT_SIZE.
1043  * also reset all data related to ICT table interrupt.
1044  */
1045 int iwl_pcie_alloc_ict(struct iwl_trans *trans)
1046 {
1047         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1048
1049         trans_pcie->ict_tbl =
1050                 dma_alloc_coherent(trans->dev, ICT_SIZE,
1051                                    &trans_pcie->ict_tbl_dma,
1052                                    GFP_KERNEL);
1053         if (!trans_pcie->ict_tbl)
1054                 return -ENOMEM;
1055
1056         /* just an API sanity check ... it is guaranteed to be aligned */
1057         if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
1058                 iwl_pcie_free_ict(trans);
1059                 return -EINVAL;
1060         }
1061
1062         IWL_DEBUG_ISR(trans, "ict dma addr %Lx\n",
1063                       (unsigned long long)trans_pcie->ict_tbl_dma);
1064
1065         IWL_DEBUG_ISR(trans, "ict vir addr %p\n", trans_pcie->ict_tbl);
1066
1067         /* reset table and index to all 0 */
1068         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1069         trans_pcie->ict_index = 0;
1070
1071         /* add periodic RX interrupt */
1072         trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
1073         return 0;
1074 }
1075
1076 /* Device is going up inform it about using ICT interrupt table,
1077  * also we need to tell the driver to start using ICT interrupt.
1078  */
1079 void iwl_pcie_reset_ict(struct iwl_trans *trans)
1080 {
1081         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1082         u32 val;
1083         unsigned long flags;
1084
1085         if (!trans_pcie->ict_tbl)
1086                 return;
1087
1088         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1089         iwl_disable_interrupts(trans);
1090
1091         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1092
1093         val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
1094
1095         val |= CSR_DRAM_INT_TBL_ENABLE;
1096         val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1097
1098         IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
1099
1100         iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
1101         trans_pcie->use_ict = true;
1102         trans_pcie->ict_index = 0;
1103         iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
1104         iwl_enable_interrupts(trans);
1105         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1106 }
1107
1108 /* Device is going down disable ict interrupt usage */
1109 void iwl_pcie_disable_ict(struct iwl_trans *trans)
1110 {
1111         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1112         unsigned long flags;
1113
1114         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1115         trans_pcie->use_ict = false;
1116         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1117 }
1118
1119 /* legacy (non-ICT) ISR. Assumes that trans_pcie->irq_lock is held */
1120 static irqreturn_t iwl_pcie_isr(int irq, void *data)
1121 {
1122         struct iwl_trans *trans = data;
1123         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1124         u32 inta, inta_mask;
1125 #ifdef CONFIG_IWLWIFI_DEBUG
1126         u32 inta_fh;
1127 #endif
1128
1129         lockdep_assert_held(&trans_pcie->irq_lock);
1130
1131         trace_iwlwifi_dev_irq(trans->dev);
1132
1133         /* Disable (but don't clear!) interrupts here to avoid
1134          *    back-to-back ISRs and sporadic interrupts from our NIC.
1135          * If we have something to service, the irq thread will re-enable ints.
1136          * If we *don't* have something, we'll re-enable before leaving here. */
1137         inta_mask = iwl_read32(trans, CSR_INT_MASK);
1138         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1139
1140         /* Discover which interrupts are active/pending */
1141         inta = iwl_read32(trans, CSR_INT);
1142
1143         if (inta & (~inta_mask)) {
1144                 IWL_DEBUG_ISR(trans,
1145                               "We got a masked interrupt (0x%08x)...Ack and ignore\n",
1146                               inta & (~inta_mask));
1147                 iwl_write32(trans, CSR_INT, inta & (~inta_mask));
1148                 inta &= inta_mask;
1149         }
1150
1151         /* Ignore interrupt if there's nothing in NIC to service.
1152          * This may be due to IRQ shared with another device,
1153          * or due to sporadic interrupts thrown from our NIC. */
1154         if (!inta) {
1155                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1156                 goto none;
1157         }
1158
1159         if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1160                 /* Hardware disappeared. It might have already raised
1161                  * an interrupt */
1162                 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1163                 return IRQ_HANDLED;
1164         }
1165
1166 #ifdef CONFIG_IWLWIFI_DEBUG
1167         if (iwl_have_debug_level(IWL_DL_ISR)) {
1168                 inta_fh = iwl_read32(trans, CSR_FH_INT_STATUS);
1169                 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, "
1170                               "fh 0x%08x\n", inta, inta_mask, inta_fh);
1171         }
1172 #endif
1173
1174         trans_pcie->inta |= inta;
1175         /* the thread will service interrupts and re-enable them */
1176         if (likely(inta))
1177                 return IRQ_WAKE_THREAD;
1178         else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1179                  !trans_pcie->inta)
1180                 iwl_enable_interrupts(trans);
1181         return IRQ_HANDLED;
1182
1183 none:
1184         /* re-enable interrupts here since we don't have anything to service. */
1185         /* only Re-enable if disabled by irq  and no schedules tasklet. */
1186         if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1187             !trans_pcie->inta)
1188                 iwl_enable_interrupts(trans);
1189
1190         return IRQ_NONE;
1191 }
1192
1193 /* interrupt handler using ict table, with this interrupt driver will
1194  * stop using INTA register to get device's interrupt, reading this register
1195  * is expensive, device will write interrupts in ICT dram table, increment
1196  * index then will fire interrupt to driver, driver will OR all ICT table
1197  * entries from current index up to table entry with 0 value. the result is
1198  * the interrupt we need to service, driver will set the entries back to 0 and
1199  * set index.
1200  */
1201 irqreturn_t iwl_pcie_isr_ict(int irq, void *data)
1202 {
1203         struct iwl_trans *trans = data;
1204         struct iwl_trans_pcie *trans_pcie;
1205         u32 inta, inta_mask;
1206         u32 val = 0;
1207         u32 read;
1208         unsigned long flags;
1209
1210         if (!trans)
1211                 return IRQ_NONE;
1212
1213         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1214
1215         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1216
1217         /* dram interrupt table not set yet,
1218          * use legacy interrupt.
1219          */
1220         if (unlikely(!trans_pcie->use_ict)) {
1221                 irqreturn_t ret = iwl_pcie_isr(irq, data);
1222                 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1223                 return ret;
1224         }
1225
1226         trace_iwlwifi_dev_irq(trans->dev);
1227
1228         /* Disable (but don't clear!) interrupts here to avoid
1229          * back-to-back ISRs and sporadic interrupts from our NIC.
1230          * If we have something to service, the tasklet will re-enable ints.
1231          * If we *don't* have something, we'll re-enable before leaving here.
1232          */
1233         inta_mask = iwl_read32(trans, CSR_INT_MASK);
1234         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1235
1236         /* Ignore interrupt if there's nothing in NIC to service.
1237          * This may be due to IRQ shared with another device,
1238          * or due to sporadic interrupts thrown from our NIC. */
1239         read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1240         trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
1241         if (!read) {
1242                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1243                 goto none;
1244         }
1245
1246         /*
1247          * Collect all entries up to the first 0, starting from ict_index;
1248          * note we already read at ict_index.
1249          */
1250         do {
1251                 val |= read;
1252                 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1253                                 trans_pcie->ict_index, read);
1254                 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1255                 trans_pcie->ict_index =
1256                         iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
1257
1258                 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1259                 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
1260                                            read);
1261         } while (read);
1262
1263         /* We should not get this value, just ignore it. */
1264         if (val == 0xffffffff)
1265                 val = 0;
1266
1267         /*
1268          * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1269          * (bit 15 before shifting it to 31) to clear when using interrupt
1270          * coalescing. fortunately, bits 18 and 19 stay set when this happens
1271          * so we use them to decide on the real state of the Rx bit.
1272          * In order words, bit 15 is set if bit 18 or bit 19 are set.
1273          */
1274         if (val & 0xC0000)
1275                 val |= 0x8000;
1276
1277         inta = (0xff & val) | ((0xff00 & val) << 16);
1278         IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1279                       inta, inta_mask, val);
1280
1281         inta &= trans_pcie->inta_mask;
1282         trans_pcie->inta |= inta;
1283
1284         /* iwl_pcie_tasklet() will service interrupts and re-enable them */
1285         if (likely(inta)) {
1286                 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1287                 return IRQ_WAKE_THREAD;
1288         } else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1289                  !trans_pcie->inta) {
1290                 /* Allow interrupt if was disabled by this handler and
1291                  * no tasklet was schedules, We should not enable interrupt,
1292                  * tasklet will enable it.
1293                  */
1294                 iwl_enable_interrupts(trans);
1295         }
1296
1297         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1298         return IRQ_HANDLED;
1299
1300  none:
1301         /* re-enable interrupts here since we don't have anything to service.
1302          * only Re-enable if disabled by irq.
1303          */
1304         if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1305             !trans_pcie->inta)
1306                 iwl_enable_interrupts(trans);
1307
1308         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1309         return IRQ_NONE;
1310 }