1 /******************************************************************************
3 * Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
29 #include <linux/sched.h>
30 #include <linux/wait.h>
31 #include <linux/gfp.h>
36 #include "iwl-op-mode.h"
38 /******************************************************************************
42 ******************************************************************************/
45 * Rx theory of operation
47 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
48 * each of which point to Receive Buffers to be filled by the NIC. These get
49 * used not only for Rx frames, but for any command response or notification
50 * from the NIC. The driver and NIC manage the Rx buffers by means
51 * of indexes into the circular buffer.
54 * The host/firmware share two index registers for managing the Rx buffers.
56 * The READ index maps to the first position that the firmware may be writing
57 * to -- the driver can read up to (but not including) this position and get
59 * The READ index is managed by the firmware once the card is enabled.
61 * The WRITE index maps to the last position the driver has read from -- the
62 * position preceding WRITE is the last slot the firmware can place a packet.
64 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
67 * During initialization, the host sets up the READ queue position to the first
68 * INDEX position, and WRITE to the last (READ - 1 wrapped)
70 * When the firmware places a packet in a buffer, it will advance the READ index
71 * and fire the RX interrupt. The driver can then query the READ index and
72 * process as many packets as possible, moving the WRITE index forward as it
73 * resets the Rx queue buffers with new memory.
75 * The management in the driver is as follows:
76 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
77 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
78 * to replenish the iwl->rxq->rx_free.
79 * + In iwl_pcie_rx_replenish (scheduled) if 'processed' != 'read' then the
80 * iwl->rxq is replenished and the READ INDEX is updated (updating the
81 * 'processed' and 'read' driver indexes as well)
82 * + A received packet is processed and handed to the kernel network stack,
83 * detached from the iwl->rxq. The driver 'processed' index is updated.
84 * + The Host/Firmware iwl->rxq is replenished at irq thread time from the
85 * rx_free list. If there are no allocated buffers in iwl->rxq->rx_free,
86 * the READ INDEX is not incremented and iwl->status(RX_STALLED) is set.
87 * If there were enough free buffers and RX_STALLED is set it is cleared.
92 * iwl_rxq_alloc() Allocates rx_free
93 * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls
94 * iwl_pcie_rxq_restock
95 * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx
96 * queue, updates firmware pointers, and updates
97 * the WRITE index. If insufficient rx_free buffers
98 * are available, schedules iwl_pcie_rx_replenish
100 * -- enable interrupts --
101 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
102 * READ INDEX, detaching the SKB from the pool.
103 * Moves the packet buffer from queue to rx_used.
104 * Calls iwl_pcie_rxq_restock to refill any empty
111 * iwl_rxq_space - Return number of free slots available in queue.
113 static int iwl_rxq_space(const struct iwl_rxq *q)
115 int s = q->read - q->write;
118 /* keep some buffer to not confuse full and empty queue */
126 * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
128 static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr)
130 return cpu_to_le32((u32)(dma_addr >> 8));
134 * iwl_pcie_rx_stop - stops the Rx DMA
136 int iwl_pcie_rx_stop(struct iwl_trans *trans)
138 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
139 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
140 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
144 * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue
146 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_rxq *q)
151 spin_lock_irqsave(&q->lock, flags);
153 if (q->need_update == 0)
156 if (trans->cfg->base_params->shadow_reg_enable) {
157 /* shadow register enabled */
158 /* Device expects a multiple of 8 */
159 q->write_actual = (q->write & ~0x7);
160 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, q->write_actual);
162 struct iwl_trans_pcie *trans_pcie =
163 IWL_TRANS_GET_PCIE_TRANS(trans);
165 /* If power-saving is in use, make sure device is awake */
166 if (test_bit(STATUS_TPOWER_PMI, &trans_pcie->status)) {
167 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
169 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
170 IWL_DEBUG_INFO(trans,
171 "Rx queue requesting wakeup,"
172 " GP1 = 0x%x\n", reg);
173 iwl_set_bit(trans, CSR_GP_CNTRL,
174 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
178 q->write_actual = (q->write & ~0x7);
179 iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
182 /* Else device is assumed to be awake */
184 /* Device expects a multiple of 8 */
185 q->write_actual = (q->write & ~0x7);
186 iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
193 spin_unlock_irqrestore(&q->lock, flags);
197 * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool
199 * If there are slots in the RX queue that need to be restocked,
200 * and we have free pre-allocated buffers, fill the ranks as much
201 * as we can, pulling from rx_free.
203 * This moves the 'write' index forward to catch up with 'processed', and
204 * also updates the memory address in the firmware to reference the new
207 static void iwl_pcie_rxq_restock(struct iwl_trans *trans)
209 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
210 struct iwl_rxq *rxq = &trans_pcie->rxq;
211 struct iwl_rx_mem_buffer *rxb;
215 * If the device isn't enabled - not need to try to add buffers...
216 * This can happen when we stop the device and still have an interrupt
217 * pending. We stop the APM before we sync the interrupts because we
218 * have to (see comment there). On the other hand, since the APM is
219 * stopped, we cannot access the HW (in particular not prph).
220 * So don't try to restock if the APM has been already stopped.
222 if (!test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status))
225 spin_lock_irqsave(&rxq->lock, flags);
226 while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) {
227 /* The overwritten rxb must be a used one */
228 rxb = rxq->queue[rxq->write];
229 BUG_ON(rxb && rxb->page);
231 /* Get next free Rx buffer, remove from free list */
232 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
234 list_del(&rxb->list);
236 /* Point to Rx buffer via next RBD in circular buffer */
237 rxq->bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma);
238 rxq->queue[rxq->write] = rxb;
239 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
242 spin_unlock_irqrestore(&rxq->lock, flags);
243 /* If the pre-allocated buffer pool is dropping low, schedule to
245 if (rxq->free_count <= RX_LOW_WATERMARK)
246 schedule_work(&trans_pcie->rx_replenish);
248 /* If we've added more space for the firmware to place data, tell it.
249 * Increment device's write pointer in multiples of 8. */
250 if (rxq->write_actual != (rxq->write & ~0x7)) {
251 spin_lock_irqsave(&rxq->lock, flags);
252 rxq->need_update = 1;
253 spin_unlock_irqrestore(&rxq->lock, flags);
254 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
259 * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD
261 * A used RBD is an Rx buffer that has been given to the stack. To use it again
262 * a page must be allocated and the RBD must point to the page. This function
263 * doesn't change the HW pointer but handles the list of pages that is used by
264 * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly
267 static void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority)
269 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
270 struct iwl_rxq *rxq = &trans_pcie->rxq;
271 struct iwl_rx_mem_buffer *rxb;
274 gfp_t gfp_mask = priority;
277 spin_lock_irqsave(&rxq->lock, flags);
278 if (list_empty(&rxq->rx_used)) {
279 spin_unlock_irqrestore(&rxq->lock, flags);
282 spin_unlock_irqrestore(&rxq->lock, flags);
284 if (rxq->free_count > RX_LOW_WATERMARK)
285 gfp_mask |= __GFP_NOWARN;
287 if (trans_pcie->rx_page_order > 0)
288 gfp_mask |= __GFP_COMP;
290 /* Alloc a new receive buffer */
291 page = alloc_pages(gfp_mask, trans_pcie->rx_page_order);
294 IWL_DEBUG_INFO(trans, "alloc_pages failed, "
296 trans_pcie->rx_page_order);
298 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
300 IWL_CRIT(trans, "Failed to alloc_pages with %s."
301 "Only %u free buffers remaining.\n",
302 priority == GFP_ATOMIC ?
303 "GFP_ATOMIC" : "GFP_KERNEL",
305 /* We don't reschedule replenish work here -- we will
306 * call the restock method and if it still needs
307 * more buffers it will schedule replenish */
311 spin_lock_irqsave(&rxq->lock, flags);
313 if (list_empty(&rxq->rx_used)) {
314 spin_unlock_irqrestore(&rxq->lock, flags);
315 __free_pages(page, trans_pcie->rx_page_order);
318 rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer,
320 list_del(&rxb->list);
321 spin_unlock_irqrestore(&rxq->lock, flags);
325 /* Get physical address of the RB */
327 dma_map_page(trans->dev, page, 0,
328 PAGE_SIZE << trans_pcie->rx_page_order,
330 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
332 spin_lock_irqsave(&rxq->lock, flags);
333 list_add(&rxb->list, &rxq->rx_used);
334 spin_unlock_irqrestore(&rxq->lock, flags);
335 __free_pages(page, trans_pcie->rx_page_order);
338 /* dma address must be no more than 36 bits */
339 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
340 /* and also 256 byte aligned! */
341 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
343 spin_lock_irqsave(&rxq->lock, flags);
345 list_add_tail(&rxb->list, &rxq->rx_free);
348 spin_unlock_irqrestore(&rxq->lock, flags);
352 static void iwl_pcie_rxq_free_rbs(struct iwl_trans *trans)
354 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
355 struct iwl_rxq *rxq = &trans_pcie->rxq;
358 /* Fill the rx_used queue with _all_ of the Rx buffers */
359 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
360 /* In the reset function, these buffers may have been allocated
361 * to an SKB, so we need to unmap and free potential storage */
362 if (rxq->pool[i].page != NULL) {
363 dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
364 PAGE_SIZE << trans_pcie->rx_page_order,
366 __free_pages(rxq->pool[i].page,
367 trans_pcie->rx_page_order);
368 rxq->pool[i].page = NULL;
370 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
375 * iwl_pcie_rx_replenish - Move all used buffers from rx_used to rx_free
377 * When moving to rx_free an page is allocated for the slot.
379 * Also restock the Rx queue via iwl_pcie_rxq_restock.
380 * This is called as a scheduled work item (except for during initialization)
382 static void iwl_pcie_rx_replenish(struct iwl_trans *trans)
384 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
387 iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL);
389 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
390 iwl_pcie_rxq_restock(trans);
391 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
394 static void iwl_pcie_rx_replenish_now(struct iwl_trans *trans)
396 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC);
398 iwl_pcie_rxq_restock(trans);
401 static void iwl_pcie_rx_replenish_work(struct work_struct *data)
403 struct iwl_trans_pcie *trans_pcie =
404 container_of(data, struct iwl_trans_pcie, rx_replenish);
406 iwl_pcie_rx_replenish(trans_pcie->trans);
409 static int iwl_pcie_rx_alloc(struct iwl_trans *trans)
411 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
412 struct iwl_rxq *rxq = &trans_pcie->rxq;
413 struct device *dev = trans->dev;
415 memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
417 spin_lock_init(&rxq->lock);
419 if (WARN_ON(rxq->bd || rxq->rb_stts))
422 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
423 rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
424 &rxq->bd_dma, GFP_KERNEL);
428 /*Allocate the driver's pointer to receive buffer status */
429 rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
430 &rxq->rb_stts_dma, GFP_KERNEL);
437 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
438 rxq->bd, rxq->bd_dma);
445 static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
447 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
449 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
451 if (trans_pcie->rx_buf_size_8k)
452 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
454 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
457 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
458 /* reset and flush pointers */
459 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);
460 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);
461 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RDPTR, 0);
463 /* Reset driver's Rx queue write index */
464 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
466 /* Tell device where to find RBD circular buffer in DRAM */
467 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
468 (u32)(rxq->bd_dma >> 8));
470 /* Tell device where in DRAM to update its Rx status */
471 iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
472 rxq->rb_stts_dma >> 4);
475 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
476 * the credit mechanism in 5000 HW RX FIFO
477 * Direct rx interrupts to hosts
478 * Rx buffer size 4 or 8k
482 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
483 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
484 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
485 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
487 (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
488 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
490 /* Set interrupt coalescing timer to default (2048 usecs) */
491 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
494 int iwl_pcie_rx_init(struct iwl_trans *trans)
496 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
497 struct iwl_rxq *rxq = &trans_pcie->rxq;
502 err = iwl_pcie_rx_alloc(trans);
507 spin_lock_irqsave(&rxq->lock, flags);
508 INIT_LIST_HEAD(&rxq->rx_free);
509 INIT_LIST_HEAD(&rxq->rx_used);
511 INIT_WORK(&trans_pcie->rx_replenish,
512 iwl_pcie_rx_replenish_work);
514 iwl_pcie_rxq_free_rbs(trans);
516 for (i = 0; i < RX_QUEUE_SIZE; i++)
517 rxq->queue[i] = NULL;
519 /* Set us so that we have processed and used all buffers, but have
520 * not restocked the Rx queue with fresh buffers */
521 rxq->read = rxq->write = 0;
522 rxq->write_actual = 0;
524 memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
525 spin_unlock_irqrestore(&rxq->lock, flags);
527 iwl_pcie_rx_replenish(trans);
529 iwl_pcie_rx_hw_init(trans, rxq);
531 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
532 rxq->need_update = 1;
533 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
534 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
539 void iwl_pcie_rx_free(struct iwl_trans *trans)
541 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
542 struct iwl_rxq *rxq = &trans_pcie->rxq;
545 /*if rxq->bd is NULL, it means that nothing has been allocated,
548 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
552 cancel_work_sync(&trans_pcie->rx_replenish);
554 spin_lock_irqsave(&rxq->lock, flags);
555 iwl_pcie_rxq_free_rbs(trans);
556 spin_unlock_irqrestore(&rxq->lock, flags);
558 dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
559 rxq->bd, rxq->bd_dma);
564 dma_free_coherent(trans->dev,
565 sizeof(struct iwl_rb_status),
566 rxq->rb_stts, rxq->rb_stts_dma);
568 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
569 rxq->rb_stts_dma = 0;
573 static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans,
574 struct iwl_rx_mem_buffer *rxb)
576 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
577 struct iwl_rxq *rxq = &trans_pcie->rxq;
578 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
580 bool page_stolen = false;
581 int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
587 dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE);
589 while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) {
590 struct iwl_rx_packet *pkt;
591 struct iwl_device_cmd *cmd;
594 int index, cmd_index, err, len;
595 struct iwl_rx_cmd_buffer rxcb = {
597 ._rx_page_order = trans_pcie->rx_page_order,
599 ._page_stolen = false,
603 pkt = rxb_addr(&rxcb);
605 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID))
608 IWL_DEBUG_RX(trans, "cmd at offset %d: %s (0x%.2x)\n",
609 rxcb._offset, get_cmd_string(trans_pcie, pkt->hdr.cmd),
612 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
613 len += sizeof(u32); /* account for status word */
614 trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len);
615 trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len);
617 /* Reclaim a command buffer only if this packet is a response
618 * to a (driver-originated) command.
619 * If the packet (e.g. Rx frame) originated from uCode,
620 * there is no command buffer to reclaim.
621 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
622 * but apparently a few don't get set; catch them here. */
623 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME);
627 for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) {
628 if (trans_pcie->no_reclaim_cmds[i] ==
636 sequence = le16_to_cpu(pkt->hdr.sequence);
637 index = SEQ_TO_INDEX(sequence);
638 cmd_index = get_cmd_index(&txq->q, index);
641 cmd = txq->entries[cmd_index].cmd;
645 err = iwl_op_mode_rx(trans->op_mode, &rxcb, cmd);
648 kfree(txq->entries[cmd_index].free_buf);
649 txq->entries[cmd_index].free_buf = NULL;
653 * After here, we should always check rxcb._page_stolen,
654 * if it is true then one of the handlers took the page.
658 /* Invoke any callbacks, transfer the buffer to caller,
659 * and fire off the (possibly) blocking
660 * iwl_trans_send_cmd()
661 * as we reclaim the driver command queue */
662 if (!rxcb._page_stolen)
663 iwl_pcie_hcmd_complete(trans, &rxcb, err);
665 IWL_WARN(trans, "Claim null rxb?\n");
668 page_stolen |= rxcb._page_stolen;
669 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN);
672 /* page was stolen from us -- free our reference */
674 __free_pages(rxb->page, trans_pcie->rx_page_order);
678 /* Reuse the page if possible. For notification packets and
679 * SKBs that fail to Rx correctly, add them back into the
680 * rx_free list for reuse later. */
681 spin_lock_irqsave(&rxq->lock, flags);
682 if (rxb->page != NULL) {
684 dma_map_page(trans->dev, rxb->page, 0,
685 PAGE_SIZE << trans_pcie->rx_page_order,
687 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
689 * free the page(s) as well to not break
690 * the invariant that the items on the used
691 * list have no page(s)
693 __free_pages(rxb->page, trans_pcie->rx_page_order);
695 list_add_tail(&rxb->list, &rxq->rx_used);
697 list_add_tail(&rxb->list, &rxq->rx_free);
701 list_add_tail(&rxb->list, &rxq->rx_used);
702 spin_unlock_irqrestore(&rxq->lock, flags);
706 * iwl_pcie_rx_handle - Main entry function for receiving responses from fw
708 static void iwl_pcie_rx_handle(struct iwl_trans *trans)
710 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
711 struct iwl_rxq *rxq = &trans_pcie->rxq;
717 /* uCode's read index (stored in shared DRAM) indicates the last Rx
718 * buffer that the driver may process (last buffer filled by ucode). */
719 r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
722 /* Rx interrupt, but nothing sent from uCode */
724 IWL_DEBUG_RX(trans, "HW = SW = %d\n", r);
726 /* calculate total frames need to be restock after handling RX */
727 total_empty = r - rxq->write_actual;
729 total_empty += RX_QUEUE_SIZE;
731 if (total_empty > (RX_QUEUE_SIZE / 2))
735 struct iwl_rx_mem_buffer *rxb;
738 rxq->queue[i] = NULL;
740 IWL_DEBUG_RX(trans, "rxbuf: HW = %d, SW = %d (%p)\n",
742 iwl_pcie_rx_handle_rb(trans, rxb);
744 i = (i + 1) & RX_QUEUE_MASK;
745 /* If there are a lot of unused frames,
746 * restock the Rx queue so ucode wont assert. */
751 iwl_pcie_rx_replenish_now(trans);
757 /* Backtrack one entry */
760 iwl_pcie_rx_replenish_now(trans);
762 iwl_pcie_rxq_restock(trans);
766 * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card
768 static void iwl_pcie_irq_handle_error(struct iwl_trans *trans)
770 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
772 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
773 if (trans->cfg->internal_wimax_coex &&
774 (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
775 APMS_CLK_VAL_MRB_FUNC_MODE) ||
776 (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
777 APMG_PS_CTRL_VAL_RESET_REQ))) {
778 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
779 iwl_op_mode_wimax_active(trans->op_mode);
780 wake_up(&trans_pcie->wait_command_queue);
784 iwl_pcie_dump_csr(trans);
785 iwl_pcie_dump_fh(trans, NULL);
787 set_bit(STATUS_FW_ERROR, &trans_pcie->status);
788 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
789 wake_up(&trans_pcie->wait_command_queue);
792 iwl_op_mode_nic_error(trans->op_mode);
796 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
798 struct iwl_trans *trans = dev_id;
799 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
800 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
806 lock_map_acquire(&trans->sync_cmd_lockdep_map);
808 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
810 /* Ack/clear/reset pending uCode interrupts.
811 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
813 /* There is a hardware bug in the interrupt mask function that some
814 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
815 * they are disabled in the CSR_INT_MASK register. Furthermore the
816 * ICT interrupt handling mechanism has another bug that might cause
817 * these unmasked interrupts fail to be detected. We workaround the
818 * hardware bugs here by ACKing all the possible interrupts so that
819 * interrupt coalescing can still be achieved.
821 iwl_write32(trans, CSR_INT,
822 trans_pcie->inta | ~trans_pcie->inta_mask);
824 inta = trans_pcie->inta;
826 if (iwl_have_debug_level(IWL_DL_ISR))
827 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
828 inta, iwl_read32(trans, CSR_INT_MASK));
830 /* saved interrupt in inta variable now we can reset trans_pcie->inta */
831 trans_pcie->inta = 0;
833 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
835 /* Now service all interrupt bits discovered above. */
836 if (inta & CSR_INT_BIT_HW_ERR) {
837 IWL_ERR(trans, "Hardware error detected. Restarting.\n");
839 /* Tell the device to stop sending interrupts */
840 iwl_disable_interrupts(trans);
843 iwl_pcie_irq_handle_error(trans);
845 handled |= CSR_INT_BIT_HW_ERR;
850 if (iwl_have_debug_level(IWL_DL_ISR)) {
851 /* NIC fires this, but we don't use it, redundant with WAKEUP */
852 if (inta & CSR_INT_BIT_SCD) {
854 "Scheduler finished to transmit the frame/frames.\n");
858 /* Alive notification via Rx interrupt will do the real work */
859 if (inta & CSR_INT_BIT_ALIVE) {
860 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
865 /* Safely ignore these bits for debug checks below */
866 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
868 /* HW RF KILL switch toggled */
869 if (inta & CSR_INT_BIT_RF_KILL) {
872 hw_rfkill = iwl_is_rfkill_set(trans);
873 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
874 hw_rfkill ? "disable radio" : "enable radio");
878 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
880 set_bit(STATUS_RFKILL, &trans_pcie->status);
881 if (test_and_clear_bit(STATUS_HCMD_ACTIVE,
882 &trans_pcie->status))
883 IWL_DEBUG_RF_KILL(trans,
884 "Rfkill while SYNC HCMD in flight\n");
885 wake_up(&trans_pcie->wait_command_queue);
887 clear_bit(STATUS_RFKILL, &trans_pcie->status);
890 handled |= CSR_INT_BIT_RF_KILL;
893 /* Chip got too hot and stopped itself */
894 if (inta & CSR_INT_BIT_CT_KILL) {
895 IWL_ERR(trans, "Microcode CT kill error detected.\n");
897 handled |= CSR_INT_BIT_CT_KILL;
900 /* Error detected by uCode */
901 if (inta & CSR_INT_BIT_SW_ERR) {
902 IWL_ERR(trans, "Microcode SW error detected. "
903 " Restarting 0x%X.\n", inta);
905 iwl_pcie_irq_handle_error(trans);
906 handled |= CSR_INT_BIT_SW_ERR;
909 /* uCode wakes up after power-down sleep */
910 if (inta & CSR_INT_BIT_WAKEUP) {
911 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
912 iwl_pcie_rxq_inc_wr_ptr(trans, &trans_pcie->rxq);
913 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++)
914 iwl_pcie_txq_inc_wr_ptr(trans, &trans_pcie->txq[i]);
918 handled |= CSR_INT_BIT_WAKEUP;
921 /* All uCode command responses, including Tx command responses,
922 * Rx "responses" (frame-received notification), and other
923 * notifications from uCode come through here*/
924 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
925 CSR_INT_BIT_RX_PERIODIC)) {
926 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
927 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
928 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
929 iwl_write32(trans, CSR_FH_INT_STATUS,
932 if (inta & CSR_INT_BIT_RX_PERIODIC) {
933 handled |= CSR_INT_BIT_RX_PERIODIC;
935 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
937 /* Sending RX interrupt require many steps to be done in the
939 * 1- write interrupt to current index in ICT table.
941 * 3- update RX shared data to indicate last write index.
943 * This could lead to RX race, driver could receive RX interrupt
944 * but the shared data changes does not reflect this;
945 * periodic interrupt will detect any dangling Rx activity.
948 /* Disable periodic interrupt; we use it as just a one-shot. */
949 iwl_write8(trans, CSR_INT_PERIODIC_REG,
950 CSR_INT_PERIODIC_DIS);
952 iwl_pcie_rx_handle(trans);
955 * Enable periodic interrupt in 8 msec only if we received
956 * real RX interrupt (instead of just periodic int), to catch
957 * any dangling Rx interrupt. If it was just the periodic
958 * interrupt, there was no dangling Rx activity, and no need
959 * to extend the periodic interrupt; one-shot is enough.
961 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
962 iwl_write8(trans, CSR_INT_PERIODIC_REG,
963 CSR_INT_PERIODIC_ENA);
968 /* This "Tx" DMA channel is used only for loading uCode */
969 if (inta & CSR_INT_BIT_FH_TX) {
970 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
971 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
973 handled |= CSR_INT_BIT_FH_TX;
974 /* Wake up uCode load routine, now that load is complete */
975 trans_pcie->ucode_write_complete = true;
976 wake_up(&trans_pcie->ucode_write_waitq);
979 if (inta & ~handled) {
980 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
981 isr_stats->unhandled++;
984 if (inta & ~(trans_pcie->inta_mask)) {
985 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
986 inta & ~trans_pcie->inta_mask);
989 /* Re-enable all interrupts */
990 /* only Re-enable if disabled by irq */
991 if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status))
992 iwl_enable_interrupts(trans);
993 /* Re-enable RF_KILL if it occurred */
994 else if (handled & CSR_INT_BIT_RF_KILL)
995 iwl_enable_rfkill_int(trans);
998 lock_map_release(&trans->sync_cmd_lockdep_map);
1002 /******************************************************************************
1006 ******************************************************************************/
1008 /* a device (PCI-E) page is 4096 bytes long */
1009 #define ICT_SHIFT 12
1010 #define ICT_SIZE (1 << ICT_SHIFT)
1011 #define ICT_COUNT (ICT_SIZE / sizeof(u32))
1013 /* Free dram table */
1014 void iwl_pcie_free_ict(struct iwl_trans *trans)
1016 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1018 if (trans_pcie->ict_tbl) {
1019 dma_free_coherent(trans->dev, ICT_SIZE,
1020 trans_pcie->ict_tbl,
1021 trans_pcie->ict_tbl_dma);
1022 trans_pcie->ict_tbl = NULL;
1023 trans_pcie->ict_tbl_dma = 0;
1028 * allocate dram shared table, it is an aligned memory
1029 * block of ICT_SIZE.
1030 * also reset all data related to ICT table interrupt.
1032 int iwl_pcie_alloc_ict(struct iwl_trans *trans)
1034 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1036 trans_pcie->ict_tbl =
1037 dma_alloc_coherent(trans->dev, ICT_SIZE,
1038 &trans_pcie->ict_tbl_dma,
1040 if (!trans_pcie->ict_tbl)
1043 /* just an API sanity check ... it is guaranteed to be aligned */
1044 if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
1045 iwl_pcie_free_ict(trans);
1049 IWL_DEBUG_ISR(trans, "ict dma addr %Lx\n",
1050 (unsigned long long)trans_pcie->ict_tbl_dma);
1052 IWL_DEBUG_ISR(trans, "ict vir addr %p\n", trans_pcie->ict_tbl);
1054 /* reset table and index to all 0 */
1055 memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1056 trans_pcie->ict_index = 0;
1058 /* add periodic RX interrupt */
1059 trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
1063 /* Device is going up inform it about using ICT interrupt table,
1064 * also we need to tell the driver to start using ICT interrupt.
1066 void iwl_pcie_reset_ict(struct iwl_trans *trans)
1068 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1070 unsigned long flags;
1072 if (!trans_pcie->ict_tbl)
1075 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1076 iwl_disable_interrupts(trans);
1078 memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1080 val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
1082 val |= CSR_DRAM_INT_TBL_ENABLE;
1083 val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1085 IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
1087 iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
1088 trans_pcie->use_ict = true;
1089 trans_pcie->ict_index = 0;
1090 iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
1091 iwl_enable_interrupts(trans);
1092 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1095 /* Device is going down disable ict interrupt usage */
1096 void iwl_pcie_disable_ict(struct iwl_trans *trans)
1098 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1099 unsigned long flags;
1101 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1102 trans_pcie->use_ict = false;
1103 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1106 /* legacy (non-ICT) ISR. Assumes that trans_pcie->irq_lock is held */
1107 static irqreturn_t iwl_pcie_isr(int irq, void *data)
1109 struct iwl_trans *trans = data;
1110 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1111 u32 inta, inta_mask;
1113 lockdep_assert_held(&trans_pcie->irq_lock);
1115 trace_iwlwifi_dev_irq(trans->dev);
1117 /* Disable (but don't clear!) interrupts here to avoid
1118 * back-to-back ISRs and sporadic interrupts from our NIC.
1119 * If we have something to service, the irq thread will re-enable ints.
1120 * If we *don't* have something, we'll re-enable before leaving here. */
1121 inta_mask = iwl_read32(trans, CSR_INT_MASK);
1122 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1124 /* Discover which interrupts are active/pending */
1125 inta = iwl_read32(trans, CSR_INT);
1127 if (inta & (~inta_mask)) {
1128 IWL_DEBUG_ISR(trans,
1129 "We got a masked interrupt (0x%08x)...Ack and ignore\n",
1130 inta & (~inta_mask));
1131 iwl_write32(trans, CSR_INT, inta & (~inta_mask));
1135 /* Ignore interrupt if there's nothing in NIC to service.
1136 * This may be due to IRQ shared with another device,
1137 * or due to sporadic interrupts thrown from our NIC. */
1139 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1143 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1144 /* Hardware disappeared. It might have already raised
1146 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1150 if (iwl_have_debug_level(IWL_DL_ISR))
1151 IWL_DEBUG_ISR(trans,
1152 "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1154 iwl_read32(trans, CSR_FH_INT_STATUS));
1156 trans_pcie->inta |= inta;
1157 /* the thread will service interrupts and re-enable them */
1159 return IRQ_WAKE_THREAD;
1160 else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1162 iwl_enable_interrupts(trans);
1166 /* re-enable interrupts here since we don't have anything to service. */
1167 /* only Re-enable if disabled by irq and no schedules tasklet. */
1168 if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1170 iwl_enable_interrupts(trans);
1175 /* interrupt handler using ict table, with this interrupt driver will
1176 * stop using INTA register to get device's interrupt, reading this register
1177 * is expensive, device will write interrupts in ICT dram table, increment
1178 * index then will fire interrupt to driver, driver will OR all ICT table
1179 * entries from current index up to table entry with 0 value. the result is
1180 * the interrupt we need to service, driver will set the entries back to 0 and
1183 irqreturn_t iwl_pcie_isr_ict(int irq, void *data)
1185 struct iwl_trans *trans = data;
1186 struct iwl_trans_pcie *trans_pcie;
1190 unsigned long flags;
1195 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1197 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1199 /* dram interrupt table not set yet,
1200 * use legacy interrupt.
1202 if (unlikely(!trans_pcie->use_ict)) {
1203 irqreturn_t ret = iwl_pcie_isr(irq, data);
1204 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1208 trace_iwlwifi_dev_irq(trans->dev);
1210 /* Disable (but don't clear!) interrupts here to avoid
1211 * back-to-back ISRs and sporadic interrupts from our NIC.
1212 * If we have something to service, the tasklet will re-enable ints.
1213 * If we *don't* have something, we'll re-enable before leaving here.
1215 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1217 /* Ignore interrupt if there's nothing in NIC to service.
1218 * This may be due to IRQ shared with another device,
1219 * or due to sporadic interrupts thrown from our NIC. */
1220 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1221 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
1223 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1228 * Collect all entries up to the first 0, starting from ict_index;
1229 * note we already read at ict_index.
1233 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1234 trans_pcie->ict_index, read);
1235 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1236 trans_pcie->ict_index =
1237 iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
1239 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1240 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
1244 /* We should not get this value, just ignore it. */
1245 if (val == 0xffffffff)
1249 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1250 * (bit 15 before shifting it to 31) to clear when using interrupt
1251 * coalescing. fortunately, bits 18 and 19 stay set when this happens
1252 * so we use them to decide on the real state of the Rx bit.
1253 * In order words, bit 15 is set if bit 18 or bit 19 are set.
1258 inta = (0xff & val) | ((0xff00 & val) << 16);
1259 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled(sw) 0x%08x ict 0x%08x\n",
1260 inta, trans_pcie->inta_mask, val);
1261 if (iwl_have_debug_level(IWL_DL_ISR))
1262 IWL_DEBUG_ISR(trans, "enabled(hw) 0x%08x\n",
1263 iwl_read32(trans, CSR_INT_MASK));
1265 inta &= trans_pcie->inta_mask;
1266 trans_pcie->inta |= inta;
1268 /* iwl_pcie_tasklet() will service interrupts and re-enable them */
1270 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1271 return IRQ_WAKE_THREAD;
1272 } else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1273 !trans_pcie->inta) {
1274 /* Allow interrupt if was disabled by this handler and
1275 * no tasklet was schedules, We should not enable interrupt,
1276 * tasklet will enable it.
1278 iwl_enable_interrupts(trans);
1281 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1285 /* re-enable interrupts here since we don't have anything to service.
1286 * only Re-enable if disabled by irq.
1288 if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1290 iwl_enable_interrupts(trans);
1292 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);