1 /******************************************************************************
3 * Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
29 #include <linux/sched.h>
30 #include <linux/wait.h>
31 #include <linux/gfp.h>
36 #include "iwl-op-mode.h"
38 /******************************************************************************
42 ******************************************************************************/
45 * Rx theory of operation
47 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
48 * each of which point to Receive Buffers to be filled by the NIC. These get
49 * used not only for Rx frames, but for any command response or notification
50 * from the NIC. The driver and NIC manage the Rx buffers by means
51 * of indexes into the circular buffer.
54 * The host/firmware share two index registers for managing the Rx buffers.
56 * The READ index maps to the first position that the firmware may be writing
57 * to -- the driver can read up to (but not including) this position and get
59 * The READ index is managed by the firmware once the card is enabled.
61 * The WRITE index maps to the last position the driver has read from -- the
62 * position preceding WRITE is the last slot the firmware can place a packet.
64 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
67 * During initialization, the host sets up the READ queue position to the first
68 * INDEX position, and WRITE to the last (READ - 1 wrapped)
70 * When the firmware places a packet in a buffer, it will advance the READ index
71 * and fire the RX interrupt. The driver can then query the READ index and
72 * process as many packets as possible, moving the WRITE index forward as it
73 * resets the Rx queue buffers with new memory.
75 * The management in the driver is as follows:
76 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
77 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
78 * to replenish the iwl->rxq->rx_free.
79 * + In iwl_pcie_rx_replenish (scheduled) if 'processed' != 'read' then the
80 * iwl->rxq is replenished and the READ INDEX is updated (updating the
81 * 'processed' and 'read' driver indexes as well)
82 * + A received packet is processed and handed to the kernel network stack,
83 * detached from the iwl->rxq. The driver 'processed' index is updated.
84 * + The Host/Firmware iwl->rxq is replenished at irq thread time from the
85 * rx_free list. If there are no allocated buffers in iwl->rxq->rx_free,
86 * the READ INDEX is not incremented and iwl->status(RX_STALLED) is set.
87 * If there were enough free buffers and RX_STALLED is set it is cleared.
92 * iwl_rxq_alloc() Allocates rx_free
93 * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls
94 * iwl_pcie_rxq_restock
95 * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx
96 * queue, updates firmware pointers, and updates
97 * the WRITE index. If insufficient rx_free buffers
98 * are available, schedules iwl_pcie_rx_replenish
100 * -- enable interrupts --
101 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
102 * READ INDEX, detaching the SKB from the pool.
103 * Moves the packet buffer from queue to rx_used.
104 * Calls iwl_pcie_rxq_restock to refill any empty
111 * iwl_rxq_space - Return number of free slots available in queue.
113 static int iwl_rxq_space(const struct iwl_rxq *rxq)
115 int s = rxq->read - rxq->write;
119 /* keep some buffer to not confuse full and empty queue */
127 * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
129 static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr)
131 return cpu_to_le32((u32)(dma_addr >> 8));
135 * iwl_pcie_rx_stop - stops the Rx DMA
137 int iwl_pcie_rx_stop(struct iwl_trans *trans)
139 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
140 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
141 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
145 * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue
147 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans,
153 spin_lock_irqsave(&rxq->lock, flags);
155 if (rxq->need_update == 0)
158 if (trans->cfg->base_params->shadow_reg_enable) {
159 /* shadow register enabled */
160 /* Device expects a multiple of 8 */
161 rxq->write_actual = (rxq->write & ~0x7);
162 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual);
164 struct iwl_trans_pcie *trans_pcie =
165 IWL_TRANS_GET_PCIE_TRANS(trans);
167 /* If power-saving is in use, make sure device is awake */
168 if (test_bit(STATUS_TPOWER_PMI, &trans_pcie->status)) {
169 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
171 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
172 IWL_DEBUG_INFO(trans,
173 "Rx queue requesting wakeup,"
174 " GP1 = 0x%x\n", reg);
175 iwl_set_bit(trans, CSR_GP_CNTRL,
176 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
180 rxq->write_actual = (rxq->write & ~0x7);
181 iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
184 /* Else device is assumed to be awake */
186 /* Device expects a multiple of 8 */
187 rxq->write_actual = (rxq->write & ~0x7);
188 iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
192 rxq->need_update = 0;
195 spin_unlock_irqrestore(&rxq->lock, flags);
199 * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool
201 * If there are slots in the RX queue that need to be restocked,
202 * and we have free pre-allocated buffers, fill the ranks as much
203 * as we can, pulling from rx_free.
205 * This moves the 'write' index forward to catch up with 'processed', and
206 * also updates the memory address in the firmware to reference the new
209 static void iwl_pcie_rxq_restock(struct iwl_trans *trans)
211 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
212 struct iwl_rxq *rxq = &trans_pcie->rxq;
213 struct iwl_rx_mem_buffer *rxb;
217 * If the device isn't enabled - not need to try to add buffers...
218 * This can happen when we stop the device and still have an interrupt
219 * pending. We stop the APM before we sync the interrupts because we
220 * have to (see comment there). On the other hand, since the APM is
221 * stopped, we cannot access the HW (in particular not prph).
222 * So don't try to restock if the APM has been already stopped.
224 if (!test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status))
227 spin_lock_irqsave(&rxq->lock, flags);
228 while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) {
229 /* The overwritten rxb must be a used one */
230 rxb = rxq->queue[rxq->write];
231 BUG_ON(rxb && rxb->page);
233 /* Get next free Rx buffer, remove from free list */
234 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
236 list_del(&rxb->list);
238 /* Point to Rx buffer via next RBD in circular buffer */
239 rxq->bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma);
240 rxq->queue[rxq->write] = rxb;
241 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
244 spin_unlock_irqrestore(&rxq->lock, flags);
245 /* If the pre-allocated buffer pool is dropping low, schedule to
247 if (rxq->free_count <= RX_LOW_WATERMARK)
248 schedule_work(&trans_pcie->rx_replenish);
250 /* If we've added more space for the firmware to place data, tell it.
251 * Increment device's write pointer in multiples of 8. */
252 if (rxq->write_actual != (rxq->write & ~0x7)) {
253 spin_lock_irqsave(&rxq->lock, flags);
254 rxq->need_update = 1;
255 spin_unlock_irqrestore(&rxq->lock, flags);
256 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
261 * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD
263 * A used RBD is an Rx buffer that has been given to the stack. To use it again
264 * a page must be allocated and the RBD must point to the page. This function
265 * doesn't change the HW pointer but handles the list of pages that is used by
266 * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly
269 static void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority)
271 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
272 struct iwl_rxq *rxq = &trans_pcie->rxq;
273 struct iwl_rx_mem_buffer *rxb;
276 gfp_t gfp_mask = priority;
279 spin_lock_irqsave(&rxq->lock, flags);
280 if (list_empty(&rxq->rx_used)) {
281 spin_unlock_irqrestore(&rxq->lock, flags);
284 spin_unlock_irqrestore(&rxq->lock, flags);
286 if (rxq->free_count > RX_LOW_WATERMARK)
287 gfp_mask |= __GFP_NOWARN;
289 if (trans_pcie->rx_page_order > 0)
290 gfp_mask |= __GFP_COMP;
292 /* Alloc a new receive buffer */
293 page = alloc_pages(gfp_mask, trans_pcie->rx_page_order);
296 IWL_DEBUG_INFO(trans, "alloc_pages failed, "
298 trans_pcie->rx_page_order);
300 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
302 IWL_CRIT(trans, "Failed to alloc_pages with %s."
303 "Only %u free buffers remaining.\n",
304 priority == GFP_ATOMIC ?
305 "GFP_ATOMIC" : "GFP_KERNEL",
307 /* We don't reschedule replenish work here -- we will
308 * call the restock method and if it still needs
309 * more buffers it will schedule replenish */
313 spin_lock_irqsave(&rxq->lock, flags);
315 if (list_empty(&rxq->rx_used)) {
316 spin_unlock_irqrestore(&rxq->lock, flags);
317 __free_pages(page, trans_pcie->rx_page_order);
320 rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer,
322 list_del(&rxb->list);
323 spin_unlock_irqrestore(&rxq->lock, flags);
327 /* Get physical address of the RB */
329 dma_map_page(trans->dev, page, 0,
330 PAGE_SIZE << trans_pcie->rx_page_order,
332 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
334 spin_lock_irqsave(&rxq->lock, flags);
335 list_add(&rxb->list, &rxq->rx_used);
336 spin_unlock_irqrestore(&rxq->lock, flags);
337 __free_pages(page, trans_pcie->rx_page_order);
340 /* dma address must be no more than 36 bits */
341 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
342 /* and also 256 byte aligned! */
343 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
345 spin_lock_irqsave(&rxq->lock, flags);
347 list_add_tail(&rxb->list, &rxq->rx_free);
350 spin_unlock_irqrestore(&rxq->lock, flags);
354 static void iwl_pcie_rxq_free_rbs(struct iwl_trans *trans)
356 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
357 struct iwl_rxq *rxq = &trans_pcie->rxq;
360 lockdep_assert_held(&rxq->lock);
362 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
363 if (!rxq->pool[i].page)
365 dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
366 PAGE_SIZE << trans_pcie->rx_page_order,
368 __free_pages(rxq->pool[i].page, trans_pcie->rx_page_order);
369 rxq->pool[i].page = NULL;
374 * iwl_pcie_rx_replenish - Move all used buffers from rx_used to rx_free
376 * When moving to rx_free an page is allocated for the slot.
378 * Also restock the Rx queue via iwl_pcie_rxq_restock.
379 * This is called as a scheduled work item (except for during initialization)
381 static void iwl_pcie_rx_replenish(struct iwl_trans *trans)
383 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
386 iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL);
388 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
389 iwl_pcie_rxq_restock(trans);
390 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
393 static void iwl_pcie_rx_replenish_now(struct iwl_trans *trans)
395 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC);
397 iwl_pcie_rxq_restock(trans);
400 static void iwl_pcie_rx_replenish_work(struct work_struct *data)
402 struct iwl_trans_pcie *trans_pcie =
403 container_of(data, struct iwl_trans_pcie, rx_replenish);
405 iwl_pcie_rx_replenish(trans_pcie->trans);
408 static int iwl_pcie_rx_alloc(struct iwl_trans *trans)
410 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
411 struct iwl_rxq *rxq = &trans_pcie->rxq;
412 struct device *dev = trans->dev;
414 memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
416 spin_lock_init(&rxq->lock);
418 if (WARN_ON(rxq->bd || rxq->rb_stts))
421 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
422 rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
423 &rxq->bd_dma, GFP_KERNEL);
427 /*Allocate the driver's pointer to receive buffer status */
428 rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
429 &rxq->rb_stts_dma, GFP_KERNEL);
436 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
437 rxq->bd, rxq->bd_dma);
444 static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
446 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
448 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
450 if (trans_pcie->rx_buf_size_8k)
451 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
453 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
456 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
457 /* reset and flush pointers */
458 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);
459 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);
460 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RDPTR, 0);
462 /* Reset driver's Rx queue write index */
463 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
465 /* Tell device where to find RBD circular buffer in DRAM */
466 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
467 (u32)(rxq->bd_dma >> 8));
469 /* Tell device where in DRAM to update its Rx status */
470 iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
471 rxq->rb_stts_dma >> 4);
474 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
475 * the credit mechanism in 5000 HW RX FIFO
476 * Direct rx interrupts to hosts
477 * Rx buffer size 4 or 8k
481 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
482 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
483 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
484 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
486 (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
487 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
489 /* Set interrupt coalescing timer to default (2048 usecs) */
490 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
493 static void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq)
497 lockdep_assert_held(&rxq->lock);
499 INIT_LIST_HEAD(&rxq->rx_free);
500 INIT_LIST_HEAD(&rxq->rx_used);
503 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
504 list_add(&rxq->pool[i].list, &rxq->rx_used);
507 int iwl_pcie_rx_init(struct iwl_trans *trans)
509 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
510 struct iwl_rxq *rxq = &trans_pcie->rxq;
515 err = iwl_pcie_rx_alloc(trans);
520 spin_lock_irqsave(&rxq->lock, flags);
522 INIT_WORK(&trans_pcie->rx_replenish, iwl_pcie_rx_replenish_work);
524 /* free all first - we might be reconfigured for a different size */
525 iwl_pcie_rxq_free_rbs(trans);
526 iwl_pcie_rx_init_rxb_lists(rxq);
528 for (i = 0; i < RX_QUEUE_SIZE; i++)
529 rxq->queue[i] = NULL;
531 /* Set us so that we have processed and used all buffers, but have
532 * not restocked the Rx queue with fresh buffers */
533 rxq->read = rxq->write = 0;
534 rxq->write_actual = 0;
535 memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
536 spin_unlock_irqrestore(&rxq->lock, flags);
538 iwl_pcie_rx_replenish(trans);
540 iwl_pcie_rx_hw_init(trans, rxq);
542 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
543 rxq->need_update = 1;
544 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
545 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
550 void iwl_pcie_rx_free(struct iwl_trans *trans)
552 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
553 struct iwl_rxq *rxq = &trans_pcie->rxq;
556 /*if rxq->bd is NULL, it means that nothing has been allocated,
559 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
563 cancel_work_sync(&trans_pcie->rx_replenish);
565 spin_lock_irqsave(&rxq->lock, flags);
566 iwl_pcie_rxq_free_rbs(trans);
567 spin_unlock_irqrestore(&rxq->lock, flags);
569 dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
570 rxq->bd, rxq->bd_dma);
575 dma_free_coherent(trans->dev,
576 sizeof(struct iwl_rb_status),
577 rxq->rb_stts, rxq->rb_stts_dma);
579 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
580 rxq->rb_stts_dma = 0;
584 static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans,
585 struct iwl_rx_mem_buffer *rxb)
587 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
588 struct iwl_rxq *rxq = &trans_pcie->rxq;
589 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
591 bool page_stolen = false;
592 int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
598 dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE);
600 while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) {
601 struct iwl_rx_packet *pkt;
602 struct iwl_device_cmd *cmd;
605 int index, cmd_index, err, len;
606 struct iwl_rx_cmd_buffer rxcb = {
608 ._rx_page_order = trans_pcie->rx_page_order,
610 ._page_stolen = false,
614 pkt = rxb_addr(&rxcb);
616 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID))
619 IWL_DEBUG_RX(trans, "cmd at offset %d: %s (0x%.2x)\n",
620 rxcb._offset, get_cmd_string(trans_pcie, pkt->hdr.cmd),
623 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
624 len += sizeof(u32); /* account for status word */
625 trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len);
626 trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len);
628 /* Reclaim a command buffer only if this packet is a response
629 * to a (driver-originated) command.
630 * If the packet (e.g. Rx frame) originated from uCode,
631 * there is no command buffer to reclaim.
632 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
633 * but apparently a few don't get set; catch them here. */
634 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME);
638 for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) {
639 if (trans_pcie->no_reclaim_cmds[i] ==
647 sequence = le16_to_cpu(pkt->hdr.sequence);
648 index = SEQ_TO_INDEX(sequence);
649 cmd_index = get_cmd_index(&txq->q, index);
652 cmd = txq->entries[cmd_index].cmd;
656 err = iwl_op_mode_rx(trans->op_mode, &rxcb, cmd);
659 kfree(txq->entries[cmd_index].free_buf);
660 txq->entries[cmd_index].free_buf = NULL;
664 * After here, we should always check rxcb._page_stolen,
665 * if it is true then one of the handlers took the page.
669 /* Invoke any callbacks, transfer the buffer to caller,
670 * and fire off the (possibly) blocking
671 * iwl_trans_send_cmd()
672 * as we reclaim the driver command queue */
673 if (!rxcb._page_stolen)
674 iwl_pcie_hcmd_complete(trans, &rxcb, err);
676 IWL_WARN(trans, "Claim null rxb?\n");
679 page_stolen |= rxcb._page_stolen;
680 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN);
683 /* page was stolen from us -- free our reference */
685 __free_pages(rxb->page, trans_pcie->rx_page_order);
689 /* Reuse the page if possible. For notification packets and
690 * SKBs that fail to Rx correctly, add them back into the
691 * rx_free list for reuse later. */
692 spin_lock_irqsave(&rxq->lock, flags);
693 if (rxb->page != NULL) {
695 dma_map_page(trans->dev, rxb->page, 0,
696 PAGE_SIZE << trans_pcie->rx_page_order,
698 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
700 * free the page(s) as well to not break
701 * the invariant that the items on the used
702 * list have no page(s)
704 __free_pages(rxb->page, trans_pcie->rx_page_order);
706 list_add_tail(&rxb->list, &rxq->rx_used);
708 list_add_tail(&rxb->list, &rxq->rx_free);
712 list_add_tail(&rxb->list, &rxq->rx_used);
713 spin_unlock_irqrestore(&rxq->lock, flags);
717 * iwl_pcie_rx_handle - Main entry function for receiving responses from fw
719 static void iwl_pcie_rx_handle(struct iwl_trans *trans)
721 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
722 struct iwl_rxq *rxq = &trans_pcie->rxq;
728 /* uCode's read index (stored in shared DRAM) indicates the last Rx
729 * buffer that the driver may process (last buffer filled by ucode). */
730 r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
733 /* Rx interrupt, but nothing sent from uCode */
735 IWL_DEBUG_RX(trans, "HW = SW = %d\n", r);
737 /* calculate total frames need to be restock after handling RX */
738 total_empty = r - rxq->write_actual;
740 total_empty += RX_QUEUE_SIZE;
742 if (total_empty > (RX_QUEUE_SIZE / 2))
746 struct iwl_rx_mem_buffer *rxb;
749 rxq->queue[i] = NULL;
751 IWL_DEBUG_RX(trans, "rxbuf: HW = %d, SW = %d (%p)\n",
753 iwl_pcie_rx_handle_rb(trans, rxb);
755 i = (i + 1) & RX_QUEUE_MASK;
756 /* If there are a lot of unused frames,
757 * restock the Rx queue so ucode wont assert. */
762 iwl_pcie_rx_replenish_now(trans);
768 /* Backtrack one entry */
771 iwl_pcie_rx_replenish_now(trans);
773 iwl_pcie_rxq_restock(trans);
777 * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card
779 static void iwl_pcie_irq_handle_error(struct iwl_trans *trans)
781 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
783 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
784 if (trans->cfg->internal_wimax_coex &&
785 (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
786 APMS_CLK_VAL_MRB_FUNC_MODE) ||
787 (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
788 APMG_PS_CTRL_VAL_RESET_REQ))) {
789 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
790 iwl_op_mode_wimax_active(trans->op_mode);
791 wake_up(&trans_pcie->wait_command_queue);
795 iwl_pcie_dump_csr(trans);
796 iwl_pcie_dump_fh(trans, NULL);
798 set_bit(STATUS_FW_ERROR, &trans_pcie->status);
799 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
800 wake_up(&trans_pcie->wait_command_queue);
803 iwl_op_mode_nic_error(trans->op_mode);
807 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
809 struct iwl_trans *trans = dev_id;
810 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
811 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
817 lock_map_acquire(&trans->sync_cmd_lockdep_map);
819 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
821 /* Ack/clear/reset pending uCode interrupts.
822 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
824 /* There is a hardware bug in the interrupt mask function that some
825 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
826 * they are disabled in the CSR_INT_MASK register. Furthermore the
827 * ICT interrupt handling mechanism has another bug that might cause
828 * these unmasked interrupts fail to be detected. We workaround the
829 * hardware bugs here by ACKing all the possible interrupts so that
830 * interrupt coalescing can still be achieved.
832 iwl_write32(trans, CSR_INT,
833 trans_pcie->inta | ~trans_pcie->inta_mask);
835 inta = trans_pcie->inta;
837 if (iwl_have_debug_level(IWL_DL_ISR))
838 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
839 inta, iwl_read32(trans, CSR_INT_MASK));
841 /* saved interrupt in inta variable now we can reset trans_pcie->inta */
842 trans_pcie->inta = 0;
844 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
846 /* Now service all interrupt bits discovered above. */
847 if (inta & CSR_INT_BIT_HW_ERR) {
848 IWL_ERR(trans, "Hardware error detected. Restarting.\n");
850 /* Tell the device to stop sending interrupts */
851 iwl_disable_interrupts(trans);
854 iwl_pcie_irq_handle_error(trans);
856 handled |= CSR_INT_BIT_HW_ERR;
861 if (iwl_have_debug_level(IWL_DL_ISR)) {
862 /* NIC fires this, but we don't use it, redundant with WAKEUP */
863 if (inta & CSR_INT_BIT_SCD) {
865 "Scheduler finished to transmit the frame/frames.\n");
869 /* Alive notification via Rx interrupt will do the real work */
870 if (inta & CSR_INT_BIT_ALIVE) {
871 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
876 /* Safely ignore these bits for debug checks below */
877 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
879 /* HW RF KILL switch toggled */
880 if (inta & CSR_INT_BIT_RF_KILL) {
883 hw_rfkill = iwl_is_rfkill_set(trans);
884 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
885 hw_rfkill ? "disable radio" : "enable radio");
889 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
892 * Clear the interrupt in APMG if the NIC is going down.
893 * Note that when the NIC exits RFkill (else branch), we
894 * can't access prph and the NIC will be reset in
897 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
898 APMG_RTC_INT_STT_RFKILL);
899 set_bit(STATUS_RFKILL, &trans_pcie->status);
900 if (test_and_clear_bit(STATUS_HCMD_ACTIVE,
901 &trans_pcie->status))
902 IWL_DEBUG_RF_KILL(trans,
903 "Rfkill while SYNC HCMD in flight\n");
904 wake_up(&trans_pcie->wait_command_queue);
906 clear_bit(STATUS_RFKILL, &trans_pcie->status);
909 handled |= CSR_INT_BIT_RF_KILL;
912 /* Chip got too hot and stopped itself */
913 if (inta & CSR_INT_BIT_CT_KILL) {
914 IWL_ERR(trans, "Microcode CT kill error detected.\n");
916 handled |= CSR_INT_BIT_CT_KILL;
919 /* Error detected by uCode */
920 if (inta & CSR_INT_BIT_SW_ERR) {
921 IWL_ERR(trans, "Microcode SW error detected. "
922 " Restarting 0x%X.\n", inta);
924 iwl_pcie_irq_handle_error(trans);
925 handled |= CSR_INT_BIT_SW_ERR;
928 /* uCode wakes up after power-down sleep */
929 if (inta & CSR_INT_BIT_WAKEUP) {
930 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
931 iwl_pcie_rxq_inc_wr_ptr(trans, &trans_pcie->rxq);
932 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++)
933 iwl_pcie_txq_inc_wr_ptr(trans, &trans_pcie->txq[i]);
937 handled |= CSR_INT_BIT_WAKEUP;
940 /* All uCode command responses, including Tx command responses,
941 * Rx "responses" (frame-received notification), and other
942 * notifications from uCode come through here*/
943 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
944 CSR_INT_BIT_RX_PERIODIC)) {
945 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
946 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
947 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
948 iwl_write32(trans, CSR_FH_INT_STATUS,
951 if (inta & CSR_INT_BIT_RX_PERIODIC) {
952 handled |= CSR_INT_BIT_RX_PERIODIC;
954 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
956 /* Sending RX interrupt require many steps to be done in the
958 * 1- write interrupt to current index in ICT table.
960 * 3- update RX shared data to indicate last write index.
962 * This could lead to RX race, driver could receive RX interrupt
963 * but the shared data changes does not reflect this;
964 * periodic interrupt will detect any dangling Rx activity.
967 /* Disable periodic interrupt; we use it as just a one-shot. */
968 iwl_write8(trans, CSR_INT_PERIODIC_REG,
969 CSR_INT_PERIODIC_DIS);
971 iwl_pcie_rx_handle(trans);
974 * Enable periodic interrupt in 8 msec only if we received
975 * real RX interrupt (instead of just periodic int), to catch
976 * any dangling Rx interrupt. If it was just the periodic
977 * interrupt, there was no dangling Rx activity, and no need
978 * to extend the periodic interrupt; one-shot is enough.
980 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
981 iwl_write8(trans, CSR_INT_PERIODIC_REG,
982 CSR_INT_PERIODIC_ENA);
987 /* This "Tx" DMA channel is used only for loading uCode */
988 if (inta & CSR_INT_BIT_FH_TX) {
989 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
990 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
992 handled |= CSR_INT_BIT_FH_TX;
993 /* Wake up uCode load routine, now that load is complete */
994 trans_pcie->ucode_write_complete = true;
995 wake_up(&trans_pcie->ucode_write_waitq);
998 if (inta & ~handled) {
999 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1000 isr_stats->unhandled++;
1003 if (inta & ~(trans_pcie->inta_mask)) {
1004 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
1005 inta & ~trans_pcie->inta_mask);
1008 /* Re-enable all interrupts */
1009 /* only Re-enable if disabled by irq */
1010 if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status))
1011 iwl_enable_interrupts(trans);
1012 /* Re-enable RF_KILL if it occurred */
1013 else if (handled & CSR_INT_BIT_RF_KILL)
1014 iwl_enable_rfkill_int(trans);
1017 lock_map_release(&trans->sync_cmd_lockdep_map);
1021 /******************************************************************************
1025 ******************************************************************************/
1027 /* a device (PCI-E) page is 4096 bytes long */
1028 #define ICT_SHIFT 12
1029 #define ICT_SIZE (1 << ICT_SHIFT)
1030 #define ICT_COUNT (ICT_SIZE / sizeof(u32))
1032 /* Free dram table */
1033 void iwl_pcie_free_ict(struct iwl_trans *trans)
1035 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1037 if (trans_pcie->ict_tbl) {
1038 dma_free_coherent(trans->dev, ICT_SIZE,
1039 trans_pcie->ict_tbl,
1040 trans_pcie->ict_tbl_dma);
1041 trans_pcie->ict_tbl = NULL;
1042 trans_pcie->ict_tbl_dma = 0;
1047 * allocate dram shared table, it is an aligned memory
1048 * block of ICT_SIZE.
1049 * also reset all data related to ICT table interrupt.
1051 int iwl_pcie_alloc_ict(struct iwl_trans *trans)
1053 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1055 trans_pcie->ict_tbl =
1056 dma_alloc_coherent(trans->dev, ICT_SIZE,
1057 &trans_pcie->ict_tbl_dma,
1059 if (!trans_pcie->ict_tbl)
1062 /* just an API sanity check ... it is guaranteed to be aligned */
1063 if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
1064 iwl_pcie_free_ict(trans);
1068 IWL_DEBUG_ISR(trans, "ict dma addr %Lx\n",
1069 (unsigned long long)trans_pcie->ict_tbl_dma);
1071 IWL_DEBUG_ISR(trans, "ict vir addr %p\n", trans_pcie->ict_tbl);
1073 /* reset table and index to all 0 */
1074 memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1075 trans_pcie->ict_index = 0;
1077 /* add periodic RX interrupt */
1078 trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
1082 /* Device is going up inform it about using ICT interrupt table,
1083 * also we need to tell the driver to start using ICT interrupt.
1085 void iwl_pcie_reset_ict(struct iwl_trans *trans)
1087 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1089 unsigned long flags;
1091 if (!trans_pcie->ict_tbl)
1094 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1095 iwl_disable_interrupts(trans);
1097 memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1099 val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
1101 val |= CSR_DRAM_INT_TBL_ENABLE;
1102 val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1104 IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
1106 iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
1107 trans_pcie->use_ict = true;
1108 trans_pcie->ict_index = 0;
1109 iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
1110 iwl_enable_interrupts(trans);
1111 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1114 /* Device is going down disable ict interrupt usage */
1115 void iwl_pcie_disable_ict(struct iwl_trans *trans)
1117 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1118 unsigned long flags;
1120 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1121 trans_pcie->use_ict = false;
1122 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1125 /* legacy (non-ICT) ISR. Assumes that trans_pcie->irq_lock is held */
1126 static irqreturn_t iwl_pcie_isr(int irq, void *data)
1128 struct iwl_trans *trans = data;
1129 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1130 u32 inta, inta_mask;
1132 lockdep_assert_held(&trans_pcie->irq_lock);
1134 trace_iwlwifi_dev_irq(trans->dev);
1136 /* Disable (but don't clear!) interrupts here to avoid
1137 * back-to-back ISRs and sporadic interrupts from our NIC.
1138 * If we have something to service, the irq thread will re-enable ints.
1139 * If we *don't* have something, we'll re-enable before leaving here. */
1140 inta_mask = iwl_read32(trans, CSR_INT_MASK);
1141 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1143 /* Discover which interrupts are active/pending */
1144 inta = iwl_read32(trans, CSR_INT);
1146 if (inta & (~inta_mask)) {
1147 IWL_DEBUG_ISR(trans,
1148 "We got a masked interrupt (0x%08x)...Ack and ignore\n",
1149 inta & (~inta_mask));
1150 iwl_write32(trans, CSR_INT, inta & (~inta_mask));
1154 /* Ignore interrupt if there's nothing in NIC to service.
1155 * This may be due to IRQ shared with another device,
1156 * or due to sporadic interrupts thrown from our NIC. */
1158 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1162 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1163 /* Hardware disappeared. It might have already raised
1165 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1169 if (iwl_have_debug_level(IWL_DL_ISR))
1170 IWL_DEBUG_ISR(trans,
1171 "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1173 iwl_read32(trans, CSR_FH_INT_STATUS));
1175 trans_pcie->inta |= inta;
1176 /* the thread will service interrupts and re-enable them */
1178 return IRQ_WAKE_THREAD;
1179 else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1181 iwl_enable_interrupts(trans);
1185 /* re-enable interrupts here since we don't have anything to service. */
1186 /* only Re-enable if disabled by irq and no schedules tasklet. */
1187 if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1189 iwl_enable_interrupts(trans);
1194 /* interrupt handler using ict table, with this interrupt driver will
1195 * stop using INTA register to get device's interrupt, reading this register
1196 * is expensive, device will write interrupts in ICT dram table, increment
1197 * index then will fire interrupt to driver, driver will OR all ICT table
1198 * entries from current index up to table entry with 0 value. the result is
1199 * the interrupt we need to service, driver will set the entries back to 0 and
1202 irqreturn_t iwl_pcie_isr_ict(int irq, void *data)
1204 struct iwl_trans *trans = data;
1205 struct iwl_trans_pcie *trans_pcie;
1209 unsigned long flags;
1214 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1216 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1218 /* dram interrupt table not set yet,
1219 * use legacy interrupt.
1221 if (unlikely(!trans_pcie->use_ict)) {
1222 irqreturn_t ret = iwl_pcie_isr(irq, data);
1223 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1227 trace_iwlwifi_dev_irq(trans->dev);
1229 /* Disable (but don't clear!) interrupts here to avoid
1230 * back-to-back ISRs and sporadic interrupts from our NIC.
1231 * If we have something to service, the tasklet will re-enable ints.
1232 * If we *don't* have something, we'll re-enable before leaving here.
1234 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1236 /* Ignore interrupt if there's nothing in NIC to service.
1237 * This may be due to IRQ shared with another device,
1238 * or due to sporadic interrupts thrown from our NIC. */
1239 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1240 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
1242 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1247 * Collect all entries up to the first 0, starting from ict_index;
1248 * note we already read at ict_index.
1252 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1253 trans_pcie->ict_index, read);
1254 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1255 trans_pcie->ict_index =
1256 iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
1258 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1259 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
1263 /* We should not get this value, just ignore it. */
1264 if (val == 0xffffffff)
1268 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1269 * (bit 15 before shifting it to 31) to clear when using interrupt
1270 * coalescing. fortunately, bits 18 and 19 stay set when this happens
1271 * so we use them to decide on the real state of the Rx bit.
1272 * In order words, bit 15 is set if bit 18 or bit 19 are set.
1277 inta = (0xff & val) | ((0xff00 & val) << 16);
1278 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled(sw) 0x%08x ict 0x%08x\n",
1279 inta, trans_pcie->inta_mask, val);
1280 if (iwl_have_debug_level(IWL_DL_ISR))
1281 IWL_DEBUG_ISR(trans, "enabled(hw) 0x%08x\n",
1282 iwl_read32(trans, CSR_INT_MASK));
1284 inta &= trans_pcie->inta_mask;
1285 trans_pcie->inta |= inta;
1287 /* iwl_pcie_tasklet() will service interrupts and re-enable them */
1289 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1290 return IRQ_WAKE_THREAD;
1291 } else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1292 !trans_pcie->inta) {
1293 /* Allow interrupt if was disabled by this handler and
1294 * no tasklet was schedules, We should not enable interrupt,
1295 * tasklet will enable it.
1297 iwl_enable_interrupts(trans);
1300 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1304 /* re-enable interrupts here since we don't have anything to service.
1305 * only Re-enable if disabled by irq.
1307 if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1309 iwl_enable_interrupts(trans);
1311 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);