1 /******************************************************************************
3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/etherdevice.h>
31 #include <linux/sched.h>
32 #include <linux/slab.h>
33 #include <net/mac80211.h>
34 #include "iwl-eeprom.h"
39 #include "iwl-helpers.h"
42 * iwl_txq_update_write_ptr - Send new write index to hardware
44 void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
47 int txq_id = txq->q.id;
49 if (txq->need_update == 0)
52 /* if we're trying to save power */
53 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
54 /* wake up nic if it's powered down ...
55 * uCode will wake up, and interrupt us again, so next
56 * time we'll skip this part. */
57 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
59 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
60 IWL_DEBUG_INFO(priv, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
62 iwl_set_bit(priv, CSR_GP_CNTRL,
63 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
67 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
68 txq->q.write_ptr | (txq_id << 8));
70 /* else not in power-save mode, uCode will never sleep when we're
71 * trying to tx (during RFKILL, we're not trying to tx). */
73 iwl_write32(priv, HBUS_TARG_WRPTR,
74 txq->q.write_ptr | (txq_id << 8));
78 EXPORT_SYMBOL(iwl_txq_update_write_ptr);
81 void iwl_free_tfds_in_queue(struct iwl_priv *priv,
82 int sta_id, int tid, int freed)
84 if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
85 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
87 IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
88 priv->stations[sta_id].tid[tid].tfds_in_queue,
90 priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
93 EXPORT_SYMBOL(iwl_free_tfds_in_queue);
96 * iwl_tx_queue_free - Deallocate DMA queue.
97 * @txq: Transmit queue to deallocate.
99 * Empty queue by removing and destroying all BD's.
101 * 0-fill, but do not free "txq" descriptor structure.
103 void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
105 struct iwl_tx_queue *txq = &priv->txq[txq_id];
106 struct iwl_queue *q = &txq->q;
107 struct device *dev = &priv->pci_dev->dev;
113 /* first, empty all BD's */
114 for (; q->write_ptr != q->read_ptr;
115 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
116 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
118 /* De-alloc array of command/tx buffers */
119 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
122 /* De-alloc circular buffer of TFDs */
124 dma_free_coherent(dev, priv->hw_params.tfd_size *
125 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
127 /* De-alloc array of per-TFD driver data */
131 /* deallocate arrays */
137 /* 0-fill queue descriptor structure */
138 memset(txq, 0, sizeof(*txq));
140 EXPORT_SYMBOL(iwl_tx_queue_free);
143 * iwl_cmd_queue_free - Deallocate DMA queue.
144 * @txq: Transmit queue to deallocate.
146 * Empty queue by removing and destroying all BD's.
148 * 0-fill, but do not free "txq" descriptor structure.
150 void iwl_cmd_queue_free(struct iwl_priv *priv)
152 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
153 struct iwl_queue *q = &txq->q;
154 struct device *dev = &priv->pci_dev->dev;
161 for (; q->read_ptr != q->write_ptr;
162 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
163 /* we have no way to tell if it is a huge cmd ATM */
164 i = get_cmd_index(q, q->read_ptr, 0);
166 if (txq->meta[i].flags & CMD_SIZE_HUGE) {
171 pci_unmap_single(priv->pci_dev,
172 pci_unmap_addr(&txq->meta[i], mapping),
173 pci_unmap_len(&txq->meta[i], len),
174 PCI_DMA_BIDIRECTIONAL);
178 pci_unmap_single(priv->pci_dev,
179 pci_unmap_addr(&txq->meta[i], mapping),
180 pci_unmap_len(&txq->meta[i], len),
181 PCI_DMA_BIDIRECTIONAL);
184 /* De-alloc array of command/tx buffers */
185 for (i = 0; i <= TFD_CMD_SLOTS; i++)
188 /* De-alloc circular buffer of TFDs */
190 dma_free_coherent(dev, priv->hw_params.tfd_size * txq->q.n_bd,
191 txq->tfds, txq->q.dma_addr);
193 /* deallocate arrays */
199 /* 0-fill queue descriptor structure */
200 memset(txq, 0, sizeof(*txq));
202 EXPORT_SYMBOL(iwl_cmd_queue_free);
204 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
207 * Theory of operation
209 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
210 * of buffer descriptors, each of which points to one or more data buffers for
211 * the device to read from or fill. Driver and device exchange status of each
212 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
213 * entries in each circular buffer, to protect against confusing empty and full
216 * The device reads or writes the data in the queues via the device's several
217 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
219 * For Tx queue, there are low mark and high mark limits. If, after queuing
220 * the packet for Tx, free space become < low mark, Tx queue stopped. When
221 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
224 * See more detailed info in iwl-4965-hw.h.
225 ***************************************************/
227 int iwl_queue_space(const struct iwl_queue *q)
229 int s = q->read_ptr - q->write_ptr;
231 if (q->read_ptr > q->write_ptr)
236 /* keep some reserve to not confuse empty and full situations */
242 EXPORT_SYMBOL(iwl_queue_space);
246 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
248 static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
249 int count, int slots_num, u32 id)
252 q->n_window = slots_num;
255 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
256 * and iwl_queue_dec_wrap are broken. */
257 BUG_ON(!is_power_of_2(count));
259 /* slots_num must be power-of-two size, otherwise
260 * get_cmd_index is broken. */
261 BUG_ON(!is_power_of_2(slots_num));
263 q->low_mark = q->n_window / 4;
267 q->high_mark = q->n_window / 8;
268 if (q->high_mark < 2)
271 q->write_ptr = q->read_ptr = 0;
272 q->last_read_ptr = 0;
273 q->repeat_same_read_ptr = 0;
279 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
281 static int iwl_tx_queue_alloc(struct iwl_priv *priv,
282 struct iwl_tx_queue *txq, u32 id)
284 struct device *dev = &priv->pci_dev->dev;
285 size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
287 /* Driver private data, only for Tx (not command) queues,
288 * not shared with device. */
289 if (id != IWL_CMD_QUEUE_NUM) {
290 txq->txb = kmalloc(sizeof(txq->txb[0]) *
291 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
293 IWL_ERR(priv, "kmalloc for auxiliary BD "
294 "structures failed\n");
301 /* Circular buffer of transmit frame descriptors (TFDs),
302 * shared with device */
303 txq->tfds = dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr,
306 IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz);
321 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
323 int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
324 int slots_num, u32 txq_id)
328 int actual_slots = slots_num;
331 * Alloc buffer array for commands (Tx or other types of commands).
332 * For the command queue (#4), allocate command space + one big
333 * command for scan, since scan command is very huge; the system will
334 * not have two scans at the same time, so only one is needed.
335 * For normal Tx queues (all other queues), no super-size command
338 if (txq_id == IWL_CMD_QUEUE_NUM)
341 txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots,
343 txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * actual_slots,
346 if (!txq->meta || !txq->cmd)
347 goto out_free_arrays;
349 len = sizeof(struct iwl_device_cmd);
350 for (i = 0; i < actual_slots; i++) {
351 /* only happens for cmd queue */
353 len = IWL_MAX_CMD_SIZE;
355 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
360 /* Alloc driver data array and TFD circular buffer */
361 ret = iwl_tx_queue_alloc(priv, txq, txq_id);
365 txq->need_update = 0;
368 * Aggregation TX queues will get their ID when aggregation begins;
369 * they overwrite the setting done here. The command FIFO doesn't
370 * need an swq_id so don't set one to catch errors, all others can
371 * be set up to the identity mapping.
373 if (txq_id != IWL_CMD_QUEUE_NUM)
374 txq->swq_id = txq_id;
376 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
377 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
378 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
380 /* Initialize queue's high/low-water marks, and head/tail indexes */
381 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
383 /* Tell device where to find queue */
384 priv->cfg->ops->lib->txq_init(priv, txq);
388 for (i = 0; i < actual_slots; i++)
396 EXPORT_SYMBOL(iwl_tx_queue_init);
398 void iwl_tx_queue_reset(struct iwl_priv *priv, struct iwl_tx_queue *txq,
399 int slots_num, u32 txq_id)
401 int actual_slots = slots_num;
403 if (txq_id == IWL_CMD_QUEUE_NUM)
406 memset(txq->meta, 0, sizeof(struct iwl_cmd_meta) * actual_slots);
408 txq->need_update = 0;
410 /* Initialize queue's high/low-water marks, and head/tail indexes */
411 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
413 /* Tell device where to find queue */
414 priv->cfg->ops->lib->txq_init(priv, txq);
416 EXPORT_SYMBOL(iwl_tx_queue_reset);
418 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
421 * iwl_enqueue_hcmd - enqueue a uCode command
422 * @priv: device private data point
423 * @cmd: a point to the ucode command structure
425 * The function returns < 0 values to indicate the operation is
426 * failed. On success, it turns the index (> 0) of command in the
429 int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
431 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
432 struct iwl_queue *q = &txq->q;
433 struct iwl_device_cmd *out_cmd;
434 struct iwl_cmd_meta *out_meta;
435 dma_addr_t phys_addr;
441 cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
442 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
444 /* If any of the command structures end up being larger than
445 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
446 * we will need to increase the size of the TFD entries
447 * Also, check to see if command buffer should not exceed the size
448 * of device_cmd and max_cmd_size. */
449 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
450 !(cmd->flags & CMD_SIZE_HUGE));
451 BUG_ON(fix_size > IWL_MAX_CMD_SIZE);
453 if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) {
454 IWL_WARN(priv, "Not sending command - %s KILL\n",
455 iwl_is_rfkill(priv) ? "RF" : "CT");
459 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
460 IWL_ERR(priv, "No space in command queue\n");
461 if (iwl_within_ct_kill_margin(priv))
462 iwl_tt_enter_ct_kill(priv);
464 IWL_ERR(priv, "Restarting adapter due to queue full\n");
465 queue_work(priv->workqueue, &priv->restart);
470 spin_lock_irqsave(&priv->hcmd_lock, flags);
472 /* If this is a huge cmd, mark the huge flag also on the meta.flags
473 * of the _original_ cmd. This is used for DMA mapping clean up.
475 if (cmd->flags & CMD_SIZE_HUGE) {
476 idx = get_cmd_index(q, q->write_ptr, 0);
477 txq->meta[idx].flags = CMD_SIZE_HUGE;
480 idx = get_cmd_index(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
481 out_cmd = txq->cmd[idx];
482 out_meta = &txq->meta[idx];
484 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
485 out_meta->flags = cmd->flags;
486 if (cmd->flags & CMD_WANT_SKB)
487 out_meta->source = cmd;
488 if (cmd->flags & CMD_ASYNC)
489 out_meta->callback = cmd->callback;
491 out_cmd->hdr.cmd = cmd->id;
492 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
494 /* At this point, the out_cmd now has all of the incoming cmd
497 out_cmd->hdr.flags = 0;
498 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
499 INDEX_TO_SEQ(q->write_ptr));
500 if (cmd->flags & CMD_SIZE_HUGE)
501 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
502 len = sizeof(struct iwl_device_cmd);
503 if (idx == TFD_CMD_SLOTS)
504 len = IWL_MAX_CMD_SIZE;
506 #ifdef CONFIG_IWLWIFI_DEBUG
507 switch (out_cmd->hdr.cmd) {
508 case REPLY_TX_LINK_QUALITY_CMD:
509 case SENSITIVITY_CMD:
510 IWL_DEBUG_HC_DUMP(priv, "Sending command %s (#%x), seq: 0x%04X, "
511 "%d bytes at %d[%d]:%d\n",
512 get_cmd_string(out_cmd->hdr.cmd),
514 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
515 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
518 IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, "
519 "%d bytes at %d[%d]:%d\n",
520 get_cmd_string(out_cmd->hdr.cmd),
522 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
523 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
526 txq->need_update = 1;
528 if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl)
529 /* Set up entry in queue's byte count circular buffer */
530 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
532 phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr,
533 fix_size, PCI_DMA_BIDIRECTIONAL);
534 pci_unmap_addr_set(out_meta, mapping, phys_addr);
535 pci_unmap_len_set(out_meta, len, fix_size);
537 trace_iwlwifi_dev_hcmd(priv, &out_cmd->hdr, fix_size, cmd->flags);
539 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
540 phys_addr, fix_size, 1,
543 /* Increment and update queue's write index */
544 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
545 iwl_txq_update_write_ptr(priv, txq);
547 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
552 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
554 * When FW advances 'R' index, all entries between old and new 'R' index
555 * need to be reclaimed. As result, some free space forms. If there is
556 * enough free space (> low mark), wake the stack that feeds us.
558 static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id,
559 int idx, int cmd_idx)
561 struct iwl_tx_queue *txq = &priv->txq[txq_id];
562 struct iwl_queue *q = &txq->q;
565 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
566 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
567 "is out of range [0-%d] %d %d.\n", txq_id,
568 idx, q->n_bd, q->write_ptr, q->read_ptr);
572 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
573 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
576 IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
577 q->write_ptr, q->read_ptr);
578 queue_work(priv->workqueue, &priv->restart);
585 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
586 * @rxb: Rx buffer to reclaim
588 * If an Rx buffer has an async callback associated with it the callback
589 * will be executed. The attached skb (if present) will only be freed
590 * if the callback returns 1
592 void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
594 struct iwl_rx_packet *pkt = rxb_addr(rxb);
595 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
596 int txq_id = SEQ_TO_QUEUE(sequence);
597 int index = SEQ_TO_INDEX(sequence);
599 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
600 struct iwl_device_cmd *cmd;
601 struct iwl_cmd_meta *meta;
602 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
604 /* If a Tx command is being handled and it isn't in the actual
605 * command queue then there a command routing bug has been introduced
606 * in the queue management code. */
607 if (WARN(txq_id != IWL_CMD_QUEUE_NUM,
608 "wrong command queue %d, sequence 0x%X readp=%d writep=%d\n",
610 priv->txq[IWL_CMD_QUEUE_NUM].q.read_ptr,
611 priv->txq[IWL_CMD_QUEUE_NUM].q.write_ptr)) {
612 iwl_print_hex_error(priv, pkt, 32);
616 /* If this is a huge cmd, clear the huge flag on the meta.flags
617 * of the _original_ cmd. So that iwl_cmd_queue_free won't unmap
618 * the DMA buffer for the scan (huge) command.
621 cmd_index = get_cmd_index(&txq->q, index, 0);
622 txq->meta[cmd_index].flags = 0;
624 cmd_index = get_cmd_index(&txq->q, index, huge);
625 cmd = txq->cmd[cmd_index];
626 meta = &txq->meta[cmd_index];
628 pci_unmap_single(priv->pci_dev,
629 pci_unmap_addr(meta, mapping),
630 pci_unmap_len(meta, len),
631 PCI_DMA_BIDIRECTIONAL);
633 /* Input error checking is done when commands are added to queue. */
634 if (meta->flags & CMD_WANT_SKB) {
635 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
637 } else if (meta->callback)
638 meta->callback(priv, cmd, pkt);
640 iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index);
642 if (!(meta->flags & CMD_ASYNC)) {
643 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
644 IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s\n",
645 get_cmd_string(cmd->hdr.cmd));
646 wake_up_interruptible(&priv->wait_command_queue);
650 EXPORT_SYMBOL(iwl_tx_cmd_complete);
652 #ifdef CONFIG_IWLWIFI_DEBUG
653 #define TX_STATUS_FAIL(x) case TX_STATUS_FAIL_ ## x: return #x
654 #define TX_STATUS_POSTPONE(x) case TX_STATUS_POSTPONE_ ## x: return #x
656 const char *iwl_get_tx_fail_reason(u32 status)
658 switch (status & TX_STATUS_MSK) {
659 case TX_STATUS_SUCCESS:
661 TX_STATUS_POSTPONE(DELAY);
662 TX_STATUS_POSTPONE(FEW_BYTES);
663 TX_STATUS_POSTPONE(BT_PRIO);
664 TX_STATUS_POSTPONE(QUIET_PERIOD);
665 TX_STATUS_POSTPONE(CALC_TTAK);
666 TX_STATUS_FAIL(INTERNAL_CROSSED_RETRY);
667 TX_STATUS_FAIL(SHORT_LIMIT);
668 TX_STATUS_FAIL(LONG_LIMIT);
669 TX_STATUS_FAIL(FIFO_UNDERRUN);
670 TX_STATUS_FAIL(DRAIN_FLOW);
671 TX_STATUS_FAIL(RFKILL_FLUSH);
672 TX_STATUS_FAIL(LIFE_EXPIRE);
673 TX_STATUS_FAIL(DEST_PS);
674 TX_STATUS_FAIL(HOST_ABORTED);
675 TX_STATUS_FAIL(BT_RETRY);
676 TX_STATUS_FAIL(STA_INVALID);
677 TX_STATUS_FAIL(FRAG_DROPPED);
678 TX_STATUS_FAIL(TID_DISABLE);
679 TX_STATUS_FAIL(FIFO_FLUSHED);
680 TX_STATUS_FAIL(INSUFFICIENT_CF_POLL);
681 TX_STATUS_FAIL(FW_DROP);
682 TX_STATUS_FAIL(STA_COLOR_MISMATCH_DROP);
687 EXPORT_SYMBOL(iwl_get_tx_fail_reason);
688 #endif /* CONFIG_IWLWIFI_DEBUG */